JP2003218346A - 分子エレクトロニクス用に分子を整列させるために1つまたは複数のナノポアを形成する方法 - Google Patents

分子エレクトロニクス用に分子を整列させるために1つまたは複数のナノポアを形成する方法

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Publication number
JP2003218346A
JP2003218346A JP2002363419A JP2002363419A JP2003218346A JP 2003218346 A JP2003218346 A JP 2003218346A JP 2002363419 A JP2002363419 A JP 2002363419A JP 2002363419 A JP2002363419 A JP 2002363419A JP 2003218346 A JP2003218346 A JP 2003218346A
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JP
Japan
Prior art keywords
substrate
molecules
forming
etching
nanopore
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002363419A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003218346A5 (enExample
Inventor
Theodore I Kamins
テオドール・アイ・カミンズ
Yong Chen
ヨン・チェン
Patricia A Beck
パトリシア・エイ・ベック
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2003218346A publication Critical patent/JP2003218346A/ja
Publication of JP2003218346A5 publication Critical patent/JP2003218346A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • CCHEMISTRY; METALLURGY
    • C03GLASS; MINERAL OR SLAG WOOL
    • C03CCHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C15/00Surface treatment of glass, not in the form of fibres or filaments, by etching
    • CCHEMISTRY; METALLURGY
    • C03GLASS; MINERAL OR SLAG WOOL
    • C03CCHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C17/00Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/001General methods for coating; Devices therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Organic Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geochemistry & Mineralogy (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Analytical Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
JP2002363419A 2001-12-20 2002-12-16 分子エレクトロニクス用に分子を整列させるために1つまたは複数のナノポアを形成する方法 Withdrawn JP2003218346A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/029583 2001-12-20
US10/029,583 US20030116531A1 (en) 2001-12-20 2001-12-20 Method of forming one or more nanopores for aligning molecules for molecular electronics

Publications (2)

Publication Number Publication Date
JP2003218346A true JP2003218346A (ja) 2003-07-31
JP2003218346A5 JP2003218346A5 (enExample) 2006-02-09

Family

ID=21849787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002363419A Withdrawn JP2003218346A (ja) 2001-12-20 2002-12-16 分子エレクトロニクス用に分子を整列させるために1つまたは複数のナノポアを形成する方法

Country Status (3)

Country Link
US (2) US20030116531A1 (enExample)
JP (1) JP2003218346A (enExample)
GB (1) GB2387272B (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006005205A (ja) * 2004-06-18 2006-01-05 Nippon Telegr & Teleph Corp <Ntt> 多孔構造体及びその製造方法
US7732005B2 (en) 2004-05-25 2010-06-08 Hitachi, Ltd. Method for producing recording medium, recording medium employing said method, and information recording and reproducing apparatus
JP2010283381A (ja) * 2010-08-26 2010-12-16 Nippon Telegr & Teleph Corp <Ntt> ヘテロ構造の製造方法
WO2017057237A1 (ja) * 2015-10-02 2017-04-06 セントラル硝子株式会社 熱電変換材料及びその製造方法
KR20220044079A (ko) * 2020-09-30 2022-04-06 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 탄소-함유층을 포함하는 패터닝 재료 및 반도체 디바이스 제조 방법
KR20220044081A (ko) * 2020-09-30 2022-04-06 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 실리콘-함유 층을 포함한 재료 패터닝 및 반도체 디바이스 제조 방법

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DE10161312A1 (de) * 2001-12-13 2003-07-10 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung und Schicht-Anordnung
US6919002B2 (en) * 2002-05-17 2005-07-19 Agilent Technologies, Inc. Nanopore system using nanotubes and C60 molecules
US20050287523A1 (en) * 2004-06-01 2005-12-29 The Regents Of The University Of California Functionalized platform for individual molecule or cell characterization
US7102204B2 (en) * 2004-06-29 2006-09-05 International Business Machines Corporation Integrated SOI fingered decoupling capacitor
US7553730B2 (en) * 2006-07-14 2009-06-30 Agilent Technologies, Inc. Methods of fabrication employing nanoscale mandrels
US8192600B2 (en) * 2007-09-27 2012-06-05 The Board Of Trustees Of The University Of Illinois Solid state device
DE102008039798A1 (de) * 2008-08-15 2010-02-25 NMI Naturwissenschaftliches und Medizinisches Institut an der Universität Tübingen Verfahren zur Übertragung von Nanostrukturen in ein Substrat
WO2012045016A2 (en) 2010-09-30 2012-04-05 California Institute Of Technology Particulate nanosorting stack
US8535512B2 (en) 2010-09-30 2013-09-17 California Institute Of Technology Devices and methods for sequencing nucleic acids
US8889562B2 (en) 2012-07-23 2014-11-18 International Business Machines Corporation Double patterning method
CN104803348A (zh) * 2015-04-20 2015-07-29 中国科学院光电技术研究所 一种牺牲模板制备高深宽比聚合物纳米柱阵列的方法
US10128341B2 (en) 2016-03-18 2018-11-13 Massachusetts Institute Of Technology Nanoporous semiconductor materials and manufacture thereof
CN106315505B (zh) * 2016-08-24 2018-11-06 深圳先进技术研究院 一种增强聚酰亚胺基底和导电金属层之间的粘附力的方法
US10370247B2 (en) 2016-08-29 2019-08-06 International Business Machines Corporation Contacting molecular components
US10739299B2 (en) * 2017-03-14 2020-08-11 Roche Sequencing Solutions, Inc. Nanopore well structures and methods
WO2019195719A1 (en) 2018-04-05 2019-10-10 Massachusetts Institute Of Technology Porous and nanoporous semiconductor materials and manufacture thereof
CN110364594B (zh) * 2019-07-19 2020-05-29 中原工学院 一种氮化镓或氮化铝纳米孔的制备方法
US11674947B2 (en) 2020-06-13 2023-06-13 International Business Machines Corporation Nanopore structures

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US4407695A (en) * 1981-12-31 1983-10-04 Exxon Research And Engineering Co. Natural lithographic fabrication of microstructures over large areas
US5393373A (en) * 1991-07-11 1995-02-28 Goldstar Electron Co., Ltd. Methods of patterning and manufacturing semiconductor devices
US5569355A (en) * 1995-01-11 1996-10-29 Center For Advanced Fiberoptic Applications Method for fabrication of microchannel electron multipliers
EP0731490A3 (en) * 1995-03-02 1998-03-11 Ebara Corporation Ultra-fine microfabrication method using an energy beam
US6379572B1 (en) * 2000-06-02 2002-04-30 Sony Corporation Flat panel display with spaced apart gate emitter openings
US6274396B1 (en) * 2001-01-29 2001-08-14 Advanced Micro Devices, Inc. Method of manufacturing calibration wafers for determining in-line defect scan tool sensitivity
JP2003053699A (ja) * 2001-08-10 2003-02-26 Nikon Corp ピンホール製造方法及び測定装置
US6515325B1 (en) * 2002-03-06 2003-02-04 Micron Technology, Inc. Nanotube semiconductor devices and methods for making the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732005B2 (en) 2004-05-25 2010-06-08 Hitachi, Ltd. Method for producing recording medium, recording medium employing said method, and information recording and reproducing apparatus
JP2006005205A (ja) * 2004-06-18 2006-01-05 Nippon Telegr & Teleph Corp <Ntt> 多孔構造体及びその製造方法
JP2010283381A (ja) * 2010-08-26 2010-12-16 Nippon Telegr & Teleph Corp <Ntt> ヘテロ構造の製造方法
WO2017057237A1 (ja) * 2015-10-02 2017-04-06 セントラル硝子株式会社 熱電変換材料及びその製造方法
JPWO2017057237A1 (ja) * 2015-10-02 2018-08-30 セントラル硝子株式会社 熱電変換材料及びその製造方法
KR20220044079A (ko) * 2020-09-30 2022-04-06 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 탄소-함유층을 포함하는 패터닝 재료 및 반도체 디바이스 제조 방법
KR20220044081A (ko) * 2020-09-30 2022-04-06 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 실리콘-함유 층을 포함한 재료 패터닝 및 반도체 디바이스 제조 방법
KR102628731B1 (ko) 2020-09-30 2024-01-23 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 실리콘-함유 층을 포함한 재료 패터닝 및 반도체 디바이스 제조 방법
KR102718037B1 (ko) * 2020-09-30 2024-10-15 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 탄소-함유층을 포함하는 패터닝 재료 및 반도체 디바이스 제조 방법
US12205824B2 (en) 2020-09-30 2025-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning material including silicon-containing layer and method for semiconductor device fabrication

Also Published As

Publication number Publication date
US7922927B2 (en) 2011-04-12
US20030116531A1 (en) 2003-06-26
GB2387272A (en) 2003-10-08
GB0229598D0 (en) 2003-01-22
US20080203055A1 (en) 2008-08-28
GB2387272B (en) 2005-06-22

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