JP2003197738A5 - - Google Patents

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Publication number
JP2003197738A5
JP2003197738A5 JP2002337918A JP2002337918A JP2003197738A5 JP 2003197738 A5 JP2003197738 A5 JP 2003197738A5 JP 2002337918 A JP2002337918 A JP 2002337918A JP 2002337918 A JP2002337918 A JP 2002337918A JP 2003197738 A5 JP2003197738 A5 JP 2003197738A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2002337918A
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Japanese (ja)
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JP2003197738A (ja
JP4486303B2 (ja
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Publication date
Priority claimed from US10/026,257 external-priority patent/US20030119305A1/en
Application filed filed Critical
Publication of JP2003197738A publication Critical patent/JP2003197738A/ja
Publication of JP2003197738A5 publication Critical patent/JP2003197738A5/ja
Application granted granted Critical
Publication of JP4486303B2 publication Critical patent/JP4486303B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2002337918A 2001-12-21 2002-11-21 半導体装置の相互接続構造においてバイアとトレンチの間に生じ得るミスアライメントに起因する影響を回避するための方法 Expired - Fee Related JP4486303B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/026257 2001-12-21
US10/026,257 US20030119305A1 (en) 2001-12-21 2001-12-21 Mask layer and dual damascene interconnect structure in a semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009161396A Division JP2009224816A (ja) 2001-12-21 2009-07-08 半導体装置のマスク層および二重ダマシーン相互接続構造

Publications (3)

Publication Number Publication Date
JP2003197738A JP2003197738A (ja) 2003-07-11
JP2003197738A5 true JP2003197738A5 (enExample) 2006-01-12
JP4486303B2 JP4486303B2 (ja) 2010-06-23

Family

ID=21830765

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2002337918A Expired - Fee Related JP4486303B2 (ja) 2001-12-21 2002-11-21 半導体装置の相互接続構造においてバイアとトレンチの間に生じ得るミスアライメントに起因する影響を回避するための方法
JP2009161396A Pending JP2009224816A (ja) 2001-12-21 2009-07-08 半導体装置のマスク層および二重ダマシーン相互接続構造

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2009161396A Pending JP2009224816A (ja) 2001-12-21 2009-07-08 半導体装置のマスク層および二重ダマシーン相互接続構造

Country Status (5)

Country Link
US (2) US20030119305A1 (enExample)
JP (2) JP4486303B2 (enExample)
KR (1) KR20030053055A (enExample)
GB (1) GB2390741B (enExample)
TW (1) TWI254375B (enExample)

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US6815333B2 (en) * 2002-04-02 2004-11-09 Dow Global Technologies Inc. Tri-layer masking architecture for patterning dual damascene interconnects
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JP4104426B2 (ja) * 2002-10-30 2008-06-18 富士通株式会社 半導体装置の製造方法
US6767825B1 (en) * 2003-02-03 2004-07-27 United Microelectronics Corporation Etching process for forming damascene structure of the semiconductor
KR100487948B1 (ko) * 2003-03-06 2005-05-06 삼성전자주식회사 이중 다마신 기술을 사용하여 비아콘택 구조체를 형성하는방법
US7078344B2 (en) * 2003-03-14 2006-07-18 Lam Research Corporation Stress free etch processing in combination with a dynamic liquid meniscus
US7009281B2 (en) * 2003-03-14 2006-03-07 Lam Corporation Small volume process chamber with hot inner surfaces
US7232766B2 (en) * 2003-03-14 2007-06-19 Lam Research Corporation System and method for surface reduction, passivation, corrosion prevention and activation of copper surface
US7217649B2 (en) * 2003-03-14 2007-05-15 Lam Research Corporation System and method for stress free conductor removal
JP3757213B2 (ja) * 2003-03-18 2006-03-22 富士通株式会社 半導体装置の製造方法
JP4256347B2 (ja) 2003-04-30 2009-04-22 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
US20090026587A1 (en) * 2004-01-14 2009-01-29 International Business Machines Corporation Gradient deposition of low-k cvd materials
JP4160569B2 (ja) * 2004-05-31 2008-10-01 株式会社東芝 半導体装置の製造方法
JP2006024811A (ja) * 2004-07-09 2006-01-26 Sony Corp 半導体装置の製造方法
WO2006095915A1 (ja) * 2005-03-09 2006-09-14 Nec Corporation 多層配線構造、半導体装置、パターン転写マスク、及び多層配線構造の製造方法
JP4476171B2 (ja) 2005-05-30 2010-06-09 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
US7781892B2 (en) * 2005-12-22 2010-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
WO2007078011A1 (ja) * 2006-01-06 2007-07-12 Nec Corporation 多層配線の製造方法と多層配線構造
US20070249165A1 (en) * 2006-04-05 2007-10-25 Huang Chun-Jen Dual damascene process
US7855142B2 (en) * 2009-01-09 2010-12-21 Samsung Electronics Co., Ltd. Methods of forming dual-damascene metal interconnect structures using multi-layer hard masks
KR200453906Y1 (ko) * 2009-07-08 2011-06-02 주식회사 이노디자인 절첩식 헬멧
US8404581B2 (en) * 2009-09-29 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an interconnect of a semiconductor device
DE102010038736A1 (de) * 2010-07-30 2012-02-02 Globalfoundries Dresden Module One Llc & Co. Kg Verfahren zum Steuern der kritischen Abmessungen von Gräben in einem Metallisierungssystem eines Halbleiterbauelements während des Ätzens einer Ätzstoppschicht
CN102487036B (zh) * 2010-12-01 2014-09-03 中芯国际集成电路制造(北京)有限公司 互连结构的制造方法
JP6061610B2 (ja) * 2012-10-18 2017-01-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8668835B1 (en) 2013-01-23 2014-03-11 Lam Research Corporation Method of etching self-aligned vias and trenches in a multi-layer film stack
US8906810B2 (en) 2013-05-07 2014-12-09 Lam Research Corporation Pulsed dielectric etch process for in-situ metal hard mask shape control to enable void-free metallization
US20140342553A1 (en) * 2013-05-14 2014-11-20 United Microelectronics Corp. Method for Forming Semiconductor Structure Having Opening
US9305839B2 (en) * 2013-12-19 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Curing photo resist for improving etching selectivity
US9385000B2 (en) * 2014-01-24 2016-07-05 United Microelectronics Corp. Method of performing etching process
US9522844B2 (en) * 2014-09-03 2016-12-20 Shenzhen China Star Optoelectronics Technology Co., Ltd. Low temperature poly-silicon thin film preparation apparatus and method for preparing the same
US9786491B2 (en) 2015-11-12 2017-10-10 Asm Ip Holding B.V. Formation of SiOCN thin films
KR102547096B1 (ko) 2015-12-22 2023-06-26 에스케이하이닉스 주식회사 듀얼다마신구조를 형성하는 방법
KR102378021B1 (ko) 2016-05-06 2022-03-23 에이에스엠 아이피 홀딩 비.브이. SiOC 박막의 형성
US9964587B2 (en) 2016-05-11 2018-05-08 United Microelectronics Corp. Semiconductor structure and testing method using the same
CN107492517B (zh) * 2016-06-12 2020-05-08 中芯国际集成电路制造(上海)有限公司 互连结构及形成方法
US10847529B2 (en) * 2017-04-13 2020-11-24 Asm Ip Holding B.V. Substrate processing method and device manufactured by the same
KR102805403B1 (ko) 2017-05-05 2025-05-13 에이에스엠 아이피 홀딩 비.브이. 산소 함유 박막의 형성을 제어하기 위한 플라즈마 강화 증착 공정
US10991573B2 (en) 2017-12-04 2021-04-27 Asm Ip Holding B.V. Uniform deposition of SiOC on dielectric and metal surfaces
US10886176B2 (en) * 2018-04-03 2021-01-05 Tokyo Electron Limited Self-aligned interconnect patterning for back-end-of-line (BEOL) structures including self-aligned via through the underlying interlevel metal layer
US12341005B2 (en) 2020-01-17 2025-06-24 Asm Ip Holding B.V. Formation of SiCN thin films
US12142479B2 (en) 2020-01-17 2024-11-12 Asm Ip Holding B.V. Formation of SiOCN thin films

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US5882996A (en) * 1997-10-14 1999-03-16 Industrial Technology Research Institute Method of self-aligned dual damascene patterning using developer soluble arc interstitial layer
US6127263A (en) * 1998-07-10 2000-10-03 Applied Materials, Inc. Misalignment tolerant techniques for dual damascene fabrication
US6312874B1 (en) * 1998-11-06 2001-11-06 Advanced Micro Devices, Inc. Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials
US6156643A (en) * 1998-11-06 2000-12-05 Advanced Micro Devices, Inc. Method of forming a dual damascene trench and borderless via structure
US6309962B1 (en) * 1999-09-15 2001-10-30 Taiwan Semiconductor Manufacturing Company Film stack and etching sequence for dual damascene
US6331479B1 (en) * 1999-09-20 2001-12-18 Chartered Semiconductor Manufacturing Ltd. Method to prevent degradation of low dielectric constant material in copper damascene interconnects
DE19958904C2 (de) * 1999-12-07 2002-01-24 Infineon Technologies Ag Verfahren zur Herstellung einer Hartmaske auf einem Substrat
FR2802336B1 (fr) * 1999-12-13 2002-03-01 St Microelectronics Sa Structure d'interconnexions de type damascene et son procede de realisation
US6559070B1 (en) * 2000-04-11 2003-05-06 Applied Materials, Inc. Mesoporous silica films with mobile ion gettering and accelerated processing
JP2001308179A (ja) * 2000-04-25 2001-11-02 Sharp Corp 半導体装置の製造方法
JP4377040B2 (ja) * 2000-07-24 2009-12-02 Ｎｅｃエレクトロニクス株式会社 半導体の製造方法
US6537908B2 (en) * 2001-02-28 2003-03-25 International Business Machines Corporation Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask
US6603204B2 (en) * 2001-02-28 2003-08-05 International Business Machines Corporation Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
US20030064582A1 (en) * 2001-09-28 2003-04-03 Oladeji Isaiah O. Mask layer and interconnect structure for dual damascene semiconductor manufacturing

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