JP2003158250A - SiGe/SOIのCMOSおよびその製造方法 - Google Patents

SiGe/SOIのCMOSおよびその製造方法

Info

Publication number
JP2003158250A
JP2003158250A JP2002269227A JP2002269227A JP2003158250A JP 2003158250 A JP2003158250 A JP 2003158250A JP 2002269227 A JP2002269227 A JP 2002269227A JP 2002269227 A JP2002269227 A JP 2002269227A JP 2003158250 A JP2003158250 A JP 2003158250A
Authority
JP
Japan
Prior art keywords
layer
silicon
germanium layer
silicon germanium
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002269227A
Other languages
English (en)
Japanese (ja)
Inventor
Ten Suu Shien
テン スー シェン
Douglas J Tweet
ジェイ. ツイート ダグラス
David R Evans
ラッセル エバンス ダビッド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/016,373 external-priority patent/US20020168802A1/en
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of JP2003158250A publication Critical patent/JP2003158250A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
JP2002269227A 2001-10-30 2002-09-13 SiGe/SOIのCMOSおよびその製造方法 Withdrawn JP2003158250A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/016,373 US20020168802A1 (en) 2001-05-14 2001-10-30 SiGe/SOI CMOS and method of making the same
US10/016,373 2001-10-30

Publications (1)

Publication Number Publication Date
JP2003158250A true JP2003158250A (ja) 2003-05-30

Family

ID=21776792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002269227A Withdrawn JP2003158250A (ja) 2001-10-30 2002-09-13 SiGe/SOIのCMOSおよびその製造方法

Country Status (4)

Country Link
JP (1) JP2003158250A (zh)
KR (1) KR100522275B1 (zh)
CN (1) CN1237587C (zh)
TW (1) TWI298911B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005197405A (ja) * 2004-01-06 2005-07-21 Toshiba Corp 半導体装置とその製造方法
JP2007513511A (ja) * 2003-12-05 2007-05-24 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体基板を作製する方法
US7449379B2 (en) 2003-08-05 2008-11-11 Fujitsu Limited Semiconductor device and method for fabricating the same
JP2010226080A (ja) * 2008-10-02 2010-10-07 Sumitomo Chemical Co Ltd 半導体基板、電子デバイス、および半導体基板の製造方法
JP2010226079A (ja) * 2008-10-02 2010-10-07 Sumitomo Chemical Co Ltd 半導体基板、電子デバイス、および半導体基板の製造方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
US7169226B2 (en) * 2003-07-01 2007-01-30 International Business Machines Corporation Defect reduction by oxidation of silicon
US6989058B2 (en) * 2003-09-03 2006-01-24 International Business Machines Corporation Use of thin SOI to inhibit relaxation of SiGe layers
US7550370B2 (en) * 2004-01-16 2009-06-23 International Business Machines Corporation Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density
US7217949B2 (en) * 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
CN100336171C (zh) * 2004-09-24 2007-09-05 上海新傲科技有限公司 基于注氧隔离技术的绝缘体上锗硅材料及其制备方法
EP1650794B1 (en) * 2004-10-19 2008-01-16 S.O.I. Tec Silicon on Insulator Technologies S.A. A method for fabricating a wafer structure with a strained silicon layer and an intermediate product of this method
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
TW200733244A (en) * 2005-10-06 2007-09-01 Nxp Bv Semiconductor device
KR100776173B1 (ko) * 2006-08-23 2007-11-12 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
KR100782497B1 (ko) * 2006-11-20 2007-12-05 삼성전자주식회사 얇은 응력이완 버퍼패턴을 갖는 반도체소자의 제조방법 및관련된 소자
KR100880106B1 (ko) * 2006-12-29 2009-01-21 주식회사 실트론 SiGe 희생층을 이용하여 표면 거칠기를 개선한 SOI웨이퍼의 제조 방법
FR3051595B1 (fr) * 2016-05-17 2022-11-18 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7449379B2 (en) 2003-08-05 2008-11-11 Fujitsu Limited Semiconductor device and method for fabricating the same
JP2007513511A (ja) * 2003-12-05 2007-05-24 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体基板を作製する方法
JP2005197405A (ja) * 2004-01-06 2005-07-21 Toshiba Corp 半導体装置とその製造方法
US7737466B1 (en) 2004-01-06 2010-06-15 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
JP2010226080A (ja) * 2008-10-02 2010-10-07 Sumitomo Chemical Co Ltd 半導体基板、電子デバイス、および半導体基板の製造方法
JP2010226079A (ja) * 2008-10-02 2010-10-07 Sumitomo Chemical Co Ltd 半導体基板、電子デバイス、および半導体基板の製造方法

Also Published As

Publication number Publication date
KR100522275B1 (ko) 2005-10-18
CN1237587C (zh) 2006-01-18
TWI298911B (en) 2008-07-11
KR20030036006A (ko) 2003-05-09
CN1416159A (zh) 2003-05-07

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20060110