JP2003150104A - Method for driving el display device, and el display device and information display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an EL display device without dispersion in brightness in a display plane. SOLUTION: In each pixel, a TFT 11a1 and a TFT 11a2 for driving use are formed. The two TFT 11a share a gate terminal. The current Iw from a source signal line 18 is programmed in a capacitor 19. In a 1st firld, a TFT 11f1 is brought into ON sate, and a current Idd1 is made to flow through an EL element 15. The EL element emits light with brightness corresponding to Idd1. In a 2nd field, a TFT 11f2 is brought into ON state, and a current Idd2 is made to flow through the EL element 15. The EL element 15 emits light with brightness corresponding to Idd2. Since a program current is Iw=Idd1+Idd2, an average light emitting brightness of the EL element 15 in the two fields corresponds to a half of the program current Iw.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to an EL display panel which displays an image by self-emission, and an information display device such as a mobile phone using the EL display panel.

[0002]

2. Description of the Related Art Liquid crystal display panels are widely used in portable devices and the like because of their thinness and low power consumption. Therefore, devices such as word processors, personal computers, televisions (TV), and viewfinders for video cameras are used. It is also used for monitors.

[0003]

However, since the liquid crystal display panel is not a self-luminous device, there is a problem that an image cannot be displayed unless a backlight is used. Since a predetermined thickness is required to form the backlight, there is a problem that the display module becomes thick. Further, in order to perform color display on the liquid crystal display panel, it is necessary to use a color filter. for that reason,
There is a problem that the light utilization efficiency is low. In the EL display device,

[0004]

In order to solve the above-mentioned problems, according to the present invention, pixels are arranged in a matrix, and each of the pixels has an EL element, a drive transistor element for applying a current to the EL element, and An EL display device is characterized in that a capacitor that holds a gate terminal voltage of a drive transistor element for a predetermined period and a switching element that short-circuits both ends of the capacitor are formed.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present specification, each drawing has a portion omitted or / and enlarged or reduced in order to facilitate understanding and / or drawing. For example, in the cross-sectional view of the display panel of FIG. 7, the sealing film 73 and the like are shown sufficiently thick. Further, in FIG. 1 and the like, a thin film transistor (TFT) for applying a signal to the pixel electrode is omitted. Further, in the display panel and the like of the present invention, a phase film or the like for phase compensation is omitted, but it is desirable to add it at a proper time. The above also applies to the following drawings. Further, the parts having the same numbers or symbols have the same or similar forms or materials or functions or operations.

The contents described in the drawings and the like can be combined with other embodiments and the like, unless otherwise specified. For example, a touch panel or the like may be added to the display panel of FIG. 1 to provide the information display device of FIGS. 19 and 49. In addition, a video camera with a magnifying lens attached (Fig. 44)
A viewfinder (see FIG. 45) such as (see FIG. 45) can also be configured. In addition, the driving method of the present invention described with reference to FIGS. 31, 51, 104, 106, and the like can be applied to any display device or display panel of the present invention. Further, although the present invention mainly describes an active matrix type display panel in which a TFT is formed in each pixel, it is not limited to this and needless to say, it can be applied to a simple matrix type.

As described above, even if not specifically exemplified in the specification, matters described or explained in the specification and drawings,
The contents and specifications can be combined with each other and described in the claims. This is because it is impossible to describe all combinations in the specification or the like.

As a display panel which has low power consumption and high display quality and can be further thinned, an organic EL display panel constructed by arranging a plurality of organic electroluminescence (EL) elements in a matrix has attracted attention. ing.

As shown in FIG. 4, the organic EL display panel includes an electron transport layer, a light emitting layer, a hole transport layer, etc. on a glass plate 49 (array substrate) on which a transparent electrode 48 as a pixel electrode is formed. At least one organic functional layer (EL
A layer) 47 and a metal electrode (reflection film) 46 are laminated. A positive voltage is applied to the anode (anode) of the transparent electrode (pixel electrode) 48 and a negative voltage is applied to the cathode (cathode) of the metal electrode (reflection electrode) 46, that is, the transparent electrode 4
8 is applied between the metal electrode 46 and the metal electrode 46, the organic functional layer (EL layer) 47 emits light. By using an organic compound, which can be expected to have good light emitting characteristics, in the organic functional layer, the EL display panel can be put to practical use.

The cathode electrode, the anode electrode or the reflection film may be formed by forming an optical interference film made of a dielectric multilayer film on the ITO electrode. The dielectric multilayer film is formed by alternately forming a low refractive index dielectric film and a high refractive index dielectric film. That is, it is a dielectric mirror. This dielectric multilayer film has a function of improving the color tone of light emitted from the organic EL structure (filter effect). The ITO may be another material such as IZO. The same applies to the pixel electrode.

A large current flows through the wirings 51 and 63 for supplying a current to the anode or the cathode. For example,
When the screen size of the EL display device becomes 40 inches, a current of about 100 A flows. Therefore, the resistance value of these wirings must be made sufficiently low. With respect to this problem, in the present invention, first, the wiring such as the anode is formed of a thin film. Then, the conductor is formed thick on the thin film wiring by an electrolytic plating technique. Also, if necessary,
The wiring itself or metal wiring made of thin copper is added to the wiring.

Further, in order to supply a large current to the anode or cathode wiring, a high-voltage, small-current power wiring is connected from the current supply means to the vicinity of the anode wiring or the like, and a low voltage is supplied by using a DCDC converter or the like. The power is converted into a high current and supplied. That is, the power supply is wired to the power consumption target with a high voltage, small current wiring, and converted into a large current and a low voltage near the power consumption target. As such a thing, a DCDC converter, a transformer, etc. are illustrated.

For the metal electrode 46, it is preferable to use one having a small work function such as lithium, silver, aluminum, magnesium, indium, copper or an alloy of each.
In particular, it is preferable to use, for example, an Al-Li alloy.
For the transparent electrode 48, a conductive material having a large work function such as ITO or gold can be used. When gold is used as the electrode material, the electrode becomes semitransparent. The ITO may be another material such as IZO. The same applies to the pixel electrode.

When depositing a thin film on the pixel electrode 46 or the like, it is advisable to form an organic EL film in an argon atmosphere. In addition, by forming a carbon film on the ITO as the pixel electrode 46 with a thickness of 20 to 50 nm, the stability of the interface is improved and the emission brightness and emission efficiency are also improved.

Needless to say, the EL film is not limited to being formed by vapor deposition and may be formed by ink jet.

Hereinafter, in order to facilitate understanding of the structure of the EL display panel of the present invention, a method of manufacturing the organic EL display panel of the present invention will be described first.

In order to improve the heat dissipation of the substrate 49, it may be made of sapphire glass. Alternatively, a thin film or a thick film having good thermal conductivity may be formed. For example, it is exemplified to use a substrate on which a diamond thin film (DLC or the like) is formed. Of course, a quartz glass substrate or a soda glass substrate may be used. Alternatively, a ceramic substrate such as alumina may be used, a metal plate made of copper or the like may be used, or a metal film may be vapor-deposited or applied on the insulating film. When the pixel electrode is of a reflective type, light is emitted from the surface direction of the substrate as the substrate material. Therefore, in addition to a transparent or translucent material such as glass, quartz or resin, a non-transmissive material such as stainless steel is used. You can also This configuration is shown in FIG.
The cathode electrode is formed of a transparent electrode 72 such as ITO.

In the embodiment of the present invention, the cathode and the like are formed of a metal film, but the present invention is not limited to this and may be formed of a transparent film such as ITO or IZO.
In this way, by making both the anode and cathode electrodes of the EL element 15 transparent electrodes, a transparent EL display panel can be constructed. By increasing the transmittance to about 80% without using a metal film, it is possible to display characters and pictures while allowing the other side of the display panel to be almost transparent.

Needless to say, a plastic substrate may be used as the substrate. The plastic substrate is hard to break,
Also, since it is lightweight, it is optimal as a display panel substrate for mobile phones. The plastic substrate is preferably used as a laminated substrate by adhering an auxiliary substrate to one surface of a base substrate which is a core material with an adhesive. Of course, these substrates 321 and the like are not limited to plates, and have a thickness of 0.3 m.
A film of m or less and 0.05 mm or more may be used.

An alicyclic polyolefin resin is preferably used as the base substrate. As such an alicyclic polyolefin resin, ARTON manufactured by Japan Synthetic Rubber Co., Ltd.
An example is a single plate having a thickness of 200 μm. From a polyester resin, polyethylene resin or polyether sulfone resin, etc., on one surface of the base substrate, a hard coat layer having heat resistance, solvent resistance or moisture permeation resistance function and a gas barrier layer having air permeation resistance function are formed. Place an auxiliary substrate (or film or membrane) that will become.

When the substrate 49 is made of plastic as described above, the substrate 49 is made up of a base substrate and an auxiliary substrate. On the other surface of the base substrate, an auxiliary substrate (or film or film) made of polyethersulfone resin or the like having a hard coat layer and a gas barrier layer formed thereon is arranged as described above. It is preferable that the angle formed by the optical slow axis of the auxiliary substrate and the optical slow axis of the auxiliary substrate be 90 degrees. Note that the base substrate and the auxiliary substrate are attached to each other with an adhesive or a pressure-sensitive adhesive to form a laminated substrate.

As the adhesive, it is preferable to use a UV (ultraviolet) curing type acrylic resin.
Further, it is preferable to use an acrylic resin having a fluorine group. Besides, an epoxy adhesive or pressure-sensitive adhesive may be used. It is preferable to use an adhesive or pressure-sensitive adhesive having a refractive index of 1.47 or more and 1.54 or less. Further, it is preferable that the difference in refractive index from the refractive index of the substrate 49 be 0.03 or less. In particular, it is preferable that the adhesive be added with a light diffusing material such as titanium oxide as described above to function as a light scattering layer.

When the auxiliary substrate and the auxiliary substrate are attached to the base substrate, the angle formed by the optical slow axis of the auxiliary substrate and the optical slow axis of the auxiliary substrate should be 45 degrees or more and 120 degrees or less. preferable. More preferably 80 degrees or more 1
It is preferable to set it to 00 degrees or less. Within this range, the phase difference generated in the auxiliary substrate and the auxiliary substrate, such as polyethersulfone resin, can be completely canceled in the laminated substrate. Therefore, the plastic substrate for the display panel can be treated as an isotropic substrate having no phase difference. Therefore, in the configuration using the circularly polarizing plate, unevenness of the display panel due to different phase states does not occur.

With this structure, versatility is remarkably widened as compared with a film substrate or a film laminated substrate having a phase difference. That is, by combining with a retardation film, it becomes possible to convert linearly polarized light into elliptically polarized light as designed. If there is a phase difference on the substrate 49 or the like, an error from the design value occurs due to this phase difference.

Here, as the hard coat layer, polyester resin, epoxy resin, urethane resin, acrylic resin or the like can be used, and the stripe-shaped electrodes or pixel electrodes are used as the first undercoat layer of the transparent conductive film. Also serves as.

Further, as the gas barrier layer, SiO2, S
Inorganic materials such as iOx, or polyvinyl alcohol,
An organic material such as polyimide can be used. As the pressure-sensitive adhesive, the adhesive or the like, an epoxy-based adhesive, a polyester-based adhesive, or the like can be used in addition to the acrylic-based adhesive described above. The thickness of the adhesive layer is 100μ.
m or less. However, it is preferably 10 μm or more in order to smooth the surface irregularities of the substrate and the like.

Further, as the auxiliary substrate and the auxiliary substrate constituting the substrate 49, it is preferable to use one having a thickness of 40 μm or more and 400 μm. Further, by setting the thickness of the auxiliary substrate and the thickness of the auxiliary substrate to 120 μm or less, it is possible to suppress unevenness or phase difference at the time of melt extrusion molding called a die line of the polyethersulfone resin. Preferably, the thickness of the auxiliary substrate is 50 μm or more and 80 μm or less.

Next, on this laminated substrate, SiOx is formed as an auxiliary undercoat layer of a transparent conductive film, and if necessary, a transparent conductive film made of ITO to be a pixel electrode is formed by a sputtering technique. In addition, if necessary, I
A TO film is formed. The transparent conductive film of the plastic substrate for a display panel manufactured as described above can realize a sheet resistance value of 25Ω / □ and a transmittance of 80% as its film characteristics.

The thickness of the base substrate is 50 μm to 100 μm
When m is thin, the display panel plastic substrate is curled by heat treatment in the manufacturing process of the display panel. Also, good results cannot be obtained when connecting circuit components. When the thickness of the base substrate is 200 μm or more and 500 μm or less with one plate, the substrate is not deformed, the smoothness is excellent, the transportability is good, and the transparent conductive film characteristics are stable. Moreover, the connection of the circuit components can be performed without any problem. Furthermore, the thickness is particularly preferably 250 μm or more and 450 μm or less. This is probably because it has appropriate flexibility and flatness. The ITO may be another material such as IZO. The same applies to the pixel electrode.

When an organic material such as the above-mentioned plastic substrate is used as the substrate 49, it is preferable to form a thin film made of an inorganic material as a barrier layer also on the surface in contact with the light modulation layer. The barrier layer made of this inorganic material is
It is preferable to use the same material as the AIR coat. Needless to say, the sealing substrate 41 can be manufactured by the same technique or configuration as the substrate 49.

When the barrier film is formed on the pixel electrode or the stripe-shaped electrode, it is preferable to use a low dielectric constant material in order to reduce the loss of the voltage applied to the light modulation layer as much as possible. For example, an amorphous carbon film containing fluorine (relative dielectric constant of 2.0 to 2.5) is exemplified. In addition, the LKD series (LKD-T200 series (dielectric constant 2.5-
2.7), LKD-T400 series (relative permittivity 2.0
~ 2.2)) are exemplified. LKD series is MSQ
(Methy-silsesquioxane) based spin coating type, with a relative dielectric constant of 2.0-2.
It is as low as 7, which is preferable. In addition, an organic material such as polyimide, urethane, or acrylic, or an inorganic material such as SiNx or SiO2 may be used. It goes without saying that these barrier film materials may be used for the auxiliary substrate.

By using the substrate 49 or 41 made of plastic, it is possible to exert the advantages that it is not broken and the weight can be reduced. Another advantage is that it can be pressed. That is, a substrate having an arbitrary shape can be manufactured by pressing or cutting (see FIG. 25). Further, it can be processed into any shape and thickness by melting or chemical treatment. For example, it may be formed into a circular shape, a spherical shape (curved surface or the like), or a conical shape. Also, by pressing,
Simultaneously with the production of the substrate, the unevenness 252 can be formed on one substrate surface to form a scattering surface or embossing.

Further, it is easy to form the positioning pins of the backlight or the cover substrate into the holes of the substrate 41 formed by pressing the plastic. Further, an electric circuit such as a capacitor or a resistor formed by the thick film technique or the thin film technique may be formed in the substrates 49 and 41. Further, a recess (not shown) is formed on the substrate 41, a convex portion 251 is formed on the substrate 49, and the concave portion and the convex portion are formed so that they can be fitted into each other just by fitting the substrate 41 and the substrate 49. It may be configured so that they can be integrated.

In the case of using the glass substrate, a bank used for vapor deposition of EL was formed around the pixel 16. The bank (rib) is made of a resin material and is formed in a convex shape with a thickness of 1.0 μm or more and 3.5 μm or less. More preferably, the height is 1.5 μm or more and 2.5 μm or less. Bank Embankment (convex) 251 made of this resin on the substrate 4
It can also be produced simultaneously with the formation of 1 or 49. The bank material is acrylic resin, polyimide resin, S
It may be an OG material. The bank simultaneously forms the resin protrusions 251 when the substrate 41 or the substrate 49 is pressed (see FIG. 25). This is a great effect that occurs when the substrates 41 and 49 are made of resin.

By thus forming the resin portion at the same time as the substrate, the manufacturing time can be shortened and the cost can be reduced. Further, when the substrate 49 and the like are manufactured, the convex portions 251 are formed in a dot shape in the display area portion. This convex portion 251 is preferably formed between adjacent pixels. The convex portion 251 is formed on the substrate 41.
And a predetermined space between the substrate 49 and the substrate 49 is maintained. The bank shape may be a square shape surrounding the pixel electrode or a stripe shape.

In the above embodiment, the convex portion 251 functioning as a bank is formed, but the present invention is not limited to this. For example, the pixel portion may be dug down (recessed portion) by pressing or the like. Note that the uneven portion 252 and the convex portion 251 are formed at the same time as the substrate, and a method of forming a flat substrate first and then pressing by reheating to form the uneven portion is also included.

Alternatively, the substrates 41 and 49 may be directly colored to form a mosaic color filter. Dyes, pigments, etc. are applied to the substrate by a technique such as ink jet printing and made to penetrate. After permeation, it may be dried at a high temperature, and the surface may be coated with a resin such as a UV resin or an inorganic material such as silicon oxide or nitric oxide.
Further, a color filter is formed by a gravure printing technique, an offset printing technique, a semiconductor pattern forming technique of applying and developing a film with a spinner. Similarly, a black matrix (BM) may be directly formed by using a technique, in addition to the color filter, by coloring in a black color, a dark color, or a complementary color of modulated light. In addition, a recess may be formed on the surface of the substrate so as to correspond to the pixel, and a color filter, BM, or TFT may be embedded in the recess. In particular, it is preferable to coat the surface with an acrylic resin. This configuration also has an advantage that the pixel electrode surface and the like are flattened.

Alternatively, the resin on the substrate surface may be made conductive by a conductive polymer or the like to directly form the pixel electrode or the cathode electrode. To make it even bigger, make a hole in the board,
A configuration in which an electronic component such as a capacitor is inserted into this hole is also exemplified. The advantage is that the substrate can be made thin.

By cutting the surface of the substrate,
The pattern may be freely formed. In addition, the substrate 41,
It may be formed by melting the peripheral portion of 49. In the case of an organic EL display panel, in order to prevent moisture from entering from the outside, the peripheral portion of the substrate may be melted and sealed.

As described above, by forming the substrate with resin, it is easy to make a hole in the substrate. Further, the substrate shape can be freely configured by pressing or the like. It is also possible to form holes in the substrates 41 and 49 and fill the holes with a conductive resin to electrically connect the front and back of the substrates. The boards 41 and 49 can be used as a multilayer circuit board or a double-sided board.

A conductive pin or the like may be inserted instead of the conductive resin. You may comprise so that the terminal of electronic components, such as a capacitor, can be inserted in the formed hole. Further, circuit wiring, a capacitor, a coil or a resistor made of a thin film may be formed in the substrate. That is, the boards 41 and 49 themselves may be multilayer wiring boards. Multi-layering consists of laminating thin substrates. One or more substrates (films) to be laminated may be colored.

Further, the substrate itself can be colored by adding a dye or pigment to the substrate material, or a filter can be formed. Further, the serial number can be formed at the same time when the substrate is manufactured. Further, by coloring only the portion other than the display area, it is possible to prevent malfunction due to irradiation of light on the mounted IC chips.

Further, half of the display area of the substrate can be colored with different colors. For this, a resin plate processing technique (injection processing, complexion processing, etc.) may be applied. Further, by using the same processing technique, half of the display area can have different EL layer thicknesses. Further, the display portion and the circuit portion can be formed at the same time. It is also easy to change the substrate thickness between the display area and the driver loading area.

It is also possible to form a microlens on the substrate 41 or the substrate 49 so as to correspond to a pixel or a display area. Also, the substrate 4
The diffraction grating may be formed by processing 1, 49. In addition, it is possible to improve the viewing angle or to provide the viewing angle dependency by forming unevenness finer than the pixel size. It should be noted that such arbitrary shape processing and fine processing technology can be realized by the stamper technology developed by OMRON Corporation for forming microlenses.

Striped electrodes (not shown) are formed on the substrates 41 and 49. An antireflection film (AIR coat) is formed on the surface of the substrate that comes into contact with air. Board 4
When a polarizing plate or the like is not attached to the substrates 1 and 49, the antireflection film (AIR coat) is directly formed on the substrates 41 and 49. When another constituent material such as a polarizing plate (polarizing film) is attached, an antireflection film (AIR coat) is formed on the surface of the constituent material.

In the above embodiments, the substrates 41 and 49 are mainly made of plastic, but the present invention is not limited to this. For example, the substrates 41, 49
Even if the substrate is a glass substrate or a metal substrate, the concavo-convex portion 252, the convex portion 252, or the like can be formed or configured by pressing, cutting, or the like. Further, it is possible to color the substrate. Therefore, the matters described are not limited to plastic substrates. Further, it is not limited to the substrate. For example, it may be a film or a sheet.

Further, in order to prevent or suppress the adhesion of dust to the surface of the polarizing plate, it is effective to form a thin film made of fluororesin. Further, in order to prevent static electricity, a thin film having a hydrophilic group, a conductive polymer film, a conductive film such as a metal film may be applied or deposited.

A polarizing plate (polarizing film) arranged or formed on the light incident surface or the light emitting surface of the display panel 82.
Is not limited to linearly polarized light, but may be elliptically polarized light. Also, a plurality of polarizing plates can be laminated together, a polarizing plate and a retardation plate can be combined,
Alternatively, a laminated product may be used.

TAC film (triacetyl cellulose film) is used as a main material for the polarizing film.
Is the best. This is because the TAC film has excellent optical properties, surface smoothness and processability.

The AIR coat is exemplified by a dielectric single layer film or a multilayer film. Others, 1.35
A resin having a low refractive index of 1.45 may be applied. For example, a fluorinated acrylic resin is exemplified. In particular, those having a refractive index of 1.37 or more and 1.42 or less have good characteristics.

The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide visible wavelength band. This is called a multi coat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band. This is called a V coat. The multi coat and the V coat are used properly according to the use of the display panel. The number of layers is not limited to two or more, and one layer may be used.

In the case of multi-coating, aluminum oxide (Al2O3) having an optical film thickness nd = λ / 4, zirconium (ZrO2) nd1 = λ / 2, and magnesium fluoride (MgF2) nd1 = λ / 4 are laminated. To form. Normal,
A thin film is formed with λ of 520 nm or a value in the vicinity thereof.

In the case of V coat, silicon monoxide (Si
O) is an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF2) is nd1 = λ / 4, or yttrium oxide (Y2O3) and magnesium fluoride (MgF2) are nd1.
= Λ / 4 stacked layers. Since SiO has an absorption band on the blue side, it is better to use Y2O3 when modulating blue light. In addition, Y2O3 is more stable in terms of the stability of the substance, which is preferable. Alternatively, a SiO2 thin film may be used. Of course, the AIR coat may be made by using a resin having a low refractive index. For example, acrylic resin such as fluorine is exemplified. It is preferable to use an ultraviolet curing type of these.

In order to prevent the display panel from being charged with static electricity, a hydrophilic resin is applied to the surface of the light guide plate such as the cover substrate or the display panel 82, or the substrate material of the panel or the like. It is preferable to use a material having good hydrophilicity.

A thin film transistor (TFT) as a plurality of switching elements or current control elements is formed in one pixel. The TFTs to be formed may be TFTs of the same type, or P-channel type and N-channel type TFTs.
Although different types of TFTs may be used, it is desirable that the switching transistor and the driving transistor have the same polarity. The structure of the TFT is not limited to the planar type TFT, and may be a stagger type or an inverted stagger type, or a structure in which the impurity regions (source, drain) are formed by using the self-alignment method. A non-self-aligned method may be used.

The EL display element 15 of the present invention is formed on a substrate by
It has an EL structure in which ITO serving as a hole injection electrode (pixel electrode), one or more kinds of organic layers, and an electron injection electrode are sequentially stacked. TFTs are provided on the substrate.

To manufacture the EL display element of the present invention, first, an array of TFTs is formed in a desired shape on a substrate.
Then, as a pixel electrode on the flattening film, the transparent electrode I
TO is formed into a film by a sputtering method and patterned. afterwards,
An organic EL layer, an electron injection electrode, etc. are laminated.

As the TFT, an ordinary polycrystalline silicon T is used.
FT may be used. The TFT is provided at the end of each pixel of the EL structure and has a size of about 10 to 30 μm. The size of the pixel is 20 μm × 20 μm to 300 μm.
It is about μm × 300 μm.

Wiring electrodes of TFTs are provided on the substrate. The wiring electrode has a low resistance and has a function of electrically connecting the hole injecting electrode to suppress the resistance value to a low level. Generally, the wiring electrode is made of Al, Al and a transition metal (however, Ti
However, a material containing one or more of Ti and titanium nitride (TiN) is used, but the present invention is not limited to this material. The total thickness of the hole injecting electrode, which is the base of the EL structure, and the wiring electrode of the TFT is not particularly limited, but is usually about 100 to 1000 nm.

An insulating layer is provided between the wiring electrode of the TFT 11 and the organic layer of the EL structure. The insulating layer is formed by forming an inorganic material such as silicon oxide such as SiO2 or silicon nitride by sputtering or vacuum deposition, a silicon oxide layer formed by SOG (spin on glass), a photoresist, a polyimide, an acrylic resin. Any film having insulating properties such as a coating film of a resin material such as Of these, polyimide is preferable. The insulating layer also plays a role of a corrosion / water resistant film that protects the wiring electrodes from moisture and corrosion.

The EL structure may have two or more emission peaks. In the EL display element of the present invention, the green and blue light emitting portions are obtained by, for example, combining a blue green light emitting EL structure with a green transmission layer or a blue transmission layer. The red light emitting portion is composed of a blue green light emitting EL structure and this E structure.
It can be obtained by a fluorescence conversion layer that converts the blue-green emission of the L structure into a wavelength close to red.

Next, the EL structure which constitutes the EL display element 15 of the present invention will be described. The EL structure of the present invention has an electron injection electrode which is a transparent electrode, at least one organic layer, and a hole injection electrode. The organic layer has at least one hole transport layer and at least one light emitting layer, for example, an electron injecting and transporting layer, a light emitting layer, a hole transporting layer, and a hole injecting layer in that order. The hole transport layer may be omitted. The organic layer of the EL structure of the present invention can have various constitutions, such as omitting the electron injecting / transporting layer or integrating with the light emitting layer, or by mixing the hole injecting / transporting layer and the light emitting layer. May be. The electron injection electrode is made of a metal, compound or alloy having a small work function, which is preferably formed by a vapor deposition method such as a vapor deposition method or a sputtering method.

Since the hole injecting electrode has a structure in which light emitted from the hole injecting electrode side is extracted, for example,
Examples thereof include ITO (tin-doped indium oxide), IZO (zinc-doped indium oxide), ZnO, SnO2, In2O3, and the like, with ITO and IZO being particularly preferable. The thickness of the hole injecting electrode may be a certain thickness or more so that hole injection can be sufficiently performed, and it is usually preferable to set the thickness to about 10 to 500 nm. A low drive voltage is required to improve the reliability of the element, but the preferable one is
Examples of the ITO include 10 to 30 Ω / □ (film thickness 50 to 300 nm). In actual use, the film thickness and optical constants of the electrodes may be set so that the interference effect due to reflection at the hole injection electrode interface such as ITO sufficiently satisfies the light extraction efficiency and color purity.

The hole injecting electrode can be formed by a vapor deposition method or the like, but is preferably formed by a sputtering method. The sputtering gas is not particularly limited, and an inert gas such as Ar, He, Ne, Kr, Xe, or a mixed gas thereof may be used.

The electron injecting electrode is made of a metal, compound or alloy having a low work function, which is formed by vapor deposition, sputtering or the like, preferably vapor deposition. The constituent material of the electron injection electrode to be formed is, for example, K, Li, Na, Mg, L.
a, Ce, Ca, Sr, Ba, Al, Ag, In, S
It is preferable to use a simple metal element such as n, Zn, or Zr, or a two-component or three-component alloy system containing them in order to improve stability. As an alloy system, for example, Ag · M
g (Ag: 1 to 20 at%), Al.Li (Li: 0.3
˜14 at%), In.Mg (Mg: 50-80 at%),
Al.Ca (Ca: 5 to 20 at%) and the like are preferable.

The thickness of the electron injecting electrode thin film may be a certain thickness or more for sufficiently injecting electrons, and is 0.1 nm or more,
The thickness is preferably 1 nm or more. The upper limit value is not particularly limited, but usually the film thickness may be about 100 to 500 nm.

The hole injecting layer has a function of facilitating injection of holes from the hole injecting electrode, and the hole transporting layer has a function of transporting holes and a function of hindering electrons, and injects charge. It is also called a layer or a charge transport layer.

The electron injecting and transporting layer is provided when the electron injecting and transporting function of the compound used for the light emitting layer is not so high, and the function of facilitating the injection of electrons from the electron injecting electrode,
It has a function of transporting electrons and a function of hindering holes.
The hole injection layer, the hole transport layer, and the electron injection transport layer increase and confine holes and electrons injected into the light emitting layer, optimize the recombination region, and improve the light emission efficiency. Note that the electron injecting and transporting layer may be separately provided in a layer having an injecting function and a layer having a transporting function.

The thickness of the light emitting layer, the combined thickness of the hole injecting layer and the hole transporting layer, and the thickness of the electron injecting and transporting layer are not particularly limited and may vary depending on the forming method.
It is preferably about nm.

The thickness of the hole injecting layer, the hole transporting layer and the thickness of the electron injecting and transporting layer are the same as the thickness of the light emitting layer or about 1/10 to 10 times, depending on the design of the recombination / light emitting region. And it is sufficient. The thicknesses of the hole injection layer and the hole transport layer, and the thicknesses of the electron injection layer and the electron transport layer when separated, are preferably 1 nm or more for the injection layer and 20 nm or more for the transport layer. At this time, the upper limit of the thickness of the injection layer and the transport layer is usually about 100 nm in the injection layer and 100 nm in the transport layer.
It is a degree. For such a film thickness, the injection and transport layer should be 2
The same applies when layers are provided.

The recombination can be achieved by controlling the film thickness while considering the carrier mobility and carrier density (determined by the ionization potential and electron affinity) of the light emitting layer, electron injecting and transporting layer and hole injecting and transporting layer to be combined. It is possible to freely design the area and the light emitting area, and it is possible to design the light emitting color, control the light emitting luminance and the light emitting spectrum by the interference effect of both electrodes, and control the spatial distribution of light emission.

The light emitting layer of the EL device 15 of the present invention contains a fluorescent substance which is a compound having a light emitting function. Examples of the fluorescent substance include, for example, JP-A-63-2646.
No. 92, etc., metal complex dyes such as tris (8-quinolinolato) aluminum [Alq3], JP-A-6-110569 (phenylanthracene derivative), and JP-A-6-114456 (tetraarylethene). Derivative), JP-A-6-100857,
A blue-green light emitting material such as that disclosed in JP-A-2-247278 can be used.

The organic EL device 15 for blue light emission is made of a material for the light emitting layer, such as "DMPhen (Triphenyla) having an emission wavelength of about 400 nm.
mine) ”is recommended. At this time, an electron injection layer (Bathocuproine) and a hole injection layer (mM
It is preferable to use the same material as TDATXA) with the same band gap as that of the light emitting layer. If only DMPhen with a large band gap of 3.4 eV is used in the light emitting layer, the electrons remain in the electron injecting layer and the holes remain in the hole injecting layer, and recombination of electrons and holes does not easily occur in the light emitting layer. is there. The problem that the structure of the light emitting material having amine group such as DMPhen is unstable and it is difficult to prolong the life can be solved by transferring the energy excited in DMPhen to the dopant and causing the dopant to emit light.

The luminous efficiency can be improved by using a phosphorescent material as the EL material. The external quantum efficiency of the fluorescent light emitting material is about 2 to 3%. The fluorescent material has an internal quantum efficiency of 25% (the efficiency of energy converted into light by excitation), whereas the phosphorescent material has a quantum efficiency of nearly 100%, resulting in a high external quantum efficiency.

C is used as the host material of the light emitting layer of the organic EL device.
It is preferable to use BP. Red (R) and green (G),
It is doped with a blue (B) phosphorescent material. All doped materials contain Ir. R material is Btp2Ir
(acac), G material may be (ppy) 2Ir (acac), and B material may be FIrpic.

The hole injecting layer / hole transporting layer may be formed, for example, in JP-A-63-295695 and JP-A-2-19.
1694, JP 3-792, JP 5-
234681, JP-A-5-239455,
JP-A-5-299174 and JP-A-7-12622
Japanese Patent Laid-Open No. 5-126226, Japanese Patent Laid-Open No. 8-126226
Various organic compounds described in 100172, EP0650955A1 and the like can be used. To form the hole injecting and transporting layer, the light emitting layer and the electron injecting and transporting layer,
It is preferable to use the vacuum vapor deposition method because a uniform thin film can be formed.

The manufacturing method and structure of the EL display panel of the present invention will be described in more detail below. As described above, first, the TFTs 11 for driving the pixels are formed on the array substrate 49. One pixel is composed of 4 or 5 TFTs. In addition, the pixel is current-programmed, and the programmed current is supplied to the EL element 15. Usually, the current programmed value is held in the storage capacitor 19 as a voltage value. The pixel configuration such as the combination of the TFTs 11 will be described later. Next, TFT11
A pixel electrode as a hole injecting electrode is formed on. The pixel electrode 48 is patterned by photolithography. A light-shielding film is formed or placed on the lower layer or the upper layer of the TFT 11 in order to prevent image quality deterioration due to a photoconductor phenomenon (hereinafter referred to as photocon) that occurs when light is incident on the TFT 11.

In the current programming, a program current is applied from the source driver circuit 14 to the pixel (or absorbed by the source driver circuit 14 from the pixel), and a signal value corresponding to this current is held in the pixel. . A current corresponding to the held signal value is made to flow in the EL element 15 (or made to flow from the EL element 15). That is,
The current is programmed, and a current corresponding to (corresponding to) the programmed current is passed through the EL element 15.

On the other hand, the voltage programming is to apply a program voltage from the source driver circuit 14 to the pixel and hold a signal value corresponding to this voltage in the pixel. A current corresponding to the held voltage is passed through the EL element 15. In other words, the voltage is programmed, the voltage is converted into a current value in the pixel, and a current corresponding to (corresponding to) the programmed voltage is passed through the EL element 15.

In order to form a TFT on a plastic substrate, an electronic thin film may be formed by processing the surface on which an organic semiconductor is formed and utilizing pentacene molecules composed of carbon and hydrogen. This thin film has a size 20 to 100 times as large as that of a conventional crystal grain, and has sufficient semiconductor characteristics suitable for electronic device manufacturing.

Pentacene tends to adhere to surface impurities as it grows on a silicon substrate. This results in irregular growth and grain sizes that are too small to produce high quality devices. In order to grow the crystal grains larger, a single layer of molecules called cyclohexene "molecular buffer" may be applied first on a silicon substrate. This layer covers "sticky sites" on the silicon, creating a clean surface and allowing pentacene to grow to very large grains.

By using these new thin film of large crystal grains, it is possible to manufacture a flexible transistor (TFT) using pentacene of large crystal grains. For mass production of such a flexible transistor, a transistor (TFT) can be manufactured by applying a liquid material at a low temperature.

Alternatively, a semiconductor thin film may be formed by forming a metal thin film to be a gate and islands on a substrate, depositing or coating an amorphous silicon film on this, and then heating. The semiconductor film is excellently crystallized in the island-shaped portion. Therefore, the mobility becomes good.

As the organic transistor (TFT), it is preferable to adopt a structure called a static induction transistor (SIT). Amorphous pentacene is used. The hole mobility is 1 × 10 cm 2 / Vs, which is lower than that of crystallized pentacene. However, the frequency characteristic can be improved by adopting the SIT structure. The thickness of pentacene is preferably 100 to 300 nm.

A p-type field effect transistor may be used as the organic TFT. TFTs can be formed on a plastic substrate. Since it is possible to fold the plastic substrate together, it is preferable that pentacene, which can form a flexible TFT display panel, be in a polycrystalline state. It is preferable to use PMMA as the material of the gate insulating film.
You may use naphthacene for the active layer of an organic transistor.

If oxygen plasma and an O 2 asher are used during cleaning, the flattening film 71 on the peripheral portion of the pixel electrode 48 is also ashed at the same time, and the peripheral portion of the pixel electrode 48 is scooped out. In order to solve this problem, in the present invention, an edge protection film 81 made of acrylic resin is formed around the pixel electrode 48 as shown in FIG. Examples of the constituent material of the edge protection film 81 include the same materials as the organic materials such as acrylic resin and polyimide resin that form the flattening film 71, and other examples include inorganic materials such as SiO2 and SiNx. Needless to say, it may be Al2O3 or the like.

The edge protection film 81 is formed so as to fill the space between the pixel electrodes 48 after the patterning 48 of the pixel electrodes 48. Of course, this edge protection film 81 is formed to a height of 2 to 4 μm and the bank 3661 of the metal mask (metal mask is the pixel electrode 48) when the organic EL materials are separately coated.
Needless to say, it may be used as a spacer so as not to come into direct contact with.

Further, enlarging the pixel electrode 48 as shown in FIG. 366 is also effective in improving the light emission efficiency. In FIG. 366, a bank 3661 which also serves as an edge protection film is formed around the pixel electrode 48. Bank 3661
Is formed to a height of 2 to 4 μm. Bank 3661
Serves as a spacer for preventing direct contact with the metal mask (not shown) pixel electrode 48 when the organic EL material is separately coated.

In the present invention shown in FIG. 366, the second pixel electrode 3662 is formed so as to overlap the pixel electrode 48 and the bank 3661. Second pixel electrode 3662
Are formed of the same material as the pixel electrode 48. Of course, the material may be changed. The second pixel electrode is electrically connected to the pixel electrode 48. In addition, bank 3661
Are formed on top of each other. Therefore, the pixel aperture ratio is high.

An EL film (47R (red), 47G (green), 47B (blue)) is formed on the second pixel electrode 3662. Each EL film is formed with a slight gap, or the peripheral portions are overlapped. Almost no light is emitted at the overlapped portions. Further, an aluminum film serving as a cathode is formed on the EL film 47. Note that in FIG. 366, the second electrode may be a reflective electrode and the reflective film 46 may be a transparent electrode originally. In other words, it is the upper extraction of light.

In the configuration of FIG. 366, the slope of the bank 3661 is used as the pixel opening. Therefore, the current density applied to the EL film can be reduced, and the light emitting area is widened, so that the efficiency is improved (the pixel aperture ratio is significantly improved).

Hereinafter, other methods for improving the efficiency of extracting light generated in the EL display panel will be described. FIG. 279 illustrates a problem of the conventional EL display device. In FIG. 279, 2791 shows the locus of light.

The light generated by the EL film 47 is emitted by the cathode 46.
The light is emitted from the substrate 49 on which the driver circuit 12 (14) is formed by being reflected. This light 2791a is transmitted to the substrate 49
Light incident at a predetermined angle on the interface between the air and the air is emitted from the substrate 49. However, the light 2791b incident at an angle equal to or greater than the critical angle θ is totally reflected inside the substrate 49. This totally reflected light 2791b is irregularly reflected in the substrate 49,
Reduces display contrast.

The totally reflected light 2791b becomes a loss. The proportion of light that causes this loss reaches 2/3 of the total luminous flux generated by the EL element 15. Therefore, reducing the generation of the light 2791b directly leads to the improvement of the light utilization rate.

The configuration for solving this problem is shown in FIG. 280. A refraction sheet (a light refraction member or a light refraction plate) is attached (arranged or formed) on the sealing film 73 described with reference to FIG. Refraction sheet 28
Reference numeral 01 denotes a refracting portion 2801 formed in a triangle, a polygon, or an arc so as to correspond to the pixel 16.
The refracting portion 2801 may be entirely made of a transparent member, or a reflective film may be formed on the portion indicated by a in FIG. 280 (the inner surface of the refracting portion 2802). The reflection film may be a metal film of Al, silver, or the like, or may be an interference film formed by forming a low refractive index dielectric film and a high refractive index dielectric film in multiple layers. Further, the shape may be set so as to be a total reflection area according to Snell's law.

In addition to the structure in which the bending sheet 2802 formed on the refraction sheet is mounted on the sealing film 73,
The bent portion 2802 may be formed directly on the sealing film 73. In the case of extracting light under the light, the substrate 49 itself may be processed to form the bent portion 2802. It may also be formed or arranged on the sealing plate.

The shape of the bent portion 2802 is not limited to the slope shape or the arc shape, but may be a polygonal shape or a vertical shape. Alternatively, a large number of needle-shaped protrusions may be formed. The bent portion 2802 is the pixel 1
It is basically formed on the periphery of the light emitting portion of No. 6. That is, if the aperture ratio of the pixel 16 is 30%, it is formed in the non-light emitting portion (that is, 70% portion) of the pixel 16. Of course, it goes without saying that the formation position of the bent portion 2802 may overlap the light emission position.

Although the bent portion 2802 is basically formed in the peripheral portion of the light emitting portion of the pixel 16, it is preferable to slightly change the central portion of the display region 21 in the peripheral portion. In the central portion of the display area 21, the bent portion 2802 is formed so as to be arranged just around the light emitting portion of the pixel 16. In the peripheral portion of the display area 21, the bent portion 2802 is formed.
Are formed so as to be displaced (formed) from the center position of the light emitting portion of the pixel 16 to the outside. In this way, the bent portion 28
By changing the formation position of 02 in the central portion and the peripheral portion of the display area, it is possible to suppress the occurrence of moire and the occurrence of color unevenness.

Further, by forming the position of the bent portion 2802 at random for each pixel, it is possible to suppress the occurrence of moire and also suppress the occurrence of color unevenness.

The inside of the bent portion 2802 is the EL element 1
The light emitted at 5 may pass, and may be refracted at the bent portion 2802 and emitted to the front surface of the panel. That is, the bent portion 2802 functions as a prism. In this case, the bent portion 2802 needs to be made of a light transmitting material.

When the bent portion 2802 is made of a light transmitting material, coloring this material is effective. EL element 1
This is because the effect of the color filter that cuts the band of the light emitted from No. 5 can be exhibited. Therefore, the color purity of the EL display panel is improved and the white balance is improved. When the EL element 15 emits white light, the bent portion 2802 can be used as a color filter without providing a color filter. Of course, it goes without saying that a color filter may be separately formed and the colored bent portion 2802 may be formed or arranged. Further, the bent portion 2802 or the refraction sheet 2801 may be colored directly. In addition, the bent portion 2802 or the refraction sheet 28
01 may be formed of a coloring material.

As the colorant, a colorant or a pigment in which resin is dispersed may be used, or gelatin or casein may be dyed with an acid dye like a color filter. A fluoran dye can also be used by coloring it. Further, the three colors of RGB are not required, and any one or more colors may be used. Moreover, a natural resin can be dyed using a pigment. Further, a material in which a pigment is dispersed in a synthetic resin can be used. The range of selection of the dye may be an appropriate one selected from azo dyes, anthraquinone dyes, phthalocyanine dyes, triphenylmethane dyes, and the like, or a combination of two or more thereof.

A polymer (2861) is preferably used as the constituent material of the bent portion 2802 and the refraction sheet 2801. As the polymer (2861), a photo-curing type resin is used in terms of ease of manufacturing process, separation from the liquid crystal phase, and the like. As a specific example, an ultraviolet curable acrylic resin is exemplified, and a resin containing an acrylic monomer or an acrylic oligomer which is polymerized and cured by ultraviolet irradiation is particularly preferable. Among them, the photocurable acrylic resin having a fluorine group shows little change with time and has good light resistance.

Examples of the polymer-forming monomer constituting the polymer (2861) include 2-ethylhexyl acrylate, 2-hydroxyethyl acrylate, neopentyl glycol acrylate, hexanediol diacrylate, diethylene glycol diacrylate, tripropylene glycol diacrylate, polyethylene. Glycol diacrylate, trimethylolpropane triacrylate, pentaerythritol acrylate and the like.

Examples of the oligomer or prepolymer include polyester acrylate, epoxy acrylate and polyurethane acrylate.

A polymerization initiator may be used in order to carry out the polymerization rapidly, and as an example thereof, 2-hydroxy-2-
Methyl-1-phenylpropan-1-one (“Darocur 1173” manufactured by Merck), 1- (4-isopropylphenyl) -2-hydroxy-2-methylpropan-1-
On (Merck "Darocur 1116"), 1-vidroxycyclohexyl phenyl ketone (Ciba-Gaiki "Irgacure 184"), benzyl methyl ketal (Ciba-Geigy "Irgacure 651") and the like. In addition, a chain transfer agent, a photosensitizer, a dye, a cross-linking agent and the like can be appropriately used in combination as optional components.

The above-mentioned matters concerning the polymer (2861) are mainly applied to the manufacturing method of FIGS. 286, 287 and 290. In the case of the manufacturing method of FIG. 288, the bent portion 2802 is made of an inorganic material. Of course, Figure 2
Even in the case of 88, it may be formed of an organic material such as a polymer.

The bent portion 2802 may be arranged in a hexagonal shape as shown in FIG. Of course, it may be octagonal or more. A bent portion 28 is provided around the light emitting portion of the pixel 16.
02 is formed. With the hexagonal shape as described above, when the EL display panel is observed, the occurrence of color unevenness and color shift can be extremely reduced even when the viewpoint for viewing the display screen is changed. Further, the occurrence of moire due to the displacement between the light emitting position of the pixel 16 and the position of the bent portion 2802 is small.

FIG. 281 shows an embodiment in which the same color is arranged in the vertical direction of the screen 21 (vertical stripe structure).
By forming (arranging) the color arrangement of pixels in a mosaic shape as shown in FIG. 282, the resolution in the diagonal direction of the image is improved even when the number of dots forming the display panel is relatively small.

Further, as shown in FIG. 283, a plurality of bent portions 2802 may be formed or arranged in one pixel 16. In the example of FIG. 283, the pixel 16 has one pixel electrode, and three bent portions 2801 (2801a, 2801b, 2801) are provided for this one pixel electrode.
c) is formed (arranged). Of course, one pixel 16 may have a plurality of pixel electrodes, and the bent portion 2801 may be formed (arranged) for each pixel electrode. Even if the pixel electrode is divided into a plurality of pixel electrodes with respect to one pixel electrode, the aperture ratio does not decrease much. This is because a driving or switching TFT or the like is arranged in the peripheral portion of the pixel electrode.

Of course, as shown in FIG.
Arrangement (formation) of one bent portion 2802 in one pixel 284
You may. Further, as shown in FIG. 285 (a),
One pixel has two columns and a plurality of pixels (2 × in FIG. 285 (a))
Six bent portions 2802 may be formed. Also, FIG.
As shown in FIG. 85 (b), a plurality of polygonal bent portions 2802 such as a hexagon (three in FIG. 285 (b)) may be formed in one pixel electrode.

Hereinafter, the bent portion 2802 (refractive sheet 280
1 may be included) may be included) will be described.

FIG. 286 shows the first embodiment of the present invention.
First, the TFT 11, the pixel 16, the driver circuits 12 and 14
The EL film 47 is formed on the substrate 49 on which the above are formed. For formation, a low molecular weight EL film may be formed by vapor deposition, or a high molecular weight EL film may be formed by an inkjet method. An electrode is formed on the EL film 47, and a sealing film 73 is formed on the electrode.
Are formed (FIG. 286 (a)). Moreover, you may attach a sealing plate. These items will be omitted here because they will be described in detail elsewhere.

Further, the manufacturing method described in the specification of the present invention is applied except for the matters described below. Also, EL
Configuration of element 15, pixel configuration, array configuration, panel configuration,
It goes without saying that the driving method and driving circuit are also applied to the following manufacturing method or manufactured panel. Further, it goes without saying that an information display device, a television, a monitor, a camera, and the like can be configured using a panel manufactured by the following manufacturing method.

Next, as shown in FIG. 286 (b), an uncured polymer material (transparent film 2861) is applied onto the sealing film 73. The polymer material 2861 is the material of the refraction part 2802 described above. The application may be performed by any method (technology) such as offset printing, screen printing, roller application, and spinner application.

After application of the uncured polymeric material 2861,
Place in oven to pre-dry. Alternatively, weak light (ultraviolet (UV) or visible light may be used) polymer 286
1 to reduce the fluidity of the polymer material 2861. After that, the roller 2862 having the shape of the bent portion 2802 is rotated and pressed against the transparent film 2861. In this way, the concavo-convex shape of the roller 2862 is changed to the transparent film 2
Transfer to 861. By this transfer, irregularities (recesses) 2863 corresponding to the refraction portions 2801 are formed on the transparent film 2862. After the uneven portion 2863 is formed, the entire transparent film 2861 is irradiated with UV or visible light to completely cure the transparent film 2861.

Temperature control when polymerizing the transparent film 2861 is important. The heating temperature is 40 degrees or more and about 60 degrees. Ultraviolet (UV) is 20 to 30 mW / depending on the spectral distribution
Irradiation with an intensity of about cm2 for about 2 to 8 seconds. The temperature and the irradiation conditions of ultraviolet rays must be determined in consideration of the additive material of the transparent film 2861. If the conditions are not right, the surface becomes cloudy. Moreover, it becomes a fine unevenness. In the present invention, the transparent film 2861 is irradiated with ultraviolet rays (irradiation intensity on the substrate surface: 30 mW / cm 2) for 6 seconds at a temperature of 50 ° C. by using an ultra-high pressure mercury lamp as a light source.
Was cured.

A light source for ultraviolet rays (UV2902) is arranged inside the roller 2862, and the roller 2862 is
The UV may be irradiated to the transparent film 2861 to sequentially cure the transparent film 2861 as the process proceeds. Also, separately from the roller 2862,
A source of UV2902 may be provided, and the transparent film 2861 may be irradiated with UV from this source in accordance with the progress of the roller 2862 to be sequentially cured. Further, a reflective film or the like is formed on a required portion of the bent portion 2802. The structure of the reflective film has been described with reference to FIG.

Further, the refraction portion 2802 may be formed by the manufacturing method shown in FIG. 290 (a) and 290 (b) are the same as FIGS. 286 (a) and 286 (b), and therefore the description thereof will be omitted.
In FIG. 290 (c), a stamper 290 made of a transparent material is used.
1 (press plate) is used. The press plate 2901 has
Concavities and convexities having a shape opposite to that of the bent portion 2802 are formed. The press plate 2901 is made of a transparent material such as quartz glass. By pressing the press plate 2901 against the transparent film 2861, the unevenness of the press plate 2901 is transferred to the transparent film 2861.

In this way, the uneven shape of the press plate 2901 is transferred to the transparent film 2861. By this transfer, the transparent film 2
862 is an unevenness (recess) 286 corresponding to the refraction part 2801.
3 form. After forming the uneven portion 2863, the transparent film 28
The entire 61 is irradiated with UV or visible light 2902 through the press plate 2901 to completely cure the transparent film 2861.

On the uneven surface of the press plate 2901, it is preferable to form a film having good releasability, which is made of an olephone-based material or the like. The transparent film 2861 and the press plate 29 are formed by forming these thin films having good releasability on the uneven surface.
The mold releasability from 01 is improved, and the manufacturing efficiency is improved. Note that temperature control is important for both the press plate 2901 and the transparent material 2861. It is preferable that the temperature of the press plate 2901 is lower than that of the transparent film 2861 by about 5 to 15 degrees. Depending on the type of the transparent film 2861, the releasability and the like may be better when the temperatures are reversed. Therefore, it is necessary to sufficiently carry out the experiment and determine the conditions.

Examples of the release film include silicon resin films, fluororesin films, olefin resin films such as polyethylene and polypropylene, and those obtained by coating the surface of the resin film with silicon resin or fluororesin. To be done. Any other material may be used as long as it transmits ultraviolet rays and has some flexibility. For example, a glass substrate or the like can also be used.

Further, as shown in 290 (d), after removing the press plate 2901, the entire transparent film 2861 is irradiated with UV (visible light) to completely cure the uncured resin component. This is also the case when the transparent film 2861 is of a thermosetting type or the like.

In the manufacturing method described with reference to FIGS. 286 and 290, the transparent film 2861 is of the ultraviolet curing type, but the present invention is not limited to this.
For example, it goes without saying that a thermoplastic type resin material, a thermosetting type resin material, and a two-component type room temperature curing type resin material which begins to cure when two liquids are mixed can be used. In the above cases, polymer 2861 need not be a transparent material. The selection range of the polymer material 2861 is widened, and an epoxy resin, a phenol resin, or the like can be used. in this case,
After the unevenness 2863 is formed, the bent portion 28 is heated or left to stand.
02 is formed. Of course, the press plate 2901 may be cured while being pressed against the transparent film 2861. Also,
A reflective film or the like is formed on a required portion of the bent portion 2802.
The structure of the reflective film has been described with reference to FIG.

FIG. 287 shows another embodiment of the present invention.
The process up to FIG. 287 (a) is the same as that of the other embodiments, and therefore its explanation is omitted.

In FIG. 287 (b), the convex portion 2871 is formed on the sealing film 73. The formation position of the convex portion 2871 is made to coincide with the formation position of the bent portion 2802. That is,
It is the periphery of the pixel or the periphery of the light emitting portion of the pixel. In the liquid crystal display panel, this is the position where the black matrix (BM) is formed. The convex portion 2871 is formed by using an inorganic material such as SiO2 or SiNx. Alternatively, an organic material such as the transparent film 2861 may be used. As a method of forming the convex portion 2871, an inorganic thin film or an organic thin film is vapor-deposited or applied on the sealing film 73 or the sealing plate in a thickness of 0.5 to 3 μm. A mask is formed thereover, and negative or positive etching is performed using the mask (FIG. 287 (b)).

Next, as shown in FIG. 287 (c),
A transparent film 2861 is applied to the entire display area 21. The application may be performed by any method (technology) such as offset printing, screen printing, roller application, and spinner application.

The resin to be applied has a viscosity of 5 cp or more and 40 c or more.
It is preferably p or less. That is, a material having a relatively low viscosity is used. The transparent film 2861 is smoothly formed along the convex portion 2871. As described above, in FIG. 287, the bent portion 2802 is formed by the convex portion 287 and the transparent film 2861. Further, a reflective film or the like is formed on a required portion of the bent portion 2802. For the structure of the reflective film, see FIG.
Since it has been described above, it will be omitted.

Although the transparent film is applied to the entire display area 21 in FIG. 287 (c), the present invention is not limited to this, and a thin film made of an inorganic material may be deposited. The bent portion 2802 is formed by the projections and depressions of the projections 2871 by depositing an inorganic material.

FIG. 288 shows another embodiment of the present invention.
The process up to FIG. 288 (a) is the same as that of the other embodiments, and therefore its explanation is omitted. In FIG. 288 (b), a metal mask 2881 is placed on the sealing film 73 or the sealing lid. The opening of the metal mask 2881 is wide on the sealing film 73 side and narrow on the other surface side.

The metal mask 2881 is made of a magnetic material, and the metal mask 2881 is formed from the back surface of the substrate 49 with a magnet.
Is attracted by magnetic force. Magnetic mask 2881
Adheres to the substrate without any gap.

The metal mask 2881 described with reference to FIG. 288.
Forms a protrusion having a height of 1.5 to 3 μm on the back surface of the metal mask 2881 so as not to directly touch the sealing film 73 (or to prevent it from coming into contact with the sealing film 73 as much as possible). Alternatively, a protrusion having a height of 1.5 to 3 μm is formed on the surface of the sealing film 73 or the sealing lid. This protrusion is formed at a location where the EL film 47 is not vapor-deposited. For example, between adjacent pixels.

As shown in FIG. 288 (b), an inorganic material such as SiO2 or SiNx is deposited through a metal mask 2881. The deposition location is the location where the bent portion 2802 is formed. Further, an organic material such as the transparent film 2861 may be used instead of the inorganic material. As described above, the bent portion 2802 can be formed using the metal mask 2881.

FIG. 280 shows a bent portion (or light reflecting portion) 2802 having a prism shape. However, the present invention is not limited to this. For example, as shown in FIG. 289, a microlens-shaped bent portion 2802 may be formed corresponding to the pixel 16. It is preferable that the microlenses have a sine curve shape. Further, although it is preferable to form it in an arc shape, the shape is not limited to this, and it may be a kamaboko shape. The height of the micro lens is 1
The thickness is preferably 5 μm or more and 3100 μm or less.

Ti is vapor-deposited on a soda glass substrate which is a base of the microlens substrate, and a circular window corresponding to a pixel is opened by photolinography. Next, it is dipped in a molten solution of nitrate of monovalent ions and heat-treated at 400 ° C. or higher. During heating, cations in the melt are isotropically diffused into the glass substrate through the opening window, and ion exchange is performed. When ion-exchanged, the portion has a refractive index profile. The refractive index is 1.5 to 1.7. The microlens is manufactured as described above.

The microlenses are formed by the stamper technique. This stamper technology is a method adopted by Omron as a method for forming microlenses, and Matsushita Electric uses a CD.
The method used as the method of forming a minute lens in the pickup lens of is applied. Further, the bent portion 2802 in FIG. 289 can also be formed by a diffraction grating. Since other matters are the same as those in FIG. 280, description thereof will be omitted.

In the structure of FIG. 280, the refraction sheet is attached (arranged or formed) on the sealing film 73. The refraction sheet 2801 has a triangular shape, a polygonal shape, or an arc shape so as to correspond to the pixels 16.
801 is formed. That is, the refraction part 2801 is assumed to be uneven, but the present invention is not limited to this. For example, as shown in FIG. 362, the recess may be filled (formed) with the refractive material 2802b. Alternatively, the convex portion may be filled (formed) with the refractive material 2802a.

The refraction part 2802a is formed (filled) with a high refractive index material, and the refraction part 2802b is formed (filled) with a low refractive index material. Alternatively, the refractive portion 2802a may be formed (filled) with a low refractive index material, and the refractive portion 2802b may be formed (filled) with a high refractive index material. The low refractive material is selected from magnesium difluoride, silicon dioxide, aluminum trioxide, cerium difluoride and silicon monoxide.
The high refractive material is selected from yttrium trioxide, zirconium dioxide, hafnium dioxide, ditantalum pentoxide, cerium dioxide, titanium dioxide, zinc sulfide, ITO, and IZO.

The above are inorganic materials, but organic materials may be used. For example, a fluorine-based acrylic resin is exemplified as the low-refractive-index material. In addition, liquid or gel can be used. Examples of the low refractive index material having a refractive index of 1.3 or more and 1.50 or less include pure, gels such as silicon and ethylene glycol, ethyl alcohol, methyl alcohol, and the like. As a relatively high refractive index material, methyl salicylate is used. Liquids such as The refraction sheet 2801 is configured by filling these.

When the refraction sheet 2801 is formed as shown in FIG. 362, the sheet 2801 becomes flat, and a polarizing plate or the like can be easily attached to this flat surface. Further, the surface can be easily coated with a UV resin of 6H or more. Therefore, the surface of the sheet 2801 can be protected. The refraction sheet 2801 may be mounted upside down as shown in FIG. 363. With this structure, it is possible to prevent the bending portion 2802a from being mechanically damaged. Note that 73 may function as a protective sheet (protective film) instead of functioning as a sealing film.

The same applies to the embodiment of FIG. 289.
As illustrated in FIG. 364, the convex portion of the refraction portion 2802a may be filled (formed) with the refraction material 2802b. Alternatively, the concave portion of the refraction portion 2802b may be filled (formed) with the refraction material 2802a.

Further, similarly to FIG. 363, the refraction sheet 2801 may be mounted upside down as shown in FIG. 365. According to this structure, the refraction portion 2802
A can be prevented from being mechanically damaged. Note that 73 does not function as a sealing film, but a protective sheet (protective film).
May function as.

As the vacuum vapor deposition apparatus, an apparatus obtained by modifying a commercially available high vacuum vapor deposition apparatus (EBV-6DA type manufactured by Nippon Vacuum Technology Co., Ltd.) is used. The main evacuation device is a turbo molecular pump (TC1500 manufactured by Osaka Vacuum Co., Ltd.) with an evacuation speed of 1500 liters / min, and the ultimate vacuum is about 1 × 10e.
-6 Torr or less, all vapor deposition is 2-3 × 10e
Perform in the range of -6 Torr. In addition, all vapor deposition may be performed by connecting a DC power source (PAK10-70A, manufactured by Kikusui Electronics Co., Ltd.) to a resistance heating type vapor deposition boat made of tungsten.

A carbon film of 20 to 50 nm is formed on the array substrate thus arranged in the vacuum layer. Next, 4- (N, N-bis (p-methylphenyl) amino) -α-phenylstilbene was added as a hole injection layer to 0.3
A film thickness of about 5 nm is formed at a vapor deposition rate of nm / sec.

As the hole transport layer, N, N'-bis (4 '
-Diphenylamino-4-biphenylyl) -N, N'-
Diphenylbenzidine (Hodogaya Chemical Co., Ltd.),
4-N, N-diphenylamino-α-phenylstilbene was added to 0.3 nm / s and 0.01 nm / s, respectively.
Was co-deposited at a vapor deposition rate of to form a film thickness of about 80 nm. Tris (8-quinolinolato) as a light emitting layer (electron transport layer)
Aluminum (Dojindo Co., Ltd.) 0.3 nm / se
A film thickness of about 40 nm is formed at a vapor deposition rate of c.

Next, as an electron injection electrode, an AlLi alloy (manufactured by Kojundo Chemical Co., Ltd., Al / Li weight ratio 99/1) was used.
At a low temperature, only Li was formed at a vapor deposition rate of about 0.1 nm / sec to a film thickness of about 1 nm, and then the AlLi alloy was further heated to remove Li from the state of about 1 nm. It was formed to a film thickness of about 100 nm at a vapor deposition rate of 0.5 nm / s to form a laminated electron injection electrode.

In the organic thin film EL element thus produced, after leaking the inside of the vapor deposition tank with dry nitrogen, the sealing lid 41 made of Corning 7059 glass was sealed with the seal adhesive (sealant) 45 under the dry nitrogen atmosphere. (Made by Anelva Co., Ltd.
A display panel was pasted with a product name Super Back Sticker 953-7000). A desiccant 55 is placed in the space between the sealing lid 41 and the array substrate 49. this is,
This is because the organic EL film is weak against humidity. The desiccant 55 absorbs the water that permeates the sealant 45 and prevents the deterioration of the organic EL film 47.

In order to suppress the permeation of water from the sealant 45, it is a good measure to lengthen the path from the outside. Therefore, in the display panel of the present invention, fine irregularities 43 and 44 are formed in the peripheral portion of the display area. The convex portions 44 formed on the peripheral portion of the array substrate 49 are formed at least twice. Distance between protrusions (formation pitch)
Is preferably 100 μm or more and 500 μm or less, and the height of the protrusion is preferably 30 μm or more and 300 μm or less. This convex portion is formed by a stamper technique. This stamper technology applies the method adopted by Omron as a method for forming a microlens, the method used by Matsushita Electric as a method for forming a minute lens in a pickup lens of a CD, and the like.

On the other hand, the convex portion 43 is also formed on the sealing lid 41. The formation pitch of the convex portions 43 is the same as the formation pitch of the convex portions 44. In this way, by forming the convex portions 43 and 44 at the same formation pitch, the convex portions 44 just fit into the convex portions 43. Therefore, at the time of manufacturing the display panel, the sealing lid 4
There is no displacement between 1 and the array substrate 49. Convex part 4
A sealant 45 is placed between 3 and 44. Sealing agent 45
Protects the sealing lid 41 and the array substrate 49 from each other and prevents moisture from entering from the outside.

As the sealant 45, it is preferable to use a UV (ultraviolet) curing type acrylic resin. Further, it is preferable to use an acrylic resin having a fluorine group. Besides, an epoxy adhesive or pressure-sensitive adhesive may be used. It is preferable to use an adhesive or pressure-sensitive adhesive having a refractive index of 1.47 or more and 1.54 or less. Particularly, as the seal adhesive, it is preferable to add fine powder of titanium oxide, fine powder of silicon oxide or the like in a ratio of 65% or more and 95% or less by weight. The particle size of the fine powder is preferably 20 μm or more and 100 μm or less in average diameter. The larger the weight ratio of the fine powder, the higher the effect of suppressing the entry of humidity from the outside. However, if the amount is too large, bubbles and the like tend to enter, and the space becomes rather large and the sealing effect decreases.

The weight of the desiccant is preferably 0.04 g or more and 0.2 g or less per 10 mm length of the seal.
Especially, 0.06g or more per 10mm of seal length 0.1
It is desirable that the amount is 5 g or less. When the amount of the desiccant is too small, the effect of preventing moisture is small and the organic EL layer is deteriorated immediately. If it is too much, the desiccant will hinder the sealing,
A good seal cannot be made.

In FIG. 4, the glass lid 41 is used for sealing, but a film may be used as shown in FIG. For example, as a sealing film, a DLC (diamond-like
It is exemplified that a material obtained by vapor depositing carbon) is used.
This film has extremely poor water permeability (moisture proof). This film is used as the sealing film 74. Further, it goes without saying that a structure in which a DLC film or the like is directly vapor-deposited on the surface of the electrode 72 may be used. That is, it is sealed with a thin film. The thickness of the thin film is n
・ D (n is the refractive index of the thin film, and when multiple thin films are stacked, the total refractive index is calculated (n and d of each thin film are calculated)
And calculate. d is a film thickness of a thin film, and when a plurality of thin films are laminated, their refractive indexes are comprehensively calculated. )
However, it is preferable that the light emission main wavelength λ of the EL element 15 be equal to or less than. By satisfying this condition, the EL element 1
The light extraction efficiency from No. 5 is more than double that in the case of sealing with a glass substrate. Also, an alloy or mixture of aluminum and silver or a laminate may be formed.

As described above, without using the lid 41, the sealing film 7
The configuration of sealing with 4 is called thin film sealing. For thin film encapsulation in the case of taking out light from the substrate 49 side, after forming an EL film, an aluminum electrode to be a cathode is formed on the EL film. Next, a resin layer as a buffer layer is formed on this aluminum film. Examples of the buffer layer include organic materials such as acrylic and epoxy. Further, the film thickness is preferably 1 μm or more and 10 μm or less. More preferably, the film thickness is 2 μm or more and 6 μm or less. Sealing film 7 on this buffer film
4 is formed. Without the buffer film, the structure of the EL film collapses due to stress, causing streak-like defects. As described above, the sealing film 74 is formed of DLC (diamond-like carbon),
Alternatively, a layer structure of an electric field capacitor (a structure in which dielectric thin films and aluminum thin films are alternately deposited in multiple layers) is exemplified.

In the thin film encapsulation for extracting light from the EL layer side, the Ag film is formed on the EL film and then the Ag-Mg film serving as the cathode is formed on the EL film at 20 angstroms or more 300
It is formed with a film thickness of angstrom. On top of that, ITO
A transparent electrode is formed to reduce the resistance. Next, a resin layer as a buffer layer is formed on this electrode film. The sealing film 74 is formed on this buffer film.

Half of the light emitted from the organic EL layer 47 is
The light is reflected by the reflection film 46, transmitted through the array substrate 49, and emitted. However, the reflection film 46 reflects external light and causes reflection, which reduces the display contrast. To prevent this, the array substrate 49 has a λ / 4 plate 50 and a polarizing plate 54.
Are arranged. When the pixel is a reflective electrode, the light generated from the EL layer 47 is emitted upward. Therefore, it goes without saying that the phase plate 50 and the polarizing plate 54 are arranged on the light emitting side. The reflective pixel is obtained by forming the pixel electrode 48 with aluminum, chromium, silver, or the like. Further, by providing the convex portion (or the concave and convex portion) on the surface of the pixel electrode 48, the interface with the organic EL layer is widened, the light emitting area is increased, and the luminous efficiency is improved. The circularly polarizing plate is not necessary when a reflective film serving as a cathode (anode) is formed on the transparent electrode or the reflectance can be reduced to 30% or less. This is because the reflection is significantly reduced. In addition, light interference is reduced, which is desirable.

Further, the contrast of the organic EL panel can be improved by canceling the external light reflection realized by forming the two-layer thin film inside the display by optical interference. The cost can be reduced as compared with the case where the conventional circularly polarizing plate is used. Further, it is possible to solve the problems of diffuse reflection that the circularly polarizing plate has, the viewing angle dependence of the display color, and the film thickness dependence of the organic EL light emitting layer.

Between the substrate 49 and the polarizing plate (polarizing film) 54, one or a plurality of phase films (phase plate, phase rotating means, phase difference plate, phase difference film) are arranged. It is preferable to use polycarbonate as the phase film. The phase film generates a phase difference between the incident light and the emitted light and contributes to efficient light modulation.

In addition, as the phase film, an organic resin plate or an organic resin film of polyester resin, PVA resin, polysulfone resin, vinyl chloride resin, Zeonex resin, acrylic resin, polystyrene resin or the like may be used. Alternatively, crystals such as quartz may be used.
The phase difference of one phase plate is 50 nm or more in the uniaxial direction 350
The thickness is preferably not more than nm, more preferably not less than 80 nm and not more than 220 nm.

Needless to say, a circularly polarizing plate 74 (circularly polarizing film) in which a phase film and a polarizing plate are integrated as shown in FIG. 7 may be used.

The phase film 50 is preferably colored with a dye or a pigment so as to have a function as a filter.
In particular, organic EL has a poor red (R) purity. Therefore, the colored phase film 50 cuts a certain wavelength range to adjust the color temperature. The color filter is generally provided by a pigment dispersion type resin as a dyeing filter. The pigment absorbs light in a specific wavelength band and transmits light in the unabsorbed wavelength band.

As described above, a part or the whole of the phase film may be colored, or a part or the whole may have a diffusing function. You can also emboss the surface,
An antireflection film may be formed to prevent reflection.
In addition, it is preferable to form a light-shielding film or a light-absorbing film at a position that is not effective for image display or a position that does not hinder the display, thereby reducing the black level of the display image and exhibiting a contrast improving effect by preventing halation. Further, the microlenses may be formed in a semicylindrical shape or a matrix shape by forming irregularities on the surface of the phase film. The microlenses are arranged so as to correspond to one pixel electrode or pixels of three primary colors, respectively.

As described above, the color filter may have the function of the phase film. For example, the phase difference can be generated by rolling when forming the color filter or by causing the phase difference to occur in a certain direction by photopolymerization. Alternatively, the smoothing film 71 of FIG. 7 may be photopolymerized to have a phase difference. With this structure, it is not necessary to form or dispose the phase film outside the substrate, the structure of the display panel is simplified, and cost reduction can be expected. Needless to say, the above items may be applied to the polarizing plate.

A TAC film (triacetyl cellulose film) is most suitable as a main material constituting the polarizing plate (polarizing film) 54. This is because the TAC film has excellent optical properties, surface smoothness and processability. For the production of TAC film, it is optimal to produce it by the solution casting film forming technique.

The polarizing plate is exemplified by a resin film in which iodine or the like is added to polyvinyl alcohol (PVA) resin. The polarizing plates of the pair of polarization separation means perform polarization separation by absorbing a polarization component of the incident light in a direction different from the specific polarization axis direction, and therefore the light utilization efficiency is relatively poor. Therefore, a polarized component of the incident light in a direction different from the specific polarization axis direction (reflective polarization)
er: a reflective polarizer that reflects polarized light to separate polarized light may be used. According to this structure, the light utilization efficiency is increased by the reflective polarizer, and a brighter display can be performed as compared with the above example using the polarizing plate.

In addition to such a polarizing plate and a reflective polarizer, as the polarized light separating means of the present invention, for example, a combination of a cholesteric liquid crystal layer and a (1/4) λ plate, the Brewster angle is used. Then, it is also possible to use one that separates the reflected polarized light and the transmitted polarized light, one that uses a hologram, and a polarized beam splitter (PBS).

Although not shown in FIG. 4, an AIR coat is applied to the surface of the polarizing plate 54. The AIR coat is exemplified by a structure formed of a dielectric single layer film or a multilayer film. In addition, a resin having a low refractive index of 1.35 to 1.45 may be applied. For example, a fluorinated acrylic resin is exemplified. In particular, those having a refractive index of 1.37 or more and 1.42 or less have good characteristics.

The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide wavelength band of visible light, and this is called multicoat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band, and this is called a V coat. The multi coat and the V coat are used properly according to the use of the display panel. The number of layers is not limited to two or more, and one layer may be used.

In the case of multi-coating, aluminum oxide (Al2O3) having an optical film thickness of nd = λ / 4, zirconium (ZrO2) having nd1 = λ / 2, and magnesium fluoride (MgF2) having nd1 = λ / 4 are laminated. To form. Usually, a thin film is formed with λ of 520 nm or a value in the vicinity thereof. In the case of V coat, silicon monoxide (S
iO) is an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF2) is nd1 = λ / 4, or yttrium oxide (Y2O3) and magnesium fluoride (MgF2).
Are formed by stacking n d1 = λ / 4. Since SiO has an absorption band on the blue side, Y2O3 is used to modulate blue light.
It is better to use. In addition, due to the stability of the substance, Y2O3
Is preferable because it is more stable. Alternatively, a SiO2 thin film may be used. Of course, the AIR coat may be made by using a resin having a low refractive index. For example, acrylic resin such as fluorine is exemplified. It is preferable to use an ultraviolet curing type of these.

In order to prevent the display panel from being charged with static electricity, it is preferable to apply a hydrophilic resin to the surface of the display panel or the like. In addition, in order to prevent surface reflection, the surface of the polarizing plate 54 may be embossed.

Although the TFT is connected to the pixel electrode 48, it is not limited to this. The active matrix means a thin film transistor (TFT) as a switching element, a diode type (TFD), a varistor, a thyristor, a ring diode, a photo diode, a photo transistor, an FET, a MOS transistor,
It goes without saying that a PLZT element or the like may be used. That is, any one of the switch element 11 and the drive element 11 can be used.

Further, it is preferable that the TFT adopts an LDD (low doping drain) structure. In addition, T
FT generally means all elements such as FETs that perform transistor operations such as switching. Further, it goes without saying that the structure of the EL film, the panel structure and the like can be applied to the simple matrix type display panel. In addition, in this specification, an organic EL element (OEL, PEL,
PLED, OLED) 15 will be described as an example, but the present invention is not limited to this, and needless to say, it is also applied to an inorganic EL element.

First, the active matrix method used for the organic EL display panel is as follows. To be able to select specific pixels and be given the necessary display information. It is necessary to satisfy the two conditions that a current can be passed through the EL element during 2 and 1 frame periods.

In order to satisfy these two conditions, FIG.
In the conventional organic EL device configuration shown in FIG.
1a is a switching transistor for selecting a pixel, and the second TFT 11b is a driving transistor for supplying a current to the EL element (EL film) 15.

Compared with the active matrix system used for liquid crystal, the switching transistor 11a is also required for liquid crystal, but the driving transistor 11b is necessary for lighting the EL element 15.
The reason for this is that in the case of liquid crystal, the ON state can be maintained by applying a voltage, but in the case of the EL element 15,
This is because the lighting state of the pixel 16 cannot be maintained unless current is continuously supplied.

Therefore, in the EL display panel, the transistor 11b must be kept on in order to keep the current flowing. First, when both the scanning line and the data line are turned on, charges are accumulated in the capacitor 19 through the switching transistor 11a. This capacitor 1
Since 9 continues to apply a voltage to the gate of the driving transistor 11b, even if the switching transistor 11a is turned off, current continues to flow from the current supply line 20 and the pixel 16 can be turned on for one frame period.

When displaying gradations using this configuration,
It is necessary to apply a voltage according to the gradation as the gate voltage of the driving transistor 11b. Therefore, the variation in the on-current of the driving transistor 11b appears on the display as it is.

The on-current of a transistor is extremely uniform if it is a transistor formed of a single crystal, but the formation temperature at which it can be formed on an inexpensive glass substrate is 45.
In the low temperature polycrystalline transistor formed by the low temperature poly-silicon technique of 0 degrees or less, the variation in the threshold value is ± 0.2V to
Since there is variation in the range of 0.5 V, the on-current flowing through the driving transistor 11b varies correspondingly, and display unevenness occurs. These irregularities occur not only in the variation of the threshold voltage but also in the mobility of the TFT and the thickness of the gate insulating film. The characteristics also change due to deterioration of the TFT 11.

Therefore, in the method of displaying gray scales in an analog manner, it is necessary to strictly control the characteristics of the device in order to obtain a uniform display. In the current low temperature polycrystal polysilicon TFT, this variation is within a predetermined range. I can't satisfy the specifications to keep within. In order to solve this problem, four transistors are provided in one pixel, and the variation in threshold voltage is compensated by a capacitor to obtain a uniform current. A constant current circuit is formed for each pixel to make the current uniform. It is possible to consider a method of achieving this.

However, in these methods, since the programmed current is programmed through the EL element 15, the transistor controlling the drive current becomes the source follower for the switching transistor connected to the power supply line when the current path changes. The drive margin becomes narrow. Therefore, there is a problem that the driving voltage becomes high.

Further, it is necessary to use the switching transistor connected to the power source in the region of low impedance, and there is also a problem that this operating range is affected by the characteristic variation of the EL element 15. In addition, when the kink current occurs in the voltage-current characteristics in the saturation region, or when the threshold voltage of the transistor changes, the stored current value also changes.

In the EL device structure of the present invention, in order to solve the above problems, even if the transistor 11 for controlling the current flowing through the EL device 15 does not have the source follower configuration and the transistor has a kink current, the kink current It is possible to minimize the influence of the above and reduce the fluctuation of the stored current value.

The EL device structure of the present invention is specifically shown in FIG.
As shown in (a), the unit pixel is formed by a plurality of transistors 11 each including at least four and an EL element.
Note that the pixel electrode is formed so as to overlap with the source signal line. That is, an insulating film or a flattening film made of an acrylic material is formed on the source signal line 18 for insulation, and a pixel electrode is formed on this insulating film. In this way, the source signal line 1
High aperture (HA) with a structure in which pixel electrodes are stacked on top of 8
Call it the structure.

First gate signal line (first scanning line) 17
First transistor (TFT or switching element) by activating a (applying ON voltage)
The second transistor 11b is connected to the first transistor 11b and the third transistor (TFT or switching element) 11c so that a current value to be passed through the EL element 15 is caused to flow and the gate and drain of the first transistor are short-circuited. The gate signal line 17a is opened by being activated (applying an ON voltage), and at the same time, the current value is passed through a capacitor (capacitor, storage capacitance) 19 connected between the gate and source of the first transistor 11a. The gate voltage (or drain voltage) of the first transistor 11a is stored.

Note that the source-gate capacitance (capacitor) 19 of the first transistor 11a is preferably 0.2 pF or more. As another configuration, a configuration in which the capacitor 19 is separately formed is also exemplified. That is, the storage capacitor is formed from the capacitor electrode layer, the gate insulating film, and the gate metal. From the viewpoint of preventing a decrease in luminance due to the leakage of the M3 transistor 11c and stabilizing the display operation, it is preferable to separately configure the capacitor in this way. The size of the capacitor (storage capacity) 19 is preferably 0.2 pF or more and 2 pF or less, and particularly the capacitor (storage capacity) 1
The size of 9 is preferably 0.4 pF or more and 1.2 pF or less.

It is preferable that the capacitor 19 is generally formed in the non-display area between adjacent pixels. Generally, when forming a full-color organic EL, since the organic EL layer is formed by mask vapor deposition using a metal mask, the formation position of the EL layer occurs due to the mask position shift. When the position shift occurs, there is a risk that the organic EL layers of the respective colors overlap.
Therefore, the non-display area between adjacent pixels of each color is 10μ.
You have to leave This portion does not contribute to light emission. Therefore, forming the storage capacitor 19 in this region is an effective means for improving the aperture ratio.

The metal mask 2881 is made of a magnetic material, and the metal mask 2881 is formed from the back surface of the substrate 49 with a magnet.
Is attracted by magnetic force. Magnetic mask 2881
Adheres to the substrate without any gap. The matters regarding the above manufacturing method are also applied to the other manufacturing methods of the present invention.

Next, the first gate signal line 17a is made inactive (OFF voltage is applied), and the second gate signal line 17 is made.
b is made active, and the path through which the current flows is switched to the path including the fourth transistor 11d connected to the first transistor 11a and the EL element 15 and the EL element 15, and the stored current is stored in the EL element 15
It works like flowing to.

This circuit has four transistors 11 in one pixel, the gate of the first transistor M1 is connected to the source of the second transistor M2, and the second transistor and the third transistor M3 are connected. The gate of M2 is the first gate signal line 17a, and the drain of M2 is M
3 and the source of the fourth transistor M4, and the drain of M3 is connected to the source signal line 18. The gate of the transistor M4 is connected to the second gate signal line 17b, and the drain of the transistor M4 is E
It is connected to the anode electrode of the L element 15.

Note that, in FIG. 1, all TFTFs are constructed by P channels. Although the P-channel has somewhat lower mobility than the N-channel TFT, it is preferable because it has a large withstand voltage and is less likely to deteriorate. However, the present invention is not limited to the configuration of the EL device including P channels. You may comprise only N channels (refer FIG. 42, FIG. 43, FIG. 67 etc.). Also, N
It may be configured using both channels and P channels.

It is preferable that the third and fourth transistors have the same polarity and are N-channel, and the first and second transistors are P-channel. In general, P-channel transistors have characteristics such as higher reliability and less kink current than N-channel transistors, and for EL elements that obtain the desired emission intensity by controlling the current, The effect of making the first transistor 11a P-channel is large.

The EL element structure of the present invention will be described below with reference to FIG. The EL element structure of the present invention is controlled by two timings. The first timing is a timing for storing a necessary current value. When the TFT 11b and the TFT 11c are turned on at this timing, an equivalent circuit is shown in FIG. here,
A predetermined current I1 is written from the signal line. As a result, the TFT 11a is in a state in which the gate and the drain are connected, and the current I1 is passed through the TFT 11a and the TFT 11c.
Flows. Therefore, the gate-source voltage of the TFT 11a becomes the voltage V1 at which I1 flows.

The second timing is the TFT 11a and the TFT.
11c is closed and TFT 11d is opened,
The equivalent circuit at that time is shown in FIG. TFT11
The voltage V1 between the source and gate of a remains held. In this case, since the transistor 11a of M1 always operates in the saturation region, the current of I1 is constant.

The gate of the transistor 11a and the gate of the transistor 11c are connected to the same gate signal line 11a. However, the gate of the transistor 11a and the gate of the transistor 11c have different gate signal lines 1
1 (SA1 and SA2 can be controlled separately). That is, the gate signal line for one pixel is 3
It becomes a book (the structure of FIG. 1 is two). Transistor 1
By individually controlling the ON / OFF timing of the gate of 1a and the ON / OFF timing of the gate of the transistor 11c, E
It is possible to further reduce the variation in the current value of the L element 15.

The first gate signal line 17a and the second gate signal line 17b are commonly used, and the third and fourth transistors have different conductivity types (N channel and P channel).
Then, the driving circuit can be simplified and the aperture ratio of the pixel can be improved.

With this structure, the write path from the signal line is turned off in the operation timing of the present invention.
That is, when a predetermined current is stored, an accurate current value is not stored in the source-gate capacitance (capacitor) of M1 if there is a branch in the current flow path. TFT M3 and T
By making the FTM4s of different conductivity types, it is possible to turn on M4 after turning off M3 without fail at the timing of switching the scanning lines by controlling the threshold values of each other.

However, in this case, it is necessary to control the threshold values of each other accurately, and therefore the process needs to be careful. Although the circuit described above can be realized with at least four transistors, the transistor 11e (M5) is shown in FIG. 1 (b) for more accurate timing control or for reducing the Miller effect, as will be described later. The principle of operation is the same even if the total number of transistors is 4 or more by cascade connection. Thus transistor 1
With the configuration including 1e, the transistor M3
The current programmed through the EL element 1 is more accurate.
It becomes possible to flow to 5.

In the configuration of FIG. 1, it is further preferable that the current value Ids in the saturation region of the first transistor 11a satisfies the condition of the following equation. In the equation below, the value of λ is 0.06 or less between adjacent pixels 0.0
Satisfy one or more conditions.

Ids = k * (Vgs-Vth) ² (1+
Vds * λ) In the present invention, the operating range of the transistor 11a is limited to the saturation region, but in general, the transistor characteristics in the saturation region deviate from the ideal characteristics and are affected by the source-drain voltage. This effect is called the mirror effect.

Consider a case where a threshold shift of ΔVt occurs in each transistor 11a in adjacent pixels. In this case, the stored current values are the same. If the shift of the threshold value is ΔL, about ΔV × λ is about 1
This corresponds to the deviation of the current value of the EL element 15 due to the change in the threshold value of 1a. Therefore, the deviation of the current is x
In order to suppress the threshold value to less than or equal to (%), y is set to 0.
It can be seen that it must be 01 × x / y or less.

This permissible value changes depending on the brightness of the application. In the luminance region where the luminance is 100 cd / m ² to 1000 cd / m ² , if the variation amount is 2% or more, a person recognizes the varied boundary line. Therefore, it is necessary that the variation amount of the brightness (current amount) is within 2%. When the brightness is higher than 100 cd / cm ² , the brightness change amount of the adjacent pixels is 2% or more. When the EL display element of the present invention is used as a display for a mobile terminal, the required brightness is about 100 cd / m ² . When the pixel configuration of FIG. 1 was actually prototyped and the fluctuation of the threshold value was measured, it was found that the maximum value of the fluctuation of the threshold value was 0.3 V in the transistor 11a of the adjacent pixel. Therefore, λ must be 0.06 or less in order to suppress the fluctuation of the luminance within 2%. However, it need not be 0.01 or less. This is because humans cannot recognize the change. Further, in order to achieve this variation in the threshold, it is necessary to make the transistor size sufficiently large, which is unrealistic.

Further, it is preferable that the current value Ids in the saturation region of the first transistor 11a satisfies the following equation. The variation of λ is 5% or less and 1% or more between adjacent pixels.

Ids = k * (Vgs-Vth) ² (1+
Vds * λ) Even if there is no change in the threshold value between adjacent pixels, if there is a change in λ in the above formula, the value of the current flowing through the EL changes. To keep the fluctuation within ± 2%,
The variation of λ must be suppressed to ± 5%. However, however, it does not have to be 1% or less. This is because humans cannot recognize the change. Further, in order to achieve 1% or less, the transistor size needs to be considerably increased, which is unrealistic.

Further, according to experiments, array trial manufactures, and studies, the channel length of the first transistor 11a is 10 μm.
It is preferable that the thickness is 200 μm or less. More preferably, the channel length of the first transistor 11a is 1
The thickness is preferably 5 μm or more and 150 μm or less. This is considered to be because when the channel length L is lengthened, the grain boundaries included in the channel increase, and the electric field is relaxed, and the kink effect is suppressed to a low level.

Further, the transistor 11 forming the pixel
Is preferably formed of a polysilicon TFT formed by a laser recrystallization method (laser annealing), and the directions of the channels in all transistors are preferably the same as the laser irradiation direction.

The object of the invention of this patent is to propose a circuit configuration in which variations in transistor characteristics do not affect the display, and therefore four or more transistors are required. When the circuit constant is determined based on these transistor characteristics, it is difficult to obtain an appropriate circuit constant unless the four transistors have the same characteristics. When the channel direction is horizontal or vertical with respect to the long-axis direction of laser irradiation, the threshold and mobility of transistor characteristics are different. The degree of variation is the same in both cases. The mobility and the average value of the thresholds are different between the horizontal direction and the vertical direction. Therefore, it is desirable that the channel directions of all the transistors forming the pixel are the same.

Further, the capacitance value of the storage capacitor 19 is set to Cs, the second
When the off-state current value of the transistor 11b is Ioff, it is preferable to satisfy the following equation.

3 <Cs / Ioff <24 More preferably, it is preferable to satisfy the following formula.

6 <Cs / Ioff <18 By setting the off current of the transistor 11b to 5 pA or less, it is possible to suppress the change in the current value flowing through the EL to 2% or less. This is because when the leak current increases, the charge stored between the gate and the source (both ends of the capacitor) cannot be retained for one field in the voltage non-writing state. Therefore, the larger the storage capacity of the capacitor 19, the larger the allowable amount of off-current. By satisfying the above equation, the fluctuation of the current value between adjacent pixels can be reduced by 2
% Or less.

Further, it is preferable that the transistors forming the active matrix are formed of p-ch polysilicon thin film transistors, and the transistor 11b has a multi-gate structure having at least dual gates. Since the transistor 11b acts as a switch between the source and drain of the transistor 11a, it is turned on / off as much as possible.
High OFF ratio characteristics are required. Transistor 11b
A high ON / OFF ratio characteristic can be realized by adopting a multi-gate structure having a dual gate structure or more as the gate structure.

Further, it is preferable that the transistors forming the active matrix are formed of polysilicon thin film transistors, and the (channel width W) * (channel length L) of each transistor is set to 54 μm ² or less. There is a correlation between (channel width W) * (channel length L) and variations in transistor characteristics. The cause of the variation in transistor characteristics is largely due to the variation in energy due to laser irradiation. Therefore, in order to absorb this, the laser irradiation pitch (generally 10 and several μm) should be set as much as possible within the channel. A structure containing many is desirable. By setting the (channel width W) * (channel length L) of each transistor to 54 μm ² or less, it is possible to obtain a thin film transistor having uniform characteristics without variations due to laser irradiation. It should be noted that if the transistor size becomes too small, the characteristics will vary depending on the area. Therefore, the (channel width W) * (channel length L) of each transistor is set to be 9 μm ² or more. It is more preferable that the (channel width W) * (channel length L) of each transistor be 16 μm ² or more and 45 μm ² or less.

Further, it is preferable that the mobility fluctuation of the first transistor 11a in the adjacent unit pixel is 20% or less. Due to the lack of mobility, the charging capacity of the switching transistor deteriorates, and the gate-source capacitance of M1 cannot be charged by the time the necessary current value is passed. Therefore, by suppressing the variation in movement within 20%, it is possible to reduce the variation in luminance between pixels to the recognition limit or less.

In the above description, the pixel configuration has been described as the configuration of FIG. 1, but the above items are shown in FIG. 21, FIG. 43, FIG.
It can also be applied to the configuration shown in FIG. The pixel configuration shown in FIG. 21 and the like will be described below.

When setting the current flowing through the EL element 15, T
The signal current flowing in the FT11a is Iw, and as a result, the TFT11
The gate-source voltage generated in a is Vgs. At the time of writing, the gate of the TFT 11a is controlled by the TFT 11d.
Since the drains are short-circuited, the TFT 11a operates in the saturation region. Therefore, Iw is given by the following formula.

Iw = μ1 · Cox1 · W1 / L1 / 2 (Vgs−Vth1) ² (1) Here, Cox is the gate capacitance per unit area,
It is given by Cox = ε0 · εr / d. Vth is TFT
Threshold, μ is carrier mobility, W is channel width, L
Is the channel length, ε0 is the mobility of vacuum, εr is the relative dielectric constant of the gate insulating film, and d is the thickness of the gate insulating film.

When the current flowing through the EL element 15 is Idd, Idd is the TFT connected in series with the EL element 15.
The current level is controlled by 1b. In the present invention, since the gate-source voltage thereof matches Vgs of the equation (1), assuming that the TFT 1b operates in the saturation region,
The following formula holds.

Idrv = μ2 · Cox2 · W2 / L2 / 2 (Vgs-Vth2) ² (2) The condition for the insulated gate field effect thin film transistor (TFT) to operate in the saturation region is that Vds is drained.
The voltage between sources is generally given by the following formula.

| Vds |> | Vgs−Vth | (3) Since the TFT 11a and the TFT 11b are formed close to each other inside a small pixel, approximately μ1 = μ2 and Co
x1 = Cox2, and V is V unless otherwise devised.
It is considered that th1 = Vth2. Then, at this time, the following equations are easily derived from the equations (1) and (2).

Idrv / Iw = (W2 / L2) / (W1 / L1) (4) The point to be noted here is that the values of μ, Cox, and Vth in equations (1) and (2) are , Per pixel, per product,
Or it is usually different for each production lot,
Since Equation (4) does not include these parameters, Idr
This means that the value of v / Iw does not depend on these variations.

If W1 = W2 and L1 = L2 are designed, Idrv / Iw = 1, that is, Iw and Idrv have the same value. That is, the drive current Idd flowing through the EL element 15 is exactly the same as the signal current Iw regardless of the characteristic variation of the TFT.
The emission brightness of can be accurately controlled.

As described above, Vth of the conversion TFT 11a
1 and Vth2 of the driving TFT 11b are basically the same, so that when a cutoff level signal voltage is applied to the gates of both TFTs having a common potential, the TFTs
Both 11a and TFT 11b should be in a non-conducting state. However, in reality, Vth2 may be lower than Vth1 due to factors such as parameter variations within a pixel. At this time, the driving TFT 11
Since a subthreshold level leak current flows in b, the EL element 15 emits a slight amount of light. This slight light emission lowers the contrast of the screen and impairs the display characteristics.

In the present invention, particularly, the threshold voltage Vth2 of the driving TFT 11b is set so as not to become lower than the threshold voltage Vth1 of the corresponding conversion TFT 11a in the pixel. For example, if the gate length L2 of the TFT 11b is made longer than the gate length L1 of the TFT 11a, and Vth2 is Vth2 even if the process parameters of these thin film transistors change.
It should not be lower than 1. This makes it possible to suppress a minute current leak. The above items also apply to the relationship between the TFT 11a and the TFT 11d in FIG.

As shown in FIG. 21, in addition to the driving transistor TFT11b for controlling the driving current flowing through the light emitting element including the converting transistor TFT11a through which the signal current flows and the EL element 15, the first scanning line scanA (S).
Incorporating transistor TFT11c for connecting or disconnecting the pixel circuit and the data line data under the control of A),
Switching transistors TFT11d and TFT11 that short-circuit the gate and drain of the TFT 1111a during the writing period by controlling the second scanning line scanB (SB).
A capacitor C19 for holding the gate-source voltage of a after writing is completed and an EL element 15 as a light emitting element.
Etc. Therefore, since each pixel has two gate signal lines, the configuration, functions, operations, etc. of the entire specification of the present invention described with reference to FIGS. 1, 2, and 3 described above can be applied. .

In FIG. 21, the TFT 11c is an N channel MO.
The S (NMOS) and the other transistors are P-channel MOS (PMOS), but this is an example, and it is not always necessary. The capacity C is
One terminal thereof is connected to the gate of the TFT 11a and the other terminal is connected to Vdd (power supply potential).
Not limited to dd, any constant potential may be used. The cathode (cathode) of the EL element 15 is connected to the ground potential. Therefore, it goes without saying that the above items also apply to FIG.

The terminal voltage of the EL element 15 also changes with temperature. Usually, it is high when the temperature is low, and becomes low when the temperature is high. This tendency has a linear relationship. Therefore, the Vdd voltage depends on the external temperature (to be exact, E
It is preferable to adjust (by the temperature of the L element 15).
The temperature sensor detects the external temperature and the Vdd voltage is changed by feeding back the Vdd voltage generator. Vdd
The voltage is preferably changed by 2% or more and 8% or less with a change of 10 ° C. Above all, it is preferably 3% or more and 6% or less.

It should be noted that the Vdd voltage in FIG.
It is preferable to lower the off-voltage. Specifically, Vgh (gate off-voltage) is at least Vdd-.
Should be higher than 0.5 (V). If it is lower than this, off-leakage of the TFT occurs and the shot unevenness of the laser anneal becomes conspicuous. Also, Vdd + 4
Should be lower than (V). If it is too high, on the contrary, the amount of off leak increases. Therefore, the gate off voltage (Vgh in FIG. 1, that is, the voltage side close to the power supply voltage)
Is less than the power supply voltage (Vdd in FIG. 1) by -0.5.
It should be above (V) and below +4 (V). More preferably, the power supply voltage (Vdd in FIG. 1) is more than 0.
It should be above (V) and below +2 (V). That is, the off-voltage of the TFT applied to the gate signal line is set to be sufficiently off. If the TFT has n channels, Vg
l is the off voltage. Therefore, Vgl is set within the range of -4 (V) or more and 0.5 (V) or less with respect to the GND voltage. More preferably -2 (V) or more and 0 (V)
The following range is preferable.

The above items have been described with respect to the pixel configuration of the current program of FIG. 1, but the present invention is not limited to this, and it is needless to say that they can be applied to the pixel configurations of the voltage program of FIGS. 54, 67, 103 and the like. Yes. In addition,
Vt offset cancellation of voltage program is R,
It is preferable to compensate G and B individually.

The configuration of FIG. 21 has the scan lines scanA and scanS.
scan line drive circuit that sequentially selects canB, a data line drive circuit that includes a current source CS that generates a signal current Iw having a current level according to luminance information and sequentially supplies it to the data line data, and each scan line scanA, The plurality of pixels are provided at the intersections of scanB and each data line data, and include a current-driven EL element 15 that emits light when supplied with a drive current.

As a characteristic feature, the pixel configuration shown in FIG. 21 has a receiving portion for taking in the signal current Iw from the data line data when the scanning line scanA is selected, and a current level of the taken signal current Iw. A conversion unit that converts the voltage into a level and holds the level, and a drive current having a current level according to the held voltage level, the light emitting element OLED
5 (otherwise, it may be abbreviated as EL, OEL, PEL, PLED). Specifically, the receiving part is composed of a take-in transistor TFT11c.

The conversion section includes a conversion thin film transistor TFT1 having a gate, a source, a drain and a channel.
1a and a capacitor C connected to its gate.
The conversion thin film transistor TFT11a and the signal current Iw taken in by the receiving part are caused to flow in the channel to generate the converted voltage level in the gate, and the voltage level generated in the capacitor C19 is held.

Further, the conversion part includes a switching thin film transistor TFT11d inserted between the drain and the gate of the conversion thin film transistor TFT11a.
The switching thin film transistor TFT11d becomes conductive when converting the current level of the signal current Iw into a voltage level, electrically connects the drain and gate of the converting thin film transistor TFT11a, and generates a voltage level with the source as a reference at the gate of the TFT11a. Close. Also, the switching thin film transistor TFT11d is cut off when the voltage level is held in the capacitor C, and the conversion thin film transistor T11d is cut off.
The gate of FT11a and the capacitor C19 connected to this are T
Separate from the drain of FT11a.

Further, the driving unit includes a gate, a drain,
Driving thin film transistor T having source and channel
FT11b is included. Driving thin film transistor TF
Tb receives the voltage level held in the capacitor C19 at its gate and causes a drive current having a corresponding current level to flow through the EL element 15 through the channel. The gate of the conversion thin film transistor TFT11a and the gate of the driving thin film transistor TFT11b are directly connected to form a current mirror circuit, and the current level of the signal current Iw and the current level of the driving current have a proportional relationship.

The driving thin film transistor TFT11b operates in a saturation region, and a driving current corresponding to the difference between the voltage level applied to its gate and the threshold voltage is passed through the EL element 15.

The driving thin film transistor TFT11b is
The threshold voltage is set so as not to be lower than the threshold voltage of the corresponding conversion thin film transistor TFT11a in the pixel. Specifically, the TFT 11b has a gate length of T
It is set so as not to be shorter than the gate length of FT11A. Alternatively, the TFT 11b may be set so that its gate insulating film is not thinner than the corresponding gate insulating film of the TFT 11a in the pixel.

Alternatively, the TFT 11b may be set by adjusting the concentration of impurities implanted in its channel so that the threshold voltage does not become lower than the threshold voltage of the corresponding TFT 11a in the pixel. If the threshold voltages of the TFT 11a and the TFT 11b are set to be the same, and if a cutoff level signal voltage is applied to the gates of both commonly connected thin film transistors, both of the TFTs 11a and 11b should be turned off. Is. However, in reality, there is a slight variation in the process parameters within the pixel, and the threshold voltage of the TFT 11b may be lower than the threshold voltage of the TFT 11a.

At this time, a weak current of sub-threshold level flows through the driving TFT 11b even if the signal voltage is lower than the cutoff level, so that the EL element 15 slightly emits light and the contrast of the screen deteriorates. Therefore, the gate length of the TFT 11b is made longer than that of the TFT 11a. As a result, even if the process parameters of the thin film transistor vary within the pixel, the threshold voltage of the TFT 11b remains TF.
Make sure that it does not fall below the threshold voltage of T11a.

In the short channel effect region A having a relatively short gate length L, Vth rises as the gate length L increases.
On the other hand, in the suppression region B having a relatively large gate length L, Vth is almost constant regardless of the gate length L. By utilizing this characteristic, the gate length of the TFT 11b is made longer than that of the TFT 11a. For example, when the gate length of the TFT 11a is 7 μm, the gate length of the TFT 11b is 10 μm.
Set to about m.

The gate length of the TFT 11a may belong to the short channel effect region A, while the gate length of the TFT 11b may belong to the suppression region B. As a result, the TFT 11
It is possible to suppress the short channel effect in b and to suppress the threshold voltage reduction due to the change of the process parameter. As described above, it is possible to suppress the sub-threshold level leak current flowing in the TFT 11b, suppress the slight light emission of the EL element 15, and contribute to the improvement of contrast.

A method of driving the pixel circuit shown in FIG. 21 will be briefly described. First, at the time of writing, the first scanning line sca
The nA and the second scanning line scanB are brought into the selected state. When both scanning lines are selected, the current source CS is applied to the data line data.
By connecting with, the signal current Iw according to the luminance information flows through the TFT 11a. The current source CS is a variable current source controlled according to the brightness information. At this time, the TFT 11
Since the gate-drain of a is electrically short-circuited by the TFT 11d, the equation (3) holds, and the TFT 11a
Operates in the saturation region. Therefore, the voltage Vgs given by the equation (1) is generated between the gate and the source.

Next, scanA and scanB are brought into a non-selected state. Specifically, first, scanB is set to a low level to turn off the TFT 11d. This makes Vgs
Is held by the capacitor C19. Next, by setting scanA to a high level and turning it off, the pixel circuit and the data line data are electrically cut off, and thereafter, writing to another pixel can be performed via the data line data. . Here, the data output as the current level of the signal current by the current source CS needs to be valid at the time when scanB becomes unselected, but thereafter it is set to an arbitrary level (for example, write data of the next pixel). Good.

The TFT 11b has a gate and a source commonly connected to the TFT 11a, and both are formed close to the inside of a small pixel. Therefore, if the TFT 11b operates in the saturation region, the current flowing through the TFT 11b is (2 ), Which is the drive current Idd flowing through the EL element 15. In order to operate the TFT 11b in the saturation region, a sufficient power supply potential is set to Vd so that the formula (3) is still satisfied even if the voltage drop in the EL element 15 is taken into consideration.
It should be given to d.

Needless to say, TFTs 11e and 11f may be added as shown in FIG. 22 for the purpose of increasing the impedance as in the case of FIG. 1B. In this way, the TFTs 11e, 11
Better current drive can be realized by adding f. The other items have been described with reference to FIG.

A DC voltage was applied to the EL display element manufactured as described above with reference to FIGS.
It was continuously driven at a constant current density of m2. The EL structure is
7.0V, 200cd / cm2 green (Maximum emission wavelength λmax = 4
The emission of 60 nm) was confirmed. The blue light emitting portion has a brightness of 10
At 0 cd / cm 2, color coordinates are x = 0.129, y = 0.10.
5. The green light emitting part has a brightness of 200 cd / cm2 and a color coordinate of x.
= 0.340, y = 0.625, the red light emitting portion has a brightness of 1
At 00 cd / cm2, the color coordinates are x = 0.649, y = 0.3
38 emission colors were obtained.

Hereinafter, a display device, a display module, an information display device and a driving circuit and a driving method thereof, which are shown in FIGS. 1, 21, 43, 71 and 22, will be described.

In a full-color organic EL display panel, improvement of the aperture ratio is an important development issue. This is because increasing the aperture ratio increases the light use efficiency, which leads to higher brightness and longer life. In order to increase the aperture ratio, the area of the TFT that blocks the light from the organic EL layer may be reduced. Low temperature polycrystalline Si-TFT is 10-
Since it has 100 times the performance and high current supply capability, T
The size of FT can be made very small. Therefore, in the organic EL display panel, it is preferable to manufacture the pixel transistor and the peripheral drive circuit by the low temperature polysilicon technique. Of course, it may be formed by the amorphous silicon technique, but the pixel aperture ratio becomes considerably small.

By forming a driving circuit such as the gate driver 12 or the source driver 14 on the glass substrate 46, it is possible to reduce the resistance which is a particular problem in a current driven organic EL display panel. In addition to eliminating the connection resistance of TCP, the lead wire from the electrode is shortened by 2 to 3 mm and the wiring resistance is reduced as compared with the case of TCP connection.
Furthermore, there is an advantage that the process for TCP connection is eliminated and the material cost is reduced.

Next, the EL display panel or E of the present invention is used.
The L display device will be described. FIG. 2 is an explanatory diagram centering on the circuit of the EL display device. The pixels 16 are arranged or formed in a matrix. A source driver 14 that outputs a current for performing a current program of each pixel is connected to each pixel 16. At the output stage of the source driver 14, a current mirror circuit corresponding to the number of bits of the video signal is formed. For example, in the case of 64 gradations, 63 current mirror circuits are formed in each source signal line, and a desired current can be applied to the source signal line 18 by selecting the number of these current mirror circuits. Has been done.

The minimum output current of one current mirror circuit is set to 10 nA or more and 50 nA. In particular, the minimum output current of the current mirror circuit should be 15 nA or more and 35 nA. This is to ensure the accuracy of the transistors forming the current mirror circuit in the driver IC 14.

Further, a precharge or discharge circuit for forcibly releasing or charging the electric charge of the source signal line 18 is incorporated. It is preferable that the voltage (current) output value of the precharge or discharge circuit for forcibly discharging or charging the charge of the source signal line 18 can be set independently by R, G, and B. EL element 15
This is because the threshold value of is different for RGB.

It goes without saying that the pixel configuration, array configuration, panel configuration, etc. described above are applied to the configurations, methods, and devices described below. Further, it goes without saying that the pixel configuration, array configuration, panel configuration, etc. already described are applied to the configurations, methods, and devices described below.

It is known that the organic EL element has a large temperature dependence characteristic (temperature characteristic). In order to adjust the change in emission brightness due to this temperature characteristic, a non-linear element such as a thermistor or posistor that changes the output current is added to the current mirror circuit, and the change due to the temperature characteristic is adjusted with the thermistor etc. Create an electric current.

In this case, since it is uniquely determined by the EL material to be selected, it is often unnecessary to control the software such as a microcomputer. That is, the liquid crystal material may be fixed at a fixed shift amount or the like. What is important is that the temperature characteristics differ depending on the luminescent color material, and the luminescent color (R,
That is, it is necessary to perform optimum temperature compensation for each of G and B).

The temperature characteristics of the R, G and B EL elements must be within a certain range. It goes without saying that it is preferable that the R, G and B EL elements 15 have no temperature characteristics. At least the R, G, and B temperature characteristic directions should be the same direction or should not change. Also, the change is a change of 10 degrees Celsius for each color,
It is preferable to change it by 2% or more and 8% or less.
Above all, it is preferably 3% or more and 6% or less.

The temperature compensation may be performed by a microcomputer. The temperature of the EL display panel is measured by the temperature sensor, and the temperature is changed by a microcomputer (not shown) or the like. Further, at the time of switching, the reference current or the like may be automatically switched by microcomputer control or the like, or may be controlled so that a specific menu display can be displayed. Also,
It can be configured to be switchable using a mouse or the like.
Further, the display screen of the EL display device may be a touch panel, and a menu may be displayed to switch the display screen by pressing a specific portion.

In the present invention, the source driver is formed of a semiconductor silicon chip and is connected to the terminal of the source signal line 18 of the substrate 46 by the glass on chip (COG) technique.
Wiring for signal lines such as the source signal line 18 is made of metal such as chromium, aluminum, and silver. This is because a low resistance wiring can be obtained with a narrow wiring width. When the pixel is of a reflective type, the wiring is a material forming a reflective film of the pixel, and is preferably formed at the same time as the reflective film. This is because the process can be simplified.

The present invention is not limited to the COG technique, and the driver IC 14 described above may be mounted on the chip-on-film (COF) technique and connected to the signal line of the display panel. The drive IC is a power supply IC1
02 may be separately manufactured to have a three-chip configuration.

Also, TCF tape may be used. TC
Films for F tape are polyimide film and copper (C
u) The foil can be thermocompressed without the use of adhesives.
Attach Cu to polyimide film without using adhesive T
In addition to the above, for the CP tape film, there are a method in which molten polyimide is superposed on a Cu foil and cast molding, and a method in which Cu is plated or deposited on a metal film formed by sputtering on the polyimide film. Although any of these may be used, the method of using a TCP tape in which Cu is attached to a polyimide film without using an adhesive is most preferable. For a lead pitch of 30 μm or less, a Cu beam laminated plate that does not use an adhesive is used. Among the Cu beam laminates that do not use adhesive, the method of forming the Cu layer by plating or vapor deposition is
Since it is suitable for thinning the Cu layer, it is advantageous for miniaturizing the lead pitch.

On the other hand, the gate driver circuit 12 is formed by the low temperature polysilicon technique. That is, it is formed in the same process as the pixel TFT. This is because the internal structure is easier and the operating frequency is lower than that of the source driver 14. Therefore, it can be easily formed even if it is formed by the low-temperature poly-silicon technique, and a narrow frame can be realized. Of course, it goes without saying that the gate driver 12 may be formed of a silicon chip and mounted on the substrate 46 using COG technology or the like. Further, switching elements such as pixel TFTs, gate drivers, etc. may be formed by a high temperature polysilicon technique or may be formed by an organic material (organic TFT).

The gate driver 12 has a gate signal line 17a.
And a shift register 22b for the gate signal line 17b. Each shift register 22 has positive and negative phase clock signals (CLKxP, CLK).
xN) and start pulse (STx). In addition, it is preferable to add an enable (ENABL) signal that controls output and non-output of the gate signal line and an up-down (UPDWM) signal that vertically reverses the shift direction.
Besides, the start pulse is shifted to the shift register,
Then, it is preferable to provide an output terminal or the like for confirming that the data is being output. The shift timing of the shift register is controlled by a control signal from a control IC (not shown). In addition, it has a built-in level shift circuit that shifts the level of external data. It also has a built-in inspection circuit.

Since the buffer capacity of the shift register 22 is small, the gate signal line 17 cannot be directly driven. Therefore, at least two inverter circuits 23 are formed between the output of the shift register 22 and the output gate 24 that drives the gate signal line 17.

The same applies to the case where the source driver 14 is directly formed on the substrate 46 by a polysilicon technique such as low temperature polysilicon, and between the gate of an analog switch such as a transfer gate for driving the source signal line and the shift register of the source driver. A plurality of inverter circuits are formed.
The following items (the output of the shift register and the output stage that drives the signal line (the items related to the inverter circuit placed between the output stages such as the output gate or the transfer gate) are common to the source drive and gate drive circuits. For example, in FIG.
Although the output of 4 is directly connected to the source signal line 18, the output of the shift register of the source driver is actually connected to a multi-stage inverter circuit so that the output of the inverter is an analog such as a transfer gate. It is connected to the gate of the switch.

The inverter circuit 23 is a P-channel MO
It is composed of an S-transistor and an N-channel MOS transistor. As described above, the inverter circuit 23 is connected to the output terminal of the shift register circuit 22 of the gate driver circuit 12 in multiple stages, and the final output thereof is connected to the output gate 24. The inverter circuit 23 may be composed of only P channels. However, in this case, it may be configured as a simple gate circuit instead of the inverter.

The channel width of the P-channel or N-channel TFT constituting each inverter circuit 23 is W,
The channel length is L (when the width is more than double gate, the width or channel length of the channel to be added is added), the order of the inverter near the register is 1 and the order of the inverter near the display side is N (Nth stage). To do.

When the number of connected stages of the inverter circuit 23 is large, the characteristic difference of the connected inverters 23 is multiplexed (stacked), and a difference occurs in the transmission time from the shift register 22 to the output gate 24 (delay time variation). For example, in an extreme case, in FIG. 2, the output gate 24a is turned on (the output voltage is switched) after 1.0 μsec (starting counting after the pulse is output from the shift register), but the output gate 24a is turned on. 24b is 1.5 μsec
After that (after the pulse is output from the shift register and counting is started), the state of being on (the output voltage is switched) occurs.

Therefore, it is preferable that the number of inverter circuits 23 formed between the shift register 22 and the output gate 24 is small, but the gate width W of the channel of the TFT forming the output gate 24 is very large. Further, the gate drive capability of the output stage of the sist register 22 is small. Therefore, it is impossible to directly drive the output gate 24 by the gate circuit (NAND circuit or the like) that constitutes the shift register. Therefore, it is necessary to connect the inverters in multiple stages. For example, W4 / L4 of the inverter 23d in FIG.
If the ratio of (the channel width of the P channel / the channel length of the P channel) and the size of the W3 / L3 of the inverter 23c is large, the delay time becomes long and the characteristics of the inverter also vary greatly.

FIG. 3 shows the relationship between delay time variation (shown by the dotted line) and delay time ratio (shown by the solid line). The horizontal axis is (Wn-
It is shown as 1 / Ln-1) / (Wn / Ln). For example, in FIG. 2, the inverter 23d and the inverter 23c have the same L and 2W3.
= W4, (W3 / L3) / (W4 / L4) = 0.
It is 5. In the graph of FIG. 3, the delay time ratio is (Wn-1
/Ln-1)/(Wn/Ln)=0.5 is set to 1 and time variation is set to 1 as well as delay.

In FIG. 3, (Wn-1 / Ln-1) / (Wn / Ln)
It is shown that the larger the number of connected inverters 23, the greater the number of connected stages of the inverter 23 and the greater the variation in delay time. It shows that the delay time to the inverter 23 becomes long. From this graph, it is advantageous in design that the delay time ratio and the delay time variation are within 2. Therefore, it suffices to satisfy the condition of the following equation.

0.25 ≤ (Wn-1 / Ln-1) / (Wn /
Ln) ≤ 0.75 Further, the W / L ratio (W of the P channel of each inverter 23 (W
The p / Lp) and the n-channel W / L ratio (Ws / Ls) must satisfy the following relationship.

0.4 ≦ (Ws / Ls) / (Wp / Lp)
≦ 0.8 Furthermore, the inverter 2 formed between the output end of the shift register and the output gate (or transfer gate)
When the number of stages n of 3 satisfies the following equation, there is little variation in delay time and it is good.

3 ≤ n ≤ 8 Mobility μ also has a problem. If the mobility μn of the n-channel transistor is small, the sizes of the TG and the inverter are large, and the power consumption and the like are large. Also,
The driver formation area is increased. Therefore, the panel size becomes large. On the other hand, if it is large, the characteristics of the transistor are likely to deteriorate. Therefore, the mobility μn is preferably in the following range.

50 ≤ μn ≤ 150 The slew rate of the clock signal in the shift register 22 is set to 500 V / μsec or less. If the slew rate is high, the deterioration of the n-channel transistor is severe.

Although the inverter 23 is connected to the output of the shift register in multiple stages in FIG. 2, it may be a NAND circuit. This is because a NAND circuit can also form an inverter. That is, the connection stage number of the inverter 23 may be considered as the gate connection stage number. Also in this case, the relationship such as the W / L ratio explained so far is applied. Also,
The matters described with reference to FIGS. 2 and 3 above are shown in FIGS.
4, FIG. 84 and the like.

Further, in FIG. 2 and the like, when the pixel switching transistor is a P channel, the output from the final stage inverter has an ON voltage Vgl of the gate signal line 1
7, and the off voltage Vgh is applied to the gate signal line 17. Conversely, the pixel switching transistor is N
In case of channel, the output from the last inverter is
The off voltage Vgl is applied to the gate signal line 17, and the on voltage Vgh is applied to the gate signal line 17.

In the above embodiments, the gate driver is made at the same time as the pixel 16 by the high temperature polysilicon or the low temperature polysilicon technique, but the invention is not limited to this. For example, as shown in FIG. 26, the source driver IC 14 and the gate driver IC 12 made of semiconductor chips may be separately mounted on the display panel 82.

When the display panel 82 is used for an information display device such as a mobile phone, it is preferable to mount the driver ICs 14 and 15 on one side of the display panel as shown in FIG. A configuration in which the driver IC is mounted is called a three-side free configuration (structure), and conventionally, the gate driver IC 12 is mounted on the X side of the display area, and Y is used.
The source driver IC 14 was mounted on the side). This is because it is easy to design so that the center line of the screen 21 becomes the center of the display device, and also the mounting of the driver IC becomes easy. Note that the gate driver circuit may be formed in a structure with three sides free by high-temperature polysilicon or low-temperature polysilicon technology (that is, at least one of 14 and 12 in FIG. 26 is directly formed on the substrate 49 by polysilicon technology). Form).

The three-side free structure is not limited to the structure in which the ICs are directly mounted or formed on the substrate 49, and the IC1
It also includes a structure in which a film (TCP, TAB technology, etc.) to which 4, 12, etc. are attached is attached to one side (or almost one side) of the substrate 49. That is, it means a configuration, an arrangement or the like in which ICs are not mounted or attached on two sides.

When the gate driver 12 is arranged beside the source driver 14 as shown in FIG. 26, the gate signal line 17 must be formed along the side C and up to the screen display area 21 (see FIG. 27 etc.). .

The pitch of the gate signal lines 17 formed on the C side is 5 μm or more and 12 μm or less. When the thickness is less than 5 μm, noise is added to the adjacent gate signal line due to the influence of parasitic capacitance. According to the experiment, the effect of the parasitic capacitance remarkably occurs at 7 μm or less. Further, if it is less than 5 μm, image noise such as beats is intensely generated on the display screen. In particular, the generation of noise differs between the left and right of the screen, and it is difficult to reduce this image noise such as beats. Also, reduction of 12 μm
If it exceeds, the frame width D of the display panel becomes too large to be practical.

In order to reduce the above-mentioned image noise, in the lower layer or upper layer of the portion where the gate signal line 17 is formed,
This can be reduced by arranging a grant pattern (a conductive pattern in which the voltage is fixed to a constant voltage or is set to a stable potential as a whole). Further, a separately provided shield plate (shield foil (conducting pattern in which voltage is fixed to a constant voltage or set to a stable potential as a whole)) may be arranged on the gate signal line 17.

The gate signal line 17 on the C side in FIG. 26 is made of ITO.
Although it may be formed of an electrode, it is preferably formed by stacking ITO and a metal thin film in order to reduce the resistance. Also,
It is preferably formed of a metal film. In the case of stacking with ITO, a titanium film is formed on ITO, and aluminum or an aluminum-molybdenum alloy thin film is formed thereon. Alternatively, a chrome film is formed on ITO. In the case of a metal film, it is formed of an aluminum thin film or a chromium thin film. The above matters also apply to other embodiments of the present invention.

Note that, in FIG. 27 and the like, the wiring 17 and the like are arranged on one side of the display area, but the invention is not limited to this and may be arranged on both sides. For example, by arranging (forming) the gate signal line 17a on the right side of the display area 21,
The gate signal line 17b may be arranged (formed) on the left side of the display area 21. The above matters are the same in other embodiments.

In FIG. 30, the source driver IC 14 and the gate driver IC 12 are integrated into one chip (one-chip driver IC 14a). With one chip, only one IC chip needs to be mounted on the display panel 82. Therefore,
The mounting cost can also be reduced. 1-chip driver IC
Various voltages used within can also be generated at the same time.

The source driver IC 14, the gate driver IC 12, and the one-chip driver IC 14a are made of a semiconductor wafer such as silicon and mounted on the display panel 82, but the present invention is not limited to this. Display panel 8 by silicon technology
It goes without saying that it may be directly formed on the second layer.

In FIG. 28, the gate driver ICs 12a and 15b are mounted (or formed) on both ends of the source driver IC 14, but the present invention is not limited to this. For example, as shown in FIG. 26, the source driver I
One gate driver IC on one side adjacent to C14
12 may be arranged. Note that, in FIG. 26 and the like, a thick solid line portion indicates a portion where the gate signal lines 17 are formed in parallel. Therefore, the gate signal lines 17 corresponding to the number of scanning signal lines are formed in parallel in the portion b (the lower portion of the screen), and the gate signal line 17 is formed in the portion a (the upper portion of the screen).
Is formed.

When two gate drivers 12a and 12b are used as shown in FIG. 28, the number of gate signal lines 17a formed in parallel with the side C of FIG. 28 is ½ of the number of scanning lines.
(1/2 of the number of gate signal lines can be arranged on the left and right of the screen). Therefore, it goes without saying that there is a feature that the frame is even on the left and right of the screen.

The present invention relates to the scanning direction of the gate signal line 17,
There is also a feature in screen division. For example, in FIG. 28, the gate driver 12a is connected to the gate signal line 17b at the top of the screen. Further, the gate driver 12b is connected to the gate signal line 17a at the bottom of the screen. Gate signal line 1
The scanning direction of 7 is also from the upper part to the lower part of the screen as shown by arrow A. The source signal line 18 is common to the upper part of the screen and the lower part of the screen.

In FIG. 29, the gate driver 12a is connected differently from the adjacent gate signal line 17 at the top of the screen. The gate driver 12a is connected to the odd-numbered gate signal line b. The gate driver 12b is connected to the even-numbered gate signal lines 17a. Regarding the scanning direction of the gate signal line, the gate signal line 17b is from the upper part to the lower part of the screen (arrow A). Gate signal line 17a
Is from the bottom to the top of the screen (arrow B). By connecting the gate signal line 17 to the gate driver IC 12 in this way and by setting the scanning method of the gate signal line in a predetermined direction, no luminance inclination occurs on the screen 21 and flicker is also suppressed. be able to.

The source signal line 18 is common to the upper part of the screen and the lower part of the screen. However, it goes without saying that the screen may be divided at the top and bottom. The above items also apply to other embodiments.

In FIG. 30, the gate driver 12a is connected to the gate signal line 17b at the top of the screen. Further, the gate driver 12b is connected to the gate signal line 17a at the bottom of the screen. The scanning direction of the gate signal line 17b is arrow A.
The direction is from the top of the screen to the bottom as shown in. The scanning direction of the gate signal line 17a is from the bottom to the top of the screen as shown by arrow B. The source signal line 18 is common to the upper part of the screen and the lower part of the screen. By connecting the gate signal line 17 to the gate driver IC 12 in this way and by setting the scanning method of the gate signal line in a predetermined direction, no luminance inclination occurs on the screen 21 and flicker is also suppressed. be able to.

Further, in FIG. 30, the source driver IC1
4 and the gate driver IC 12 are integrated into one chip (one chip driver IC 14a). With one chip, only one IC chip needs to be mounted on the display panel 82. Therefore, the mounting cost can be reduced. Further, various voltages used in the one-chip driver IC can be generated at the same time. The one-chip driver IC 14a is made of a semiconductor wafer such as silicon and mounted on the display panel 82. However, the invention is not limited to this. The one-chip driver IC 14a may be directly formed on the display panel 82 by a low temperature polysilicon technique or a high temperature polysilicon technique. Needless to say. In addition, a driver IC that drives the upper part of the screen is arranged on the upper side of the display screen,
It goes without saying that the driver IC that drives the lower part of the screen may be arranged on the lower side of the display screen (that is, the mounting I
C has 2 chips). The above items also apply to other embodiments of the present invention.

In FIGS. 28 and 30, the screen is divided at the central portion, but the present invention is not limited to this. For example, in the case of FIG. 28, the display screen 21a may be made smaller and the display screen 21b may be made larger. Display screen 21
Let a be a partial display area (see FIG. 110). The partial display area mainly displays time and date.
The partial display area is used in the low power consumption mode. 28 and 30, the display area 21a is displayed by the gate signal line 17b, and the display area 2 is displayed by the gate signal line 17a.
Display 1b.

Also, in FIG. 110 and the like, as shown in FIG. 111, the display area 21a has a structure with three sides free,
The display area 21b may be configured such that the conventional source driver 14 and the gate driver 12 are arranged on separate sides.
That is, the gate signal line 17a and the source signal line 18a are 1
It is output from the chip driver IC 14a.

Further, as shown in FIG. 114, the display area 21 may be divided into two areas 21a and 21b, and the source driver IC 14 and the gate driver 12 corresponding to each area may be arranged. In FIG. 114, the writing time of the video signal output from each source driver 14 is twice as long as that of the other embodiments, so that the signal can be sufficiently written in the pixel. Further, as shown in FIG. 113, one display area 21 may be provided, and one source driver IC 14 may be arranged above and below the screen. This can be similarly applied to the gate driver IC 12.

In the above embodiment, the gate signal lines 17 are formed in parallel and are wired up to the pixel region.
It is needless to say that the present invention is not limited to this, and the source signal line 18 may be wired in parallel to one side as shown in FIG.

In FIGS. 110, 111, 114, etc., it is possible to reduce the power consumption by changing the frame rate (driving frequency or the number of screen rewritings per unit time (1 second)) in the display areas 21a and 21b. It is an effective means. Further, changing the number of display colors or the display colors in the display areas 21a and 21b is also effective in reducing power consumption.

In the structure shown in FIG. 1, the cathode of the EL element 15 is connected to the Vs1 potential. However, there is a problem in that the driving voltage of the organic EL that constitutes each color is different. For example, 0.01 per square centimeter
When the current of (A) is passed, the terminal voltage of the EL element is 5 (V) in blue (B), but is 9 (V) in green (G) and red (R). That is, the terminal voltage differs between B, G, and R. Therefore, in B, G, and R, the source-drain voltage (SD voltage) of the transistor 11c11d held by
Is different. Therefore, the off-leakage current between the source-drain voltage (SD voltage) of the transistor is different for each color. When an off-leakage current is generated and the off-leakage characteristics are different for each color, flicker occurs in a state where the color balance is deviated, and the gamma characteristic shifts in correlation with the emission color, resulting in a complicated display state.

In order to address this problem, the present invention is shown in FIG.
As shown in, at least one of R, G, and B colors is
The potential of one cathode electrode is different from the potential of another color cathode electrode. Specifically, in FIG.
B is the cathode electrode 53a, and G and R are the cathode electrode 5
3b. Note that, although FIG. 5 assumes lower extraction for extracting light from the glass surface, it may also be upper extraction. In this case, the cathode and the anode may be reversed.

It goes without saying that it is preferable that the terminal voltages of the R, G, and B EL elements 15 are made to match as much as possible. At least the white peak brightness is displayed and the color temperature is 60
EL of R, G, B in the range from 00K to 9000K
It is necessary to select the material or structure so that the terminal voltage of the device is 10 (V) or less. Further, among R, G, and B, the difference between the maximum terminal voltage and the minimum terminal voltage of the EL element needs to be within 2.5 (V). More preferably, it should be 1.5 (V) or less. Although the colors are RGB in the above embodiments, the colors are not limited to these. This will be explained later.

It is also necessary to correct color unevenness. This is caused by variations in film thickness and characteristics because EL materials of different colors are applied separately. To correct this, white raster display is performed at a luminance of 30% and 70%, and the in-plane distribution of each color in the display area 21 is measured. The in-plane distribution is measured at least every 30 pixels. The measurement data is stored in a table composed of a memory, and the stored data is used to correct the input image data and display it on the display screen 21.

Note that the pixels are the three primary colors of R, G, and B, but the present invention is not limited to this, and three colors of cyan, yellow, and magenta may be used. Also, two colors of B and yellow may be used. Of course, it may be a single color. Further, six colors of R, G, B, cyan, yellow and magenta may be used. R, G,
Five colors of B, cyan and magenta may be used. These are natural colors with a wide color reproduction range and good display. In addition, four colors of R, G, B, and white may be used. R,
Seven colors of G, B, cyan, yellow, magenta, black, and white may be used. Alternatively, white emission pixels may be formed (produced) in the entire display region 21 and a three primary color display may be performed using a color filter such as RGB. In this case, light emitting materials of respective colors may be stacked on the EL layer. Alternatively, one pixel may be painted separately such as B and yellow. As described above, the EL of the present invention
The display device is not limited to one that performs color display with the three primary colors of RGB.

There are mainly three methods for colorizing the organic EL display panel, and the color conversion method is one of them.
It is only necessary to form a single layer of blue as the light emitting layer, and the remaining green and red required for full colorization are created by color conversion from blue light. Therefore, there are advantages that it is not necessary to separately paint each layer of RGB, and it is not necessary to prepare organic EL materials of each color of RGB. The color conversion method does not reduce the yield unlike the color-coding method. The EL panel and the like of the present invention are applicable in any of these systems.

Also, as shown in FIG. 168, pixels 16W that emit white light in addition to the three primary colors may be formed. The white light emitting pixel 16W can be realized by manufacturing (forming or configuring) by stacking R, G, and B light emitting structures. One set of pixels is composed of three primary colors of RGB and a pixel 16W that emits white light. By forming the pixels that emit white light, the white peak luminance can be easily expressed. Therefore, it is possible to realize a bright image display.

Even when one set of pixels of three primary colors such as RGB is formed, it is preferable that the area of the pixel electrode of each color be different as shown in FIG. Of course, the same area may be used as long as the luminous efficiency of each color is well balanced and the color purity is well balanced. However, if the balance of one or more colors is poor, it is preferable to adjust the pixel electrode (light emitting area). The electrode area for each color may be determined based on the current density. In other words, the color temperature is 6000K
When the white balance is adjusted in the range of (Kelvin) or more and 9000K or less, the difference between the current densities of the respective colors should be within ± 30%. It is more preferably within ± 15%. For example, if the current density is 100 A / square meter, all three primary colors should be 70 A / square meter or more and 130 A / square meter or less. More preferably, all three primary colors are set to 85 A / square meter or more and 115 A / square meter or less.

Further, as shown in FIG. 170, it is preferable to arrange the adjacent three pixel rows so that the arrangement of the three primary colors is different. For example, even-numbered rows are R, G, B from the left.
In this arrangement, the odd-numbered rows have B, G, and R arrangements.
By arranging in this way, the resolution in the diagonal direction of the image is improved even with a small number of pixels. Further, the first row is the arrangement of R, G, B, R, G, B from the left, the second row is the arrangement of G, B, R, G, B, R, and the third row is B, R,
In order to arrange G, B, R, and G, in three or more pixel rows,
The pixel arrangement may be different.

The cathode electrode 53a is formed by using a metal mask technique in which organic ELs of different colors are separately applied. The metal mask is used because the organic EL is weak in water and cannot be etched. Using a metal mask (not shown), the cathode electrode 53a is vapor-deposited, and at the same time, the contact hole 52a is connected. The contact hole 52a can be electrically connected to the B cathode wiring 51a.

Similarly, the cathode electrode 53b is also formed by using a metal mask technique in which organic EL of each color is separately applied.
Using a metal mask (not shown), the cathode electrode 53
b is vapor-deposited, and at the same time, connection is made at the contact hole 52b. RG cathode wiring 5 through the contact hole 52b
An electrical connection can be made with 1b. The cathode electrode may be formed to have an aluminum film thickness of 70 nm or more and 200 nm or less.

With the above structure, different voltages can be applied to the cathode electrodes 51a and 51b. Therefore, even if the Vdd voltage in FIG.
The voltage applied to at least one color EL can be changed. In FIG. 5, the same cathode electrode 53b is used for RG, but the present invention is not limited to this, and R and G may be different cathode electrodes.

With the above structure, it is possible to prevent the off-leakage current between the source-drain voltage (SD voltage) of the transistor and the kink phenomenon for each color. Therefore, flicker does not occur, the gamma characteristic does not shift in correlation with the emission color, and good image display can be realized.

Also, let Vs1 in FIG. 1 be the cathode voltage,
The cathode voltage is set to be different for each color, but the present invention is not limited to this, and it goes without saying that the anode voltage Vdd may be set to be different for each color.
For example, the Vdd of the R pixel is set to 8 (V), G is set to 6 (V), and B is set to 10 (V). It is preferable that these anode voltage and cathode voltage can be adjusted within a range of ± 1 (V).

Even if the panel size is about 2 inches,
A current of nearly 100 mA is output from the anode connected to Vdd. Therefore, it is essential to reduce the resistance of the anode wiring 20 (current supply line). In order to cope with this problem, in the present invention, the anode 63 wiring is supplied from the upper side and the lower side of the display area as shown in FIG. 6 (power supply at both ends). By supplying power to both ends as described above, the occurrence of a brightness gradient at the top and bottom of the screen is eliminated.

In order to increase the emission brightness, the pixel 48 may be roughened. This structure is shown in FIG. First, fine unevenness is formed in a place where the pixel electrode 48 is formed by using a stamper technique. When the pixel is a reflection type, a pixel electrode 48 is formed by forming a metal thin film of aluminum having a thickness of about 200 nm by a sputtering method. A convex portion is provided at a position where the pixel electrode 48 is in contact with the organic EL and is roughened. In the case of a simple matrix type display panel, the image electrode 48 has a striped electrode shape. Further, the convex portion is not limited to the convex shape and may be a concave shape. Moreover, you may form a concave and a convex simultaneously.

The size of the protrusions is about 4 μm and the average value of the distance between adjacent portions is 10 μm, 20 μm, 40 μm, and the unit area density of the protrusions is 1000 to 120 μm.
0 / square millimeter, 100 to 120 / mm
The luminance was measured at 2,600 to 800 pieces / square millimeter. Then, it was found that the larger the unit area density of the protrusions, the stronger the emission brightness. Therefore, it was found that by changing the unit area density of the protrusions on the pixel electrode 48, the surface state of the pixel electrode can be changed to adjust the emission brightness. According to the examination, good results could be obtained when the unit area density of the protrusions was 800 / square millimeter or less and 100 / square millimeter or less.

The organic EL is a self-luminous element. When the light generated by this light emission enters a TFT as a switching element, a photoconductor phenomenon (photocon) occurs. The photocon refers to a phenomenon in which a leak (off leak) when a switching element such as a TFT is turned off increases due to photoexcitation.

In order to cope with this problem, the present invention is shown in FIG.
As shown in FIG. 5, a light shielding film 91 under the gate driver 12 (source driver 14 in some cases) and under the pixel transistor 11 is formed. The light-shielding film 91 is formed of a metal thin film such as chromium and has a film thickness of 50 nm or more and 150 n or less.
m or less. If the film thickness is thin, the light-shielding effect is poor, and if it is thick, irregularities occur and patterning of the upper TFT 11A1 becomes difficult.

A smoothing film 71a made of an inorganic material having a thickness of 20 to 100 nm is formed on the light shielding film 91. One layer of the storage capacitor 19 may be formed using the layer of the light shielding film 91. In this case, it is preferable that the smoothing film 71a be made as thin as possible to increase the capacitance value of the storage capacitor. Alternatively, the light shielding film 91 may be formed of aluminum, a silicon oxide film may be formed on the surface of the light shielding film 91 by using an anodic oxidation technique, and this silicon oxide film may be used as the dielectric film of the storage capacitor 19. A pixel electrode having a high aperture (HA) structure is formed on the smoothing film 71b.

The driver circuit 12 and the like are not limited to the back surface,
Ingress of light from the surface should also be suppressed. This is because a malfunction occurs due to the influence of photo control. Therefore, in the present invention, when the cathode electrode is a metal film, the cathode electrode is also formed on the surface of the driver 12 or the like, and this electrode is used as a light shielding film.

However, when the cathode electrode is formed on the driver 12, there is a possibility that the electric field from the cathode electrode may cause a malfunction of the driver or an electrical contact between the cathode electrode and the driver circuit. In order to cope with this problem, in the present invention, at least one layer, preferably a plurality of layers of organic EL film is formed on the driver circuit 12 and the like at the same time when the organic EL film is formed on the pixel electrode.

Since the organic EL film is basically an insulator,
By forming the organic EL film on the driver, the cathode and the driver are isolated from each other. Therefore, the above-mentioned problem can be solved.

If a short circuit occurs between terminals of one or more TFTs 11 of a pixel or between a TFT 11 and a signal line, the EL element 15
May always be a bright spot that lights up. Since these bright spots are visually unnoticeable, it is necessary to turn them into black dots (not lit). For the bright spot, the corresponding pixel 16 is detected and the capacitor 19
Irradiate a laser beam on to short-circuit between the terminals of the capacitor. Therefore, the electric charge cannot be retained in the capacitor 19, so that the TFT 11a can stop the flow of current.

It should be noted that the position corresponds to the position where laser light is emitted. It is desirable to remove the cathode film. This is to prevent a short circuit between the terminal electrode of the capacitor 19 and the cathode film due to laser irradiation.

The structure shown in FIG. 175 is also illustrated. FIG. 175 shows an example of a lower extraction structure for extracting light from the glass substrate 49 side. Also in FIG. 175, the light shielding film below the gate driver 12 (source driver 14 in some cases) and below the pixel transistor 11 is formed. The light-shielding film is formed of a metal thin film such as chromium and has a film thickness of 50 nm or more and 150 nm or less. If the film thickness is thin, the light-shielding effect is poor, and if it is thick, unevenness occurs and the upper TFT1
Patterning of 1A1 becomes difficult.

The TFT 11 and the driver circuit 1 are provided on the light-shielding film.
2 (14) is formed. The driver circuit 12 (14) and the like should prevent light from entering not only from the back surface but also from the front surface. This is because a malfunction occurs due to the influence of photo control.
Therefore, in the present invention, the cathode electrode 46 is used as a light shielding film.

However, if the cathode electrode is formed on the driver 12 (14), the electric field from the cathode electrode may cause the driver to malfunction or the cathode electrode and the driver circuit to electrically contact with each other. In order to cope with this problem, in the present invention, at least one layer, preferably a plurality of layers of organic EL film is formed on the driver circuit 12 and the like at the same time when the organic EL film is formed on the pixel electrode.

On the other hand, when the cathode (or anode) electrode is a transparent electrode, the pixel electrode is of a reflection type, and the common electrode is a transparent electrode (ITO, IZO, etc.), which is a light extraction structure (light is extracted from the glass substrate 49 side). In the case of the lower extraction and the upper extraction of extracting light from the EL film deposition surface), the sheet resistance value of the transparent electrode becomes a problem. Although the transparent electrode has a high resistance, it is necessary to pass a current with a high current density to the cathode of the organic EL. Therefore, if the cathode electrode is formed of a single layer of the ITO film, heat is generated due to heat generation, or an extreme brightness gradient occurs on the display screen.

In order to address this problem, the resistance lowering wiring 92 made of a metal thin film is formed on the surface of the cathode electrode. The low resistance wiring 92 has the same structure as the black matrix (BM) of the liquid crystal display panel (film thickness of 50 nm to 200 nm made of chromium or aluminum material), and at the same position (between the pixel electrodes, on the driver 12, etc.). is there. However, in the organic EL, it is not necessary to form the BM, so that the function is completely different. The low resistance wiring 92 is not limited to the front surface of the transparent electrode 72, but may be formed on the back surface (the surface in contact with the organic EL film). As the BM-shaped metal film, an alloy such as Mg.Ag, Mg.Li, or Al.Li or a laminated structure such as aluminum, magnesium, indium, copper, or an alloy of each may be used. In addition, in order to prevent corrosion and the like on the BM, ITO and IZO films are further stacked, and SiNx and SiO2 are also stacked.
An inorganic thin film such as or an organic thin film such as polyimide is formed.

When light is to be extracted from the vapor deposition surface of the EL film (upper extraction), Mg-on the organic EL film 47 is used.
It is preferable to form an Al film and then form an ITO or IZO film thereon. In addition, Mg-Al on the organic EL film 47
It is preferable to form a film and form a black matrix (black matrix such as a liquid crystal display panel) on the film. This black matrix is chrome, A
l, Ag, Au, Cu, etc., and SiO
2. It is preferable to form a protective film made of an inorganic insulating film such as SiNx or an organic insulating film such as polyester or acrylic. Further, an antireflection film (AIR
Coat).

The AIR coat has a three-layer structure or a two-layer structure. Aluminum oxide (Al2
O3) has an optical film thickness of nd = λ / 4 and zirconium (Zr
O2) is nd1 = λ / 2, magnesium fluoride (MgF
2) is formed by stacking nd1 = λ / 4. Usually, a thin film is formed with λ of 520 nm or a value in the vicinity thereof.

In the case of a two-layer structure, silicon monoxide (Si
O) is an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF2) is nd1 = λ / 4, or yttrium oxide (Y2O3) and magnesium fluoride (MgF2) are nd1.
= Λ / 4 stacked layers.

For a single layer, magnesium fluoride (Mg
F2) is formed by stacking nd1 = λ / 2.

Even in the case of the bottom extraction, it is effective to increase the transmittance of the metal film of the cathode electrode 46. Even if the display image is viewed from the substrate 49 side,
This is because the high transmissivity of the metal film 46 reduces the reflection. If the reflection is reduced, the circularly polarizing plate 74 becomes unnecessary. Therefore, the light extraction efficiency may be improved as compared with the upper extraction. The transmittance of the metal film 46 is 60%
It is preferably not less than 90%. In particular, it is preferably 70% or more and 90% or less. If it is 60% or less, the sheet resistance value of the cathode electrode becomes low. However, the reflection becomes large. On the contrary, when it is 90% or more, the sheet resistance value of the cathode electrode becomes high. Therefore, the brightness gradient of the display image becomes large.

To increase the transmittance of the metal film 46, the Al film is thinly formed. The thickness is 20 nm or more and 100 nm or less. It is preferable to form an ITO or IZO film on it. Further, it is preferable to form a black matrix on the Al film 46. This black matrix is formed of chromium, Al, Ag, Au, Cu or the like, and a protective film 176 made of an inorganic insulating film such as SiO2 or SiNx, or an organic insulating film such as polyester or acrylic is formed on the black matrix.
1 is preferably formed. Furthermore, this protective film 17
It is preferable to form an antireflection film (AIR coat) on 61.

As shown in FIG. 176, the pixel electrode 48
The circular arc shape increases the light emitting area of the EL film 47. Therefore, the current density is reduced and the life of the EL element 47 can be extended. Moreover, since the terminal voltage of the EL element 15 is also reduced, the power efficiency is improved.

In FIG. 176, the smoothing film 71 is formed in an arc shape, and a contact hole for making contact with the drain terminal of the TFT 11 is formed in this arc shape smoothing film. The transparent electrode 48 made of ITO is electrically connected to the drain terminal through this contact hole.

50 nm or more and 150 nm on the pixel electrode 48
The following carbon film is vapor-deposited thinly, and the EL film 47 is formed thereon. The EL film 47 is separately applied on the entire surface in the case of a single color and by using a metal mask in the case of RGB (FIG. 177).
(See (f)).

After forming the EL film 47, an Al film 46 to be a cathode electrode is formed (FIG. 177 (g)). Furthermore, A
A protective film 1761 is formed on the I film 46 (FIG. 177).
(H)).

The EL film 47 or the pixel electrode 48 is
The shape is not limited to the arc shape, but may be a triangular pyramid shape, a conical shape, a sine curve shape, or a structure in which these are combined. In addition, a minute arc on one pixel, triangular pyramid shape,
A conical shape, a sine curve shape, a combination of these shapes, or random irregularities may be formed. Further, although it is a convex arc shape in FIG. 176, it may be a concave arc shape. The above matters may be in the shape of a triangular pyramid, the shape of a cone, the shape of a sine curve, or the structure in which these are combined.

FIG. 177 is an explanatory diagram of a method of manufacturing the EL display panel described in FIG. As illustrated in FIG. 177 (a), the TFT 11, the gate driver circuit 12 and the like are formed on the array substrate 49.

Next, as shown in FIG. 177 (b), a smoothing film 71 made of an organic material such as acrylic resin is applied on the substrate 49. The smoothing film 71 may be an inorganic material such as SOG. The film thickness is 1.5 μm or more and 3 μm
The following is preferable. Next, a mask 1771 is formed on the smoothing film 71. The mask 1771 is formed of a metal material, and its formation position corresponds to the pixel 16.
Next, etching is performed. The etching may be either wet etching or dry etching such as O2 plasma. The smoothing film 71 is etched from between the masks 1771. Therefore, as shown in FIG. 1771 (c), the smoothing film 71 has an arc shape.

Further, as shown in FIG. 177 (d), a mask (not shown) is formed on the smoothing film 71 to form a contact hole 1772. Alternatively, FIG.
Contact hole 1772 is formed in the etching process of FIG.
Is also formed at the same time.

Next, as shown in FIG. 177 (e), I
The pixel electrode 48 is formed of a transparent electrode such as TO or IZO. The pixel electrode 48 and the TFT 11 are connected by the pixel contact portion 1751. This contact hole is ITO
The transparent electrode 48 and the drain terminal are electrically connected.

50 nm or more and 150 nm on the pixel electrode 48
The following carbon film is vapor-deposited thinly, and the EL film 47 is formed thereon. The EL film 47 is separately applied on the entire surface in the case of a single color and by using a metal mask in the case of RGB (FIG. 177).
(See (f)). After forming the EL film 47, an Al film 46 to be a cathode electrode is formed (FIG. 177 (g)). further,
A protective film 1761 is formed on the Al film 46 (FIG. 177).
(H)).

To increase the transmittance of the metal film 46, the Al film 46 is formed thin. The thickness is 20 nm or more and 100 nm or less. It is preferable to form an ITO or IZO film on it. Further, it is preferable to form a black matrix on the Al film 46. This black matrix is made of chromium, Al, Ag, Au, Cu, etc.,
On top of this, a protective film 1 made of an inorganic insulating film such as SiO2 or SiNx and an organic insulating film such as polyester or acrylic
It is preferable to form 761. Further, it is preferable to form an antireflection film (AIR coat) on the protective film 1761. The minimum film thickness of the protective film 1761 is 1
It should be at least μm.

The protective film 1761 may be a protective layer using a film. For example, as the protective layer, it is exemplified to use a film of an electrolytic capacitor on which DLC (diamond-like carbon) is vapor-deposited. This film has extremely poor water permeability (moisture proof). This film is used as the protective layer 1761.

The film thickness of the protective layer 1761 is calculated by n · d (n is the refractive index of a thin film, and when a plurality of thin films are laminated, the refractive indices thereof are totaled (the n / d of each thin film is calculated). D is a film thickness of a thin film, and when a plurality of thin films are laminated, the refractive index thereof is comprehensively calculated.) It is preferable that the light emission main wavelength λ of the EL element 15 is equal to or less than that.

FIG. 178 shows a panelized construction (cross-sectional view).
Is. Although the same applies to other drawings, in the present specification, each drawing is omitted or / and enlarged or reduced for easy understanding and / or drawing. Also in the cross-sectional view of the display panel of FIG. 178, the smoothing film 71 and the like are shown sufficiently thick. However, the thickness of the substrate 49 is also very thin. Further, TFTs and the like are omitted in the drawing.

In FIG. 178, the sealing plate 41 and the substrate 4
A spacer 1781 is arranged between the nine plates so that the protective film 1761 or the reflective film 46 or the EL film 47 and the sealing plate 41 are not in direct contact with each other. The desiccant is arranged or filled in the peripheral portion of the display area. A cylindrical or spherical spacer is used. Height is 10 μm
It is preferably 100 μm or less. Further, the protective film 1761 can be processed to serve as a spacer. That is, a part or the whole of the protective film 1761 is processed or formed into a projection shape, a pillar shape, or a stripe shape so that the protection film 1761 has a function of a spacer. In addition,
A configuration in which the spacer 1781 is used as a desiccant is also preferable.

The pixels shown in FIG. 21 are the TFT 11b and the TFT.
11a is a current mirror relationship. Characteristics of the current mirror relationship between 11b and 11a (threshold values Vt, S
Value, mobility μ, etc.) must match. Needless to say, it is preferable that the TFTs in the pixel of FIG. 1 have the same characteristics.

The semiconductor film forming the TFT 11 of the pixel 16 is generally formed by laser annealing in the low temperature polysilicon technique. This laser animation
The variations in the conditions of the above-mentioned conditions cause variations in the characteristics of the TFT 11. However, if the characteristics of the TFTs 11 in one pixel 16 are the same, a predetermined current may flow through the EL element 15 in the method of performing current programming shown in FIGS. 1, 21, 22, 43, and 71. Can be driven to. This is an advantage over voltage programming.

To address this problem, in the present invention, as shown in FIG. 23, the laser irradiation spot 23 at the time of annealing is irradiated in parallel to the source signal line 18. Further, the laser irradiation spot 23 is moved so as to coincide with one pixel column. Of course, the number of pixels is not limited to one pixel row, and for example, RGB in FIG. 23 may be irradiated with a laser in units of one pixel 16 (in this case, three pixel rows).

In particular, the pixel is made up of three RGB pixels and has a square shape. Therefore, R, G,
Each pixel of B has a vertically long pixel shape. Therefore, pixel 1
The TFTs 11 formed in 6 are arranged in the vertical direction as shown in FIG. 23 (TFTs 11a, 11).
b). Therefore, when the laser irradiation spot 23 is vertically elongated and annealed, the TFT 11 is formed within one pixel.
It is possible to prevent the characteristic variations of the above from occurring.

Generally, the length of the laser irradiation spot 23 is a fixed value such as 10 inches. Since this laser irradiation spot 23 is moved, it is necessary to arrange the panel so that one laser irradiation spot 23 is placed within the movable range (that is, the laser irradiation spot 23 is located at the center of the display area 21 of the panel). Do not overlap).

In the structure shown in FIG. 24, three panels are vertically arranged within the length of the laser irradiation spot 23. The annealing device that irradiates the laser irradiation spot 23 recognizes the positioning markers 242a and 24ab on the glass substrate 241 and recognizes the laser irradiation spot 2.
Move 3 The recognition of the positioning marker 242 is performed by the pattern recognition device. An anneal device (not shown) recognizes the positioning marker 242 and determines the position of the pixel row. Then, the laser irradiation spot 23 is irradiated so as to exactly overlap the pixel row position, and annealing is sequentially performed.

The laser annealing described with reference to FIGS. 23 and 24.
It is preferable that the method (method of irradiating a linear laser spot in parallel with the source signal line 18) is particularly adopted in the current program method of the organic EL panel. This is because the characteristics of the TFT 11 match in the direction parallel to the source signal line (pixel TFTs that are vertically adjacent to each other).
Are similar in characteristics). Therefore, the change in the voltage level of the source signal line is small during current driving, and insufficient current writing is less likely to occur (for example, in the case of white raster display, the currents flowing to the TFTs 11a of adjacent pixels are almost the same, so the source driver The change in the amplitude of the current output from the IC 14 is small).

Further, it is possible to realize uniform image display (because display unevenness is not likely to occur mainly due to variations in TFT characteristics) by the method of simultaneously writing a plurality of pixel rows described with reference to FIGS. 87 and 88. . In FIG. 87 and the like, since a plurality of pixel rows are selected at the same time, if the TFTs of adjacent pixels are uniform, the TFT characteristic unevenness in the vertical direction will be
Can be absorbed by 4.

As shown in FIG. 1, the gate signal line 17a is rendered conductive during the row selection period (here, the transistor 1 of FIG.
Since 1 is a p-channel transistor, it becomes conductive at a low level), and the gate signal line 17b becomes conductive during the non-selection period.

When the current value for gradation 1 is applied and the row selection period is operated for 75 μs when the source signal line is in the gradation 0 display state, as shown in FIG. 55 (a). When the parasitic capacitance of the source signal line 18 increases, the EL element 1
The current value output to 5 decreases.

FIG. 55B shows the case where the current value for gradation 1 is made to flow ten times as much as that in FIG.
The decrease rate of the current value output to the EL element 15 becomes smaller with respect to the increase of the parasitic capacitance of.

Since a variation of about 10% with respect to the predetermined current value cannot be observed as a difference in brightness for human eyes, if the reduction of about 10% is allowed, the allowable source capacitance is 2 pF or less in (a), 8 25pF in (b)
It is the following.

The time t required to change the current value of the source signal line 18 is t = C · V, where C is the size of the stray capacitance, V is the voltage of the source signal line, and I is the current flowing through the source signal line.
Since / I, the current value can be increased ten times, and the time required to change the current value can be shortened to nearly one tenth.
Alternatively, it indicates that the current value can be changed to a predetermined current value even if the source capacitance is increased 10 times. Therefore, it is effective to increase the current value in order to write a predetermined current value within a short horizontal scanning period.

If the input current is multiplied by 10, the output current is also increased by 10.
Since the brightness of EL becomes 10 times, the conductive period of the transistor 17d in FIG. 1 is set to 1/10 and the light emission period is set to 1/10 of the conventional one in order to obtain a predetermined brightness. Displayed the brightness.

That is, the parasitic capacitance of the source signal line 18 is sufficiently charged and discharged, and the predetermined current value is set to the TFT1 of the pixel 16.
To program 1a, source driver 14
It is necessary to output a relatively large current from the. But,
When such a large current is passed through the source signal line 18, this current value is programmed in the pixel, and a large current flows through the EL element 15 with respect to a predetermined current. For example, 1
If programming is performed with a current of 0 times, naturally, a current of 10 times flows through the EL element 15, and the EL element 15 emits light with a brightness of 10 times. In order to obtain a predetermined emission brightness, the EL element 15
It suffices to reduce the time for flowing to 1/10. By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained.

A ten times larger current value is applied to the pixel TFT 11.
It is assumed that the ON time of the EL element 15 is set to 1/10 by writing in a (correctly, the terminal voltage of the capacitor 19 is set), but this is an example. In some cases, 10
A double current value may be written in the TFT 11a of the pixel, and the ON time of the EL element 15 may be reduced to 1/5. On the contrary, there may be a case where a 10 times larger current value is written in the pixel TFT 11a to double the ON time of the EL element 15. The present invention is
It is characterized in that the write current to the pixel is set to a value other than a predetermined value and the current flowing in the EL element 15 is driven in an intermittent state. In this specification, for ease of explanation, it is assumed that an N times larger current value is written in the TFT 11 of the pixel and the ON time of the EL element 15 is made 1 / N times larger. However, the present invention is not limited to this, and the N1 times the current value is applied to the pixel TF.
Write to T11 and set the ON time of EL element 15 to 1 / N2
It goes without saying that it may be doubled (different from N1 and N2). The intermittent intervals are not limited to equal intervals. For example, it may be random (as a whole, the display period or the non-display period has a predetermined value (constant rate)). Further, it may be different for RGB. That is,
For optimal white balance, R, G,
The B display period or the non-display period may be adjusted (set) to be a predetermined value (constant rate).

Also, for ease of explanation, 1 / N is 1
It is assumed that 1F is set to 1 / N based on F (1 field or 1 frame). However, when one pixel row is selected and the current value is programmed (typically 1
There is a horizontal scanning period (1H), and an error occurs depending on the scanning state. Therefore, the above explanation is only a matter of convenience for facilitating the explanation,
It is not limited to this.

Another problem is that the organic (inorganic) EL display device is basically different in display method from a display such as a CRT which displays an image as a set of line displays by an electron gun. That is, the EL display device holds the current (voltage) written in the pixel for a period of 1F (one field or one frame). Therefore, when a moving image is displayed, the problem occurs that the outline of the displayed image is blurred.

In the present invention, E only during the period of 1 F / N
A current is passed through the L element 15 for another period (1F (N-1)
/ N) does not pass an electric current. Consider the case where this driving method is implemented and one point on the screen is observed. In this display state, image data display and black display (non-lighting) are repeatedly displayed for each 1F. That is, the image data display state becomes a temporally intermittent display (intermittent display) state. When the moving image data display is viewed in this intermittent display state, the outline of the image is not blurred and a good display state can be realized. That is, it is possible to realize moving image display close to that of a CRT. Although the intermittent display is realized, the main clock of the circuit is the same as the conventional one. Therefore, the power consumption of the circuit does not increase.

In the case of a liquid crystal display panel, image data (voltage) for light modulation is held in the liquid crystal layer. Therefore,
In order to perform black insertion display, it is necessary to rewrite the data applied to the liquid crystal layer. Therefore, it is necessary to increase the operation clock of the source driver IC 14 and apply the image data and the black display data to the source signal line 18 alternately. Therefore, black insertion (intermittent display such as black display)
In order to realize, it is necessary to raise the main clock of the circuit. Also, an image memory for performing the time axis expansion is required.

FIGS. 1, 43, 44, 53, 54,
In the pixel configuration of the EL display panel of the present invention shown in FIGS. 67 to 78 and the like, image data is held in the capacitor 19. A current corresponding to the terminal voltage of the capacitor 19 is passed through the EL element 15. Therefore, the image data is not held in the light modulation layer like the liquid crystal display panel.

In the present invention, the current flowing through the EL element 15 is controlled only by turning on / off the switching TFT 11d or TFT 11e. That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is still held in the capacitor 19. Therefore, at the next timing, the switching element 11d etc. is turned on, and the EL
If a current is passed through the element 15, the current that flows is the same as the value of the current that was flowing before. In the present invention, when black insertion (intermittent display such as black display) is to be realized, it is not necessary to raise the main clock of the circuit. Also, an image memory is unnecessary because it is not necessary to perform time-axis expansion. In addition, the organic EL element 15 has a short time from applying a current to emitting light and has a high-speed response. Therefore, it is suitable for displaying moving images, and by implementing intermittent display, it is possible to solve the problem of displaying moving images, which is a problem of conventional data-holding type display panels (liquid crystal display panels, EL panels, etc.).

For example, as shown in FIG. 33, the gate signal line 17b has a conventional conduction period of 1F (normal programming time is 1H when the current programming time is 0), and the number of pixel rows of the EL display device is at least 100 rows. Since the above is the case, the error is 1% or less even with 1F), and N = 1.
If 0 is set, according to FIG. 55, it is possible to change from gradation 0 to gradation 1, which takes the longest time to change, to gradation 1 in about 75 μsec if the source capacitance is about 20 pF. This indicates that an EL display device of about 2 type can be driven at a frame frequency of 60 Hz.

In the case of a large-sized display device having a large source capacitance, the source current may be increased 10 times or more.
Generally, when the source current value is multiplied by N, the gate signal line 1
The conduction period of 7b (TFT 11d) may be 1 F / N. As a result, it can be applied to display devices for televisions and monitors.

A more detailed description will be given below with reference to the drawings. First, the parasitic capacitance 404 in FIG. 1 is generated by the coupling capacitance between the source signal lines, the buffer output capacitance of the drive IC 14, the cross capacitance between the gate signal line 17 and the source signal line 18, and the like. This capacitance 404 is usually 10 pF
That is all. In the case of voltage driving, since a voltage is applied to the source signal line 18 from the driver IV14 with low impedance, there is no problem in driving even if the parasitic capacitance is somewhat large.

However, in the current drive, particularly in the image display of the black level, the pixel capacitor 19 is supplied with a minute current of 5 nA or less.
Need to be programmed. Therefore, the parasitic capacitance 4
When 04 occurs with a magnitude equal to or larger than a predetermined value, it is not limited to within 1H (usually within 1H, but since 2 pixel rows may be written at the same time, it is within 1H). The parasitic capacitance cannot be charged or discharged. If charging / discharging cannot be performed in the 1H period, writing to the pixel becomes insufficient, and the resolution is not at all.

In the case of the pixel configuration of FIG. 1, as shown in FIG. 13A, the program current I1 flows through the source signal line 18 during current programming. This current I1 is the TFT 11
V1 of the capacitor 19 is set (programmed) so that the current flowing through a and flowing through I1 is retained. At this time, the TFT 11d is in the open state (off state).

Next, the TFT 11 operates as shown in FIG. 13B during the period in which the current flows through the EL element 15. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and T
The FTs 11a and 11c are turned off. On the other hand, the gate signal line 1
An on-voltage (Vgl) is applied to 7b, and the TFT 11d is turned on.

Now, assuming that the current I1 is N times the current (predetermined value) originally flowing, the current flowing through the EL element 15 in FIG. 13B is also I1. Therefore, the EL element 15 emits light with a brightness 10 times the predetermined value.

Therefore, the TFT 11d is turned on for a period of 1 / N of the originally on time (about 1F) and the other period (N
If it is turned off during the -1) / N period, the average brightness of the entire 1F becomes a predetermined brightness. This display state is similar to that of a CRT scanning the screen with an electron gun. The difference is that 1 / N of the entire screen (where the entire screen is 1) lights up in the range where the image is displayed (in the CRT, the range where the light is illuminated is 1 pixel row (strictly speaking). Is 1 pixel).

In the present invention, this 1 / N image display area moves from the top to the bottom of the screen 21 as shown in FIG. 31 (a1). In the present invention, the current flows through the EL element 15 only during the period of 1F / N, and the other period (1F · (N−1) / N)
Does not flow current. Therefore, the image is displayed intermittently. However, since the image is held by the afterimage in human eyes, the entire screen appears to be displayed uniformly.

In this display state, image data display and black display (non-lighting) are repeatedly displayed for each 1F. That is,
The image data display state becomes a temporally intermittent display (intermittent display) state. In the liquid crystal display panel (EL display panel other than the present invention), data is held in the pixel for the period of 1F, and therefore, in the case of moving image display, even if the image data changes, the change cannot be followed, The image was blurred (outlined image). However, in the present invention, since the image is displayed intermittently, the outline of the image is not blurred and a good display state can be realized. That is, it is possible to realize moving image display close to that of a CRT.

Further, in the EL display device, the black display is completely non-lighted, so that the contrast is not lowered unlike the case where the liquid crystal display panel is intermittently displayed. Further, as shown in FIG. 13, the intermittent display can be realized only by turning on / off the TFT 11d. This is because the image data is stored in the capacitor 19 (the number of gradations is infinite because it is an analog value). That is, for each pixel 16,
The image data is held for the period of 1F. Whether or not a current corresponding to the held image data is passed through the EL element 15 is realized by controlling the TFT 11d.

It is important to maintain the terminal voltage of the capacitor 19. This is because if the terminal voltage of the capacitor 19 changes (charges and discharges) in one field (frame) period, the screen brightness changes and flicker (such as flicker) occurs when the frame rate decreases. TFT 11a is 1
The current flowing through the EL element 15 during the frame (one field) period needs to be kept at least 65% or less. The 65% means that the pixel 16 is written, and EL
This means that, when the current flowing through the element 15 is 100% at the beginning, the current flowing through the EL element 15 immediately before writing to the pixel 16 in the next frame (field) is 65% or more.

Therefore, the number of TFTs 11 constituting one pixel does not change between the case where the intermittent display is realized and the case where it is not realized. That is, with the pixel configuration unchanged, the influence of the parasitic capacitance 404 of the source signal line 18 is eliminated to realize a good current program. In addition, a moving image display similar to a CRT is realized.

Since the operating clock of the gate driver circuit 12 is sufficiently slow as compared with the operating clock of the source driver circuit 14, the main clock of the circuit does not become high. Moreover, the value of N can be easily changed.

The image display direction (image writing direction) is shown in FIG.
As illustrated in FIG. 04, the first field may be in the downward direction from the screen (FIG. 104 (a)), and the second field may be in the downward direction from the screen to the upward direction (FIG. 104 (b)). That is, FIG. 104 (a) and FIG. 104 (b) are alternately repeated.

Further, as shown in FIG. 105, in the first field, the screen is directed from the top to the bottom (see FIG.
(A)), once the entire screen is black-displayed (non-displayed) 312 (FIG. 105 (b)), then the second field may be changed from the bottom to the top of the screen (FIG. 105 (c)). . Alternatively, the entire screen may be temporarily displayed in black (non-display) 312 (FIG. 105 (d)). That is, from FIG. 105 (a) to FIG.
The state of 05 (d) is alternately repeated.

In FIGS. 104 and 105, etc.
Although the screen writing method is set to be from top to bottom or bottom to top of the screen, it is not limited to this. The writing direction of the screen is constantly fixed from the top to the bottom of the screen or from the bottom to the top, and the operation direction of the non-display area 312 is from the top to the bottom of the screen in the first field and below the screen in the second field. It may be upward from. The above matters also apply to other embodiments of the present invention.

In FIG. 31 (a), the image display area 311 is
N, non-display area (non-lighting area, black display area) 312
Is set to (N-1) / N (however, this is the case of an ideal state. In reality, the capacitor 19 and the TFT 11a are
(There is a penetration due to the source-gate (SG) capacitance of the above, which is different). That is, this is the case where the number of image display areas 311 is one. The image display area 311 is, as indicated by the arrow,
Move from the top to the bottom of the screen (Fig. 31 (a1) → Fig. 3
1 (a2) → FIG. 31 (a3) → FIG. 31 (a1) →). However, the movement of the image display area 311 is not limited to the movement from the top to the bottom of the screen, and the movement from the bottom to the top of the screen may be performed. Also, even if the first frame (first field) is moved (moved) downwards from the top of the screen, the next second frame (second field) is moved upwards from the bottom of the screen. It goes without saying that it is good. Further, scanning (operation) may be performed from right to left of the screen or from left to right of the screen.

FIG. 33 shows operation timing waveforms. As described above, it is assumed that one screen is displayed in the period of 1F and current programming is performed in the period of 1H. FIG. 33A shows a timing waveform of the gate signal line 17a in FIGS. 1A and 1B. Also, FIG. 33 (b)
Shows a timing waveform of the gate signal line 17b. Basically, when the gate signal line 17b becomes Vgl, the TFT
11d becomes conductive (1F / N for a period), a current whose peak current is N times the predetermined value I1 flows in the EL element 15, and the EL element emits light at a brightness (N · B) N times the predetermined brightness B. 1F /
The TFT 11d is turned off during the period of (N-1) / N.

Control of this gate signal line is performed by controlling two shift registers (22a, 22a) in the gate driver 12 as shown in FIG.
22b) can be easily realized. This is because the shift register 22a may hold (scan) the control data of the gate signal line 17a, and the shift register 22b may hold (scan) the control data of the gate signal line 17b.

FIG. 56 shows the waveform of the gate signal line 17b. FIG. 56A shows the gate signal line 17b of the first pixel row.
56B shows the voltage waveform of the gate signal line 17b of the second pixel row adjacent to the first pixel row. Similarly, FIG. 56C shows the voltage waveform of the gate signal line 17b in the next third pixel row, and FIG. 56D shows the voltage waveform of the gate signal line 17b in the fourth pixel row.

As described above, the waveforms of the gate signal lines 17b are made the same in each pixel row, and they are applied while being shifted at intervals of 1H. By scanning in this manner, it is possible to sequentially shift the pixel rows to be lit, while defining the lighting time of the EL element 15 to 1 F / N. In this way, it is easy to realize that the gate signal lines 17b have the same waveform and are shifted in each pixel row. This is because it is sufficient to control ST1 and ST2 which are the data applied to the shift registers 22a and 22b in FIG. For example, if Vgl is output to the gate signal line 17b when the input ST2 is at the L level and Vgh is output to the gate signal line 17b when the input ST2 is at the H level, then ST2 applied to the shift register 17b is 1F / N
Input at the L level only for the period of, and set to the H level for the other periods. A clock C that synchronizes this input ST2 with 1H.
It just shifts in LK2.

Similarly, the gate signal line 1 shown in FIG.
It is easy to create the waveform of 7a. This is because ST1 which is the input data of the shift register 22a in FIG. 2 may be controlled. For example, if Vgl is output to the gate signal line 17a when the input ST1 is at the L level and Vgh is output to the gate signal line 17a when the input ST1 is at the H level, then ST1 applied to the shift register 17a is Input at the L level only for the period of 1H, and set to the H level for the other periods. A clock C that synchronizes this input ST1 with 1H.
It just shifts in LK1.

In FIG. 31B, the image display area 311 is
(2N), and two image display areas 311a and 311b
Is an example of moving from the top to the bottom of the screen as shown by the arrow (FIG. 31 (b1) → FIG. 31 (b2) → FIG. 31 (b).
3) → FIG. 31 (b1) →). However, the movement of the image display areas 311a and 311b is not limited to moving from the top of the screen to the bottom of the screen, and may be moved from the bottom of the screen to the top. In addition, the first frame (first field) is moved from the top of the screen downwards,
It goes without saying that the next second frame (second field) may be scanned (operated) so as to move upward from the bottom of the screen. Further, scanning (operation) may be performed from right to left of the screen or from left to right of the screen. Further, the image display area 311a may be moved downward from the top of the screen, and the image display area 311b may be moved upward from the bottom of the screen.

Further, FIG. 31C shows the image display area 31.
1 is set to 1 / (3N), and three image display areas 311a,
This is an example in which 311b is moved downward from the top of the screen as shown by the arrow (FIG. 31 (c1) → FIG. 31 (c2) → FIG. 31 (c3) → FIG. 31 (c1) →).

As shown in FIGS. 31 (b) and 31 (c), the more the image display area 311 is divided, the more the frame rate of the entire image display (the number of times the screen is written per second, for example, the frame rate 60). Rewrites the screen 60 times per second). If the frame rate is reduced, the operating clock of the circuit can be reduced accordingly, and the power consumption can be reduced.

That is, the light emitting period of the EL element 15 is shortened, the apparent instantaneous brightness is increased, and the image display area 311 and the non-lighted area 312 are repeated at high speed, so that flicker is reduced. Therefore, the frame rate can be reduced.

[0395] As described above, one frame (one field)
Flicker can be reduced by increasing the number of times of lighting. When the number of times of lighting is increased, the frequency component becomes high when the EL element is turned on, which makes it difficult for human eyes to observe. For example, one lighting period is 1/7
When the light was turned on seven times in one frame, a display without flicker could be realized even at a frame frequency of 30 Hz.

The brightness of the image can be adjusted (varied) by controlling the on / off of the TFT 11d. For example, in the case of FIG. 31A (the image display area 311 is 1
In the two cases, the brightness of the screen 21 changes by changing the area of the non-lighted area 312 (see FIG.
32 (a2) is darker than 1), and FIG. 32 (a3) is darker than FIG. 32 (a2).

Similarly, in the case of FIG. 31 (b) (when there are two image display areas 311), FIG.
(B2) is dark, and the display brightness of the screen 21 is darker in FIG. 32 (b3) than in FIG. 32 (b2). In addition, FIG.
The same applies to the case of (c) (when there are three image display areas 311; that is, three or more) (from FIG. 32 (c1) to FIG. 32).
32 (c2) is dark, and FIG. 32 (c3) is darker than FIG. 32 (c2). ).

Although it is assumed that the image display area 311 scans the screen 21 in FIG. 31, the present invention is not limited to this, and one frame (one field) as shown in FIGS. 32 (c1) and (c2). The eyes are in a non-illuminated state on the full screen 312
In the next second frame (2nd field), the entire screen may be in the image display state 311. That is, the entire screen is alternately switched between the image display state and the non-lighting state. However, the image display time and the non-lighting time are not limited to the equal time. For example, the image display time may be 1F / 4 and the non-lighting time may be 3F / 4. In this way, the display brightness of the image can be changed (adjusted) by changing the ratio between the image display time and the non-lighting time.

In any case, as shown in FIG. 34, the display brightness B of the image can be linearly changed by changing the value of N. Further, the brightness of the image can be easily changed only by controlling the value of N.

FIG. 35 is a block diagram of a circuit for adjusting (controlling) the display brightness according to the present invention. The frame memory (field memory) 354 stores video data input from the outside. The CPU 353 calculates using the accumulated video data. The calculation is at least one of the maximum brightness, the optimum brightness, the average brightness, and the brightness distribution of the video data.
Use one or more. In addition, the maximum brightness, the optimum brightness, the average brightness, the brightness distribution and the rate of change thereof of each frame of continuous video data are also considered.

The calculated result is stored in the luminance memory 352. The brightness memory 352 is data in which the brightness of the image is corrected. For example, on a bright screen such as a beach, the average brightness of the image is corrected to be bright, and if there is a relatively dark portion in the image data, it is converted to image data that is darker than the actual value. Further, on a screen at night, etc., since the image is entirely dark, a relatively bright part is corrected to be brighter.

The counter circuit 351 is a circuit for counting the N value in FIG. Gate signal line 1
In the waveform of 7b, the N value is changed in real time.
Since the N value is time, it can be easily changed by counting with the counter, and the brightness of the image can be changed.

The switching circuit 355 is the TFT 1 of the pixel 16.
It is a circuit for switching a voltage Vgl for turning on 1 and a voltage Vgh for turning off (in the case where the pixel TFT 11 is a P channel, the reverse is true for the N channel). That is, based on the output of the counter circuit 351, 1 shown in FIG.
Change the F / N period. Therefore, the brightness of the image 21 can be easily changed in real time.

The display brightness is controlled in real time according to the video signal data. By controlling in this way, the dynamic range of brightness expression can be substantially expanded to three times or more. In addition, since the EL display device is completely in black display (non-lighting) when no current is applied to the EL, black floating in image display does not occur. That is, the contrast is also high. Especially in the case of current programming, the current value programmed in the pixel is as small as 10 nA for black display. Therefore, the parasitic capacitance 404 cannot be sufficiently charged and discharged, and it is difficult to realize perfect black display. Further, the pulse applied to the gate signal line 17 supplies electric power to the source signal line 18 (piercing voltage), and black floating occurs.

In the present invention, the TFT 11d is forcibly turned off, and the supply of current to the EL element 15 is stopped. Therefore, the EL element 15 is completely turned off. Therefore, good contrast can be realized. Further, it is necessary to adjust the output timing of the data applied to the source signal line 18 and the timing of the gate signal lines 17a and 17b. In particular, the output of Vgl (voltage for turning on the TFTs 11b and 11c in FIG. 1) of the gate signal line 17a that selects a pixel row is preferably set to be shorter than 1H. This will be described with reference to FIG.

Although the brightness of the image is changed in real time based on the video data of the video signal in FIG. 35, the invention is not limited to this. For example,
The user presses the brightness adjustment switch or turns the brightness adjustment volume. This change is detected, the counter value of the counter circuit 351 is changed, and the display image 2
The brightness of 1 (or contrast or dynamic range) may be changed. Alternatively, the brightness of external light or the like may be detected by a photo sensor, and the brightness of the display image 21 may be automatically changed based on the detected data. Further, it may be configured to change manually or automatically depending on the content and data of the image to be displayed.

[0407] The brightness is adjusted by the TFT on the EL element 15 side.
This can be realized by turning on and off (TFT 11d in FIG. 1). In this case, the program current (voltage: in the case of the voltage programming method) output from the source drive IC 14 is a fixed value (the program current is not changed). Therefore, the circuit configuration of the source driver IC can be simplified. That is, it is not necessary to change the output current (voltage) or the like in accordance with the brightness of the display screen. For example,
In the conventional liquid crystal display panel, when displaying 64 gradations, the 64th gradation having the maximum brightness is used. From this, when lowering the brightness by adjusting the brightness, up to the 32nd gradation is used.
If the circuit is configured in this way, the number of gradations displayed decreases when the screen brightness is dark.

However, in the method of turning on / off the TFT 11 on the EL element 15 side (intermittingly displaying the current flowing through the EL element 15), the brightness can be freely adjusted by adjusting the off period. In that case, the brightness adjustment according to the present invention can be held by gamma adjustment, and the linearity can be held even if the brightness is changed. The power supply voltage Vdd also has a fixed value, which is advantageous in terms of configuration.

By controlling the on / off state of the TFT 11d from the top to the bottom of the screen so that it has a Gaussian distribution, the brightness of the screen can be easily Gaussian distributed. Almost no control is required for control. This method will be described later.

The period for turning on / off the EL element 15 must be 0.5 msec or more. When this cycle is short, the image is not completely displayed in black due to the afterimage characteristic of human eyes, and the image becomes blurry and the resolution is lowered. Further, the display state of the data holding type display panel is set. However, the on / off cycle is 100 msec.
When it is above, it looks like blinking. Therefore, the ON / OFF cycle of the EL element is 0.5 μsec or more and 100 msec.
Should be: More preferably, the on / off period should be 2 msec or more and 30 msec or less. More preferably, the on / off cycle is 3 msec or more and 20 m
It should be less than sec.

If the number of divisions of the black screen 1312 is set to one, a good moving image display can be realized, but flicker on the screen is easily visible. Therefore, it is preferable to divide the black insertion part into a plurality of parts. However, if the number of divisions is too large, moving image blur occurs. The number of divisions should be 1 or more and 8 or less. More preferably, it is 1 or more and 5 or less.

It is preferable that the number of divisions of the black screen can be changed between the still image and the moving image. What is the number of divisions?
When N = 4, 75% is a black screen and 25% is an image display. At this time, the number of divisions 1 is to scan 75% of the black display portion in the vertical direction of the screen with the black band state of 75%. Two
The number of divisions is 3 when scanning is performed with 3 blocks of a 5% black screen and a 25/3% display screen. For still images, increase the number of divisions. For movies, reduce the number of divisions. The switching may be performed automatically (moving image detection or the like) according to the input image, or may be performed manually by the user. Further, it may be configured such that the image of the display device or the like can be switched according to the input outlet.

For example, on a mobile phone or the like, the number of divisions is set to 10 or more on the wallpaper display and input screen (extremely, it may be turned on and off every 1H). When displaying an NTSC video, the number of divisions should be 1 or more and 5 or less. It is preferable that the number of divisions can be switched in multiple stages of 3 or more. For example, there are no division numbers, such as 2, 4, 8 and the like.

Further, the ratio of the black screen to the entire display screen is 0.2 or more and 0.9 or less (1.2 or more and 9 or less when displayed by N) when the area of the entire screen is 1. preferable. In addition, it is particularly preferably 0.25 or more and 0.6 or less (when displayed by N, 1.25 or more and 6 or less). 0.
If it is 20 or less, the effect of improving the moving image display is low. 0.9
If it is above, the brightness of a display part will become high and it will become easy to be visually recognized that a display part moves up and down.

The number of frames per second is preferably 10 or more and 100 or less (10 Hz or more and 100 Hz or less). Furthermore, 12 or more and 65 or less (12 Hz or more and 65 Hz
The following) are preferable. If the number of frames is small, flicker on the screen becomes noticeable, and if the number of frames is too large, writing from the driver circuit 14 or the like becomes difficult and the resolution deteriorates.

In any case, according to the present invention, the brightness of the image can be changed by controlling the gate signal line 17. However, it goes without saying that the brightness of the image may be changed by changing the current (voltage) applied to the source signal line 18. In addition, the control of the gate signal line 17 and the source signal line 18 described above (using FIG. 33, FIG. 35, etc.)
It goes without saying that changing the current (voltage) to be applied may be performed in combination.

It goes without saying that the above items can be applied to the pixel configuration of the voltage program shown in FIGS. 54, 67, 103, and the like. For example, in FIG. 67, TFT1
It is sufficient to control ON / OFF of 1e.

As shown in FIG. 36, the time for setting Vgl is 1F only for the period of 1F / N of the gate signal line 17b.
(It is not limited to 1F. It may be a unit period.) Any time may be used. This is because a predetermined average luminance is obtained by turning on the EL element 15 for a predetermined period in a unit time. However, in FIG.
It is better to immediately set the gate signal line 17b to Vgl to cause the EL element 15 to emit light after the program period (1H) in (a). This is because the capacitor 19 in FIG. 1 is less likely to be affected by the holding ratio characteristic. The period of 1F / N is shown in FIG.
In (b), the positions may be changed as indicated by the symbols A and B and the arrow. This change can be easily realized. This is because the timing of data to be applied to ST in FIG. 2 (when the L level is set at 1F) can be adjusted or varied.

Further, as shown in FIG. 37, the period (1 F / N) in which the gate signal line 17b is set to Vgl may be divided into a plurality of portions (the number of divisions K). In other words, the period of 1 V / (K / N) is performed K times for the period of Vgl. With such control, the image display state is as shown in FIG. 31 (b) (K = 2),
FIG. 31C (K = 3) is obtained. By thus dividing the image part (image display part 311) to be turned on into a plurality of parts, it is possible to suppress the occurrence of flicker and realize image display at a low frame rate. Further, it is preferable that the number of divisions of this image be variable. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume, this change is detected and the value of K is changed. It may be configured to change manually or automatically depending on the content and data of the image to be displayed.

Thus, the value of K (the number of divisions of the image display unit 311) can be easily changed. This is because the timing of data to be applied to ST in FIG. 2 (when the L level is set at 1F) can be adjusted or varied.

In FIG. 37, the period (1F / N) in which the gate signal line 17b is set to Vgl is divided into a plurality (division number K), and the period of 1F / (K / N) is set to K in the period of Vgl. It is said that it is carried out once, but it is not limited to this. 1F
The period of / (K / N) may be performed L (L ≠ K) times.
That is, the present invention displays the image 21 by controlling the period (time) of flowing into the EL element 15. Therefore, performing the period of 1F / (K / N) L (L ≠ K) times is included in the technical idea of the present invention. Also, L
The brightness of the image 21 can be digitally changed by changing the value of. For example, L = 2 and L =
In No. 3, there is a 50% change in brightness (contrast). These controls can also be easily realized with the circuit configurations shown in FIG. 2, FIG. 35, FIG. 60, FIG.

When dividing the image display area 311, the period during which the gate signal line 17b is set to Vgl is not limited to the same period. For example, as shown in FIG. 38, the period for which Vgl is set may be a plurality of periods such as t1 and t2.

In the above-mentioned embodiments, the display screen 21 is turned on / off (lit or unlit) by cutting off the current flowing through the EL element 15 and connecting the current flowing through the EL element. That is, substantially the same current is caused to flow through the TFT 11a a plurality of times by the electric charge held in the capacitor 19. The present invention is not limited to this. For example, by charging / discharging the charge held in the capacitor 19, the display screen 21 is turned on / off (lighted, non-lighted).
The method of doing may be used.

FIG. 303 shows an example thereof. In the pixel configuration of FIG. 1, the TFTs 11e serving as switching elements are arranged or formed at both ends of the capacitor 19. By applying an on-voltage (Vgl) to the gate signal line 17e connected to the gate terminal of the TFT 11e, T
The FT 11e turns on and shorts both ends of the capacitor 19. Therefore, the Vg voltage becomes the Vdd voltage, and the TFT
11a cannot flow current.

Of course, the drain (D) of the TFT 11a
-A switching element is arranged or formed between the gate (G) terminals, and the drain (D) -gate (G) of the TFT 11a.
Even if the terminals are short-circuited, the TFT 11a can be prevented from flowing a current. Therefore, it goes without saying that this configuration is also acceptable. For example, the gate terminal of the TFT 11b in FIG. 1 and the gate terminal of the TFT 11c can be individually controlled, and the TFT 11b is turned on to turn on the TF.
The configuration is such that the drain (D) -gate (G) terminal of T11a is short-circuited. This method is shown in FIG. 21, FIG. 43, FIG.
It can also be applied to FIG. 21, FIG. 43, FIG. 71, FIG.
2, the gate signal line 17b is turned on (Vgh)
Is applied to turn on the TFT 11d to short-circuit the drain (D) -gate (G) terminals of the TFT 11a.

Of course, the above configuration (driving TFT 11
54 and FIG. 6 for the method of charging / discharging the retained charge of FIG. 6 and the method of short-circuiting the drain (D) -gate (G) terminals
It goes without saying that the present invention can also be applied to voltage-driven pixel configurations such as 7, 7, 68, and 103.

The TFT 11e is not limited to the switching element such as TFT. Any capacitor may be used as long as it can charge and discharge the electric charge at both ends of the capacitor 19. For example, MIM, TFD (thin film diode), thyristor, varistor, etc. may be used. The capacitor 19 is not limited to the one that charges and discharges both ends of the capacitor 19, and may be one that can forcibly shift the terminal voltage Vg of the driving element for flowing a current to the EL element 15 in the current off direction. For example, a capacitor or the like may be used so that the Vg voltage can be shifted by the penetration voltage.

In the configuration of FIG. 303, the electric charge of the capacitor 19 is discharged by the operation of the TFT 11e, so that the current cannot flow again to the EL element 15. However, TFT
By controlling (adjusting) the time interval until 11e is turned on, the brightness of the display screen 21 can be easily adjusted. Further, by controlling (adjusting) the time interval until the TFT 11e is turned on for each of R, G, and B, color adjustment of the display screen 21 can be easily performed. It goes without saying that the configuration of FIG. 303 can be combined with other embodiments described in this specification, such as the reverse bias voltage method, N-fold pulse driving as shown in FIG. 87, Gaussian distribution driving, block driving, and the like. Since the other configurations and operations have already been described, they will be omitted. The above matters also apply to other present inventions.

In FIG. 303, the TFT 11e is turned on to interrupt the current flowing in the TFT 11a. However, it is also possible to control so as to increase the current flowing through the driving TFT 11a by making the TFT 11a an N channel. That is, it can be said that the screen 21 is displayed in white (white raster) by operating the TFT 11e (the screen is erased with a white screen). In addition, by operating the TFT 11e of at least one color of the RGB pixels, the screen 2
It can be said that 1 displays R, G, or B (the screen strongly displays R, G, or B colors). Needless to say, the TFT 11e may be P channel or N channel. Moreover, PWM modulation can also be implemented by turning on / off the TFT 11e. It goes without saying that the above items can be applied to other embodiments of the present specification.

The structure shown in FIG. 303 is a system in which the electric charge of the capacitor 19 is completely discharged. Therefore, the capacitor 1
The charge (image data) held in 9 is erased. In the configuration of FIG. 304, the capacitor 19 is separated into a plurality of (two in the embodiment) capacitors 19a and 19b, and the TFT 11 is provided at both ends of one capacitor (19b in the embodiment).
e is formed or arranged.

FIG. 304 shows an example thereof. TFT1
By applying an on-voltage (Vgl) to the gate signal line 17e connected to the gate terminal of 1e, the TFT 11e is turned on, and both ends of the capacitor 19b are short-circuited. Therefore, the Vg voltage becomes closer to the Vdd voltage, and the TFT 11
The current flowing by a is reduced (limited).

Therefore, in the configuration of FIG. 304, the TFT
The current supplied by 11a is not completely cut off (of course, the capacitors 19a, 19
b can be set to a constant). In the configuration of FIG. 303, the electric charge of the capacitor 19 is discharged by the operation of the TFT 11e, so that the current cannot flow again to the EL element 15. However, in the configuration of FIG. 304, when the TFT 11e is turned off, an image can be displayed again although the display brightness is lower than before. Further, by controlling (adjusting) the time interval until the TFT 11e is turned on, the brightness adjustment of the display screen 21 can be finely and finely adjusted (changed).

Further, even if there are individual differences among the panels (such as when manufacturing variations occur), it is possible to adjust the variation in the display brightness by turning on or off the TFTe for each manufactured display panel. it can.
In this case, the TFT 11e may be always on or off. Further, by controlling (adjusting) the time interval until the TFT 11e is turned on for each of R, G, and B, the color adjustment of the display screen 21 is decided and easily adjusted. As the pixel configuration, the configuration described with reference to FIG. 294 or the like may be adopted. Needless to say, the configuration shown in FIG. 304 and the like can be combined with other embodiments described in this specification, such as the reverse bias voltage method.
Since the other configurations and operations have already been described, they will be omitted. The above matters also apply to other present inventions.

In FIG. 304, the capacitors 19a, 1
Two of 9b are used, but the number is not limited to this. It is also possible to form three or more capacitors and arrange switching elements such as TFTs so that the electric charge of each capacitor can be charged and discharged. With this configuration, the brightness of the display screen 21 can be changed at another stage. Also, the RGB color balance can be adjusted (changed) in multiple stages.

Further, in FIG. 304, the current flowing through the TFT 11a is reduced by turning on the TFT 11e. However, it is also possible to control so as to increase the current flowing through the driving TFT 11a by making the TFT 11a an N channel. That is, the brightness of the screen 21 can be increased by operating the TFT 11e. Also, of the RGB pixels,
By operating at least one color TFT 11e,
The colors of the screen 21 can be increased to R, G, or B colors (the screen is strongly displayed in R, G, or B colors, and there may be a plurality of colors such as R and B).

Also, in FIG. 304, one capacitor 1 is provided between the gate (G) terminal and the source (S) terminal of the TFT 11a.
9a is formed, but the present invention is not limited to this. A configuration may be used in which a plurality of capacitors 19a are formed in series or in parallel between the gate (G) terminal and the source (S) terminal of the TFT 11a. A switching TFT 11e for short circuit may be formed at both ends of at least one of the capacitors, and the TFT 11e may be turned on to reduce the current flowing through the TFT 11a. It goes without saying that the above items also apply to the pixel configuration of the current mirror or the pixel configuration of the voltage drive.

FIG. 305 shows the pixel configuration of the current mirror described with reference to FIGS. 21, 43, 71, etc., in which the TFT 11e for short-circuiting both ends of the holding capacitor 19 is formed (arranged). The operation and the like are the same as those in FIG. The same applies to FIG. 305. The operation is explained in FIG. 304 or in FIG.
Since it can be easily inferred from the description of 4, the description is omitted.

FIG. 307 shows an example of voltage driving in which the pixel has a 2-TFT structure. The configuration of FIG. 307 also has the same operation as the current driving method described in FIG. TFTs 11e are formed (arranged) at both ends of the holding capacitor 19. In the configuration of FIG. 307, as in the configuration described above, T
Since the electric charge of the capacitor 19 is discharged by the operation of the FT 11e, the current cannot flow through the EL element 15 again. However, the brightness of the display screen 21 can be easily adjusted by controlling (adjusting) the time interval until the TFT 11e is turned on. In addition, a TFT is provided for each of R, G, and B.
By controlling (adjusting) the time interval until 11e is turned on, the color adjustment of the display screen 21 can be easily performed.

Also, with the configuration of FIG.
By changing 11a to N channel, TFT1
It is also possible to control to increase the current flowing through the driving TFT 11a by turning on 1e. That is, it can be said that the screen 21 is displayed in white (white raster) by operating the TFT 11e (the screen is erased with a white screen). Further, it is possible to display the screen 21 in R, G, or B by operating the TFT 11e of at least one color of the RGB pixels (the screen is strongly displayed in R, G, or B colors).

FIG. 308 shows an embodiment in which the technical concept of FIG. 303 is applied to the pixel configuration of the voltage program (drive) of FIGS. 67 and 68. The configuration of FIG. 308 is also the same in operation as the current driving method described in FIG. That is, the TFT 11e is formed at both ends of the holding capacitor 19 and
The electric charge of the capacitor 19 is discharged by the operation of T11e. Therefore, black is displayed. By controlling (adjusting) the time interval until the TFT 11e is turned on, the brightness of the display screen 21 can be easily adjusted, and R,
By controlling (adjusting) the time interval until the TFT 11e is turned on for each of G and B, the color adjustment of the display screen 21 can be easily performed. The other matters are the same as those in the above-described embodiment, and thus the description thereof will be omitted.

In FIG. 33, adjacent pixel rows are illustrated as being sequentially turned on (displayed), but the present invention is not limited to this. Interlaced scanning may be performed as shown in FIG.

Interlaced scanning means that an image is written in an odd pixel row in the first field (write pixel row 391 in FIG. 39 (a)), and an image is written in an even pixel row in the next second field (write in FIG. 39 (b)). Pixel row 391)
This is an image display method. The pixel row that is not written holds the image data of the previous field (holding pixel row 39
2). By performing interlaced scanning with the EL display device in this manner, flicker can be reduced.

In the driving of FIG. 39, the gate signal lines 17b of all (or a plurality of) even pixel rows can be made common,
Moreover, the gate signal lines 17b of all (or a plurality of) odd-numbered pixel rows can be made common. Therefore, the number of wirings of the gate signal line 17 can be significantly reduced. When the display state 311 and the non-display state 312 are alternately displayed on the entire screen, all the gate signal lines 17b can be shared.
These configurations are particularly effective in the configuration with three sides free as shown in FIG.

In the interlaced scanning, the image is written in the odd pixel row in the first field and the image is written in the even pixel row in the next second field, but the invention is not limited to this. For example, in the first field, an image is written every two pixel rows by skipping two pixel rows, and in the next second field, an image is not written in the first field.
An image may be written for each pixel row. Further, it may be three pixel rows or four pixel rows. Further, in the first field, an image is written by 2 pixel rows from the second row of the screen (see FIG. 106A), and in the next second field, 1 is written.
An image may be written every two pixel rows from the second row (see FIG. 1).
06 (b)). Further, as shown in FIG. 106, the writing pixel row or the writing pixel row may be controlled to be the non-display area 312. Further, in the first field, the image may be written from the top to the bottom of the screen, and in the second field, the image may be written from the bottom to the top of the screen. These are all included in the concept of interlaced scanning.

Interlaced scanning can also be easily realized by implementing the method described with reference to FIGS. 33 and 56. This is because the TFT 11d shown in FIG. 1A may be turned off for the pixel row corresponding to the display area 312 that is not illuminated.

Naturally, it is possible to combine the black display area 312 and the interlaced scanning as shown in FIG. In FIG. 50A, the scanning region 50 including the writing pixel row 391 and the holding pixel row 392.
1 is sequentially shifted. Note that in FIG. 50A, the image is written from the first line. Similarly in FIG. 50B, the scanning region 501 including the writing pixel row 391 and the holding pixel row 392 is sequentially shifted. Note that FIG.
In (b), the image is written from the second line.

Interlaced scanning (interlaced scanning, etc.)
By applying, it is possible to suppress the variation of the driving TFT 11 of the pixel 16. In FIG. 322, the drive TFTs T11a of adjacent pixel rows are formed (arranged) close to each other. That is, the TFT 11a1 of the pixel 16a and the TF of the pixel 16b
T11a2 is arranged in close proximity. Also, pixel 1
The gate signal line 17a1 for controlling 6a and the gate signal line 17a2 for controlling the pixel 16b are also arranged close to each other. The gate signal line 17a1 and the gate signal line 17a2 are arranged close to each other because the pixels 16a and 16b are arranged in line symmetry.

As shown in FIG. 322, the TFT 11a1 in the pixel row including the pixel 16a and the TF in the pixel row including the pixel 16b.
By placing T11a2 close to each other, the TFT1
The characteristics of 1a2 and TFT 11a1 are similar. Below, FIG.
FIG. 32 shows a driving method using 20 pixel arrangement configurations.
3 and FIG. 324.

FIG. 323 is an illustration of another embodiment for increasing the current flowing through the source signal line 18. Two pixel rows are selected at the same time, and the source signal line 1 is generated with the combined current of the two pixel rows.
This is a method of charging and discharging the parasitic capacitance 404 and the like of No. 8 and significantly remedying the insufficient current writing. However, since two pixel rows are selected at the same time, the driving current per pixel can be reduced to 1/2 of the current (program current) flowing through the source signal line 18. Therefore, since the current flowing through the EL element 15 can be reduced, the EL element 15 is less deteriorated. Here, for ease of explanation, as an example, N = 2 will be described (the current flowing through the source signal line is doubled). A similar driving method is shown in FIG.
7, FIG. 88 and the like. Therefore, see also these methods.

FIG. 323 (a) shows the state of writing to the display image 21. In FIG. 323 (a), 87
1 (871a, 871b) is a writing pixel row. That is, 2 pixels are written. The source signal line 18 is applied with a program current Iw that is twice the current written in the pixel. Therefore, since the number of pixel rows is two, the current written in one pixel is 1 time (predetermined value). FIG. 323
In the state of (a), the pixel 16a and the pixel 16b are 1
It means that the pixel row is selected. That is, the drive TFTs 11a1 and 11a2 of the adjacent pixels are current-programmed to operate (assuming the pixel configuration of FIG. 1). The current Iw flowing through the source signal line 18 is the driving TFT 11a1 and the driving T which are arranged close to each other.
Supplied from FT11a2.

Driving TFT 11a1 and driving TFT 11
Since a2 is formed close to each other, its characteristics are almost the same. Therefore, if the program current Iw flowing through the source signal line 18 is 2 (μA), the driving TFT
11a1 and the driving TFT 11a2 are 1 (μ
A) Supply current one by one.

From the above, by supplying the program current Iw twice the predetermined value to the source signal line 18, the current of the predetermined value is accurately programmed in the pixel. Although the current passed through the source signal line 18 is doubled (N = 2), it is not limited to this. The reason for doubling is to make it easy to understand. In actual driving, since the non-lighted area 312 is half the display area, the program current is set to 4 times.

In the pixel configuration shown in FIG. 322, one screen is rewritten with two fields (1 frame = 2 fields). In the first field, the even lines are rewritten
In the field, it is assumed that the odd line is rewritten. In FIG. 323, it is described that the even lines are rewritten, and in FIG. 324, the odd lines are described as rewritten.

In FIG. 323, 871 (871a, 81)
71b) is a writing pixel row in which two pixels are written. The source signal line 18 is applied with a program current Iw that is twice as large as the current written in the odd pixel. Therefore, the writing pixel rows 871a and 871b have the same display. Therefore, as shown in FIG. 323 (b), the EL elements 15 of the pixels corresponding to the odd-numbered lines are brought into a non-lighting state (in FIG. 1, an off voltage is applied to the gate signal line 17b and a current from the driving TFT 11a is applied. Are prevented from flowing into the EL element 15). The image data is written in the pixels while shifting the above operation by two pixel units. When scanning of one field is completed, as shown in FIG. 323 (c), all even lines are turned off 312 and odd lines are turned on 311.

FIG. 324 shows the state of writing image data in the second field. In FIG. 324 (a),
871 (871a, 871b) is a writing pixel row, and 2 pixels are written. The source signal line 18 is applied with a program current Iw that is twice as large as the current written in the odd pixel. Therefore, the write pixel rows 871a and 871b
Are the same display. As in the first field, FIG.
As shown in (b), E of pixels corresponding to even lines
The L element 15 is turned off. The image data is written in the pixels while shifting the above operation by two pixel units. When scanning of one field is completed, FIG. 324 (c)
As shown in the figure, all the odd lines (odd-numbered pixel rows) are non-lighting 312, and the even-numbered lines (even-numbered pixel rows) are lighting 311.

As described above, one screen is rewritten in one frame (two fields) by alternately repeating the driving in FIGS. 323 and 324. In addition, as shown in FIG. 322, by forming a pair of two pixel rows, the driving TFTs 11a of the two pixel rows are brought close to each other, and the occurrence of characteristic variations is suppressed. Therefore, a uniform image display can be realized.

Note that the pixel arrangement and driving method of FIG. 322 are
It is not limited to the pixel configuration of FIG. For example, it is needless to say that the present invention can be applied to the pixel configurations of the current mirror shown in FIGS. 21, 43, 71 and 22, and the voltage programmed pixel configurations shown in FIGS. 54, 67, 68 and 103.

In the pixel configurations shown in FIGS. 21, 43 and 71,
By applying the on-voltage (Vgl) to the gate signal line 17a, the current value applied to the source signal line 18 is programmed in the capacitor 19. As shown in FIG. 40, the data corresponding to the video signal is applied to the source signal line 18 from the current source 403 in the source driver IC 14. The programmed current has a current mirror efficiency of 1
At this time, the current flows into the TFT 11b, and this current is EL
It is applied to the element 15. As for this relationship (timing waveform, etc.), the matters illustrated in FIG. 33 can be used or similar, and thus need not be described. However, when performing the current program, it may be necessary to individually control the on or off timing of the TFT 11c and the TFT 11d. In this case, it goes without saying that the gate terminal for turning on / off the TFT 11c and the TFT 11d needs to be another gate signal line 17.

In order to implement the display method shown in FIG. 31 or the like, it is necessary to cut off the current flowing through the EL element 15. For the purpose of blocking this, as shown in FIG.
e is added. By setting the gate terminal of the TFT 11e to Vgl, a current is applied to the EL element 15,
EL element 1 by changing the gate terminal of 1e to Vgh
The current to 5 is cut off (non-lighting state).

Therefore, by applying the signal waveforms of the gate signal lines 17a and 17b described in FIG. 33 and the like, the image display described in FIG. 31 and the like can be realized.

Non-image display area 311 and image display area 31
2, the odd pixel row and the even pixel row may be switched for each frame (field) as shown in FIG. When the odd pixel rows are displayed and the even pixel rows are hidden in FIG. 61A, the next frame (field) (FIG. 61B) is displayed.
In (), the odd pixel rows are not shown, and the even pixel rows are displayed.

As described above, if the non-display area and the display area are repeated for each pixel row, the occurrence of flicker can be significantly suppressed.

In FIG. 61, the non-display pixel row and the display pixel row are set for each one pixel row, but the present invention is not limited to this, and the non-display pixel row may be set for every two or more pixel rows. May be set to the display pixel row.

For example, if every two rows, in the first field (frame), the first pixel row and the second pixel row are the display pixel rows, and the third pixel row and the fourth pixel row are the non-display pixel rows. To do. The 5th pixel row and the 6th pixel row are display pixel rows. In the second field (frame) next to the first field,
The first pixel row and the second pixel row are non-display pixel rows, and the third pixel row and the fourth pixel row are display pixel rows. The 5th pixel row and the 6th pixel row are non-display pixel rows. In the next third field (frame), the first pixel row and the second pixel row are the display pixel rows, and the third pixel row and the fourth pixel row are the non-display pixel rows. The 5th pixel row and the 6th pixel row are display pixel rows.

In the present specification, the terms field and frame are used synonymously or separated. Generally, in NTSC interlaced drive, one frame is 2
Composed of fields. However, in progressive driving, one frame is one field. In this way, fields and frames are used properly in the world of video signals. However, according to the present invention, the image displayed on the display panel may be either progressive or interlaced. Therefore, it is said that either one is acceptable. Conceptually, a field or frame is a unit of time for finishing writing one screen.

The display method of FIG. 62 is also effective. For ease of explanation, FIG. 62A shows a first field (first frame), FIG. 62B shows a second field (second frame), and FIG. 62C shows a third field (first frame). 62 (d) is the fourth field (fourth frame).

In the first field (frame), the first pixel row and the second pixel row are non-display pixel rows, and the third pixel row and the fourth pixel row are
The pixel row is the display pixel row. The 5th pixel row and the 6th pixel row are display pixel rows. In the second field (frame), the odd pixel rows are the display pixel rows and the even pixel rows are the non-display pixel rows. In the third field (frame),
The first pixel row and the second pixel row are display pixel rows, and the third pixel row and the fourth pixel row are non-display pixel rows. In the fourth field (frame), the odd pixel rows are non-display pixel rows,
Let the even pixel rows be the display pixel rows. Thereafter, the display state of the first field (first frame) is sequentially repeated.

In the driving method shown in FIG. 62, one loop is composed of 4 fields (frames). By thus displaying an image in a plurality of fields (a plurality of frames), the occurrence of flicker is often suppressed more than in FIG.

In the embodiment of FIG. 62, in the first field (frame), non-display pixel rows are set every two pixel rows, and in the second field (frame), every one pixel row is set as non-display pixel rows. However, it is not limited to this. In the first field (frame), the non-display pixel rows are set every two pixel rows, and in the second field (frame), the non-display pixel rows are set every one pixel row, but the present invention is not limited to this. In the first field (frame), non-display pixel rows are set every 4 pixel rows, in the second field (frame), every 2 pixel rows are set as non-display pixel rows, and in the third field (frame), 1 pixel row Each as a non-display pixel row,
In the 4th field (frame), non-display pixel rows are set every 4 pixel rows, in the 5th field (frame), 2 pixel rows are set as non-display pixel rows, and in the 6th field (frame), each pixel row is set as non-display pixel rows. It may be a non-display pixel row.

With the driving method of the present invention, it is easy to realize a display effect (animation effect, etc.). Fig. 63
The display area is as shown in FIG. 63 (a) → FIG. 63 (b) → FIG. 63.
This is a display method that appears in sequence from (c) to FIG. 63 (d). An animation effect can be realized by slowly scrolling the non-display area 312. These controls can also be easily realized with the circuit configurations shown in FIG. 2, FIG. 60, FIG. That is, the animation effect can be easily realized by controlling the gate signal line 17b without writing the black display state as an image.

A display panel which holds data for one field (one frame) period in a pixel of a liquid crystal display panel or the like has a problem that a moving image blur occurs. Since the CRT or the like is only displayed for a moment by the electron gun, the problem of moving image blur does not occur.

Black insertion is an effective means for solving this problem. The present invention can easily realize a black insertion method that approximates a CRT that displays a moving image.

FIG. 64 shows that the letter F moves from the top to the bottom of the screen. However, the letter F is used to facilitate drawing. As shown in FIG. 64, a non-display state (FIGS. 64 (b) (d) (f)) is inserted between image displays (FIGS. 64 (a) (c) (e)).
Therefore, the image is displayed in a scattered manner. for that reason.
Good moving image display can be realized without moving image blurring.

To make the entire screen a non-display area for this purpose, the circuit configuration of FIG. 60 may be adopted. The difference from FIG. 2 is E
The point is that an NBL terminal 601 is provided. ENBL terminal 6
01 is connected to one terminal of the OR circuit 602 in which the gate signal line 17 is formed. By setting the ENBL terminal to the L level, Vgh is applied to all the gate signal lines 17b.
TF that outputs the level and supplies current to the EL element 15
T11d or 11e is turned off, and the entire screen becomes the non-display area 312. When the ENBL terminal is at H level,
Normal operation is performed.

In FIG. 2, FIG. 60, FIG. 74, and FIG. 84, the data input to the ST terminal is sequentially shifted by the clock (serial operation), but the present invention is not limited to this. For example, a parallel input that determines the on / off state of each gate signal line at a time may be used (a configuration in which the on / off logic of all gate signal lines is output and determined at one time for the number of controllers or gate signal lines 17). And so on).

In the embodiment shown in FIG. 64, a moving image is displayed.
It is also easy to implement an animation effect such as flashing for each R, G, B (see FIG. 65). Figure 6
65, (a) is an image of red display 311R,
65 (b) is an image of green display 311G, FIG. 65 (c).
Is an image of blue display 311B. Image of red display 311R in FIG. 65 (a), green display 311G in FIG. 65 (b)
In FIG. 65 (c), the non-display state (FIGS. 65 (b) (d) (f)) is inserted between the blue display 311B images. This operation is shown in FIG.
If (f) is slowly performed, the R, G, and B images can be displayed as if they were flashing.

In the embodiment shown in FIG. 64, the moving image is displayed.
It is easy to implement an animation effect such as flashing different images one by one (see FIG. 66). In FIG. 66, FIG. 66 (a) shows the first image 311a and FIG.
6 (b) is the second image 311b, and FIG. 66 (c) is the third image 311B. 66 (a) is a non-display state between the first image 311a, the second image 311b of FIG. 66 (b), and the third image 311B of FIG. 66 (c) (FIG. 66 (b)).
(D) and (f) are inserted. This operation is shown in FIG.
If (a) to FIG. 66 (f) are slowly carried out, it is possible to display the first, second, and third images as if they were flashing.

In the above embodiment, conceptually, the source signal line 18 is supplied with a current N times as large as the predetermined value, and the EL element 15 is supplied with a current N times for a period of 1 / N to obtain a desired luminance. Was a method (configuration) for obtaining By this method (configuration), the problem of unexpected writing due to the presence of the parasitic capacitance 404 was solved.

The N-fold driving method improves the luminous efficiency more than the 1-fold driving method (conventional driving method). This is due to the penetration voltage of the TFT 11b (on the side of the capacitor 19) of FIG. The effect of this punch-through voltage can be reduced by multiplying it by N times. It is suitable that the N multiple is 1.5 times or more and 8 times or less. If it is more than this, the luminous efficiency of EL is lowered, and the efficiency is lowered as a whole. Preferably, N times is 2 times or more and 6 times or less. Also, to multiply by N means
That is, the light emitting period is set to 1 / N. Therefore, if N is set to 2 times or more and 6 times or less, the light emitting period is 1 /
It is preferable to set it to 2 or more and 1/6 or less (at normal brightness).

According to the present invention, the TFT 11d is turned off,
After cutting off the current to the EL element 15, the TFT 11 is turned on again.
By turning on d, a current can be passed through the EL element 15 as before. The present invention successfully applies this principle, for example, by passing a current in a period of 1 / N to obtain a predetermined brightness. This driving can be performed because the current value to be supplied is held in the capacitor 19 for each pixel 16. That is, it can be said that the present invention successfully applies the specific pixel configuration of the EL display panel when the value of the current passed through the EL element 15 is held.

The configuration shown in FIG. 69 corresponds to the drive TFT 11a.
This is a method of solving the problem of insufficient writing due to the presence of the parasitic capacitance 404 by forming the TFT 11an having a driving capacity of (N-1) times.

The difference between FIG. 69 and FIG. 1A is the drive TF.
In addition to T11a, a TFT-1an-1 driven N-1 times and a switching TFT 11f are added. Figure 1
69 will be mainly described. TFT11an-
The reason for setting 1 is that the currents of the TFT 11an-1 and the TFT 11a are multiplied by N when multiplied. Simply, the channel width W2 of TFT11an-1 is TF.
It is N-1 times the channel width W1 of T11a. For example, if N = 10 and the channel width W1 of the TFT 11a is 1, the channel width W2 of the TFT 11an-1 is 9 times. Therefore, theoretically, the TFT
If 11a passes a current of 1, TFT 11an-1 has the ability to flow a current 9 times.

In FIG. 69, the driving current of the TFT 11an-1 is set to N−1. In the configuration of FIG. 69, the TFT 11a that allows current to flow through the EL element 15 when an N times larger current is passed through the source signal line 18 is used. This is because a current that is 1 times the current is added. In the configuration shown in FIG. 71, a TFT that allows a current to flow through the EL element 15
Since the current of 11b does not flow to the source signal line 18, the driving current of the TFT 11n needs to be N times.

For ease of explanation, the TFT 11
The current of I1 is supplied to a, and the TFT 11an-1 is I
A current of n-1 shall flow. In addition, I1 + In
−1 = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15).

The gate signal line 17 is supplied during the current program period.
When a voltage of Vgl is applied to a, TFTs 11b, 11f,
11c is turned on. Further, the gate signal line 17b is applied with a voltage of Vgh, and the TFT 11d is in the off state. Therefore, the voltage corresponding to the program current Iw is programmed in the capacitor 19. That is, I1 +
In-1 = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15), and the current is the source signal line 1
It flows to 8.

Next, during the period in which a current is passed through the EL element 15, the gate signal line 17a is applied with a voltage of Vgh and the TFT
11b, 11f and 11c are turned off. Therefore, the source signal line 18 and the pixel 16 are separated. Further, a voltage of Vgl is applied to the gate signal line 17b,
The FT 11d is turned on. Therefore, the current I1 corresponding to 1 / N of the program current Iw flows through the EL element 15.

By driving as described above, the source signal line 18 can be supplied with a current N times as large as the desired value of current (current flowing through the EL element). Therefore, the influence of the parasitic capacitance (stray capacitance) 404 is excluded, and the current programming of the capacitor 19 can be sufficiently performed. On the other hand, E
A current can be applied to the L element 15 at a desired value.

In FIG. 69, a TFT having N-1 current capability
Although it has been stated that 11an-1 and one pixel are formed in the pixel, the invention is not limited to this. As shown in FIG. 70, a plurality of TFs
T (TFT 11n1 to TFT 11n6 in FIG. 70) may be manufactured. The operation is the same as that in FIG. 69, and therefore its explanation is omitted.

The structure shown in FIG. 69 corresponds to the driving TFT 11a.
This is a method of solving the problem of insufficient writing due to the presence of the parasitic capacitance 404 by forming the TFT 11an having a driving capacity of (N-1) times.

The configuration of FIG. 69 can be expanded also in the current mirror system shown in FIGS. 21, 43, and 71. As shown in FIG. 71, a TFT 11n having N times the driving capability may be formed. However, in the current mirror configuration, the switching TFT 11f is not necessary.

In FIG. 71, the ratio of the channel width W2 of the TFT 11n to the channel width W1 of the TFT 11b is
N: 1. For ease of explanation here, TF
It is assumed that the current I1 flows through T11b and the TFT 11n receives I
It is assumed that a current of n flows. Further, In 2 = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15).

In the current program period, the gate signal line 17
A voltage of Vgl is applied to a, and the TFTs 11c and 11d are turned on. Therefore, the voltage corresponding to the program current Iw is programmed in the capacitor 19. In other words, the current that is In 2 = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15) is the source signal line 1
It flows to 8. It is preferable that the TFT 11c and the TFT 11d be controlled in ON / OFF state by slightly shifting the timing. In this case, it is necessary to separate the gate signal line for controlling the TFT 11c and the gate signal line for controlling the TFT 11d and perform independent control.

Next, in the period in which a current is passed through the EL element 15, the gate signal line 17a is applied with a voltage of Vgh, and the TFT
11c and 11d are turned off. Therefore, the source signal line 18 and the pixel 16 are separated. Therefore,
The current I1 corresponding to 1 / N of the program current Iw is EL
It flows to the element 15.

By driving as described above, the source signal line 18 can be supplied with N times as much current as the desired value (current flowing through the EL element). Therefore, the influence of the parasitic capacitance (stray capacitance) 404 is excluded, and the current programming of the capacitor 19 can be sufficiently performed. On the other hand, E
A current can be applied to the L element 15 at a desired value.

It should be noted that the gate signal line 17b and the TFT 11e
As described with reference to FIG. 40, is provided for non-image display as shown in FIG. 30 or for controlling so that a current flows through the EL element 15 only for 1 / N period. Therefore, FIG.
In this configuration, an EL element 1 is supplied with a current N times larger.
By pulse-driving the current flowing in 5 for the 1 / N period, the problem of insufficient writing due to the parasitic capacitance 404 is completely eliminated. Further, black insertion display can be easily realized, and good moving image display can be realized.

The configuration of FIG. 71 is very effective. For example, in order to realize N = 10 with only the configuration of FIG. 1, it is necessary to apply a pulsed current 10 times higher than a desired value to the EL element 15. In this case, since the terminal voltage of the EL element 15 becomes high, it is necessary to design the Vdd voltage high. In addition, the EL element 15 may deteriorate.

However, in the configuration of FIG. 71, the TFT 11n
If the channel width W2 is set to 5 times that of the TFT 11b and programming is performed with a current twice as high, then 5 × 2 = 10. Therefore, it can be realized by applying a double current to the EL element 15 only for 1/2 period. Therefore, the problem of deterioration of the EL element 15 is eliminated, and it is not necessary to increase the Vdd voltage.

On the contrary, in order to realize N = 10 only by the TFT 11n, in the configuration of FIG. 71, the channel width W2 of the TFT 11n needs to be 10 times that of the TFT 11b. When it is multiplied by 10, the formation area of the TFT 11n occupies most of the pixel area. Therefore, the pixel aperture ratio becomes extremely small or unrealizable. However, in the configuration of FIG. 71, the channel width W of the TFT 11n is
Since it is only necessary to set 2 to 5 times the TFT 11b, it is possible to realize a sufficient pixel aperture ratio.

There are many ways to realize N = 10. TFT
The channel width W2 of 11n is twice that of the TFT 11b,
A 5 times higher current is applied to the EL element 15 for a 1/5 period, the channel width W2 of the TFT 11n is set to 4 times that of the TFT 11b, and a 2.5 times higher current is applied to the EL element 15 by 1/2.
For example, a method of applying the voltage for 5 periods is used. That is, the TFT 11
This is because the multiplication should be 10 in consideration of the design of n (channel width W2), the current flowing through the EL element and the period thereof. Therefore, the value of N can be freely designed.

In FIG. 71, the TFT 11 having N current capability
Although it has been stated that n and one pixel are formed in the pixel, the invention is not limited to this. As shown in FIG. 72, a plurality of TFTs (see FIG.
Then, TFT 11n1 to TFT 11n5) may be manufactured. The operation is the same as that in FIG. 71, so the description thereof will be omitted.

There are many ways to realize N = 10, also in the configuration of FIG. A method in which the channel width W2 of the TFT 11an-1 is set to be four times as large as that of the TFT 11a and a current twice as high is applied to the EL element 15 for a half period, TFT1
For example, the channel width W2 of 1an-1 is set to be twice that of the TFT 11ab, and a five times higher current is applied to the EL element 15 for ⅕ period. That is, the multiplication should be 10 in consideration of the design of the TFT 11an-1 (channel width W2), the current flowing through the EL element and the period thereof. Therefore, the value of N can be freely designed.

The matters explained above are shown in FIG. 69, FIG. 70,
Obviously, the same can be applied to FIGS. 75, 82, and 83. That is, according to the present invention, a driving TFT having a large channel width is formed in each pixel to increase the current for driving the source signal line 18. Moreover, the EL described in FIG.
In addition to increasing the current flowing through the element 15, the EL element 15
It is a method or a configuration in which the current flowing through the device is set for a predetermined period.

Also, the TFT 11d or the TFT 11e
The display described with reference to FIGS. 30, 31 and the like can be realized by controlling the on / off of. With this display, the moving image display can be improved and the brightness can be adjusted.
Therefore, in the present invention, the EL element 15 is applied with a current N times or a current proportional to N, but the present invention is not limited to this. The EL element 15 may be configured to flow a current of a predetermined value or less. Even in this case, it is possible to improve the display of the moving image and to easily adjust the brightness.

The same applies to FIGS. 1 and 69, but the TFT
When 11d is turned on, by increasing the resistance value, characteristic variation due to the kink phenomenon of the TFT 11a can be suppressed. This has been described with the configuration of FIG. The TFT 11e of FIG. 1B is arranged, and a Vbb voltage (Vgl <Vbb <Vg is applied to the gate terminal of the TFT 11e.
By applying h), variations in the current flowing through the TFT 11a are reduced.

Therefore, also in the pixel configurations of FIGS. 1 and 69, it is preferable to apply the Vbb voltage to the gate signal line 17b to turn on the TFT 11d. That is,
Vgh is applied to the TFT 11d in the off state, and Vbb is applied in the on state.

This control is easy. This is because the circuit configuration may be as shown in FIG. If the output stage inverter of the shift register 22b uses Vgh and Vbb as power sources,
In the off state, Vgh is applied to the gate signal line 17b,
This is because Vbb can be applied to the gate signal line 17b in the on state.

The on / off control of the gate signal line 17 is based on the data held by the shift register 22. However, the on / off control of the gate signal line 17 is not limited to the control by the shift register 22, and a method of independently controlling each gate signal line 17 without providing the shift register 22 may be used. For example, an arbitrary gate signal line 17 that outputs an ON voltage may be selected by a multiplexer circuit. Further, all gate signal lines may be drawn out in parallel, and an ON voltage or an OFF voltage may be freely applied to each gate signal line. As described above, by arranging such that the arbitrary gate signal line 17 can be selected regardless of the data held in the shift register 22, FIG. 31, FIG. 32, FIG. 87, FIG. 88, FIG. 198, FIG. 201, FIG. 215, FIG. 218, FIG. 220, FIG. 221, etc., it is easy to turn on / off the display screen 21 or process intensity of the luminance distribution.

Note that, similarly to FIG. 1B, as shown in FIG. 75, a TFT 11e for separately applying a Vbb voltage is applied.
It goes without saying that may be formed or arranged. The same applies to the current mirror configuration. For example, as shown in FIG. 76, a TF that applies a Vbb voltage.
The T11f may be separately formed or arranged. The same applies to the pixel configuration of FIG. As shown in FIG. 77, Vbb
The TFT 11f for applying a voltage may be separately formed or arranged.

78, the driving TFT 11
a is divided into a plurality of TFTs 11a1 and TFTs 11a2,
By connecting the gate terminals in a cascade, it is possible to suppress the kink phenomenon and also suppress variations in characteristics. This is because the TFT 11a of FIG. 1, FIG. 21, FIG. 43, and FIG.
TFT 11b, TFT 11a in FIG. 69, TF in FIG. 71
The same applies to T11b and the like (preferably adopted as the structure of the driving TFT).

70 and 72, the TFT 11n is divided into a plurality of parts. As another configuration, the TFT 11n1 and the TFT 11n divided as shown in FIG.
Whether or not 2 is operated for improving the drive current may be controlled by the potential (Vgh or Vhl) applied to the gate signal line 17c. When the TFT 11f2 is turned off, the current flowing through the source signal line 18 is
It is 1/2 that when 11n2 is operating. These controls may be determined from the viewpoint of image display data of the display panel and power consumption.

The difference between FIG. 75 and FIG. 82 is that the switching T
This is the point where the gate terminal of the FT 11f is connected to the gate signal line 17c. That is, the on / off state of the TFT 11f is not affected by the potential state of the gate signal line 17a, and independent control can be realized.

When the TFT 11f is constantly off, TF
T11n is in a state of being separated from the pixel. Therefore, the pixel configuration shown in FIG. Gate signal line 17
If c and the gate signal line 17a are logically short-circuited and used, the configuration shown in FIG. 75 is obtained.

The problem of FIG. 75 is that TFT 11n and TFT 1
If a characteristic deviation such as Vt of 1a occurs in each pixel, the current flowing through the EL element 15 varies from pixel to pixel. If the currents vary, the displayed image will appear grainy even in a uniform display such as white raster. In that respect, this problem does not occur in the configuration of FIG.

Therefore, when the screen size of the display panel is small and the influence of the parasitic capacitance 404 is small, the TFT 11f
Always use in the off state. When the screen size of the display panel is large and the influence of the parasitic capacitance 404 cannot be eliminated only by the operation of the TFT 11a, the gate signal line 17c is short-circuited with the logic of the gate signal line 17a to realize the pixel configuration of FIG. To do.

FIG. 84 shows a circuit block for driving the pixel configuration of FIG. A shift register 22c that drives the gate signal line 17c is formed, and the gate signal line 17c is driven. When driving with the pixel configuration of FIG. 1, the data of ST3 is always set to L and the gate signal line 17c is always set to Vgh.
It controls so that the voltage of is output. When used in the configuration of FIG. 82, the data input states (timing, logic, etc.) of the shift registers 22c and 22a may be the same.

The structure shown in FIG. 82 can also be realized by a current mirror structure. FIG. 83 shows the pixel structure. As shown in FIG. 83, the divided TFT 11a1 and TFT 11 are divided.
Whether or not n is operated for improving the drive current may be controlled by the potential (Vgh or Vhl) applied to the gate signal line 17c. When the TFT 11f is turned off, the current flowing through the source signal line 18 operates only in the TFT 11a.

FIG. 82 shows that the gate terminal of the switching TFT 11f is connected to the gate signal line 17c. That is, the on / off state of the TFT 11f is changed to the gate signal line 17
The point is that independent control can be realized without being affected by the potential state of a.

When the TFT 11f is constantly off, TF
T11n is in a state of being separated from the pixel. If the gate signal line 17c and the gate signal line 17a are logically short-circuited and used, the configuration shown in FIG. 75 is obtained.

Therefore, similar to the pixel configuration of FIG.
When the screen size of the display panel is small and the influence of the parasitic capacitance 404 is small, the TFT 11f is constantly used in the off state. The screen size of the display panel is large and the parasitic capacitance 404
When the influence of 1 cannot be eliminated only by the operation of the TFT 11a, the gate signal line 17c is short-circuited with the logic of the gate signal line 17a, and the drive current is increased to drive. Figure 8
The circuit block of FIG. 84 can also be applied to the pixel configuration of FIG.

In the structure of FIG. 84, the gate signal line 17
A shift register 22c for controlling c was newly formed and operated. However, the configuration is not limited to this.
The control logic of the gate signal line 17c is easy. Vgl or Vg at the gate terminal of the switching TFT 11f
This is because only the h voltage is applied. TFT 11n
All TFTs 11f in the display area 21 when not operating
The Vhg voltage may be applied to the gate terminal of the. TFT1
When operating 1n, the potential of the gate signal line 17a may be applied to the gate signal line 17c. Therefore, it is not necessary to separately use the shift register 22c as shown in FIG. That is, the data of the shift register 22a may be output to the gate signal line 17c as it is, or a gate circuit may be added so that the potentials of all the gate signal lines 17c become Vgh.

The driving method of the present invention will be described below. By multiplying the current flowing through the source signal line 18 by N times, the influence of the parasitic capacitance 404 is eliminated, and good image display with high resolution can be realized.

FIG. 87 is an explanatory diagram of another embodiment for increasing the current flowing through the source signal line. Basically, this is a method in which a plurality of pixel rows are selected at the same time, and the currents of the plurality of pixel rows are combined to charge and discharge the parasitic capacitance of the source signal line and the like, thereby significantly reducing the insufficient current writing. However, since a plurality of pixel rows are selected at the same time, the driving current per pixel can be reduced. Therefore, the current flowing through the EL element 15 can be reduced. Here, in order to facilitate the description, N = 10 will be described as an example (the current flowing through the source signal line is multiplied by 10).

In the present invention described with reference to FIG. 87 and the like, K pixel rows are simultaneously selected as pixel rows. The source driver IC applies N times the predetermined current to the source signal line 18. A current that is N / K times the current flowing through the EL element is programmed in each pixel. In order to make the EL element have a predetermined emission brightness, E
The time to flow to the L element is set to K / N time for one frame.
By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and good resolution and predetermined light emission luminance can be obtained.

That is, the current is passed through the EL element only during the K / N period of one frame, and the other period (1F (N-1)).
K / N) does not carry current. In this display state, image data display and black display (non-lighting) are repeatedly displayed for each 1F. That is, the image data display state becomes a temporally intermittent display (intermittent display) state. Therefore, the outline of the image is not blurred and a good moving image can be displayed. Further, since the source signal line 18 is driven by a current N times larger, it is not affected by parasitic capacitance and can be applied to a high-definition display panel.

First, in order to facilitate understanding, a method of selecting one pixel row and programming an N-fold current as described above will be described with reference to drive waveforms and the like.
FIG. 134 is an explanatory diagram thereof. Although the screen is illustrated as being horizontally long in the explanatory view, it is not limited to this and may be vertically long or may have another shape such as a circle.

FIG. 134 (a) shows the state of writing to the display image 21. In FIG. 134 (a), 87
Reference numeral 1 is a writing pixel row. Note that in FIG. 134A, the number of pixel rows written in the 1H period is one. Further, in the following embodiments, the pixel configuration of FIG. 1 will be described as an example, but the present invention is not limited to this, and the pixel configuration of the current mirror shown in FIGS. 21, 43 and 71 may be used. Further, it goes without saying that the present invention can also be applied to the pixel configurations of the voltage programming method shown in FIGS. 54, 67, 68, 103 and the like.

In FIG. 134 (a), the gate signal line 1
When 7a is selected, the current flowing through the source signal line 18 becomes T
It is programmed into FT11a. At this time, an off voltage is applied to the gate signal line 17b, and no current flows in the EL element 15. This is because when the TFT 11d is in the ON state on the EL element side, the capacitance component of the EL element 15 can be seen from the source signal line 18 and is affected by this capacitance so that the capacitor 19 cannot perform sufficiently accurate current programming. . Therefore, as shown in FIG. 134 (b), the pixel row to which the current is written is in the non-lighting state 312. The TFTs 11d of the other pixel rows are in the ON state, and the lighting state 31
It is 1. In addition, in the pixel configuration of the current mirror shown in FIGS.
The EL element 15 cannot be seen from the source signal line 18 even when a current flows through T11a. Therefore, FIG.
It is not necessary to set the non-lighting state as in 34 (b). That is, as shown in FIG. 134 (b), the writing pixel row is turned off 3
Setting 12 is not an essential condition of the invention.

FIG. 135 shows a voltage waveform applied to the gate signal line 17. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level).
The number of the selected pixel row is described in the lower part of FIG. Further, (1) and (2) indicate the selected pixel row number.

In FIG. 135, the gate signal line 17a
(1) is selected (Vgl voltage), and a program current flows from the TFT 11a of the selected pixel row toward the source driver 14 in the source signal line 18. This program current is N times the predetermined value (for simplicity, N = 10
As described below. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ). Therefore, the capacitor 1
9 is programmed so that a 10 times larger current flows through the TFT 11a. When the pixel row (1) is selected, the off voltage (Vgh) is applied to the gate signal line 17b (1) in the pixel configuration of FIG. 1, and no current flows in the EL element 15.

After 1H, the gate signal line 17a (2) is selected (Vgl voltage), and the TFT1 of the selected pixel row is selected.
Source signal line 1 from 1a toward source driver 14
A program current flows through 8. This program current is N times the predetermined value (for ease of explanation, N = 10 will be described). Therefore, the capacitor 19 has 10
It is programmed so that a double current flows through the TFT 11a. When the pixel row (2) is selected, the gate signal line 17b (2) is turned off (Vgh) in the pixel configuration of FIG.
Is applied, and no current flows through the EL element 15. However, the off voltage (Vgh) is applied to the gate signal line 17a (1) of the preceding pixel row (1), and the gate signal line 17b
Since the on-voltage (Vgl) is applied to (1), it is in a lighting state.

[0531] After the next 1H, the gate signal line 17a
(3) is selected, the off voltage (Vgh) is applied to the gate signal line 17b (3), and the EL element 15 of the pixel row (3) is selected.
No current flows through. However, the previous pixel row (1) (2)
To the gate signal lines 17a (1) (2) of the off voltage (Vg
h) is applied and the on-voltage (Vgl) is applied to the gate signal lines 17b (1) (2), so that the gate signal lines 17b (1) (17) are in a lighting state.

An image is displayed by synchronizing the above operation with the 1H synchronization signal. However, in the driving method of FIG.
A ten times larger current flows through the EL element 15. Therefore,
The display screen 21 is displayed with a brightness of about 10 times. Needless to say, in order to display a predetermined brightness in this state, the program current may be set to 1/10. However, if the current is 1/10, writing shortage occurs due to parasitic capacitance and the like. Therefore, it is the basic gist of the present invention to program with a high current and obtain a predetermined brightness by inserting the black screen 312.

However, the method of FIG. 134 is also within the scope of the present invention. That is, a current higher than the predetermined current is applied to the EL element 15
This is the concept that the parasitic capacitance of the source signal line 18 is sufficiently charged / discharged by allowing the current to flow to. That is, the EL element 15
It is not necessary to supply N times the current. For example, a current path is formed in parallel with the EL element 15 (a dummy EL element is formed, and this EL element is formed with a light-shielding film so as not to emit light), and the current is divided into the dummy EL element and the EL element 15. You can wash it. For example, when the signal current is 0.2 μA, the program current is 2.2 μA, and the TFT 11a
Flow 2.2 μA. Of this current, the signal current 0.
Flow 2μA to EL element 15 and 2μA to dummy EL
Flow to the element.

With the above configuration, the current flowing through the source signal line 18 is increased N times,
It is possible to program the driving TFT 11a so that N times the current flows, and to flow a current sufficiently smaller than the N times the current EL element 15. In the above method, as shown in FIG.
Without providing the non-lighting area 312, the entire display area 21 is almost or completely replaced with the image display area 31 as shown in FIG.
It can be 1.

However, theoretically, all programmed currents flow through the EL element 15 unless the dummy EL element or the like is formed. Therefore,
In FIG. 134, the display screen emits light with N times the brightness. In order to emit light with a predetermined brightness, a non-lighting display area 312 may be provided as shown in FIG. 136. FIG. 136 is an explanatory diagram of the method.

FIG. 136 (a) shows the state of writing to the display image 21. In FIG. 136 (a), 87
Reference numeral 1a is a writing pixel row. A program current is supplied from the driver IC 14 to each source signal line 18. Note that in FIG. 136 and the like, one pixel row is written in the 1H period. However, it is not limited to 1H at all,
The period may be 0.5H or 2H. Further, although the programming current is written in the source signal line 18, the present invention is not limited to the current programming method, and a voltage programming method in which the voltage is written in the source signal line 18 may be used.

In FIG. 136 (a), when the gate signal line 17a is selected, the source signal line 1 is selected as in the case of FIG.
The current flowing in 8 is programmed in the TFT 11a. At this time, an off voltage is applied to the gate signal line 17b, and no current flows in the EL element 15. This is TF on the EL element side
When T11d is in the ON state, the signal from the source signal line 18 to E
This is because the capacitance component of the L element 15 is visible and affected by this capacitance, a sufficiently accurate current program cannot be performed in the capacitor 19. Therefore, if the configuration of FIG. 1 is taken as an example, the pixel row in which the current is written becomes the non-lighting area 312 as shown in FIG. 136 (b).

Now, N (here, N =
If programmed with 10 times the current, the brightness of the screen will be 10 times. Therefore, 9 of the display area 21
The 0% range may be the non-lighting area 312. Therefore, if the horizontal scanning lines of the image display area are 220 lines (S = 220) of QCIF, 22 lines and the display region 311 can be set, and 220-22 = 198 lines can be set as the non-display region 312. Generally speaking, if the horizontal scanning line (the number of pixel rows) is S, the S / N area is the display area 311 and this display area 311 is made to emit light with N times the brightness. Then, the display area 311 is scanned in the vertical direction of the screen. Therefore, the area of S (N-1) / N is the non-lighting area 312. This non-lighting area is black display (non-light emission). Also,
The non-light emitting portion 312 is realized by turning off the TFT 11d. Although it is assumed that the light is turned on with N times the brightness, it goes without saying that the brightness is adjusted by the brightness adjustment and the gamma adjustment.
It goes without saying that the value should be doubled.

If programming is performed with a current of 10 times in the previous embodiment, the brightness of the screen is increased by 10 times, and 90% of the display area 21 should be the non-lighting area 312. . However, this is not limited to the case where the RGB pixels are commonly used as the non-lighting area 312. For example, 1/8 of the R pixel is the non-lighting area 312, 1/6 of the G pixel is the non-lighting area 312, and B pixel is
You may change 1/10 with the non-lighting area | region 312, and each color. Further, the non-lighting area 312 (or the lighting area 311) may be individually adjusted with RGB colors. In order to realize these, separate gate signal lines 17b are required for R, G, and B. However, by enabling the individual RGB adjustments described above, it becomes possible to adjust the white balance, which facilitates color balance adjustment for each gradation.

As shown in FIG. 136 (b), the pixel row including the write pixel row 871a is the non-lighting area 312, and the S / N range of the screen above the write pixel row 871a is the display area 311 ( If the write scan is from top to bottom of the screen, and vice versa if the screen is to be scanned from bottom to top). In the image display state, the display area 311 becomes a band and moves from the top to the bottom of the screen.

FIG. 137 shows the voltage waveform applied to the gate signal line 17. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level).
The number of the selected pixel row is described in the lower part of FIG. 137. Further, (1), (2), (3), ... Show the selected pixel row numbers.

In FIG. 137, the gate signal line 17a
(1) is selected (Vgl voltage), and a program current flows from the TFT 11a of the selected pixel row toward the source driver 14 in the source signal line 18. This program current is N times the predetermined value (for simplicity, N = 10
As described below. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ).

Therefore, the capacitor 19 is programmed so that a 10 times larger current flows through the TFT 11a.
When the pixel row (1) is selected, the off voltage (Vgh) is applied to the gate signal line 17b (1) in the pixel configuration of FIG. 1, and no current flows in the EL element 15.

After 1H (not limited to 1H, of course, for ease of explanation), the gate signal line 17a (2) is selected (Vgl voltage), and the TFT 11a of the selected pixel row is selected. A program current flows through the source signal line 18 toward the source driver 14. This program current is N times the predetermined value (for ease of explanation, N = 10 will be described). Therefore, the capacitor 19 is programmed so that 10 times the current flows through the TFT 11a. At this time, the gate signal line 1
The Vgl voltage (ON voltage) is applied to 7b (1). According to the embodiment of FIG. 136, the period in which the ON voltage is applied is the S / N period. After that, the gate signal line 17
Vgh (off voltage) is applied to b (1), and no current flows in the EL element 15 of the pixel row (1).

When the pixel row (2) is selected, as shown in FIG.
In the pixel configuration, the off voltage (Vgh) is applied to the gate signal line 17b (2), and no current flows in the EL element 15. However, the gate signal line 17a of the previous pixel row (1)
Since the off voltage (Vgh) is applied to (1) and the on voltage (Vgl) is applied to the gate signal line 17b (1), it is in a lighting state. According to the embodiment of FIG. 136, the period in which the ON voltage is applied is the S / N period. After that, Vgh (off voltage) is applied to the gate signal line 17b (2), and no current flows in the EL element 15 of the pixel row (2).

After the next 1H, the gate signal line 17a
(3) is selected, the off voltage (Vgh) is applied to the gate signal line 17b (3), and the EL element 15 of the pixel row (3) is selected.
No current flows through. However, the previous pixel row (1) (2)
To the gate signal lines 17a (1) (2) of the off voltage (Vg
h) is applied and the on-voltage (Vgl) is applied to the gate signal lines 17b (1) (2), so that the gate signal lines 17b (1) (17) are in a lighting state. By repeating the above operation, the display state of FIG. 136 is realized.

In the display of FIG. 136, one display area 31
1 moves downward from the top of the screen. When the frame rate is low, it is visually recognized that the display area 311 moves. In particular, it becomes easy to be recognized when the eyelids are closed or when the face is moved up and down.

To address this problem, the display area 311 may be divided into a plurality of areas, as shown in FIG. Figure 1
38 (b) divides the non-display area 312 into five. If the area obtained by adding these five areas has an area of S (N-1) / N, the brightness is equivalent to that in FIG. On the contrary, when viewed from the display area 311, the display area (lighting area) 311 is divided into six parts, and the part including the areas divided into six parts is configured to substantially match the S / N ( Drive)
The display brightness is equivalent to that of FIG.

As shown in FIG. 138 (b), it is not necessary that the divided display areas 311 be the same. Further, it is not necessary to make the divided non-display areas 312 equal.

As described above, the flicker on the screen is reduced by dividing the display area 311 into a plurality of areas. Therefore, flicker does not occur and good image display can be realized. The division may be finer. However, the more divided it is, the lower the moving image display performance becomes.

FIG. 139 shows a voltage waveform applied to the gate signal line 17. The difference between FIG. 139 and FIG. 137 is the operation of the gate signal line 17b. The gate signal lines 17b are turned on / off by the number corresponding to the number of divided screens (V
gl and Vgh) work. Since the other points are the same as those in FIG. 137, the description thereof will be omitted.

In the above embodiments, the pixel row selected simultaneously is one pixel row. FIG. 88 shows a method of simultaneously selecting a plurality of pixel rows. In FIG. 88, for ease of explanation,
Although description is made assuming that selection is performed simultaneously with five pixel rows, the present invention is not limited to this, and it is sufficient if the number of pixels is two or more. However, if the number of pixel rows selected at the same time increases, the driving TFT1
The variation absorption effect of 1a is reduced.

In the following embodiments, the pixel configuration of the current program shown in FIG. 1 will be described as an example, but the present invention is not limited to this. It goes without saying that the current mirrors shown in FIGS. 21, 43, and 71 are also effective. This is because the number of pixel rows selected at the same time becomes large, which facilitates charging and discharging of the parasitic capacitance 404 of the source signal line. In addition, the pixel configurations of the voltage program shown in FIGS. 54, 67, 68, 103, etc. are also effective. This is because, by increasing the number of pixel rows selected at the same time, the adjacent pixel rows can be precharged and can be applied to a high-definition display panel.

Also, here, for ease of explanation, the current flowing from the source driver IC 14 to the source signal line 18 (or the current drawn by the source driver IC 14 from the source signal line 18, the driving TFT 11a to the source signal line 18). The current flowing in is 10 times the predetermined value (N = 1
0) will be described.

Therefore, if the pixel rows selected at the same time are five pixel rows (K = 5), the five driving TFTs 11a operate. That is, a current of 10/5 = 2 times per pixel flows through the TFT 11a. If the pixel rows selected at the same time are two pixel rows, the two drive TFTs 11a operate. In other words, a current of 10/2 = 5 times per pixel is applied to the TFT1.
It flows to 1a.

Pixel rows selected at the same time are 5 pixel rows (K =
In case of 5), the program currents of the five TFTs 11a are added. For example, write pixel row 871a
Then, originally, if the write current Id is set and N = 10,
A current of Id × 10 is passed through the source signal line 18. The pixel row 871b (871b) adjacent to the write pixel row 871a
Reference numeral b is a pixel row that is used supplementarily to increase the amount of current to the source signal line 18. Therefore, the pixel (row) in which the image is written is 871a, and the pixel (row) that is additionally used for writing in the 871a is 871b).

Ideally, the TFTs 11a of the five pixels each supply a current of Id × 2 to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with a double current. However, in reality, each TFT of 5 pixels
Since the characteristics of 11 are deviated, the capacitor 19 of each pixel is
Variations occur in the programmed current. For example, the pixel (row) 871a has 1.8 times, and the four pixels (row) 871b have 2.2 times, 2.0 times, 1.6 times,
2.4 times the current is programmed. In this example, the write pixel row 871a is programmed with 1.8 times the current. Therefore, (2.0-1.8) /2.0=10
There is an error of%. However, the total current is 10
Doubled and kept at the specified value.

That is, the current programmed from the source driver 14 flows through the source signal line 18 as specified. However, a current corresponding to the characteristic variation flows in the selected pixel. Therefore, the larger the characteristic variation of the TFT 11a of each pixel, the more the target program current deviates from the set value. However, since the characteristics of the adjacent TFTs 11a are almost the same, uniform display can be realized even if the pixel rows selected at the same time are increased as shown in FIG.

The embodiments shown in FIGS. 87 and 88 are more effective for the display panel in which the TFT 11 is formed by the amorphous silicon technique than the display panel in which the TFT 11 is formed by the low temperature polysilicon technique. This is because the characteristics of the adjacent TFTs of the amorphous silicon TFT 11 are substantially the same. Therefore, even if the TFTs are driven by the added current, the drive current of each TFT is almost the target value.

In FIG. 88, the writing pixel (row) 87
K rows (K = 5) are simultaneously written with the image data of 1a. Therefore, the ranges of K rows (871a, 871b) are displayed in the same manner. When the same display is performed in this way, the resolution naturally lowers. To prevent this, FIG.
As shown in (b), the write pixel row 871 is set to the non-lighting display 312. Therefore, the resolution is not reduced.

After the next 1H, the same operation is performed with the position shifted by one pixel row as the write pixel row 871a. The non-lighted area 312 is also shifted by one pixel (row). Therefore,
Pixels (rows) that have been current programmed at the previous 1H are displayed.

As described above, the 871b to which the current data different from the original display data is written is not displayed. A complete image display can be realized by shifting the above operation line by line. In addition, the pixel row 871b that is used as an auxiliary
By the effect, the charging and discharging of the parasitic capacitance 404 can be realized sufficiently within 1H period.

FIG. 140 is an explanatory diagram of drive waveforms for realizing the drive method of FIG. 88. Similar to FIG. 135, the voltage waveform has an off voltage of Vgh (H level) and an on voltage of Vgl (L level). In addition, the number of the selected pixel row is described in the lower part of FIG. 140. Also,
(1), (2), (3), ... (6) represent the selected pixel row numbers. Therefore, the number of lines is 220 for the QCIF display panel and 48 for the VGA panel.
It is 0.

In FIG. 140, the gate signal line 17a
(1) is selected (Vgl voltage), and a program current flows from the TFT 11a of the selected pixel row toward the source driver 14 in the source signal line 18. Here, for ease of explanation, the write pixel row 871a is first described as the pixel row (1) th.

The program current flowing through the source signal line 18 is N times the predetermined value (N = 1 for the sake of simplicity).
It will be described as 0. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ). Also, description will be made assuming that five pixel rows are simultaneously selected (K = 5). Therefore, ideally, the capacitor 19 of one pixel has twice the current TF.
It is programmed to flow to T11a.

When the writing pixel row is the (1) th pixel row, (1), (2), (3), (4) and (5) are selected as the gate signal lines 17a as shown in FIG. . That is, the switching TFTs 11b and 11c of the pixel rows (1), (2), (3), (4) and (5) are in the ON state.
Further, the gate signal line 17b has a phase opposite to that of the gate signal line 17a. Therefore, pixel row (1) (2)
The switching TFTs 11d of (3), (4), and (5) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312.

Ideally, each of the TFTs 11a of the five pixels supplies a current of Id × 2 to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with a double current. Here, in order to facilitate understanding, the description will be made assuming that the characteristics (Vt, S value) of each TFT 11a match.

[0568] The pixel rows selected simultaneously are 5 pixel rows (K =
Since it is 5), the five driving TFTs 11a operate.
In other words, 10/5 = twice the current per pixel
It flows to 11a. The source signal line 18 has five TFTs.
A current added with the program current of 11a flows. For example, the current I originally written in the write pixel row 871a is
and a current of Id × 10 is passed through the source signal line 18. A write pixel row 871b for writing image data after the write pixel row (1) is an auxiliary pixel row used to increase the amount of current to the source signal line 18. However, since normal image data is written in the writing pixel row 871b later, there is no problem.

Therefore, the pixel row 871b displays the same as 871a during the 1H period. Therefore, the write pixel row 871a and the pixel row 871b selected to increase the current are at least in the non-display state 312. However, in the pixel configuration of the current mirror as shown in FIGS. 21, 43 and 71 and the pixel configuration of the voltage programming method as shown in FIG. 68, the display state may be set in some cases.

After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (6) is selected (Vgl voltage), and the program current flows from the TFT 11a of the selected pixel row (6) to the source driver 14 in the source signal line 18.
By operating in this way, regular image data is held in the pixel row (1).

After the next 1H, the gate signal line 17a
(2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (7) is selected (Vgl voltage), and the program current flows from the TFT 11a of the selected pixel row (7) to the source driver 14 in the source signal line 18.
By operating in this way, regular image data is held in the pixel row (2). One screen is rewritten by the above operation and scanning while shifting by one pixel row.

Although it is similar to FIG. 134, in the driving method of FIG. 140, each pixel is programmed with a double current (voltage). Therefore, the emission brightness of the EL element 15 of each pixel is ideally 2 Doubled. Therefore, the brightness of the display screen is twice the predetermined value.

In order to set this to a predetermined brightness, FIG.
As shown in FIG. 7, the non-display area 312 may include a half of the display area 21 including the write pixel row 871. Since this has been described with reference to FIG. 137 and the like, description will be omitted.

The larger the area of the black display area (non-display area) 312 in the display screen 21, the higher the moving image display performance. Therefore, as shown in FIG. 141, the non-display area 311 may be reduced and the area of the non-display area 312 may be increased.

As shown in FIG. 87, the current to be programmed in each pixel is doubled and the area of the lighting region 311 is 1 of the display screen 21.
If it is / 2, a predetermined display brightness can be obtained. However, as shown in FIG. 141, the lighting area 311 is displayed on the display screen 21.
If it is smaller than ½ of, the screen becomes dark. In order to obtain a predetermined brightness, the current programmed in each pixel may be increased. For example, the display area (lighting area) 311
Is ⅕ of the area of the display screen 21, and if five pixel rows (K = 5) are selected at the same time, the current (voltage) to be programmed in one pixel row may be five times the predetermined value. . The current flowing through the source signal line 18 is 5 × 5 pixel rows = 25 times.

In any case, in the embodiment of the present invention, the program current (voltage) can be adjusted by changing the current (voltage) supplied to the source signal line 18. That is, the current flowing through the source signal line 18 can be adjusted only by adjusting the reference current (voltage) of the source driver 14. Two
Whether the pixel rows are turned on at the same time, the 5 pixel rows are turned on at the same time, or only one pixel row is selected depends on the data to the ST * terminal applied to the shift register 22 of the gate driver 12 shown in FIG. Can be set with. Therefore, the specifications of the source driver 14 do not depend on the number of pixels to be selected. Also, the brightness of the screen depends on the gate signal line 17
Since it can be adjusted by turning on / off b, the output current from the source driver 14 is not changed by adjusting the brightness of the screen 21. Therefore, the gamma characteristic of the EL element 15 may be determined for one current. for that reason,
The configuration of the source driver 14 is extremely easy and highly versatile. It goes without saying that the above items can be applied to other embodiments of the present invention.

In the above-mentioned embodiments, one selected pixel row is arranged (formed) for each pixel row. The present invention is
The present invention is not limited to this, and one selection gate signal line may be arranged (formed) in a plurality of pixel rows.

FIG. 294 is an example thereof. For ease of explanation, the pixel configuration will be described mainly by exemplifying the case of FIG. In FIG. 294, the selection gate signal line 17a in the pixel row simultaneously selects three pixels (16R, 16G, 16B). The R symbol means a red pixel relation, the G symbol means a green pixel relation, and the B symbol means a blue pixel relation.

Therefore, the pixel 16R, the pixel 16G and the pixel 16B are simultaneously selected by the selection of the gate signal line 17a to be in the data writing state. The pixel 16R writes data from the source signal line 18R to the capacitor 19R, and the pixel 16G writes data from the source signal line 18G to the capacitor 19G. The pixel 16B writes data from the source signal line 18B to the capacitor 19B.

The TFT 11d of the pixel 16R is connected to the gate signal line 17bR. In addition, the TFT of the pixel 16G
11d is connected to the gate signal line 17bG, and is connected to the pixel 16B.
The TFT 11d is connected to the gate signal line 17bB. Therefore, the EL element 15R of the pixel 16R and the pixel 1
The 6G EL element 15G and the pixel 16B EL element 15B can be controlled to be turned on and off separately. That is, the EL element 15R, the EL element 15G, and the EL element 15B can individually control the lighting time and the lighting cycle by controlling the respective gate signal lines 17bR, 17bG, and 17bB.

To realize this operation, in the configuration of FIG. 2, a shift register 22 for scanning the gate signal line 17a, a shift register 22 for scanning the gate signal line 17bR, and a shift for scanning the gate signal line 17bG. It is appropriate to form (arrange) four registers 22 and a shift register 22 that scans the gate signal line 17bB.

FIG. 295 shows the arrangement of the pixels 16. In FIG. 295, the pixels are formed in a horizontal stripe shape (note that the conventional configuration is generally a vertical stripe shape). By arranging the pixels in a horizontal stripe shape, the connection between the gate signal line 17 and the switching element 11 becomes easy, and the pixel layout becomes easy. In addition, an EL element made of a polymer material can be easily manufactured by inkjet.

Although the pixels are formed in the horizontal stripes in FIGS. 294 and 295, it goes without saying that the pixels may be formed in the vertical stripes as in the conventional case. In addition, a reverse bias voltage applying method, a block driving method, a Vbb voltage control method, an RG, which will be described below or have been described.
It is appropriate to combine with the other embodiments described in this specification such as a configuration in which each voltage of B is separated, a system using the punch-through voltage of the TFT 11b, the system of FIG. 241, a configuration of adding a dummy pixel row, and the like. Needless to say.

FIG. 296 shows operation waveforms of the pixel configuration of FIG. 294. Note that, for ease of explanation, description will be made assuming that one pixel row (of course, if counting with RGB, this means three pixel rows) is selected. However, it goes without saying that a driving method of simultaneously selecting a plurality of pixel rows can be realized as described with reference to FIGS. 87, 88, 142, and the like. In addition, as described in FIG. 252,
Although it is necessary to control the timing of the gate signal line even within the range of the 1H period, here, in order to facilitate the description, it is assumed that the selection of the pixel row by the gate signal line 17a is in the 1H period. The above items also apply to other driving methods and panel configurations described in this specification.

In FIG. 296, when the write pixel row is the (1) th pixel row, the gate signal line 17a is set to the pixel 1
6 blocks (it is easier to understand if this is considered as one pixel row) are selected (see also FIG. 294). That is, the pixel 16R, the pixel 16G, and the pixel 16B are selected. Therefore, 16R of pixel row (1),
The switching TFT 11b and the TFT 11c of 16G of the pixel row (1) and 16B of the pixel row (1) are in the ON state.

The pixel 16R in the pixel row (1) writes the image data from the source signal line 18R in the capacitor 19R. In addition, the pixel 16G in the pixel row (1) has the source signal line 1
Write the image data from 8G to the capacitor 19G,
The pixel 16B in the pixel row (1) writes the image data from the source signal line 18B in the capacitor 19B.

Note that, in order to facilitate the explanation, in FIG. 296, it is assumed that each pixel is programmed so that N times (N = 2) current flows in the EL element 15, and 1 / frame of 1 frame (1 field) is assumed. It is assumed that a current flows through the EL element 15 during the N period. However, it goes without saying that other embodiments may be implemented, as described herein. Also, by increasing the N value, the influence of the parasitic capacitance 404 of the source signal line 18 can be ignored.
It goes without saying that the image data can be easily written in the pixel 16. That is, it is not limited to N = 2.
Further, it goes without saying that N is not limited to an integer and can be realized with a value such as 2.5. Also,
The selection time of the gate signal line 17a is not limited to 1H and may be 2H or more.

The gate signal line 17bR, the gate signal line 17bG and the gate signal line 17bB in the pixel row (1) are in the opposite phase to the gate signal line 17a. Therefore,
At least the switching TFT 11d of the pixel 16R, the pixel 16G, and the pixel 16B of the pixel row (1) is in the off state, and the EL elements (15R, 15G, 1
No current is flowing in 5B). That is, non-lighting state 3
Twelve.

After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (2) is selected (Vgl voltage), and the pixels 16R, 16G and 16 of the selected pixel row (2) are selected.
Source signal lines 18 (18R, 18G, and 18B, respectively) from the TFT 11a of B to the source driver 14
The program current flows to. By operating in this way, the image data is held in the pixels 16R, 16G, and 16B of the pixel row (1).

After the next 1H, the gate signal line 1
7a (2) becomes non-selected, and gate signal line 17b (2)
Is applied with an on-voltage (Vgl). At the same time,
The gate signal line 17a (3) is selected (Vgl voltage),
A program current flows through the source signal line 18 from the TFT 11a of the selected pixel row (3) toward the source driver 14. By operating in this way, the image data is held in the pixel row (2). One screen is rewritten by scanning the above operation while shifting it by one pixel row.

Next, the operation of the gate signal line 17b shown in FIG. 296 will be mainly described. The gate signal line 17 is provided in the pixel 16R.
bR is connected. The gate signal line 1 is provided for the pixel 16G.
7bG is connected. A gate signal line 17bB is connected to the pixel 16B. Therefore, pixel 1
6R can control on / off the current flowing through the EL element 15R by the gate signal line 17bR. Similarly, pixel 1
6G can control on / off the current flowing through the EL element 15G by the gate signal line 17bG, and the pixel 16B can control on / off current flowing through the EL element 15B by the gate signal line 17bB.

In FIG. 296, the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB have the same waveform in each pixel row. Therefore, EL
The elements 15R, 15G and 15B are simultaneously turned on / off (lighted and non-lighted). In addition, FIG. 296 shows that EL is set every 4H.
The element 15 is turned on and off, but is not limited to this. It may be every 1H or more. In principle, the EL element 15 may be turned on / off at a cycle of 1H or less.

[0593] However, if the on / off cycle is too fast, moving image blur occurs in the moving image display. Therefore, EL
It is necessary that the interval between turning on, turning off the light, and turning on the device 15 be 0.5 msec or more. When this cycle is short, the image is not completely displayed in black due to the afterimage characteristic of human eyes, and the image becomes blurry and the resolution is lowered. Further, the display state of the data holding type display panel is set. However, the on / off cycle is 100 msec.
When it is above, it looks like blinking. Therefore, the ON / OFF cycle of the EL element is 0.5 μsec or more and 100 msec.
Should be: More preferably, the on / off period should be 2 msec or more and 30 msec or less. More preferably, the on / off cycle is 3 msec or more and 20 m
It should be less than sec.

From the above relationship, the number of black screens 312 for turning on / off the screen is determined from the time required for one frame (one field) and the cycle or number of signals (Vgh, Vgl) applied to the gate signal line 17b. It Although a good moving image display can be realized by using only one black screen 312, flicker on the screen is easily visible. Therefore, it is preferable to divide the black 312 insertion part into a plurality of parts. However, if the number of divisions is too large, moving image blur occurs.
The number of divisions should be 1 or more and 8 or less. More preferably, it is 1 or more and 5 or less.

According to the present invention, the TFT 11d is turned off,
Even if the current flowing through the EL element 15 is cut off, the
When 11d is turned on, the same current as the previously flowing current can be passed through the EL element 15. This is because the current value to be passed is stored in the capacitor 19 of the pixel (analog memory). This matter is a great feature of the present invention. That is, it is possible to freely control the on / off of the current flowing through the EL element 15.

In FIG. 296, the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB have the same waveform in each pixel row. In addition, the pixel rows are selected by sequentially shifting the selected pixel rows every 1H. Therefore, the light emitting positions of the EL elements 15R, 15G, and 15B move from the top to the bottom of the screen 21 at high speed. The on / off control, the black screen 312 insertion ratio, and the number of black screens 312 inserted can be easily realized by controlling the ST data to the shift register 22 described with reference to FIG. Needless to say, the Vgh data applied to the gate signal line 17b may be controlled in parallel.

Although the signal applied to the gate signal line 17 is a periodic signal, it is not limited to this.
It may be an aperiodic signal. However, the brightness of the screen changes if the total time of turning on or off the EL element 15 is different. In addition, a color balance shift occurs. Therefore, in one frame (one field) period, it is necessary to set the sum of the times when the EL element 15 is turned on or off to a constant value. As a special case, there is a case where the total sum of the times when the EL element 15 is turned on or off in a period of two frames (two fields) or more may be set to a constant value. There are cases where one frame (field) is very high speed and cases where FSC (frame sequential control) driving is performed.

In FIG. 296, the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB have the same waveform in each pixel row. In addition, the pixel rows are selected by sequentially shifting the selected pixel rows every 1H. Figure 2
In 97, the waveform applied to the gate signal line 17bR is 2H.
The waveform applied to the gate signal line 17bG is changed in a cycle of 3H, and the waveform applied to the gate signal line 17bB is changed in a cycle of 4H. Other matters are shown in Figure 2.
The description is omitted because it is the same as 96.

Note that in FIG. 297, the gate signal line 17b
The waveform applied to R is changed in a 2H cycle, the waveform applied to the gate signal line 17bG is changed in a 3H cycle, and the waveform applied to the gate signal line 17bB is changed in a 4H cycle. To facilitate
It is not limited to 2H, 3H and the like. At least a gate signal line 16bR connected to the pixel 16R,
A gate signal line 16bG connected to the pixel 16G and a signal waveform applied to one or more gate signal lines 17b of the gate signal lines 16bB connected to the pixel 16B are different from those of the other gate signal lines 17b. Is.

When driven as shown in FIG. 297, the EL element 1
The light emission positions of 5R, 15G, and 15B move from the top of the screen 21 to the bottom at high speed. At this time, the EL element 15R
The ON / OFF (lighting / non-lighting) cycle, the EL element 15G ON / OFF (lighting / non-lighting) cycle, and the EL element 15B ON / OFF (lighting / non-lighting) cycle are different. EL element 15
The occurrence of flicker becomes less noticeable by changing the lighting cycle of.

The ON / OFF control, the black screen 312 insertion ratio, and the number of black screens 312 inserted can be easily realized by controlling the ST data to the shift register 22 described with reference to FIG. Of course, it goes without saying that the control of the signal (Vgh, Vgl) data applied to the gate signal line 17b may be controlled in parallel.

In FIG. 298, the Vgl period applied to the gate signal line 17bR is set shorter than that of the other gate signal lines 17b. Therefore, the lighting time of the EL element 15R connected to the gate signal line 17bR becomes longer (pixel 16R
The TFT 11d is turned on for a longer period). Therefore, the R emission brightness of the display screen 21 becomes strong.

As described above, by individually controlling the signals applied to the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB, the color balance of the screen 21 and the occurrence of flicker can be suppressed. That is, the EL element 1
By controlling the time, timing, and cycle of turning on 5, the color balance of the screen 21 and the occurrence of flicker can be suppressed.

In FIG. 298, the gate signal line 17b
The waveform applied to G is changed in a 3H cycle, and the waveform applied to the gate signal line 17bB is changed in a 4H cycle. This is for facilitating the drawing.
It is not limited to 3H or the like. At least the gate signal line 16bR connected to the pixel 16R and the pixel 16R
Of the signal waveforms applied to the gate signal line 16bG connected to G and one or more of the gate signal lines 17bB connected to the pixel 16B, the TFT 11
The application time of the signal for turning on (or turning off) d is different from that of the other gate signal lines 17b.

When driven as shown in FIG. 298, the EL element 1
The light emission positions of 5R, 15G, and 15B move from the top of the screen 21 to the bottom at high speed. At this time, the EL element 15R
ON (lighting) time and EL element 15G ON (lighting)
The time and the ON (lighting) time of the EL element 15B can be different. Therefore, the color balance of the screen can be adjusted, and the occurrence of flicker is less noticeable. This kind of color balance adjustment is performed by the user on the screen 21.
It is preferable to be configured so that adjustment can be performed while watching. This adjustment is easy. This is because the ON number of ST data input to the shift register 22 shown in FIG. 2 and the like may be increased or decreased. Further, this on / off control, the insertion ratio of the black screen 312, and the number of black screens 312 to be inserted are set in the ST to the shift register 22 described with reference to FIG.
This can be easily achieved by controlling the data. Of course, the signals (Vgh, Vg applied to the gate signal line 17b)
l) It goes without saying that the data control may be controlled in parallel.

Note that FIGS. 294 to 298 have been described by exemplifying the case where the pixel configuration is FIG. However, it goes without saying that the above embodiment can be applied to other pixel configurations. For example, FIG. 21, FIG. 43, FIG. 71, FIG.
2, FIG. 54, FIG. 68, FIG. 103, etc. That is, the technical idea described in FIGS. 294 to 298 can be applied to other configurations. For example, in FIG. 360, the pixel has a current mirror structure (see FIGS. 21 and 43, etc.).
It is an example in the case of. Also, FIG. 361 shows an example of the pixel configuration of the voltage program illustrated in FIG. 54 and the like.

The driving method described with reference to FIGS. 88, 87, 140, etc. is a driving method of simultaneously selecting a plurality of pixel rows. In this drive system, attention must be paid to the following points.
From the conclusion, it is preferable to provide (form) pixels (rows) (dummy pixels (rows)) that do not contribute to display. The above reasons will be described below.

FIG. 246 is an explanatory diagram of a driving method for simultaneously selecting two pixel rows. In FIG. 246, the pixel 16
The state where a and 16b are selected is illustrated. The TFT 11a of the pixel 16a and the TFT 11a of the pixel 16b respectively supply the current Idd to the source signal line 18.

For ease of explanation, the T of each pixel is
There is no variation in the current flowing through the FT 11a, and 2 × Id
Let d = Iw. That is, the source driver circuit 14 absorbs the current Iw from the source signal line 18, and the current Iw is absorbed.
Is divided into two equal parts and a current is programmed in the capacitor 19 of each pixel. For example, if Idd = 15 nA, Iw
= 30 nA.

As shown in FIG. 247 (a), two write pixel rows 871 (871a, 871b) are selected and sequentially selected from the upper side to the lower side of the screen 21. However, as shown in FIG. 871 (b), when reaching the lower side of the screen, the writing pixel row 871a exists but the writing pixel row 871b disappears. That is, only one pixel row is selected. Therefore, all the current Iw applied to the source signal line 18 is written in the pixel row 871a. Therefore, Iw
= Idd, so that twice the current is programmed in the pixel as compared with the pixel row 871a in FIG. 247 (a).

To solve this problem, the present invention is shown in FIG.
As shown in (b), a dummy pixel row 2471 is formed (arranged) on the lower side of the screen 21. Therefore, when the selected pixel row is selected up to the lower side of the screen 21, the screen 21
The last pixel row and the dummy pixel row 2471 are selected. Therefore, the current of Idd = Iw / 2 as specified is written in the writing pixel row in FIG. 247 (b).

FIG. 248 shows the state of FIG. 247 (b). As is clear from FIG. 248, the selected pixel row is displayed on the screen 2
When the pixel 16b on the lower side of 1 is selected, the screen 2
The last pixel row 2471 of 1 is selected. Also, FIG.
A pixel row 2471 is formed (arranged) as shown in FIG. However, the dummy pixel row 2471 is arranged outside the display area 21. That is, the dummy pixel row 2471 is not illuminated, is not illuminated, or is invisible even when illuminated.

Even if the dummy pixel row 2471 is formed (arranged) as shown in FIGS. 248 and 249, the gate signal line 17b and the like are shared by the lighting control line 1791 as described with reference to FIG. 179. It goes without saying that the block lighting drive can be carried out. Needless to say, it can be combined with reverse bias driving (see FIG. 250).

In FIG. 247, dummy pixels (rows) 2471 are provided (formed or arranged) on the lower side of the screen 21, but the invention is not limited to this. For example, in FIG.
As shown in FIG. 1A, when scanning is performed from the bottom side to the top side of the screen (vertical upside-down scanning), dummy pixel rows 2471 are also provided on the top side of the screen 21 as shown in FIG.
Should be formed. That is, the dummy pixel rows 2471 are formed (arranged) on the upper side and the lower side of the screen 21, respectively (see FIG. 254). With the above configuration, it is possible to support upside down scanning of the screen.

The above-mentioned embodiment is a case where two pixel rows are simultaneously selected. The present invention is not limited to this,
For example, a method of simultaneously selecting 5 pixel rows may be used.

FIG. 255 is an explanatory diagram of a driving method for simultaneously selecting 5 pixel rows. As shown in FIG. 255, four pixel dummy pixel rows 2471 are formed on the upper and lower sides of the screen.

FIG. 271 is an explanatory diagram of a driving method of the display panel of FIG. 255. Iw from the source driver circuit 14
The description will be made assuming that a current of 5 × Idd is output (or absorbed). The current Idd is a current written in each pixel (programmed current). Needless to say, Idd varies depending on the displayed image.

In the driving system in which 5 pixel rows are selected at the same time,
The source driver circuit 14 outputs a current which is 5 times the current Idd written in the pixel. In FIG. 271 (a), the screen 21
Only the uppermost pixel is selected. However, since Iw = 5 × Idd in this state, a current which is five times the predetermined value is written in the write pixel row 871.

To solve this problem, according to the present invention, FIG.
As shown in (a), four dummy pixel rows 24
71a are selected at the same time. That is, the four dummy pixel rows 2471a and the write pixel row 871 in one display area are simultaneously selected. Therefore, since Iw = 5 × Idd, a predetermined current Idd is programmed in the pixel row 871 selected in FIG. 271 (a).

In FIG. 271 (b), two write pixel rows 871 in the display area 21 are selected and the dummy pixel row 24 is selected.
One of 71a is not selected, but three are selected. Therefore, the total number of selected pixel rows is five. Therefore, I
Since w = 5 × Idd, a predetermined current Idd is programmed in the two pixel rows 871 selected in FIG. 271 (b).

Similarly, in FIG. 271 (c), the display area 2
Three write pixel rows 871 of 1 are selected, two dummy pixel rows 2471a are not selected, and two dummy pixel rows 2471a are selected. Therefore, the total number of selected pixel rows is five. Therefore, since Iw = 5 × Idd, FIG. 271 (c).
A predetermined current Idd is programmed in the two pixel rows 871 selected in.

As described above, in FIG. 271 (d), four write pixel rows 871 in the display area 21 are selected, and three dummy pixel rows 2471a are not selected, but one is selected. Also, in FIG. 271 (e), 5 of the display area 21 is displayed.
The writing pixel row 871 of the book is selected, and the dummy pixel row 2 is selected.
471a is not selected. As described above, the five pixel rows are sequentially selected (FIGS. 271 (f) (g) (h)). Screen 2
When the lower side of 1 is reached, the number of selected dummy pixel rows 2471b increases every 1H.

By driving as described above, even if the number of pixel rows to be selected simultaneously increases, when selecting the upper side or the lower side of the screen 21, the pixel rows including the dummy pixel row 2471 can be set to a constant value. Therefore, the current value output by the source driver circuit 14 can be fixed to the number of pixel rows of the image data selected simultaneously. Therefore, the configuration of the source driver circuit 14 is simplified, and a target predetermined current (voltage) is written in each pixel.

As described above, in the driving method in which five pixel rows are simultaneously selected, 5-1 = 4 dummy pixel rows may be formed on one side of the screen. That is, it is only necessary to form or arrange dummy pixel rows of (number of pixel rows-1) or more selected simultaneously.

Further, the above embodiments are the embodiments in which two pixel rows are simultaneously selected and the one in which five pixel rows are simultaneously selected. The present invention is not limited to this, and three pixel rows or more pixel rows may be simultaneously selected.

Further, in the above embodiments, it was explained that adjacent pixel rows are simultaneously selected, but the present invention is not limited to this. For example, you may select every other pixel row,
You may choose at random.

In the above embodiments, when selecting a plurality of pixel rows, the dummy pixel row 2471 is selected at the beginning or the end of the scanning of the screen 21, and the current Iw flowing through the source driver circuit 14 is set to a constant value. It is a thing. of course,
The present invention forms or arranges dummy pixel rows, and is not limited to making the current flowing through the source driver circuit 14 a constant value.

FIG. 272 shows a driving method in which the dummy pixel row 2471a is turned on while the write pixel row 871a is not selected. Also, the writing pixel row 871a
Is one pixel row, but is not limited to this,
It goes without saying that a plurality of pixel rows may be used as in FIG. As a case of performing such driving, a case of forming the gate driver circuit 12 directly on the array substrate 49 (configuration having a built-in gate driver) is exemplified.

With the structure with a built-in gate driver, it is difficult to form a complicated circuit from the viewpoint of yield or formation area. Therefore, the gate driver circuit 12 is formed with a circuit configuration that is as simple as possible. In order to simplify the circuit configuration, the operation of the formed gate driver circuit 12 may be restricted.

For example, even if data (ST) is input to the shift register 22 of the gate driver circuit 12, the ON signal (Vgl) is output to the gate signal line 17a only after 2-3 clocks (clock is set to 1H). It is illustrated that it does not. However, after the ON data is output to the gate signal line 17a (1), the ON data position is sequentially shifted in synchronization with the 1H clock.

As described above, if the gate signal line 17a (1) is not selected after 2-3 clocks, no pixel row is selected for 2-3 clocks. During this period, the output of the source driver circuit 14 is preferably set to 0 (no current input / output). However, the output stage of the source driver circuit 14 is composed of a constant current circuit. Therefore, it is difficult to completely set the flowing current to zero. When a current flows through the source signal line 18 (the source driver circuit 14 absorbs the electric charge of the source signal line 18), the potential of the source signal line 18 is lowered. When the potential of the source signal line 18 decreases, the potential of the capacitor 19 of each pixel 16 may also decrease. When the potential of the capacitor 19 decreases, the potential of the gate terminal of the TFT 11a tends to decrease.
a is the direction in which the current flows more. This state remarkably appears when the screen is in the black display state. TF of each pixel
This is because the T11a causes a black float when a current flows.

To address this problem, when none of the gate signal lines 17 in the display region 21 is selected (state), the dummy pixel row 2471 is selected and driven so that the current flows through the source signal line. That is, dummy pixel row 2
The switching TFT 11 of 471 is turned on, and the impedance of the driving TFT 11a is lowered. Therefore, the current flowing into the source driver circuit 14 is configured to be supplied from the TFT 11a of the dummy pixel row 2471.

Also, what is important is that the output stage circuit of the source driver circuit 14 is turned off as much as possible in a state where no pixel row in the display region 21 is selected.

In FIG. 272 (a1), it is assumed that the start signal is applied to the shift register 22 of the gate driver built-in circuit 12. 272 (a2) corresponds to FIG.
This is 1H after 72 (a1). Similarly, FIG.
2 (a3) is after 1H, and FIG. 272 (a4) is after 1H.

In FIG. 272 (a), none of the gate signal lines in the display area 21 is selected in the first 2H period, and the 3H period is not used.
The subsequent pixel row (1) is first selected in FIG. 272 (a3), and then shifted by one pixel row in FIG. 272 (a4), and the pixel row (2) is selected.

In FIG. 272 (a1) (272), no pixel row is selected. As a countermeasure, the dummy pixel row 2471a is selected, and the TFT1 is set in the dummy pixel row 2471a so as not to change the potential of the source signal line 18.
The current is supplied from 1a.

As described above, by supplying the current from the dummy pixel row 2471a, it is possible to realize good image display without blackening. Also, the white balance of the screen does not change.

In FIG. 272 (a), the dummy pixel row 2471a closer to the source driver circuit 14 is selected, but the present invention is not limited to this. For example, as shown in FIG. 272 (b), the dummy pixel row 2471b on the side far from the source driver 14 may be selected. Further, both the dummy pixel rows 2417a and 2471b may be selected.

Further, the driving method of FIG. 272 (b) is the same as that of FIG.
The operation is the same as 72 (a). In FIG. 272 (b1),
A start signal is applied to the shift register 22 of the circuit 12 with a built-in gate driver, and FIG.
This is 1H later than (b1). Similarly, FIG.
(B3) is after 1H, and FIG. 272 (b4) is after 1H.

As in the case of FIG. 272 (a) of FIG. 272 (b), no gate signal line in the display area 21 is selected in the first 2H period, and the first pixel row in FIG. 272 (b3) after 3H. FIG. 272 (b4) shows that the pixel row (2) is selected by shifting the pixel row by 1 pixel row after (1) is selected. As shown in FIG. 272 (b), it is easier to stabilize the potential of the source signal line 18 by selecting the dummy pixel row 2471b farther from the source driver circuit 14. This state is shown in FIG.

Although the number of pixel rows to be selected is one in the embodiment of FIG. 272, this is not restrictive.
For example, it goes without saying that the present invention can also be applied to a driving method for selecting a plurality of pixel rows as shown in FIG. In addition, in the driving method for selecting a plurality of pixel rows,
For the purpose of solving the problem of black floating or image quality change that occurs when no pixel row in the display area 21 is selected, it is not necessary to form a plurality of dummy pixel rows 2471 as shown in FIG. Absent. As shown in FIG. 272, there may be one dummy pixel row 2471. This is because the potential of the source signal line 18 and the like can be stabilized with this one dummy pixel row.

Also, dummy pixel rows 2471a and 2471
The b may change the dummy pixel row 2471 to be selected depending on the scanning direction of the screen 21 (for example, FIGS. 247 and 251).

In FIG. 272, during the period of one frame (or one field), the dummy pixel row 24 is selected in a state where no pixel row in the display area 21 is selected.
It was to select 71. However, in the actual driving state, the pixel row may not be selected in one horizontal scanning period.

FIG. 252 is an operation waveform diagram for explaining this state. In the display device of the present invention, a pixel row is selected with a clock of 1H (1 horizontal scanning period), and the selected pixel row is sequentially shifted. However, even in the 1H period, the pixel row is selected in the predetermined period.

Basically, the off voltage (Vgh) is applied to the gate signal line 17b of the selected pixel row for the entire period of 1H. In FIG. 252, when the pixel row number is 1, the off voltage is applied to the gate signal line 17b of the pixel row (1).
Further, when the pixel row number is 2, the off voltage is applied to the gate signal line 17b of the pixel row (2).

On the other hand, the selection voltage (Vgl) is applied to the gate signal line 17a in a period shorter than 1H. Therefore, when the pixel row number is 1, the pixel row (1) is not selected in the periods a and b. The reason why the non-selected period is generated as described above is that the punch-through voltage is likely to occur when the timing of changing the gate signal line 17b and the timing of changing the gate signal line 17a coincide with each other. This is because when the punch-through voltage is generated, the desired voltage (current) is not retained in the capacitor 19 and the emission brightness of the EL element 15 varies.

At least the period a shown in FIG. 252 is preferably secured. The period of b may be 0 in some cases. This may be determined in consideration of the timing of ON / OFF control of the EL element 15. Basically, from the timing when the gate signal line 17b changes from Vgl to Vgh (that is, non-selected state), at least 1H of 1
It is preferable to select the gate signal line 17a after a time of / 64 or more and a time of 1/8 or less of 1H has elapsed. Further, preferably, 1 / H of 1H or more for 1/32 time of 1H or more
It is preferable to select the gate signal line 17a after a time of / 8 or less has elapsed. Alternatively, the gate signal line 17b
From the timing when Vgl changes to Vgh (that is, the non-selected state), at least 0.5 μsec or more 20
It is preferable to select the gate signal line 17a after a lapse of μsec or less. Furthermore, preferably 1 μsec
After a lapse of 10 μsec or less, the gate signal line 17
It is preferable to select a. Further, it is more preferable to apply the precharge (discharge) voltage described in FIG. 52 or the like during the period a or the period b.

[0648] While the gate signal line 17a is being selected, the switching signal CSW shown in Fig. 252 is Vgh. The output stage of the source driver 14 is controlled to be turned off by the Vgl level of the switching signal CSW. The dummy pixel row 2471 described with reference to FIG. 272 is controlled to be selected by the Vgl level of the switching signal CSW. By configuring or operating as described above, good image display can be realized without blackening. Further, it is possible to prevent a change in the white balance of the screen from occurring.

In FIG. 253, the dummy pixel 24
Although the reference numeral 71 is shown as forming the EL element 15 and the TFT 11d, the dummy pixel 2471 basically supplies a current to the source signal line 18 (depending on the pixel configuration,
The current is absorbed from the source signal line 18). Therefore, the EL element 15 is not necessary. On the contrary, EL element 1
When 5 and the like are formed, the EL element 15 lights up, which causes a problem.

According to the present invention, the dummy pixel 2471 is shown in FIG.
As shown in the figure, the EL element 15 and the like are not formed. The capacitor 19b for generating the punch-through voltage may or may not be added. However, in the case where the pixel 19 in the display area 21 for forming the punch-through voltage is formed, it is preferable that the dummy pixel 2471 is also formed. This is because the current flowing through the TFT 11a of the dummy pixel 2471 is made equal to the current flowing through the TFT 11a of the pixel 16 in the display area 21.

FIG. 258 shows the case of the pixel configuration of FIG.
In the pixel configuration of the current mirror shown in FIGS. 21, 43, and 71, as shown in FIG. 259, in the dummy pixel 2471, the driving TFT 11b and the EL element 15 are deleted. In the case of the pixel configuration of the voltage program shown in FIGS. 54, 67, 103, etc., as shown in FIG. 260, the switching TFT 11b and the capacitor 19a are used. This is because in the voltage programming method, no current is supplied from the pixel driving TFT to the source signal line 18.

The dummy pixel 2471 shown in FIGS. 258 and 259 does not need to emit light. Therefore,
As shown in 56, the pixel electrode 4 of the dummy pixel 2471
No EL film is formed on No. 8. As shown in FIG. 256, an insulating film 2561 is formed on the pixel electrode 48 to bring it into an insulating state. Alternatively, as shown in FIG. 257, the pixel electrode 48 of the dummy pixel 2471 and the metal film of the cathode 46 are electrically short-circuited. With this configuration, the potential of the pixel electrode 48 is stable.

Similar to FIG. 136, when one display area 311 moves downward from the top of the screen as shown in FIG. 141,
When the frame rate is low, it is visually recognized that the display area 311 moves. In particular, it becomes easy to be recognized when the eyelids are closed or when the face is moved up and down.

To solve this problem, the display area 311 may be divided into a plurality of areas, as shown in FIG. Figure 1
42 (b) divides the non-display area 312 into three. If the area obtained by adding these three has an area of S (N-1) / N, the brightness becomes equivalent to that in FIG.

FIG. 143 shows the voltage waveform applied to the gate signal line 17. The difference between FIG. 140 and FIG. 143 is basically the operation of the gate signal line 17b. Gate signal line 17
b corresponds to the number of divided screens and is turned on / off (Vgl and Vgh) by that number. Other points are shown in FIG.
The description is omitted because it is almost the same as or can be inferred.

As shown in FIG. 142 (b), the scanning direction of the non-lighted display area 312 is not limited to the top to bottom direction of the screen. Scanning may be performed from the bottom of the screen upward. Also, the scanning direction from top to bottom,
The scanning direction from the bottom to the top may be scanned alternately or randomly. Also, the number of divisions for each frame,
Alternatively, it goes without saying that it may be changed at a predetermined position on the display screen 21.

As described above, the flicker on the screen is reduced by dividing the display area 311 into a plurality of areas. Therefore, flicker does not occur and good image display can be realized. The division may be finer. However, the more divided it is, the more the flicker is reduced. Especially EL element 1
Since the response of No. 5 is fast, the display brightness does not decrease even if it is turned on / off in a time less than 5 μsec.

In the driving method of the present invention, the EL element 15
ON / OFF can be controlled by turning on / off a signal applied to the gate signal line 17b. Therefore, the clock frequency is KH
It can be controlled at a low frequency of z order. Further, an image memory or the like is not required to realize the black screen insertion (non-display area 312 insertion). Therefore, the drive circuit or method of the present invention can be realized at low cost.

FIG. 144 shows a case where the pixel rows selected simultaneously are two pixel rows. According to the examination result, in the display panel formed by the low temperature polysilicon technology, the display uniformity was practical in the method of simultaneously selecting two pixel rows. this is,
It is estimated that the characteristics of the driving TFTs 11a of the adjacent pixels are extremely matched. Further, when performing laser annealing, good results were obtained by irradiating the stripe-shaped laser in the direction parallel to the source signal line 18.

In FIG. 144, when the write pixel row is the (1) pixel row, the gate signal line 17a is (1).
(2) is selected (see FIG. 145). That is, the switching TFTs 11 in the pixel rows (1) and (2)
b, the TFT 11c is in the ON state. Further, the gate signal line 17b has a phase opposite to that of the gate signal line 17a.
Therefore, at least the switching TFTs 11d of the pixel rows (1) and (2) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312. In FIG. 144, the display area 311 is divided into five in order to reduce the occurrence of flicker.

Ideally, the TFT 11a of two pixels (rows)
Respectively, a current of Id × 5 (when N = 10) is supplied to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with five times the current.

[0662] Two pixel rows (K =
Since it is 2), the two drive TFTs 11a operate.
In other words, 10/2 = 5 times the current per pixel is applied to the TFT.
It flows to 11a. The source signal line 18 has two TFTs.
A current added with the program current of 11a flows.

For example, the current Id originally written in the write pixel row 871a is set to I in the source signal line 18.
A current of d × 10 is passed. There is no problem in the writing pixel row 871b because the regular image data is written later. The pixel row 871b displays the same as the 871a during the 1H period. Therefore, the write pixel row 871a and the pixel row 871b selected to increase the current are at least in the non-display state 312.

After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (3) is selected (Vgl voltage), and the program current flows from the TFT 11a of the selected pixel row (3) to the source driver 14 in the source signal line 18.
By operating in this way, regular image data is held in the pixel row (1).

After the next 1H, the gate signal line 17a
(2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (4) is selected (Vgl voltage), and the program current flows from the TFT 11a of the selected pixel row (4) to the source driver 14 in the source signal line 18.
By operating in this way, regular image data is held in the pixel row (2). One screen is rewritten by the above operation and scanning while shifting by one pixel row.

Although it is similar to FIG. 40, in the driving method of FIG. 149, since the programming is performed with a current (voltage) of 5 times for each pixel, the emission luminance of the EL element 15 of each pixel is ideally 5 Doubled. Therefore, the brightness of the display area 311 is five times higher than the predetermined value. In order to make this a predetermined brightness, as shown in FIG. 87, the non-display area 31 includes the writing pixel row 871 and covers a range of 1/5 of the display screen 1.
It should be 2. Since this has been described with reference to FIG. 137 and the like, description will be omitted.

[0667] The larger the area of the black display area (non-display area) 312 in the display screen 21, the higher the moving image display performance. Therefore, as shown in FIG. 141, the non-display area 311 may be reduced and the area of the non-display area 312 may be increased.

In the driving method in which a plurality of pixel rows are selected at the same time, the TFT increases as the number of pixel rows selected simultaneously increases.
It becomes difficult to absorb the characteristic variation of 11a. However, if the number of selected pixels decreases, the current programmed for one pixel increases, and a large current flows through the EL element 15. If the current passed through the EL element 15 is large, the EL element 15 is likely to deteriorate.

FIG. 146 solves this problem. The basic concept of FIG. 146 is that 1 / 2H (1/2 of the horizontal scanning period) selects a plurality of pixel rows at the same time as described in FIG. 88, and then 1 / 2H (1 / the horizontal scanning period).
2) is a combination of the methods for selecting one pixel row as described in FIG. By combining in this way, it is possible to absorb the characteristic variations of the TFT 11a and to improve the in-plane uniformity at high speed.

In FIG. 146, for ease of explanation, it is assumed that 5 pixel rows are simultaneously selected in the first period and 1 pixel row is selected in the second period.

First, in the first period, FIG. 146 (a1)
As shown in FIG. 5, 5 pixel rows are simultaneously selected. This operation has been described with reference to FIG. The current passed through the source signal line is 25 times the predetermined value. Therefore, the TFT 11a of each pixel 16 is programmed with 5 times the current. 25
Since the current is double, the parasitic capacitance 404 is charged and discharged in a very short time. Therefore, the potential of the source signal line becomes the target potential in a short time, and the capacitor 19 of each pixel 16
The terminal voltage of is also programmed to flow 5 times the current.
The application time of this 25-fold current is 1 / 2H (1/2 of one horizontal scanning period).

As a matter of course, since the same image data is written in the writing pixel row of five pixel rows, the TFT 11 is turned off so as not to display. Therefore, the display state is as shown in FIG. 146 (a2).

In the next 1 / 2H period, one pixel row is selected,
Perform current (voltage) programming. This state is shown in FIG.
It is illustrated in (b1). The write pixel row 871a is current (voltage) programmed so as to flow 5 times as much current as before. In FIG. 146 (a1) and FIG. 146 (b1), the same current is supplied to each pixel so that the change in the terminal voltage of the programmed capacitor 19 can be made small so that the target current can flow faster. This is because

That is, in FIG. 146 (a1), a current is caused to flow through a plurality of pixels, and the values are brought close to a value at which an approximate current flows at high speed. In the first stage, since programming is performed by a plurality of TFTs 11a, an error occurs due to the variation of the TFTs with respect to the target value. In the next second step, only the pixel row in which data is written and held is selected, and complete programming is performed from a rough target value to a predetermined target value.

It is to be noted that scanning the non-lighted area 312 from the top of the screen to the bottom and scanning the write pixel row 871a from the top to the bottom of the screen are shown in FIGS.
The description is omitted because it is the same as the fourth embodiment.

FIG. 147 shows drive waveforms for realizing the drive method of FIG. 146. As shown in FIG. 146, 1H
(1 horizontal scanning period) is composed of two phases. These two phases are switched by the ISEL signal.
The ISEL signal is illustrated in Figure 148.

First, the ISEL signal will be described. In FIG. 148, the current output circuit 1222 includes 122
2a and 1222b. Each current output circuit 1222 outputs 8-bit gradation data to D
A DA circuit 1226 for A conversion and an open amplifier 1224 are included. The circuit operation of the current output circuit 1222 has been described above, and will be omitted. In the embodiment of 146, the current output circuit 1222a is configured to output 25 times the current. On the other hand, the current output circuit 12
22b is configured to output 5 times the current.
The outputs of the current output circuits 1222a and 1221b are ISEL.
The switch circuit 1223 is controlled by the signal and applied to the source signal line 18.

When the ISEL signal is at the L level, the current output circuit 1222a that outputs 25 times the current is selected so that the source driver IC 14 absorbs the current from the source signal line 18. At the H level, the current output circuit 1222b that outputs a quintuple current is selected and the source driver IC 14 absorbs the current from the source signal line 18. It is easy to change the magnitude of the current such as 25 times or 5 times. This is because it is sufficient to change the value of the resistor 1228. Also, the resistor 122
It can be easily changed by setting 8 as a volume or by connecting to a plurality of resistors and an analog switch and selecting.

As shown in FIG. 147, when the writing pixel row is the (1) th pixel row (see the column of pixel row number 1 in FIG. 147), the gate signal line 17a is (1) (2) (3).
(4) and (5) are selected. That is, pixel row (1)
(2) (3) (4) (5) switching TFT11
b, the TFT 11c is in the ON state. Since ISEL is at L level, the current output circuit 1222a that outputs 25 times the current is selected and connected to the source signal line 18. Further, the gate signal line 17b has an off voltage (V
gh) is being applied. Therefore, pixel row (1)
(2) (3) (4) (5) switching TFT 11d
Is in an off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312.

Ideally, the TFTs 11a of the five pixels each supply a current of Id × 2 to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with five times the current. Here, in order to facilitate understanding, the description will be made assuming that the characteristics (Vt, S value) of each TFT 11a match.

The number of pixel rows selected simultaneously is 5 pixel rows (K =
Since it is 5), the five driving TFTs 11a operate.
In other words, 25/5 = 5 times the current per pixel is applied to the TFT.
It flows to 11a. The source signal line 18 has five TFTs.
A current added with the program current of 11a flows. For example, the current I originally written in the write pixel row 871a is
and a current of Id × 25 is passed through the source signal line 18. A write pixel row 871b for writing image data after the write pixel row (1) is an auxiliary pixel row used to increase the amount of current to the source signal line 18. However, since normal image data is written in the writing pixel row 871b later, there is no problem.

Therefore, the pixel row 871b displays the same as 871a during the 1H period. Therefore, the write pixel row 871a and the pixel row 871b selected to increase the current are at least in the non-display state 312.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 871a is selected. That is,
(1) Only the pixel row is selected. As is clear from FIG. 147, only the gate signal line 17a (1) is turned on (V
gl) is applied to the gate signal lines 17a (2) (3)
In (4) and (5), off (Vgh) is applied. Therefore, although the TFT 11a of the pixel row (1) is in an operating state (a state in which current is supplied to the source signal line 18), the switching TFT 1 of the pixel rows (2) (3) (4) (5)
1b and the TFT 11c are in the off state. That is, it is in a non-selected state. Also, since ISEL is at H level, 5
The current output circuit 1222b that outputs double current is selected,
The current output circuit 1222b and the source signal line 18 are connected. The state of the gate signal line 17b does not change from the previous 1 / 2H state, and the off voltage (Vgh) is applied. Therefore, pixel rows (1) (2) (3)
(4) The switching TFT 11d of (5) is in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312.

From the above, the TFT1 of the pixel row (1) is
1a sends a current of Id × 5 to the source signal line 18. Then, in the capacitor 19 of each pixel row (1),
Five times the current is programmed.

In the next horizontal scanning period, one pixel row and the writing pixel row are shifted. That is, the write pixel row is (2) this time. In the first 1 / 2H period, when the writing pixel row is the (2) th pixel row as shown in FIG. 147,
The gate signal line 17a is (2) (3) (4) (5) (6)
Is selected. That is, pixel rows (2) (3) (4)
(5) Switching TFT 11b and TFT 11 of (6)
c is in the on state. Since ISEL is at L level, the current output circuit 1222a that outputs 25 times the current is selected and connected to the source signal line 18. Also,
An off voltage (Vgh) is applied to the gate signal line 17b. Therefore, pixel rows (2) (3) (4)
(5) The switching TFT 11d of (6) is in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312. On the other hand, since the Vgl voltage is applied to the gate signal line 17b (1) of the pixel row (1), the TFT 11d is in the ON state and the EL element 15 of the pixel row (1) is turned on.

[0686] The pixel rows selected at the same time are five pixel rows (K =
Since it is 5), the five driving TFTs 11a operate.
In other words, 25/5 = 5 times the current per pixel is applied to the TFT.
It flows to 11a. The source signal line 18 has five TFTs.
A current added with the program current of 11a flows.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 871a is selected. That is,
(2) Only the pixel row is selected. As is clear from FIG. 147, only the gate signal line 17a (2) is turned on (V
gl) is applied to the gate signal lines 17a (3) (4)
In (5) and (6), off (Vgh) is applied. Therefore, the TFTs 11a of the pixel rows (1) and (2) are in an operating state (the pixel row (1) supplies a current to the EL element 15 and the pixel row (2) supplies a current to the source signal line 18).
However, the switching TFTs 11b and 11c of the pixel rows (3), (4), (5) and (6) are in the off state. That is, it is in a non-selected state. Further, since ISEL is at the H level, the current output circuit 1222b that outputs 5 times the current
Is selected, and the current output circuit 1222b and the source signal line 18 are connected. Also, the gate signal line 17b
The state is the same as the previous 1 / 2H state, and the off voltage (Vgh) is applied. Therefore, the switching TFTs of the pixel rows (2) (3) (4) (5) (6)
11d is in the off state, and the EL element 1 of the corresponding pixel row
No current is flowing in 5. That is, the unlit state 312
Is.

[0688] From the above, the TFT1 of the pixel row (2) is
1a sends a current of Id × 5 to the source signal line 18. Then, in the capacitor 19 of each pixel row (2),
Five times the current is programmed. One screen can be displayed by sequentially performing the above operation.

In the driving method described in FIG. 146, G pixel rows (G is 2 or more) are selected in the first period, and N pixel rows are selected.
Program to flow double the current. In the second period after the first period, a B pixel row (B is smaller than G and is 1 or more) is selected, and programming is performed so that N times the current flows through the pixel.

However, there are other measures. G in the first period
Pixel rows (G is 2 or more) are selected and programmed so that the total current of each pixel row is N times the current. In the second period after the first period, B pixel rows (B is smaller than G and is 1 or more) are selected, and the total current of the selected pixel rows (however, when the selected pixel row is 1, This is a method of programming so that the current of one pixel row) becomes N times. For example, in Figure 1.
In 46 (a1), 5 pixel rows are simultaneously selected, and a double current is applied to the TFT 11a of each pixel. Therefore,
A current of 5 × 2 times = 10 times flows through the source signal line 18. In the following second period, in FIG. 146 (b1), 1
Select a pixel row. This one pixel TFT 11a has 10
Apply double the current.

With this method, a plurality of current output circuits 1222 as shown in FIG. 148 are not necessary. Therefore, the source driver IC 14 can be configured with one current output circuit 1222 for each source signal line.

In other words, in this system, the source signal line 18
The output current of the source driver IC 14 that passes the current is a constant value (of course, this constant value changes depending on the image data).
In this case, it means that it is constant regardless of the number of selected pixels during the 1H period). Therefore, the configuration of the source driver IC 14 becomes easy.

In FIG. 146, the period for simultaneously selecting a plurality of pixel rows is 1 / 2H and the period for selecting one pixel row is 1 / 2H, but the invention is not limited to this. The period for simultaneously selecting a plurality of pixel rows may be set to 1 / 4H, and the period for selecting one pixel row may be set to 3 / 4H.
Further, the period including the period for simultaneously selecting a plurality of pixel rows and the period for selecting one pixel row is set to 1H, but is not limited to this. For example, even in the 2H period, 1.5
It may be H period.

Also, in FIG. 146, the period for simultaneously selecting five pixel rows is set to 1 / 2H, and 2H is set in the next second period.
The pixel rows may be selected at the same time. Even in this case, it is possible to realize image display without any trouble in practical use.

Also, in FIG. 146, there are two stages in which the first period for simultaneously selecting five pixel rows is 1 / 2H and the second period for selecting one pixel row is 1 / 2H, but the present invention is not limited to this. Not something to do. For example, in the first stage, 5 pixel rows are simultaneously selected, in the second period, 2 pixel rows are selected from the 5 pixel rows, and finally, 1 pixel row is selected.
It may be one stage. That is, the image data may be written in the pixel rows in a plurality of stages.

In FIG. 148, each source signal line 18 is provided with two current output circuits 1222. This is
This is to output 25 times the current in the first period and output 5 times the current in the second period, which is the first embodiment of No. 46.

To realize this with one current output circuit 1222, the circuit configuration of FIG. 149 may be adopted. DA
The circuit 1224 performs digital-analog conversion with the magnitude of the reference voltage (Iref) as the maximum value. For example, if the Iref voltage is 5 (V), 5 (V) is 25
The value divided into 6 is output as an analog value as the minimum value. That is, the maximum value of the analog output is a 5 (V) -1 bit analog value, the minimum value is 0 (V), and the minimum resolution is 5 (V) / 256 (when the input is the 8-bit specification. ). If the Iref voltage is 2.5 (V), 2.5
A value obtained by dividing (V) into 256 is output as an analog value as the minimum value. In other words, the maximum value of analog output is 2.5
(V) -1 bit analog value, minimum value is 0
(V), and the minimum resolution is 2.5 (V) / 256 (when the input is 8-bit specification).

That is, the output current value can be changed by one current output circuit 1222 by dynamically switching Iref. FIG. 149 shows a realizing circuit thereof.

In FIG. 149, a resistor RI that divides the Vi voltage into four is provided. The divided voltage is input to the switch circuit 1223, and one voltage is selected and becomes the Iref voltage. This Iref voltage is input to the DA converter 1224. Therefore, the first half
By switching the current output circuits 1222 connected to all the source signal lines 18 between the Iref voltage in the 2H period and the Iref voltage in the latter half of the 1 / 2H period, the scaling factor of the output current can be changed. .

Of course, as shown in FIG.
It goes without saying that the ef voltage may be generated by selecting a plurality of DA circuits 1224.

Also in the case of FIG. 148, the number of lighting display areas 311 may be one as shown in FIG. 151. Also, FIG.
As shown in 52, it may be divided into a plurality of lighting display areas 311.

As shown in FIG. 153, when the write pixel row is the (1) pixel row, (1), (2), (3), (4) and (5) are selected as the gate signal lines 17a. . That is, the switching TFTs 11b and 11c of the pixel rows (1), (2), (3), (4) and (5) are in the ON state.
Since ISEL is at L level, the current output circuit 1222a that outputs 25 times the current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b. Therefore, the switching TFTs 11d of the pixel rows (1), (2), (3), (4), and (5) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312.

There are five pixel rows (K =
Since it is 5), the five driving TFTs 11a operate.
In other words, 25/5 = 5 times the current per pixel is applied to the TFT.
It flows to 11a. The source signal line 18 has five TFTs.
A current added with the program current of 11a flows. For example, the current I originally written in the write pixel row 871a is
and a current of Id × 25 is passed through the source signal line 18. A write pixel row 871b for writing image data after the write pixel row (1) is an auxiliary pixel row used to increase the amount of current to the source signal line 18. However, since normal image data is written in the writing pixel row 871b later, there is no problem.

Therefore, the pixel row 871b displays the same as 871a during the 1H period. Therefore, the write pixel row 871a and the pixel row 871b selected to increase the current are at least in the non-display state 312.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 871a is selected. That is,
(1) Only the pixel row is selected. Gate signal line 17a
Only (1) is applied with the on-voltage (Vgl), and the gate signal lines 17a (2) (3) (4) (5) are turned off (Vg).
h) is being applied. Therefore, T of pixel row (1)
The FT 11a is in an operating state (a state in which current is supplied to the source signal line 18), but the pixel rows (2) (3) (4)
The switching TFT 11b and the TFT 11c of (5) are in the off state. That is, it is in a non-selected state. Also, IS
Since EL is at the H level, the current output circuit 1222b that outputs 5 times the current is selected.
2b and the source signal line 18 are connected. The state of the gate signal line 17b does not change from the previous 1 / 2H state, and the off voltage (Vgh) is applied. Therefore, the switching TFTs 11d of the pixel rows (1), (2), (3), (4), and (5) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312.

From the above, the TFT1 of the pixel row (1) is
1a sends a current of Id × 5 to the source signal line 18. Then, in the capacitor 19 of each pixel row (1),
Five times the current is programmed.

In the next horizontal scanning period, one pixel row and the writing pixel row are shifted. That is, the write pixel row is (2) this time. In the first 1 / 2H period, the gate signal line 17a is (2) (3) when it is the (2) th pixel row.
(4), (5) and (6) are selected. That is, the switching TFTs of the pixel rows (2) (3) (4) (5) (6)
11b and the TFT 11c are on. Also, ISE
Since L is at L level, the current output circuit 1222a that outputs 25 times the current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b. Therefore, the switching TFTs of the pixel rows (2) (3) (4) (5) (6)
11d is in the off state, and the EL element 1 of the corresponding pixel row
No current is flowing in 5. That is, the unlit state 312
Is. On the other hand, the gate signal line 17b of the pixel row (1)
In (1), since the Vgl voltage is applied, the TFT 11
d is in the ON state, and the EL element 15 of the pixel row (1) is lit.

There are five pixel rows (K =
Since it is 5), the five driving TFTs 11a operate.
In other words, 25/5 = 5 times the current per pixel is applied to the TFT.
It flows to 11a. The source signal line 18 has five TFTs.
A current added with the program current of 11a flows.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 871a is selected. That is,
(2) Only the pixel row is selected. Gate signal line 17a
Only (2) is applied with the ON voltage (Vgl), and the gate signal lines 17a (3) (4) (5) (6) are turned off (Vg).
h) is being applied. Therefore, pixel row (1)
The TFT 11a of (2) is in the operating state (the pixel row (1) is EL
A current is passed through the element 15 and the pixel row (2) is connected to the source signal line 1
8 is a state in which a current is supplied to the pixel row (3)
(4) Switching TFTs 11b and TFs of (5) and (6)
T11c is in the off state. That is, it is in a non-selected state. Further, since ISEL is at the H level, the current output circuit 1222b that outputs a quintuple current is selected, and this current output circuit 1222b and the source signal line 18 are connected. The state of the gate signal line 17b is 1 / 2H.
The off voltage (Vgh) is applied without any change from the state. Therefore, pixel rows (2) (3) (4) (5)
The switching TFT 11d of (6) is in the off state,
No current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312.

From the above, the TFT1 of the pixel row (2) is
1a sends a current of Id × 5 to the source signal line 18. Then, in the capacitor 19 of each pixel row (2),
Five times the current is programmed. One screen can be displayed by sequentially performing the above operation.

As is apparent from the above description, the above operation is the same as in FIG. 147. The difference is the gate signal line 1
This is the operation of 7b. The gate signal lines 17b are turned on / off (Vgl and Vgh) by the number corresponding to the number of divided screens.

As shown in FIG. 152, the scanning direction of the non-lighted display area 312 is not limited to the top to bottom direction of the screen. Scanning may be performed from the bottom of the screen upward. Further, the scanning direction from the upper side to the lower side and the scanning direction from the lower side to the upper side may be alternately or randomly scanned. It goes without saying that the number of divisions may be changed for each frame or at a predetermined position on the display screen 21.

As described above, the flicker on the screen is reduced by dividing the display area 311 into a plurality of areas. Therefore, flicker does not occur and good image display can be realized. The division may be finer. However, the more divided it is, the more the flicker is reduced. Especially EL element 1
Since the response of No. 5 is fast, the display brightness does not decrease even if it is turned on / off in a time less than 5 μsec.

Also in the embodiment shown in FIG. 153, G pixel rows (G is 2 or more) are selected in the first period, and programming is performed so that N times the current flows in each pixel row, and after the first period. In the second period, B pixel rows (B is smaller than G and is 1 or more) are selected,
The pixel is programmed so as to flow N times the current. However, similar to FIG. 147, there are other measures. That is, in the first period, G pixel rows (G is 2 or more) are selected,
It is programmed so that the total current of each pixel row is N times the current. In the second period after the first period, B pixel rows (B is smaller than G and is 1 or more) are selected, and the total current of the selected pixel rows (however, when the selected pixel row is 1, This is a method of programming so that the current of one pixel row) becomes N times.

The above embodiments are methods of displaying an image by progressive scanning. That is, in terms of television signals, non-interlaced drive (progressive drive) is used. The present invention is also effective for interlaced driving. FIG. 154 is an explanatory diagram of interlaced driving.

The interlaced drive is normally 2 fields and 1 frame. Figure 154 is also 1 in 2 fields
It has been described as a frame (one screen). But this is N
In the case of a TSC television signal, it is not always necessary to follow the principle of 2 fields = 1 frame in the image display of a mobile phone or the like.

For example, one frame may consist of four fields. The first field writes 4Y-3 (Y is an integer of 0 or more) pixel rows, and the second field writes 4Y-2.
(Y is an integer of 0 or more) A pixel row is written. In the third field, 4Y-1 (Y is an integer of 0 or more) pixel rows are written, and in the fourth field, 4Y (Y is an integer of 0 or more) pixel rows are written. That is, the interlaced drive is a method of forming one frame (one screen) with a plurality of fields.

FIG. 154 (a) shows the first field,
Write even pixel rows. In FIG. 154 (b), odd pixel rows, which are the second field, are written. FIG. 155 shows FIG.
3 is a drive waveform for realizing the drive method of FIG. The odd field and the even field are for convenience.
In FIG. 154, it is assumed that an image is written from odd-numbered pixel rows.

In FIG. 154, the gate signal line 17a
(1) is selected (Vgl voltage), and a program current flows from the TFT 11a of the selected pixel row toward the source driver 14 in the source signal line 18. Here, for ease of explanation, the write pixel row 871a is first described as the pixel row (1) th.

Also, the program current flowing through the source signal line 18 is N times the predetermined value (for the sake of simplicity, the description will be made assuming that N = 10 as in the above embodiments.
It is not limited to = 10. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ).

When the write pixel row is the (1) th pixel row, the Vgl voltage is applied to the gate signal line 17a (1). The switching TFT 11b and the TFT 11c are on. The Vgh voltage is applied to the gate signal line 17b (1). Therefore, the switching TFT 11d of the pixel row (1) is in the off state,
No current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312.

In the next 1H, the writing pixel row is the (3) th pixel row. The Vgl voltage is applied to the gate signal line 17a (3). Switching TFT 11b, TF
T11c is in the on state. Also, the gate signal line 17b
The Vgh voltage is applied to (3). Therefore, the switching TFT 11d of the pixel row (3) is in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312. The Vgl voltage is applied to the gate signal line 17b (1).
The switching TFT 11d is in the on state. Therefore, the switching TFT 11d of the pixel row (1) is in the ON state, and the EL element 15 of the corresponding pixel row emits light.

At the next 1H, the writing pixel row is the (5) th pixel row. The Vgl voltage is applied to the gate signal line 17a (5). Switching TFT 11b, TF
T11c is in the on state. Also, the gate signal line 17b
The Vgh voltage is applied to (5). Therefore, the switching TFT 11d of the pixel row (5) is in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312. The Vgl voltage is applied to the gate signal line 17b (3).
The switching TFT 11d is in the on state. Therefore, the switching TFT 11d of the pixel row (3) is in the ON state, and the EL element 15 of the corresponding pixel row emits light.

As described above, in the first field, the odd-numbered pixel rows are sequentially selected and the image data is written in.

In the second field, image data is sequentially written from (2) pixel row. Gate signal line 17
The Vgl voltage is applied to a (2). The switching TFT 11b and the TFT 11c are on. Further, the Vgh voltage is applied to the gate signal line 17b (2). Therefore, the switching TFT 11d of the pixel row (2) is in the off state, and the EL of the corresponding pixel row is
No current is flowing through the element 15. That is, the non-lighting state 312.

At the next 1H, the writing pixel row is the (4) th pixel row. The Vgl voltage is applied to the gate signal line 17a (4). Switching TFT 11b, TF
T11c is in the on state. Also, the gate signal line 17b
The Vgh voltage is applied to (4). Therefore, the switching TFT 11d of the pixel row (4) is in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312. The Vgl voltage is applied to the gate signal line 17b (3).
The switching TFT 11d is in the on state. Therefore, the switching TFT 11d of the pixel row (3) is in the ON state, and the EL element 15 of the corresponding pixel row emits light.

In the next 1H, the writing pixel row is the (6) th pixel row. The Vgl voltage is applied to the gate signal line 17a (6). Switching TFT 11b, TF
T11c is in the on state. Also, the gate signal line 17b
The Vgh voltage is applied to (6). Therefore, the switching TFT 11d of the pixel row (6) is in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312. The Vgl voltage is applied to the gate signal line 17b (4).
The switching TFT 11d is in the on state. Therefore, the switching TFT 11d of the pixel row (4) is in the ON state, and the EL element 15 of the corresponding pixel row emits light.

As described above, in the second field, the even-numbered pixel rows are sequentially selected and the image data is written. One image display is completed in the first field and the second field. In the second field, when writing even pixel rows, all odd pixel rows are not illuminated 31
2 In the first field, when writing the odd pixel rows, all the even pixel rows are set to the non-lighting display 312.

However, with the driving method shown in FIG. 154, a 10-fold current (N = 10) is passed through the source signal line 18, and the TFT 11
When the current program is applied to a, the display brightness becomes 10/2 = 5 times the predetermined brightness even if the processing of alternately displaying the odd pixel rows or the even pixel rows is performed. Therefore, it is necessary to drive with N = 2 in order to increase the display brightness by one. However, when driven with N = 2, the source signal line 1
The current value written in 8 is small and the parasitic capacitance 404 cannot be sufficiently charged / discharged. Therefore, insufficient writing occurs in the capacitor 19 and the resolution decreases.

In order to solve this, as shown in FIG. 156, not only the odd pixel rows or the even pixel rows but
A part of the display screen 21 may be the non-lighted area 312a. In FIG. 156, scanning is performed in the order of FIG. 156 (a) → FIG. 156 (b) → FIG. 156 (c) → FIG. 156 (a). FIG. 156
As can be seen from (b), a display area is formed in a predetermined range on the upper side (when scanning is performed from the top to the bottom of the screen) of the write pixel row 871a. However, since the display area is an odd-numbered pixel row or an even-numbered pixel row, it becomes every one pixel row. The non-lighting area 312a is a continuous non-lighting area.

However, if the display area is partially fixed on the display screen and scanned as in the driving method shown in FIG. 156, flicker is likely to occur. However, the frame rate is 80H
If z or more, the display state of FIG. 156 (display area 311
Note that flicker does not occur even when the number is set to one). In other words, the frame rate is 80Hz
With the above, it is not necessary to divide the lighting region 311.

If the frame rate is low, it may be divided as shown in FIG. This was explained earlier. Therefore, FIG. 157 will not need explanation. However, in FIG. 157, in order to facilitate drawing, the non-lighted area 312b and the lighted area 311 are divided into areas.
It was drawn with a pair of. However, the present invention is not limited to this, and it goes without saying that a plurality of non-lighting areas 312b and a plurality of lighting areas 311 exist in the divided area.

A wide variety of configurations can be considered for the drive system. In FIG. 158, when the writing pixel row is the (1) th pixel row, (1) (G) is selected as the gate signal line 17a. That is, the switching TFTs 11b and 11c of the pixel row (1) (G) are in the ON state. Further, the Vgh voltage is applied to the gate signal line 17b. Therefore, at least the switching TFT 11d of the pixel row (1) (G) is in the OFF state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312.

There are two pixel rows (K =
Since it is 2), the two drive TFTs 11a operate.
In other words, 10/2 = 5 times the current per pixel is applied to the TFT.
It flows to 11a. The source signal line 18 has two TFTs.
A current added with the program current of 11a flows.

After the next 1H, the gate signal line 17a
(G) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (2) is selected (Vgl voltage), and the program current flows from the TFT 11a of the selected pixel row (2) to the source driver 14 in the source signal line 18.
By operating in this way, regular image data is held in the pixel row (G).

After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (3) is selected (Vgl voltage), and the program current flows from the TFT 11a of the selected pixel row (3) to the source driver 14 in the source signal line 18.
By operating in this way, regular image data is held in the pixel row (1). One screen is rewritten by the above operation and scanning while shifting by one pixel row.

If flicker is likely to occur, refer to FIG.
As shown in FIG.
11 may be divided into a plurality. This was explained earlier. Therefore, FIG. 157 will not need explanation.

FIG. 161 shows the pseudo interlace drive. Pseudo interlaced driving means that the first F (first field) has two pixels (plural pixels) of an odd pixel row and an even pixel row.
Rows are selected at the same time and image data is written without overlapping the selected pixel rows. The next 2F is a method of simultaneously selecting two pixel rows (a plurality of pixel rows) of an even pixel row and an odd pixel row except the first pixel row, and writing image data without overlapping the selected pixel rows.

FIG. 161 (a1) (a2) (a3) shows the first
161 (b1) (b2) (b3)
Is the second field. The first field is shown in FIG.
(A1) → FIG. 161 (a2) → FIG. 161 (a3) → Sequentially writing video data is written in a pair of two pixel row 871. Therefore, two pixel rows display the same image, and this display state is held for one field period. In the first field, the image data of the odd pixel row is displayed on the odd pixel row and the next even pixel row. That is, the first
The image data of the row is displayed on the first pixel row and the second pixel row,
The image data on the third row is displayed on the third pixel row and the fourth pixel row, the image data on the fifth row is displayed on the fifth pixel row and the sixth pixel row, and the image data on the seventh row is The 7th pixel row and the 8th pixel row are displayed. The same applies hereinafter.

The second field is shown in FIG. 161 (b1) → FIG.
61 (b2) → FIG. 161 (b3) → in sequence The video data is written in the writing pixel row 871 in pairs of two pixel rows. Therefore, two pixel rows display the same image, and this display state is held for one field period. In the second field, the image data of the even pixel row is displayed on the corresponding even pixel row and the next odd pixel row. That is, the image data of the second row is displayed on the second pixel row and the third pixel row, the image data of the fourth row is displayed on the fourth pixel row and the fifth pixel row, and the image of the sixth row is displayed. The data is displayed on the sixth pixel row and the seventh pixel row, and the image data on the eighth row is displayed on the eighth pixel row and the ninth pixel row. The same applies hereinafter.

Note that the first pixel row in FIG. 161 (a1) maintains the state of the first field. Also, although odd-numbered image data is written in the first field and even-numbered image data is written in the second field, they may be reversed. That is, even image data may be written in the first field and odd image data may be written in the second field.

With the image display as described above, assuming that the human eye looks at the display image of two fields by adding afterimages, the first pixel line is not displayed at the end of one frame (two fields). , A display image of the first field. Further, the second pixel row is a combination of the image data of the first pixel row of the first field and the image data of the second pixel row of the second field. The third pixel row is a combination of the image data of the third pixel row of the first field and the image data of the second pixel row of the second field. Further, the fourth pixel row is a combination of the image data of the third pixel row of the first field and the image data of the fourth pixel row of the second field. The fifth pixel row is a combination of the image data of the fifth pixel row of the first field and the image data of the fourth pixel row of the second field. The same applies hereinafter.

As described above, since each pixel row is formed by superimposing the images of two fields, the contour of the display image is smooth. In particular, some moving image blur occurs in moving image display, but good resolution is obtained (recognized as) for almost still images.

FIG. 162 shows drive waveforms for realizing the display method of FIG. The upper position of the drawing is the driving waveform of the first field (1F), and the lower position of the drawing is the driving waveform of the second field (2F).

In the first field (1F), first,
Gate signal line 17a (1) of the first pixel row and the second pixel row
(2) is selected. The source signal line 18 has 10 times (N
= 10) drive current flows. Therefore, the driving TFTs 11a of the pixel rows (1) and (2) are programmed with a current of 5 times each. At this time, the Vgh voltage is applied to the gate signal lines 17b (1) (2) of the first pixel row and the second pixel row, and the TFT 11d is in the off state. Therefore, the EL elements 15 of the first pixel row and the second pixel row do not light up.

After 2H (because image data is written for each even-numbered pixel row or odd-numbered pixel row, it becomes 2H), the gate signal lines 17a (3) (4) of the third pixel row and the fourth pixel row are selected. A drive current 10 times (N = 10) flows through the source signal line 18. Therefore, the driving TFTs 11a of the pixel rows (3) and (4) are programmed with a current of 5 times each. At this time, the Vgh voltage is applied to the gate signal lines 17b (3) (4) of the third pixel row and the fourth pixel row, and
11d is in the off state. Therefore, the EL elements 15 of the third pixel row and the fourth pixel row do not light up.

On the other hand, the Vgl voltage is applied to the gate signal lines 17b (1) (2). Therefore, the TFTs 11d of the first pixel row and the second pixel row are turned on, and the EL element 15 is turned on.

Further, after 2H, the gate signal lines 17a (5) (6) of the fifth pixel row and the sixth pixel row are selected. A drive current 10 times (N = 10) flows through the source signal line 18. Therefore, the driving TFTs 11 of the pixel rows (5) and (6) are
Each a is programmed with 5 times the current. At this time, the gate signal lines 17b of the fifth pixel row and the sixth pixel row
(5) The Vgh voltage is applied to (6), and the TFT 11d
Is off. Therefore, the EL elements 15 of the fifth pixel row and the sixth pixel row do not light up.

On the other hand, the gate signal lines 17b (1) (2)
The Vgl voltage is applied to (3) and (4). Therefore, the TFTs 11d of the first pixel row, the second pixel row, the third pixel row, and the fourth pixel row are turned on, and the EL element 15 is turned on. Perform the above operation up to the last odd pixel row of the screen, and
Display the screen.

[0750] In the second field (2F), the first
The pixel row is not selected and the state of the first field is retained. Next, the gate signal line 1 of the second pixel row and the third pixel row
7a (2) (3) is selected. A drive current 10 times (N = 10) flows through the source signal line 18. Therefore,
The driving TFTs 11a in the pixel rows (2) and (3) each have 5
Programmed with double the current. At this time, Vgh is applied to the gate signal lines 17b (2) (3) of the second pixel row and the third pixel row.
A voltage is applied and the TFT 11d is in the off state. Therefore, the EL elements 15 of the second pixel row and the third pixel row do not light up.

After 2H, the gate signal lines 17a (4) (5) of the fourth pixel row and the fifth pixel row are selected. A drive current 10 times (N = 10) flows through the source signal line 18. Therefore, the driving TFTs 11a of the pixel rows (4) and (5) are programmed with a current of 5 times. At this time, the Vgh voltage is applied to the gate signal lines 17b (4) (5) of the fourth pixel row and the fifth pixel row, and the TFT 11d is in the off state. Therefore, the EL elements 1 of the fourth pixel row and the fifth pixel row
5 does not light.

On the other hand, the Vgl voltage is applied to the gate signal lines 17b (2) (3). Therefore, the TFTs 11d of the first pixel row, the second pixel row and the third pixel row are turned on,
The EL element 15 lights up.

Further, after 2H, the gate signal lines 17a (6) (7) of the sixth pixel row and the seventh pixel row are selected. A drive current 10 times (N = 10) flows through the source signal line 18. Therefore, the driving TFTs 11 of the pixel rows (6) and (7) are
Each a is programmed with 5 times the current. At this time, the gate signal lines 17b of the sixth pixel row and the seventh pixel row
(6) The Vgh voltage is applied to (7), and the TFT 11d
Is off. Therefore, the EL elements 15 of the sixth pixel row and the seventh pixel row do not light up.

On the other hand, gate signal lines 17b (1) (2)
The Vgl voltage is applied to (3), (4) and (5). Therefore, the first pixel row, the second pixel row, the third pixel row, the fourth pixel row
The TFTs 11d of the pixel row and the fifth pixel row are turned on, and the EL
The element 15 lights up. The above operation is performed up to the last even pixel row of the screen, and one screen is displayed.

In the above embodiments, one screen is displayed with two fields. In FIG. 163, one screen is displayed with two or more fields. FIG. 163 (a) is the first field, FIG. 163 (b) is the second field, and FIG.
(C) is the third field.

In the first field, 4Y-3 (Y is an integer of 1 or more) pixel rows and 4Y-2 pixel rows are write pixel rows 871. Image data is written every two pixel rows. In the second field, the 4Y-1 pixel row and the 4Y pixel row are the write pixel row 871. The previous field is also 2
Image data is written pixel by pixel. In the third field, 4Y-2 pixel rows and 4Y-1 pixel rows are write pixel rows 871. Image data is written every two pixel rows.
By writing in 3F as described above, each pixel data is interpolated with image data of a plurality of fields.

Although FIG. 163 shows an example in which one screen is composed of three fields, image display may be realized by using more fields. For example, in the case of four fields, in the first field, 4Y-3 (Y is an integer of 1 or more) pixel rows and 4Y-2 pixel rows are the write pixel rows 871.
Image data is written every two pixel rows. In the second field, 4Y-1 pixel rows and 4Y pixel rows are write pixel rows 8
71. In the third field, 4Y-2 pixel rows and 4
The Y-1 pixel row is the write pixel row 871. Similarly to the above, the image data is written every two pixel rows. In the fourth field, the 4Y-3 pixel row and the 4Y pixel row are the write pixel row 871. Similarly, the image data is written every two pixel rows in the previous field. By writing in 4 fields as described above, each pixel data is interpolated by image data of a plurality of fields.

Although the above embodiments have been described mainly by exemplifying the pixel configuration of FIG. 1, the driving method of the present invention is as shown in FIG.
It is also effective for other current programmed pixel configurations such as those in FIGS. 43, 71, and 76.

FIG. 164 is an explanatory diagram of a driving method of the pixel configuration of FIG. Here, for ease of explanation, the current flowing from the source driver IC 14 to the source signal line 18 (or the current absorbed by the source driver IC 14 from the source signal line 18 and the current flowing from the drive TFT 11a to the source signal line 18). Is 10 times the predetermined value (N = 1
0) will be described. In addition, TFT11a and TFT1
It is assumed that the current magnification of 1b is 1: 1 (current magnification of 1).

Therefore, if the pixel rows selected at the same time are five pixel rows (K = 5), the five driving TFTs 11a operate. Since the current magnification is 1, the same current as that of the TFT 11a also flows through the TFT 11b. That is, a current of 10/5 = 2 times per pixel flows through the TFT 11a.
Since the current programmed in the TFT 11a of the pixel 16 is twice the predetermined value, the current flowing in the EL is also doubled.
Therefore, the EL element 15 is less deteriorated as compared with the case where a 10 times larger current is passed as shown in FIG. On the other hand, since the current flowing through the source signal line 18 is 10 times, FIG.
It is possible to charge and discharge the parasitic capacitance 404 in the same manner as. This also applies to FIG. 88.

If the current magnification is 2, the TFT 11b
The current flowing through the EL element 15 is 1 time. Therefore,
A predetermined current capable of obtaining a predetermined brightness can be passed through the EL element 15. That is, in the pixel configurations of FIGS. 21, 43, 71, and 76, the current magnification (TFT 11a and TFT 1
By designing (adjusting) the current ratio to 1b) and the current (programming current) flowing in the source signal line 18, it is possible to design a display panel with high versatility.

There are five pixel rows (K =
In case of 5), the program currents of the five TFTs 11a are added. For example, write pixel row 871a
Then, originally, if the write current Id is set and N = 10,
A current of Id × 10 is passed through the source signal line 18. The pixel row 871b (871b) adjacent to the write pixel row 871a
Reference numeral b is a pixel row that is used supplementarily to increase the amount of current to the source signal line 18. Therefore, the pixel (row) in which the image is written is 871a, and the pixel (row) that is additionally used for writing in the 871a is 871b).

In FIG. 164, the writing pixel (row) 8
K lines (K = 5) are simultaneously written with the image data of 71a.
Therefore, the ranges of K rows (871a, 871b) are displayed in the same manner. When the same display is performed in this way, the resolution naturally lowers. To prevent this, FIG.
As shown in (b), the write pixel row 871b is set to the non-lighting display 312. Therefore, the resolution is not reduced.

Although 871a shown in FIG. 164 (a) is in the display state, since this pixel is being programmed, it changes in the state of writing current to the pixel. Therefore, it may be the non-display area 312.

After the next 1H, the pixel row shifted by one pixel row is set as the write pixel row 871a and the same operation is performed. The non-lighted area 312 is also shifted by one pixel (row). As described above, the 871b to which the current data different from the original display data is written is not displayed. A complete image display can be realized by shifting the above operation line by line. Also, due to the effect of the pixel row 871b used as an auxiliary, the parasitic capacitance 40
The charge / discharge of No. 4 can also be realized sufficiently within 1H period.

FIG. 165 is an explanatory diagram of drive waveforms for realizing the drive method of FIG. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level). In addition, the number of the selected pixel row is described in the lower part of FIG. 165. Also, (1) (2)
(3) ... (11) indicate the selected pixel row number. Therefore, the number of pixel rows is 4 in the VGA panel.
The number is 80 and the XGA panel is 768.

In FIG. 165, the gate signal line 17a
(1) and the gate signal line 17b (1) are selected (Vgl
Voltage), a program current flows from the TFT 11a of the selected pixel row toward the source driver 14 to the source signal line 18. Further, the program current flowing through the source signal line 18 is N times the predetermined value (for the sake of simplicity, N = 1.
It will be described as 0. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ). Also, description will be made assuming that five pixel rows are simultaneously selected (K = 5). Therefore, ideally, the capacitor 19 of one pixel has twice the current TF.
It is programmed to flow to T11a.

Basically, the gate signal lines 17a and 17b
Since and have the same phase, they can be shared. However, strictly speaking, when selecting and deselecting a pixel row, it is preferable to control so that the TFT 11d is first turned off and then the TFT 11c is turned off. Therefore,
It is preferable to separate the gate signal line 17a and the gate signal line 17b.

When the write pixel row is the (1) th pixel row, as shown in FIG. 164, the gate signal line 17a,
The Vgl voltage is applied to 17b. Therefore,
Pixel rows (1), (2), (3), (4), and (5) are selected. That is, the switching TFTs 11c and 11d of the pixel rows (1) (2) (3) (4) (5) are in the ON state. The gate signal line 17b is the gate signal line 17b.
It is the opposite phase of. Therefore, pixel row (2)
The switching TFTs 11d of (3), (4), and (5) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312.

Ideally, the TFTs 11a of the five pixels each supply a current of Id × 2 to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with a double current. Here, in order to facilitate understanding, the description will be made assuming that the characteristics (Vt, S value) of each TFT 11a match.

The pixel rows selected at the same time are five pixel rows (K =
Since it is 5), the five driving TFTs 11a operate.
In other words, 10/5 = twice the current per pixel
It flows to 11a. The source signal line 18 has five TFTs.
A current added with the program current of 11a flows. For example, the current I originally written in the write pixel row 871a is
and a current of Id × 10 is passed through the source signal line 18.

The four write pixel rows 871b for writing image data after the write pixel row (1) are auxiliary pixel rows used to increase the amount of current to the source signal line 18. However, since normal image data is written in the writing pixel row 871b later, there is no problem.

Therefore, the pixel row 871b displays the same as 871a during the 1H period. Therefore, the pixel row 871b selected for increasing the current is at least in the non-display state 312.

After the next 1H, the gate signal line 17a
(1) and 17b (1) are not selected (position of pixel row number 6), and the data to be written in the pixel is fixed. At the same time, the gate signal line 17a (6) is selected (pixel number 2
Position), the program current flows from the TFT 11a of the selected pixel row (6) toward the source driver 14 to the source signal line 18. Rather than working this way,
Regular image data is held in the pixel row (1).

Next, after 1H, the gate signal line 17a
(2) and 17b (2) are not selected. Further, the gate signal line 17a (7) is selected (Vgl voltage), and the TFT 11a to the source driver 14 of the selected pixel row (7) are selected.
A program current flows through the source signal line 18 toward the. By operating in this way, regular image data is held in the pixel row (2). One screen is rewritten by the above operation and scanning while shifting by one pixel row.

Although it is similar to FIG. 134, in the driving method of FIG. 140, since the programming is performed with a double current (voltage) in each pixel, the emission brightness of the EL element 15 of each pixel is ideally 2 Doubled. Therefore, the brightness of the display screen is twice the predetermined value.

[0777] In order to make this a predetermined brightness,
As shown in FIG. 7, the non-display area 312 may include a half of the display area 21 including the write pixel row 871. Since this has been described with reference to FIG. 137 and the like, description will be omitted. The driving method of FIG. 146 is also shown in FIG.
71, 164, 76, 54, 67, 68,
It goes without saying that it can be applied to FIG. 103 and the like. Since the explanation has been given before, it will be omitted.

The larger the area of the black display area (non-display area) 312 in the display screen 21, the higher the moving image display performance. Therefore, as shown in FIG. 141, the non-display area 311 may be reduced and the area of the non-display area 312 may be increased.

In the embodiment of the present invention, the program current (voltage) can be adjusted by changing the current (voltage) supplied to the source signal line 18. That is, the current flowing through the source signal line 18 can be adjusted only by adjusting the reference current (voltage) of the source driver 14. ST * to be applied to the shift register 22 of the gate driver 12 shown in FIG. 2 and the like indicates whether to turn on two pixel rows at the same time, turn on five pixel rows at the same time, or select only one pixel row.
It can be set by data to the terminal. Therefore, the specifications of the source driver 14 do not depend on the number of pixels to be selected.

[0780] Also, the screen brightness is determined by the gate signal line 17c.
The output current from the source driver 14 is not changed by adjusting the brightness of the screen 21. Therefore, the gamma characteristic of the EL element 15 may be determined for one current. Therefore, the configuration of the source driver 14 is extremely easy and highly versatile. It goes without saying that the above items can be applied to other embodiments of the present invention.

Similarly to FIG. 136, when one display area 311 moves downward from the top of the screen as shown in FIG.
When the frame rate is low, it is visually recognized that the display area 311 moves. In particular, it becomes easy to be recognized when the eyelids are closed or when the face is moved up and down. To solve this problem, as shown in FIG.
The display area 311 may be divided into a plurality of parts.

As shown in FIG. 142 (b), the scanning direction of the non-lighted display area 312 is not limited to the top to bottom direction of the screen. Scanning may be performed from the bottom of the screen upward. Also, the scanning direction from top to bottom,
The scanning direction from the bottom to the top may be scanned alternately or randomly. Also, the number of divisions for each frame,
Alternatively, it goes without saying that it may be changed at a predetermined position on the display screen 21.

As described above, the flicker on the screen is reduced by dividing the display area 311 into a plurality of areas. Therefore, flicker does not occur and good image display can be realized. The division may be finer. However, the more divided it is, the more the flicker is reduced. Especially EL element 1
Since the response of No. 5 is fast, the display brightness does not decrease even if it is turned on / off in a time less than 5 μsec.

87, 88 are FIGS. 1, 76, 21,
The pixel configuration of the current programming method as shown in FIGS. 43 and 71 has been described as an example, but the present invention is not limited to this.
For example, the voltage programming type pixel configurations shown in FIGS. 54, 68, and 103 are also effective. By applying a voltage to a plurality of pixel rows at the same time, the pixels can be preliminarily filled, so that a high-definition display panel of SXGA or higher can be supported. Moreover, the electric drive circuit and the signal processing circuit are simplified, and good black display can be realized.

As an application example of the voltage program, the pixel configuration of FIG. 54 will be exemplified and described. Note that FIG. 166 and FIG.
Reference numeral 7 is the drive waveform. In FIG. 166 and FIG. 167, the description is given assuming that the 5 pixel rows are the non-lighting area 312, but the present invention is not limited to this. This is simply for ease of explanation. For example, two pixel rows may be simultaneously selected or ten pixel rows may be selected. Further, one pixel row may be the non-lighting area 312. This is shown in FIG. 54, FIG. 67, and FIG.
The same applies to FIG.

Also, FIG. 54, FIG. 67, FIG. 68, FIG.
It goes without saying that the driving method described with reference to FIGS. 144, 146, 151, 152, 154, 163 and the like can be applied to the pixel configuration of the voltage program illustrated in FIG. In addition, N times the current is EL element 1
It goes without saying that a driving method in which the non-lighted area 312 is formed by driving so as to flow in No. 5 can also be applied. However, since the description is complicated in FIGS. 166 and 167, it will not be described.

As shown in FIG. 167, when the writing pixel row is the (1) pixel row, the gate signal line 17a is (1).
(2), (3), (4), and (5) are selected (position of pixel row number 5). That is, pixel rows (1) (2) (3)
(4) The switching TFT 11b of (5) is on. An off voltage (Vgh) is applied to the gate signal line 17b. Therefore, pixel row (1) (2)
The switching TFTs 11d of (3), (4), and (5) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. That is, the non-lighting state 312. Therefore, the pixel row (1) is precharged with the voltage for a period of 5H.

[0788] The pre-charged pixel row has the same display as the other four pixel rows during the 5H period. Therefore, at least the pixel row in which writing is performed is set to the non-display state 312. Particularly in the video signal, the video data is similar in the adjacent pixels. Therefore, if you perform preliminary charging,
Writing regular image data is easy.

Therefore, the present invention is a method of writing image data in a plurality of pixel rows and keeping the non-display state 312 until the regular image data is written. However, 1
Even if a pixel row is selected, the display is unstable when the image data of this pixel row is being written, so that it is also a concept of the present invention to make it non-display. Further, the current flowing through the EL element 15 is set to be larger than a predetermined value, and the non-lighted area 312
To form a predetermined brightness. It is also an effect of the present invention to realize a good moving image by this display method.

At the next 1H, (2) the image data of the pixel row is fixed. As is apparent from FIG. 167, the off voltage (Vgl: since the TFT 11b is the n channel) is applied to the gate signal line 17a (1) and the gate signal line 17b (1) (pixel row number 6). Gate signal line 17a (6)
And the gate signal line 17b (6) is turned on (Vgh: TFT
11b is n channel). Therefore, the image data to the TFT 11a of the pixel row (2) is held.

As described above, 1 is synchronized with the horizontal scanning period.
The pixel row and the writing pixel row are shifted. One screen can be displayed by sequentially performing the above operation.

FIG. 166 shows a system in which the timing of the gate signal line 17b is shifted by 1H in the pixel configuration of FIG. As is clear from FIG. 166, the pixels to be set are brought into the display state.

For example, in the pixel row (1), the image data is written for the period of 5H (the period of the pixel row numbers 1-5). That is, the gate signal line 17a of the pixel row (1) is in a selected state (since the TFT 11b is an n channel, V
gh is applied). At the time of 5H, the gate signal line 17b (1) has an on-voltage (Vgl: TFT 11d is P
(Because of the channel) is applied, so EL element 1
Current is flowing through 5. Therefore, the EL element 15 is in a lighting state. This point is different from FIG. 167. In FIG. 167, the non-lighting area 312 is used. The other points are similar to those of FIG. 167, and thus the description thereof is omitted.

In the embodiment of the present invention in which a plurality of pixel rows are simultaneously turned on to write image data, the uppermost side or the lowermost side of the display area 21 or both pixel rows are turned on at the same time. There is no line. To solve this problem, dummy pixel rows may be formed or arranged on the uppermost side and / or the lowermost side of the display area 21.

For example, in the driving method for simultaneously selecting 5 pixel rows described with reference to FIG. 139, 4 pixel rows are formed on the lower side of the screen. Of course, when the upside-down driving is performed, four dummy pixel rows are also provided on the upper side of the screen. The EL element 15 is not formed in the dummy pixel row. Therefore,
Does not emit light. Of course, even if the EL element 15 is formed, it does not emit light or is shielded from light so as not to be displayed. In addition, in FIG. 1, other than the TFT 11d for one pixel may be formed. One or more dummy pixel rows are formed.

Although it has been stated that adjacent pixel rows are turned on at the same time, the present invention is not limited to this. For example, the timing of turning on a plurality of pixel rows may be different. Further, the effect is exhibited even if the first row is separated from the third row to the second pixel row. In the extreme, when selecting two pixel rows, one pixel row is fixed (for example, the pixel row at the bottom of the screen or a dummy pixel row) and turned on, and another one pixel row is scanned and sequentially turned on. You may let me.

The above embodiment is basically the same as EL element 1
The number of driving TFTs for supplying a current to 5 is one for each pixel, and the target luminance is displayed in one field (one frame). However, the present invention is not limited to this. Hereinafter, the example will be described.

FIG. 309 is based on the pixel configuration of the current program shown in FIG. The difference between FIG. 1 and FIG. 309 is that FIG.
09 is a driving TFT, and is a TFT 11a1 and a TFT 11
The point is that two a2 are formed (produced) in one pixel. A switching TFT that turns on / off (disconnects or connects) the current path between the TFT 11a1 and the EL element 15.
1f1 is formed (arranged). Furthermore, the TFT 11
A switching TFT 1f2 that turns on / off (disconnects or connects) the current path between the a2 and the EL element 15 is formed (disposed). A gate signal line 17f1 is connected to the gate (G) terminal of the TFT 11f1. By applying a Vgh voltage to the gate signal line 17f1, the TFT 1f1 is connected to the TFT 1f1.
1f1 turns on (by applying Vgl voltage, T1
FT11f1 turns off). Similarly, this TFT 11f
The gate signal line 17f2 is connected to the gate (G) terminal of No. 2 and the TFT 11f2 is turned on by applying a Vgh voltage to this gate signal line 17f2 (Vgl).
The TFT 11f2 is turned off by applying a voltage). Of course, each gate signal line 17 is common to the pixel rows. The other operations are the same as or similar to the operations described in FIG. 1, and the configurations are also the same or similar, and thus the description thereof will be omitted.

310 and 311 are explanatory views of the operation of the pixel configuration of FIG. 309. In FIGS. 310 and 311, the switching TFT 11 is shown by a switch symbol.

In the configuration of FIG. 309, the current flowing through the EL element 15 is set to a predetermined value in 2 frames (2 fields).
Here, in order to facilitate the description, it is assumed that the current flowing through the EL element 15 has a predetermined value in the period of two frames. The programmed current is Iw = 10 (μA)
(Note that this is a temporary setting. In reality, 1.2
(A current such as (μA) is programmed according to the image),
The EL element 15 has a current corresponding to the programmed current Iw.
Flow to.

Basically, in the first frame, the source driver 14 draws the program current Iw = 10 (μA). This current Iw is supplied to the pixel from both of the two driving TFTs. In the first frame, the first drive TFT
11a is selected and this current is passed through the EL element 15. EL
The element 15 emits light according to the current of the first driving TFT 11a. In the second frame, as in the first frame,
Program current Iw = 10 (μ
Inhale A). This current Iw causes two driving T
Supply from both FT.

In the second frame, the second drive TFT
11a is selected and this current is passed through the EL element 15. EL
The element 15 emits light according to the current of the second driving TFT 11a. Therefore, when the two frame periods are averaged, the EL element 15 emits light with the brightness according to the average currents flowing through the first driving TFT 11a and the second driving TFT 11a. If the program current Iw = 10 (μA), light is emitted with a brightness of 10/2 = 5 (μA). Therefore, even if the characteristics of the two drive TFTs 11 are deviated, the same program current Iw is passed to current-program the two drive TFTs. In addition, since current is passed through the EL element 15 once in each of the two driving TFTs in the two frame periods, an accurately programmed current can be passed in the EL element in the two frame periods.

In the above description, it has been explained that the target luminance is obtained in two frames regardless of the variation in the driving TFT characteristics of the pixels. However, this is not necessary when displaying an image such as a moving image. Simply mechanically two drive TFs
It suffices to flow T11a alternately to the EL element 15. To be precise, in the present embodiment, the sum of the currents passed through the EL element 15 in the two frame periods matches the program current.
However, in the video, the image is constantly changing. Therefore, even if the display state of the moving image is shifted, it is not visually recognized. It should be noted that in a still image, since there is no movement of the image, the image display does not have a droop. The details will be described below.

FIG. 310 shows a state in which the corresponding pixel is selected and current programming is being performed. Gate signal line 17a
ON voltage (Vgl) is applied to the TFT 11b, TF
T11c turns on. A program current Iw flows from the TFT 1a toward the source driver (not shown) 14. At this time, the TFT 11d is in the off state (the off voltage (Vgh) is applied to the gate signal line 17b). The on-voltage (Vgl) is applied to the gate signal line 17f1 and the gate signal line 17f2, and the TFTs 11f1 and T
FT11f2 is on.

[0805] The program current Iw is the driving TFT 11a.
1 and the TFT 11a2. If the current supplied by the TFT 11a1 is Ia1 and the current supplied by the TFT 11a2 is Ia2, the program current Iw = Ia1 + Ia
It is 2.

Originally, since the TFT 11a1 and the TFT 11a2 are formed adjacent to each other, there should be almost no characteristic deviation. However, the Vt voltage and the like are different from those formed by the low temperature polysilicon technology. Therefore, even if the gate terminals of the driving TFT 11a1 and the TFT 11a2 are made common and the same voltage is applied to this gate terminal, the driving TF
The currents flowing through T11a1 and TFT11a2 are different. In order to facilitate the explanation, the TFT 11a1 and the TFT 1
It is assumed that there is a 3: 7 difference from 1a2. That is, assuming that the program current Iw = 10 (μA), TF
T11a1 supplies a current of 3 (μA), and TFT11a
2 supplies a current of 7 (μA). That is, the program current Iw = Ia1 + Ia2 = 3 (μA) +7 (μ
A) = 10 (μA).

When the pixel is in the non-selected state, FIG.
The state of (a) is obtained. The off voltage (Vgh) is applied to the gate signal line 17a, and the TFT 11b and the TFT 11c are turned off. At the same time, the ON voltage (Vgh) is applied to the gate signal line 17b, and the TFT 11d is turned on. An on-voltage (Vgl) is applied to the gate signal line 17f1 and T
FT11f1 turns on. In addition, the gate signal line 17f2
OFF voltage (Vgh) is applied to the TFT 11f2.
Is off.

Therefore, the current Idd1 from the drive TFT 11a1 flows through the EL element 15. This current is TF
If the characteristics of T11a1 and TFT 11a2 are the same, then Idd1 = Iw / 2 = 5 (μA). But,
In reality, the characteristics of the TFT 11a1 and the TFT 11a2 are deviated. Here, for ease of explanation, the TFT 11a is
1 will be described as Idd1 = 3 (μA). Therefore, in the first frame, the EL element 15 emits light with a current of 3 (μA).

In the second frame following the first frame, the operation described in FIG. 310 is performed again. That is, the corresponding pixel is selected and the current program is being performed. As in the first frame, the ON voltage (Vgl) is applied to the gate signal line 17a, and the TFT 11b and the TFT 1
1c turns on. Program current Iw = 10 (μ) from the TFT 1 a toward the source driver (not shown) 14.
A) flows. Gate signal line 17f1, gate signal line 1
The on-voltage (Vgl) is applied also to 7f2, and the TFT 11
The f1 and the TFT 11f2 are in the ON state. In addition, as for the program current Iw, the driving T is the same as in the first frame.
It is supplied from the FT 11a1 and the TFT 11a2.

When the pixel is in the non-selected state, the state shown in FIG. 311 (b) is obtained in the second frame. Gate signal line 17a
OFF voltage (Vgh) is applied to the TFT 11b, TF
T11c turns off. At the same time, the ON voltage (Vgh) is applied to the gate signal line 17b, and the TFT 11d is turned on. An off voltage (Vgh) is applied to the gate signal line 17f1 to turn off the TFT 11f1. Further, an ON voltage (Vgl) is applied to the gate signal line 17f2, and the TFT
11f2 turns on.

Therefore, this time, the driving TFT 11a2
A current Idd2 from the element flows into the EL element 15. It has been described in the description of the first frame that this current is Idd1 = Iw / 2 = 5 (μA) if the characteristics of the TFT 11a1 and the TFT 11a2 are the same. However, the characteristics of the TFT 11a1 and the TFT 11a2 are actually different from each other. Here, in order to facilitate the description, Idd2 of the TFT 11a2 will be described as 7 (μA). Therefore,
In the second frame, the EL element 15 emits light with a current of 7 (μA).

[0812] FIG. 31 shows the above state in the display state.
It becomes the state of 2. FIG. 312 (a) shows the first frame, and FIG. 312 (b) shows the second frame. That is, the write pixel row 871 is selected in the first frame, and a current of 10 (μA) flows through the source signal line 18. Then, the pixel 16 is current-programmed and the TFT
A current of 3 (μA) is passed through the EL element 15 by 11a1.

As shown in FIG. 312 (b), the write pixel row 871 is selected in the second frame, and a current of 10 (μA) flows through the source signal line 18. Then, a current is programmed in the pixel 16, and a current of 7 (μA) is caused to flow through the EL element 15 by the TFT 11a2. Therefore, if two frames are averaged, (3 (μA) +7 (μ
A)) / 2 = 5 (μA), and the program current Iw =
A half current of 10 (μA) flows through the EL element 15.

According to the above driving method, even if the characteristics of the two driving TFTs 11a formed in the pixel vary, the average current flowing through the EL element 15 does not vary. That is, a current accurately proportional to (or the same as) the program current Iw flows through the EL element 15. Therefore, uniform image display can be realized.

In the above description, the driving TFTs 11a1 and 11a2 for supplying the current to the EL element 15 are switched every frame, and the two frame periods are
It is explained that the pixels are current-programmed with the same current. However, this is not necessary when displaying an image such as a moving image. The program current applied to the source signal line 18 is changed for each frame according to the pixel, and two drive TFs are used.
Switching between T11a1 and TFT11a2 to alternate EL
It suffices to flow it to the element 15. In the video, the image is constantly changing. Therefore, even if the display state of the moving image is shifted, it is not visually recognized. In addition, in the still image,
Since there is no image movement, the current flowing through the source signal line 18 does not change for each frame. That is, it is constant in at least two frames.

In the above case as well, the source signal line 18 is supplied with twice the current actually applied to the EL (which is, of course, twice the average of two frames). Therefore, even if the parasitic capacitance 404 exists on the source signal line 18, insufficient writing is reduced. Also, in the embodiment shown in FIG. 309, the current half of the current flowing through the source signal line 18 is E
The technical idea is to pass the light to the L element 15. The technical idea is that the N times larger current is passed through the source signal line 18 and the 1 / N current is explained in FIG.
It is the same as the method of flowing into.

The number of driving TFTs formed in one pixel is not limited to two as shown in FIG. 309. It may be three or more. However, in order to control these TFTs, the gate signal line 17 needs a switching TFT that turns on / off (disconnects or connects) the current of each TFT 11a. Of course, the gate signal line 17 is common to one pixel row. Needless to say, the above items are also applied to the following embodiments and other embodiments.

The above embodiment is the case of the pixel configuration of FIG. The technical ideas described above are applied to the pixel configurations of FIGS. 21, 43, 71, and 22. FIG. 313 is an example thereof.

The operation is similar to that of FIG. 308. In the first frame, the source driver 14 has a program current Iw = 10.
Inhale (μA). This current Iw is the driving TFT 11
Supply from a. In the first frame, the first drive T
FT11b1 is selected and this current is passed through the EL element 15. The EL element 15 emits light according to the current of the first drive TFT 11b1.

In the second frame, as in the first frame,
Program current Iw = 10 (μ
Inhale A). In the second frame, the second drive T
FT11b2 is selected and this current is passed through the EL element 15. The EL element 15 emits light according to the current of the second drive TFT 11b2. Therefore, if the two frame periods are averaged, the EL element 15 becomes the first drive TFT 11b1.
Thus, the second drive TFT 11b2 emits light with a brightness corresponding to the average current. Program current Iw = 10
If it is (μA), light is emitted with a brightness of 10/2 = 5 (μA). Therefore, the two driving TFTs 11b1 and TFTs
Even if the characteristics of 11b2 are deviated, the same program current I
By flowing w, the TFT is current-programmed while maintaining the relationship of the current mirror. In addition, since the current is passed through the EL element 15 once in each of the two FTs 11b in the two-frame period, the correctly programmed current can be passed through the EL element in the two-frame period.

FIG. 314 shows a state in which the corresponding pixel is selected and current programming is being performed in FIG. 313.
An on-voltage (Vgl) is applied to the gate signal line 17a,
The TFT 11c and the TFT 11d are turned on. TFT11a
A program current Iw flows from the source driver 14 to the source driver (not shown). The off voltage (Vgh) is applied to the gate signal line 17f1 and the gate signal line 17f2 as well.
The FT 11f1 and the TFT 11f2 are in the off state (note that in the case of a current mirror, the gate signal line 17f1,
The ON voltage (Vgl) may be applied to the gate signal line 17f2 to turn on the TFTs 11f1 and 11f2). The program current Iw is supplied from the driving TFT 11a.

Originally, since the TFT 11b1 and the TFT 11b2 are formed adjacent to each other, there should be almost no characteristic deviation. However, the Vt voltage and the like are different from those formed by the low temperature polysilicon technology. Therefore, even if the gate (G) terminals of the driving TFT 11b1 and the TFT 11b2 are made common and the same voltage is applied to the gate (G) terminal, the driving TFT 11b1 and the TFT 11b2 are not connected to each other.
The current multiplication factor is different from that of a, and the current flowing through the EL element 15 is different. Here, for ease of explanation, TF
There is a 3: 7 difference between T11b1 and TFT11b2,
The current ratio between the TFT 11a and the TFT 11b is 2: 1.
Will be explained. That is, the program current Iw = 10
(ΜA), the TFT 11b1 supplies a current of 3 (μA), and the TFT 11b2 supplies a current of 7 (μA). That is, the program current Iw = Ib1 + Ib
2 = 3 (μA) +7 (μA) = 10 (μA).

When the pixel is in the non-selected state, the state shown in FIG.
The state (a) (first frame) is obtained. Gate signal line 1
The off voltage (Vgh) is applied to 7a, the TFT 11c,
The TFT 11d turns off. At the same time, the gate signal line 17f
An on-voltage (Vgl) is applied to 1 to turn on the TFT 11f1. Further, the off voltage (Vgh) is applied to the gate signal line 17f2, and the TFT 11f2 is in the off state.

Therefore, the current Idd1 from the drive TFT 11b1 flows through the EL element 15. This current is TF
If the characteristics of T11b1 and TFT 11b2 are the same, Idd1 = Iw / 2 = 5 (μA). But,
In reality, the characteristics of the TFT 11b1 and the TFT 11b2 are deviated. Here, for ease of explanation, the TFT 11b is
1 will be described as Idd1 = 3 (μA). Therefore, in the first frame, the EL element 15 emits light with a current of 3 (μA).

In the second frame following the first frame, the operation described in FIG. 314 is performed again. That is, the corresponding pixel is selected and the current program is being performed. Similarly to the first frame, the ON voltage (Vgl) is applied to the gate signal line 17a, and the TFT 11c and the TFT 1
1d turns on. A program current Iw = 10 (μ) from the TFT 11a toward the source driver (not shown) 14.
A) flows.

When the pixel is in the non-selected state, the state shown in FIG. 315 (b) is obtained in the second frame. Gate signal line 17a
OFF voltage (Vgh) is applied to the TFT 11c, TF
T11d turns off. An off voltage (Vgh) is applied to the gate signal line 17f1 to turn off the TFT 11f1. Further, the ON voltage (Vgl) is applied to the gate signal line 17f2, and the TFT 11f2 is turned on.

Therefore, this time, the driving TFT 11b2 is
A current Idd2 from the element flows into the EL element 15. It has been described in the description of the first frame that this current is Idd1 = Iw / 2 = 5 (μA) if the characteristics of the TFT 11b1 and the TFT 11b2 are the same. However, the characteristics of the TFT 11b1 and the TFT 11b2 are actually different from each other. Here, in order to facilitate the description, Idd2 of the TFT 11b2 will be described as 7 (μA). Therefore,
In the second frame, the EL element 15 emits light with a current of 7 (μA).

The above-mentioned state is shown in FIG.
There are 12 states. FIG. 312 (a) shows the first frame, and FIG. 312 (b) shows the second frame. That is, the write pixel row 871 is selected in the first frame, and a current of 10 (μA) flows through the source signal line 18. Then, the pixel 16 is current-programmed and the TFT
A current of 3 (μA) is passed through the EL element 15 by 11a1.

As shown in FIG. 312 (b), the write pixel row 871 is selected in the second frame, and a current of 10 (μA) flows through the source signal line 18. Then, a current is programmed in the pixel 16, and a current of 7 (μA) is caused to flow through the EL element 15 by the TFT 11a2. Therefore, if two frames are averaged, (3 (μA) +7 (μ
A)) / 2 = 5 (μA), and the program current Iw =
A half current of 10 (μA) flows through the EL element 15.

According to the above driving method, even if the characteristics of the two driving TFTs 11a formed in the pixel vary, the average current flowing through the EL element 15 does not vary. That is, a current accurately proportional to (or the same as) the program current Iw flows through the EL element 15. Therefore, uniform image display can be realized.

Note that in FIG. 313, the program current Iw
The TFT that supplies the electric current is TFT 11a, and one pixel is one, and the TFT that supplies a current to the EL element 15 is the TFT 1b1.
There are two TFTs 11b2. In addition, the TFT 11b
1 and the TFT 1b2 are alternately switched for each frame to flow to the EL element 15. However, the present invention is not limited to this. For example, a TFT that supplies the program current Iw is a pixel 2 of the TFT 11a1 and the TFT 11a2.
The individual TFTs are used as TFTs 1b
It may be one. This is because there is a current mirror relationship.

In this case also, the operation is similar to that in FIG.
In the first frame, the source driver 14 draws the program current Iw = 10 (μA). This current Iw is supplied from the two TFTs 11a1 and 11a2. In the first frame, the first TFT 11a1 is selected,
The TFT 11a1 and the TFT 1b maintain a current mirror relationship, and the current of the TFT 11b is passed through the EL element 15. The EL element 15 emits light according to the current of the TFT 11b.

In the second frame, the program current Iw = 10 (μA) is drawn into the source driver 14. This current Iw is supplied from the two TFTs 11a1 and 11a2. In the second frame, the second TFT 11a
2 is selected, the current mirror relationship is maintained between the TFT 11a2 and the TFT 1b, and the current of the TFT 11b is passed through the EL element 15. The EL element 15 emits light according to the current of the TFT 11b.

With the above operation, when averaging two frames in the EL element 15 (total of two frames), there is no variation in current (correctly corresponding to the program current Iw).
You can

In the above-mentioned embodiment, the pixel configuration is the current programming, but as shown in FIG. 316, the voltage programming pixel configuration also absorbs the characteristic variations of a plurality of driving TFTs and realizes the in-plane uniform display. It goes without saying that you can do it. Driving TFT 11a1 for passing a current through the EL element 15
A switching TFT 11f1 for turning on and off the current is formed. Further, the driving TFT 11a2 for supplying a current to the EL element 15 and the switching TF for turning on / off the current.
T11f2 is formed.

The operation is almost the same except for programming in FIG. 308 with current and voltage. As illustrated in FIG. 317, in the first frame, the source driver 14 outputs the program voltage, and the capacitor 19 is programmed with the voltage. In the first frame, as shown in FIG. 318 (a), the first drive TFT 11b1 is selected, and this current is supplied to the EL element 1
Flush to 5. The EL element 15 is the first drive TFT 11
It emits light according to the current of b1.

In the second frame, as in the first frame,
The program voltage is output from the source driver 14, and the voltage is held in the capacitor 19. In the second frame,
Select the second drive TFT 11b2 and set this current to E
Flow to L element 15. The EL element 15 uses the second drive T
It emits light according to the current of the FT 11b2. Therefore, E
The L element 15 lights up with the brightness obtained by averaging the currents output from the two driving TFTs 11a.

The same applies to the pixel configuration of the voltage program shown in FIG. 68 (see FIG. 319). A driving TFT 11a1 for supplying a current to the EL element 15 and a switching TFT 11f1 for turning on / off the current are formed.
In addition, the driving TFT 11a2 that allows a current to flow through the EL element 15
A switching TFT 11f2 for turning on and off the current is formed. The operation is also similar to that of FIG. 316, and thus the description is omitted. As shown in FIG. 320, needless to say, a TFT 11g for applying a reverse bias voltage may be added to FIG. 309.

FIG. 1, FIG. 21, FIG. 43, FIG. 71, FIG.
69, 70, 71 and the like are common to the current program method, but there is a problem that black display is difficult in the current program method (of course, if the present invention shown in FIGS. However, it is effective to combine the following embodiments with each other, and it goes without saying that the following embodiments may be implemented independently without being combined with the embodiments of FIGS. Nor). For example, even if the white peak current flowing through the EL element 15 is 2 μA, in the case of 64-gradation display, the first gradation is 2 μA / 64≈30 n.
It is A. It is quite difficult to charge / discharge the parasitic capacitance (stray capacitance) 404 of the source signal line 18 or the like with this minute current during the 1H period. Although the pixels 16 are formed or arranged in a matrix, only one pixel is shown in the drawings for ease of explanation.

To address this problem, in the present invention, the voltage source 401 for writing the black level voltage (current) to the source signal line 18 is formed or arranged. Specifically, the voltage source 401 is configured so that a predetermined voltage is generated by a DC / DC converter, and this voltage can be applied by the power source switching means 403 including an analog switch or the like.

FIG. 57 shows a concrete signal waveform applied to the source signal line 18. The voltage (V which turns off the driving TFT 11b (TFT 11a in FIG. 1 etc.) or displays almost black during the first t2 period of the 1H period in which current programming is performed.
b) is applied to the source signal line 18. This voltage is generated by the voltage source 401 and applied to the source signal line 18 by the switching means 403.

[0842] In the program period, the TFTs 11c and 11d are
Is on, the voltage Vb applied to the source signal line 18 is the terminal voltage of the capacitor 19, that is, the TFT.
It becomes the gate terminal voltage of 11b. Therefore, the pixel is in black display (non-lighting state) at the beginning of the 1H period.

Originally, when the displayed image is black, the terminal voltage of the capacitor 19 is maintained as it is. When the image to be actually displayed is white display, the voltage Vw for white display (which should be expressed as Iw in the case of current programming) is applied after the Vb voltage is applied, and this voltage (current) is held in the capacitor 19. Then, the 1H period ends. Here, for ease of explanation, it is assumed that the voltage Vw (current Iw) for white display is applied because the image actually displayed is white display. But of course, in the case of natural paintings,
The voltage held in the capacitor 19 is a voltage (current) between Vb and Vw.

As shown in FIG. 57, the source signal line 18
A good black display can be realized by applying a signal to the gate line and driving the gate signal lines 17a and 17b.
An image display such as FIG. 31 can be performed.

Even with the pixel configuration of FIG. 1, good black display can be realized by applying the signal waveform of FIG. Driving TF in the first t2 period of the 1H period in which current programming is performed.
A voltage (Vb) for turning off T11a or displaying almost black is applied to the source signal line 18. This voltage is the voltage source 401
And the source signal line 18 is generated by the switching means 403.
Apply to.

[0847] In the program period, the TFTs 11b and 11c are
Is on, the voltage Vb applied to the source signal line 18 is the terminal voltage of the capacitor 19, that is, the TFT.
It becomes the gate terminal voltage of 11a. Therefore, the pixel is in black display (non-lighting state) at the beginning of the 1H period.

As described above, when the image displayed is black, the terminal voltage of the capacitor 19 is maintained as it is. When the image actually displayed is white display, the voltage Vb for white display is applied after the Vb voltage is applied (in the case of the current program, I
(which should be expressed as w) is applied, this voltage (current) is held in the capacitor 19, and the 1H period ends.

The voltage source 401 (pre-charge circuit) shown in FIG. 40 and the like is formed on the substrate 4 by low temperature polysilicon technology or the like.
Needless to say, it may be directly formed on the substrate 9. Since the EL element 15 has different element configurations and materials for R, G, and B, the voltage (current) at which light is generated is often different (rising voltage (current)). In order to deal with this characteristic, it is preferable that the precharge voltage can be set individually for R, G, and B. It is preferable that at least one of the three primary colors can be changed.

The precharge time t for applying Vb is
2 must be 1 microsecond or more. The precharge time t2 for applying Vb is preferably 1% or more and 10% or less of 1H. More preferably, it is 2% or more and 8% or less of 1H.

Further, it is preferable that the voltage to be precharged can be changed depending on the content (brightness, definition, etc.) of the display image 21. For example, when the user pushes the adjustment switch or turns the adjustment volume, this change is detected and the value of the precharge voltage (current) is changed. You may comprise so that it may change automatically according to the content and data of the image to display. For example, the intensity of external light is detected by a photo sensor, and the precharge (discharge) voltage (current) is adjusted by the detected value. In addition, the precharge (discharge) voltage (current) is adjusted according to the type of image (computer image, daytime screen, starry sky, etc.). The adjustment is determined in consideration of the average brightness of the image, the maximum brightness, the minimum brightness, the moving image, the still image, and the brightness distribution.

[0851] The precharge circuit and the like have been briefly described with reference to FIG. Further, a more detailed description will be given with reference to FIG. Since the discharge and the precharge are simply in the direction of applying the potential, hereinafter, the discharge and the precharge are synonymously described as the precharge.

FIG. 122 shows a circuit configuration in which current driving and voltage driving are combined. The switching circuit 1223 is connected to the source signal line 18 having a display area. The switching circuit 1223 is composed of an analog switch. A voltage is applied to the terminal a of the switching circuit 1223 (precharge voltage), and a program current for programming the pixel is applied to the terminal b.

The current output circuit 1222 has 8 bits (256
Gradation) IDATA is input, and this IDATA is DA
DA conversion is performed by the converter 1226 to obtain an analog voltage. This analog voltage is applied to the base terminal of the bipolar transistor (or FET) 1227, and is converted into a current output by the action of the operational amplifier 1224b and the resistor 1228. The transistor 1227 and the operational amplifier 1
The voltage-to-current conversion circuit according to 224 or the like is general and well known to those skilled in the art, so that further explanation will be unnecessary.

On the other hand, the voltage output circuit 1221 has a volume V
It is composed of a buffer circuit including an R1225 and an operational amplifier 1224a. The volume 1225 is common to all source signal lines. By adjusting the volume 1225, the precharge voltage Vb is determined.

The first precharge voltage Vb in one horizontal scanning period (1H) is applied. At this time, the switching circuit 1223 connected to all the source signal lines is connected to the terminal a. Therefore, all the source signal lines 18 are set to the precharge voltage Vb. After that, the switching circuit 1223 is switched to the terminal b, and the current data (256 gradations) corresponding to the image is applied to the source signal line 18. This current data is written in each pixel 16, and a current flows through the EL element 15 of each pixel to emit light.

In FIG. 122, the precharge voltage Vb has a fixed value. FIG. 123 shows a precharge voltage of 256.
FIG. 7 is a circuit configuration diagram that allows a value (8 bits) to be taken. In FIG. 123, the voltage output circuit 1221 receives 8-bit VDATA and is converted into an analog voltage by the DA converter 1226a. The converted analog voltage is input to the-terminal of the operational amplifier 1224c, and is configured so that it can be adjusted to a predetermined voltage with respect to the reference voltage of the VR1225.

The output of the operational amplifier 1224c is passed through the buffer amplifier 1224a to a of the switching circuit 1223a.
Applied to the terminals. On the other hand, b of the switching circuit 1223a
Current output is applied to the terminals.

VDATA is a voltage corresponding to IDATA. 1 to 10 μsec at the beginning of one horizontal scanning period (1H)
A precharge voltage Vb corresponding to VDATA is applied during a period (preferably 1/100 to 1/5 of 1H). At this time, the switching circuit 1223 connected to all the source signal lines is connected to the terminal a. Therefore, each source signal line 18 is connected to VDATA.
Is set to a precharge voltage Vb. 12
The difference from 2 is that the precharge voltage Vb is applied to each source signal line.
Can be set. That is, each source signal line 18
In addition, a DA converter for converting IDATA to DA and a DA converter for converting VDATA to DA are provided. However, each source signal line 18 has an IDA
DA converter that converts TA to DA and VDATA to D
The present invention is not limited to having a DA converter for A conversion. This is because, for example, even one DA circuit can be realized by sampling and holding the output of each source signal line.

The voltage converted from VDATA is applied in the first period of 1H. This voltage value is the ID applied later.
It becomes almost equal to the source signal line potential due to the current value corresponding to ATA. Therefore, by applying the voltage of VDATA, the potential of the source signal line becomes almost the target value, and I
Only the target value is corrected with DATA. With the above configuration, insufficient current writing to the source signal line 18 is eliminated.

In FIG. 124 (a), the switching circuit 1223a switches between the a terminal and the b terminal, but the invention is not limited to this. For example, FIG.
As shown in (b), the output of the voltage output circuit 1221 is applied to the a terminal, and the output of the current output circuit 1222 is output from the source signal line 1.
8 may be always connected.

By providing the DA converter 1226 capable of changing the output in accordance with the reference voltage, the flexibility of the circuit configuration is further improved. The output changeable according to the reference voltage means, for example, that the output can be changed at intervals of 0.01 (V) when the reference voltage V is 2.54 (V) (8 bits, 256 gradations). When using the DA converter of). When the reference voltage V is 5.08 (V), the output can be changed at intervals of 0.02 (V).

That is, by changing the reference voltage, the output of the DA converter can be instantaneously changed in proportion to the reference voltage. FIG. 124 is a circuit block diagram when such a DA converter is adopted.

In FIG. 124, the DA converter 1226a is shown.
Is applied with the Vref voltage. Vref voltage is V
RV * resistor and switch circuit 1223 for dividing v voltage into four
It is output from the circuit composed of b. Therefore, Vref
The voltage is switched in four steps by the CVS signal. That is, the output of the DA converter 1226a can be instantaneously switched in four steps.

On the other hand, the DA converter 1226b outputs Ire
The f voltage is applied. Iref voltage is Vi voltage 4
The signal is output from the circuit composed of the RV * resistor to be divided and the switch circuit 1223c. Therefore, the Iref voltage is CI
It can be switched to four stages by the S signal. That is, the output of the DA converter 1226b can be instantaneously switched in four steps.

By configuring as shown in FIG. 124, the current (voltage) output to the source signal line 18 can be changed in four steps in the period of 1H. For this usage, first apply a high voltage (current) for a moment,
The target value is quickly reached by application, and then the voltage (current) is changed to a steady value, and the target value is set. That is, the voltage (current) written in the pixel can be changed at high speed.

However, the configuration of FIG. 124 has a considerably large circuit scale. Generally, the configuration shown in FIG. 125 is sufficient. The configuration of FIG. 124 has the voltage output circuit 1
221 is configured to be able to output two voltage values. One of the two voltages is a voltage that makes the image display black. The other one is a voltage for whitening the image display.
Specifically, if the Vdd voltage in FIG. 1 is 6 (V), the black voltage is 3 (V) to 4 (V) and the white voltage is 1 (V) to.
2 (V). The white voltage and the black voltage are adjusted by VR1225, and this voltage is adjusted by the buffer amplifiers 1224a and 1224a.
It is applied to the switch circuit 1223b via 24c.
The output of the switch circuit 1223b is switched by the VSL voltage.

The first precharge voltage Vb (white voltage or black voltage) in one horizontal scanning period (1H) is applied. Each source signal line is connected to the terminal c of the switching circuit 1223a. Therefore, each source signal line 18
Set to precharge to white voltage or black voltage. After that, the switching circuit 1223 is switched to the terminal b, and the current data (256 gradations) corresponding to the image is applied to the source signal line 18. This current data is written in each pixel 16, and a current flows through the EL element 15 of each pixel to emit light.

In the above embodiments, each source signal line 18 is set to be precharged to the white voltage or the black voltage first, but the present invention is not limited to this. Display data (V
When DATA, IDATA) is above a predetermined value or below a predetermined value, it is more realistic to precharge.

FIG. 126 illustrates the case of 64-gradation display for ease of explanation. In FIG. 126 (a), 5
The range (KW) from the 7th gradation to the 63rd gradation is precharged with the white voltage. That is, the voltage output circuit 122 of FIG.
The white voltage is output from 1. Further, the range (KB) from the 0th gradation to the 7th gradation is precharged with the black voltage. That is,
The voltage output circuit 1221 of FIG. 125 outputs the black voltage. From the 8th gradation to the 56th gradation, the voltage output circuit 122
The output of 1 is in a high impedance state (the switch of the switching circuit 1223a does not select the terminal a).

As described above, the white voltage is applied to the gradation to be displayed in white, and the black voltage is applied to the gradation to be displayed in black.
Further, by not precharging the halftone portion (KM), it is possible to achieve high-speed gradation display satisfactorily.

In the case of the current program method, black display is
Program current (current written in pixel) is 5 nA or more 2
Since it is as small as 0 nA or less, insufficient writing occurs. The original black display can be realized by precharging the black voltage. However, insufficient writing may occur even with a dark gray display. In this case, it is effective to perform the second black precharge in addition to the white and black precharge.

FIG. 126 (b) shows this embodiment. KB
By precharging the range of 1 with the black voltage, the original black display can be realized. Then, by precharging the range of KB2 to the second black (gray), it is possible to realize a sufficient gray scale display of the gray portion close to black.

More specifically, in the pixel configuration of FIG. 1, if the Vdd voltage is 6 (V), the black voltage for precharging in the range of KB1 is 3 (V) to 3.5 (V). )
The black voltage for precharging KB2 in gray is 3.5 (V) to 4.0 (V). The white voltage in the KW range is 1 (V) to 2 (V). In the range of KM, precharge by voltage is not performed.

In FIG. 126 (b), for ease of explanation,
The case of 64-gradation display is illustrated. In FIG. 126B, the range (KW) from the 57th gradation to the 63rd gradation is precharged with the white voltage. Range from 0th gradation to 7th gradation (K
B1) is precharged with a black voltage. 15th from the 8th gradation
The gradation range (KB2) is precharged with the second black voltage. Voltage output circuit 1 from the 16th gradation to the 56th gradation
The output of 221 is in a high impedance state (the switch of the switching circuit 1223a does not select the terminal a).

As described above, more appropriate gradation display can be realized by dividing the black range into a plurality of ranges and procharging them with different voltages. Note that FIG.
6 (b) has two black areas, but the present invention is not limited to this and may be three or more. Further, the precharge may be collectively performed on all the source signal lines. These circuit configurations are shown in FIG.
It is easy to arrange three or more switches and select three or more switches 1223b.

In FIG. 126, the current flowing through the EL element 15 at gradation 0 (black display) is not 0 (A). E
The L element 15 does not emit light unless a predetermined current or more is passed. The current in the range that does not emit light is called dark current. The dark current is about 10 nA or more and 50 nA or less when the pixel size is 10,000 square μm. Within this dark current range, the pixel is displaying black. Therefore, current flows even at gradation 0. The driver IC 14 needs to be driven by a current to which a dark current is added.

Hereinafter, the circuit configuration shown in FIGS. 122 to 125 is referred to as an output stage circuit 1271. Output stage circuit 127
As shown in FIG. 127, 1 is a general configuration example in which it is arranged (formed) on each source signal line 18. Fig. 127
In the above, the output stage circuit 1271 is illustrated as being formed in the source driver IC 14 formed of a silicon chip, but the present invention is not limited to this, and may be formed directly on the glass substrate 82 at the same time as the pixel TFT 11 and the like. Good.
In other words, high temperature polysilicon technology, low temperature polysilicon technology, CGS (Continu
ous Grain Silicon) technology, a method of forming and growing a seed crystal on a substrate developed by Fujitsu Ltd., and a semiconductor circuit formed on a quartz substrate developed by Seiko Epson Ltd. The output stage circuit 1271 may be formed by a technique of forming it on a glass substrate or the like. When the substrate 82 is a metal substrate or a semiconductor substrate, directly
It goes without saying that the output stage circuit 1271 can be formed.

The driver IC 14 uses a gold (A) with a height of several μm to 100 μm on the signal terminal electrode portion of the IC by using a plating technique or a nail head bonding technique.
A protruding electrode (not shown) made of u) is formed.
The protruding electrode and each signal line are made of a conductive bonding layer (not shown).
Are electrically connected via. The conductive bonding layer is mainly made of epoxy-based or phenol-based adhesive as an adhesive and is mixed with flakes of silver (Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO2), etc. ,
Alternatively, it is an ultraviolet curable resin or the like. The conductive bonding layer is
It is formed on the protruding electrode by a technique such as transfer.

Although the drive IC 14 (12) is shown or described as being mounted on the substrate, the present invention is not limited to this. Alternatively, the IC 14 (12) may not be mounted on the substrate 11 and may be connected to the signal line by using a film carrier technique and using a polyimide film or the like on which the IC is mounted.

In FIG. 127, the output stage circuit 1271 is arranged only at one end of the display area 21, but the present invention is not limited to this. For example, as shown in FIG. 128, driver ICs 14a and 14b may be arranged.
In FIG. 128, two gate driver ICs 12 are also formed. That is, the display area is composed of 21a and 21b. With this configuration, the display areas 21a and 21b can display different images.

Since the screen 21 is divided into two in the configuration of FIG. 128, the video signal output from the output stage circuit 1271 may have a half operating frequency as compared with the case where there is one screen 21. Further, the parasitic capacitance generated in the source signal line 18 and the like is halved. Therefore, the output stage circuit 1271
Is ½ × 1/2 = 1/4. Therefore, even if the current output from the output stage circuit 1271 is minute, the parasitic capacitance of the source signal line 17 can be sufficiently charged and discharged. That is, the write shortage does not occur.

In the configuration of FIG. 128, the display area 21 is displayed on the screen 2
Since 1a and the screen 21b are divided into two at the central portion, a boundary may be seen at the division position. FIG. 129 addresses this issue. The source driver 14a has a display area 2
The odd pixel rows of 1 are driven, and the source driver 14b drives the even pixel rows of the display area 21. Therefore, screen 2
The boundary of 1 does not occur.

In order to further improve the shortage of the write current to the pixel, as shown in FIG.
Two outputs may be provided to the output stage circuit 1271 corresponding to each source signal line 18 in 14a and 14b. That is, the output stage circuit 1271a includes two output stages (output stage A and output stage B), the output stage A is connected to the odd pixel rows of the display region 21a, and the output stage B is an even pixel of the display region 21a. Connected to a row. Also, the output stage circuit 1271
b also has two output stages (output stage A, output stage B),
The output stage A is connected to the odd pixel rows of the display region 21b, and the output stage B is connected to the even pixel rows of the display region 21b. With such a configuration, it is possible to cause a sufficient current to flow in the source signal line even with a minute current, and good image display can be realized.

Note that in FIG. 130, the output stage circuit 127
Although 1 has been described as connecting one source signal line 18 to each pixel, the present invention is not limited to this.
Each pixel may be driven by two source signal lines (one source signal line for bias current and the other source signal line for bias current + signal current).

FIG. 131 is a more specific module configuration diagram. In FIG. 131, 14b is a source driver, and 14a is a chip in which a gate driver and a source driver are integrated. 14a drives the gate signal line of the display area 21. The driver 14a has a display area 2
The source signal line 18a of 1a is driven. 14b drives the source signal line 18b and drives the display area 21b.

FIG. 131 is an example, and the chip 1
4b also has a gate driver function, and may be configured to drive the gate signal line 17b in the display area 21b. Further, although the power supply IC 102 and the control IC 102 are illustrated as being stacked on the printed circuit board 103, the present invention is not limited to this and may be directly formed on the substrate 82. Using the previously described polysilicon technology and the like. It goes without saying that this can be applied to FIGS. 10 and 11. Other configurations are shown in FIGS.
8 and FIG. 130, etc., and the description thereof will be omitted.

The control and roll IC 101 is a driver 14a
And both 14b. Signals (power supply wiring, data wiring, etc.) supplied from the control IC 101 to the driver 14a are supplied via the flexible substrate 104c. However, since the drivers 14b are considerably distant from each other, they are first connected to the back surface of the substrate 82 by the flexible substrate 104a.

FIG. 132 is a view of the substrate 82 observed from the back surface. Signal wiring (including power wiring) on the back surface of the substrate 82
1321 is formed. The signal wiring 1321 is made of copper,
Aluminum (Al), silver, silver-palladium, palladium,
It is formed of a metal material such as gold or Al-Mo. The signal wiring 1321 transmits a signal from one end of the substrate 82 to the other. The flexible substrate 104b is connected to one end of the substrate 82, and the driver 14 is connected to the flexible substrate 104b.
A signal or the like is supplied to b. Note that FIG. 133 corresponds to FIG.
2 is a drawing when viewed from A of FIG.

FIGS. 40, 57, 122 to 126.
Has been described by exemplifying the pixel configuration of the current programming method as shown in FIGS. 1, 21, 43, and 71, but it is not limited to this. For example, FIG. 54, FIG. 67, FIG.
The pixel configurations of the voltage programming method shown in FIG. 8, FIG. 103, FIG. 120 and FIG. 121 are also effective. In that case, FIG.
The signal applied to the b terminal of the second switching circuit 1223 needs to be a voltage. This change is easy, and a person of ordinary skill in the art can easily cope with it. In the voltage driving, there is no shortage of charge due to the parasitic capacitance of the source signal line 18, but by adopting the method of simultaneously applying the voltage to a plurality of pixel rows, the driving circuit and the signal processing circuit are simplified, and good voltage This is because black display can be realized. In addition, the hidden display of the image can be realized, and the TFT
This is because the effect of 11 variations is also absorbed.

Therefore, the matters described with reference to FIGS. 122 to 126 are all the display panels, display devices, and
It goes without saying that it can be applied to information display devices and the like.

FIG. 41 shows an embodiment in which the P channel of the TFT 11 of FIG. 1 is an N channel. As described above, the present invention can be applied to various pixel configurations. Figure 4
Also in 1, the TFT 11d can be turned on / off by controlling the gate signal line 17, and it is needless to say that the image display of FIG. The drive waveforms shown in FIGS. 33 and 35 are the same or similar, and thus the description thereof will be omitted. It is also effective to use only the TFTs 11b and 11c as n-channel TFTs in FIG. This is because the punch-through voltage to the capacitor 19 is lowered and the holding characteristic of the capacitor is also improved.

Note that FIG. 41 shows a configuration including only the current source 402. That is, the voltage source 401 for performing the precharge is not provided. However, when the parasitic capacitance 404 is relatively small or the 1H period is sufficiently long, the voltage source 4
Even without 01, black display can be sufficiently realized. Also, FIG.
As described in Section 1 and the like, when implementing the complete non-display area 312, the voltage source 401 is often unnecessary. If necessary, it may be configured as shown in FIG.

Also, FIG. 43 shows an embodiment in which the P channel of the TFT 11 of FIG. 21 is an N channel. As described above, the present invention can be applied to various pixel configurations. Also in FIG. 43, the TFT 11e and the like can be turned on and off by controlling the gate signal line 17,
Needless to say, the image display shown in FIG. 31 and the like can be realized, and therefore the description thereof will be omitted. The drive waveforms shown in FIGS. 33 and 35 are the same or similar, and thus the description thereof will be omitted.

As described above, the voltage source 401 outputs Vb as described above.
Good black display can be realized by applying a voltage (Ib current).

When N = 10 or more and a high current pulse is applied to the EL element 15, the EL terminal voltage also rises. The EL element 15 has different rising voltages and gamma curves for R, G, and B. In particular, since B has a gentle gamma curve, the terminal voltage of the EL element 15 tends to increase. If the terminal voltage is adjusted to the EL element 15 of a color (R, G, B colors) having a high rising voltage and a gentle gamma curve, power consumption increases.

One method of solving this is a method of separating the cathode by R, G and B shown in FIG. Note that R,
It is not necessary for G and B to have different cathode potentials.
In particular, only one color cathode whose gamma curve is different from other colors may be separated. Alternatively,
A configuration in which the Vdd power supply voltage is separated as shown in FIG. 58 is also effective. That is, Vdd power supply for R color is set to VddR,
In this configuration, the G color Vdd power supply is VddG and the B color Vdd power supply is VddB. By separating in this way, it is possible to adjust each of RGB with separate power supplies,
Even if the terminal voltages of the RGB EL elements 15 are different, the increase in power consumption is slight.

Note that it is not necessary for R, G, and B to have different Vdd potentials. In particular, Vdd of only one color whose gamma curve is different from other colors may be separated. Further, as shown in FIG. 59, the configuration of FIG. 5 may be combined. That is, R, G, and B, which are methods of separating R, G, and B, have different cathode potentials (R pixel is Vs.
R and G pixels are VsG, and B pixels are VsB). In particular, only the cathode potential of only one color whose gamma curve differs from other colors may be separated. Further, the Vdd power supply voltage is separated. The R color Vdd power source is VddR, the G color Vdd power source is VddG, and the B color Vdd power source is Vdd.
The configuration is B. Also in this case, it is not necessary to set different Vdd potentials for R, G, and B. In particular, Vdd of only one color whose gamma curve is different from other colors may be separated.

58 and 59, the pixel 16 is shown in FIG.
However, the configuration is not limited to this, and FIG.
1, FIG. 22, FIG. 43, FIG. 44, FIG. 41, FIG. 42, FIG.
It goes without saying that the configurations shown in FIG.

The problem to be solved by the present invention is that the current applied to the EL element 15 is instantaneous, but there is a problem that it is N times larger than the conventional one. If the current is large, the life of the EL element may be shortened. In order to solve this problem, it is effective to apply the reverse bias voltage Vm to the EL element 15.

The method of applying a reverse bias will be described below. In order to apply the reverse bias, it is necessary to individually control the gate terminals of the TFT 11b and the TFT 11c in the configuration of FIG. That is, TFT 11b and T
It is necessary to individually turn on / off the FT 11c. This control method will be described with reference to FIG.

First, as shown in FIG. 52 (a), the TFT
11c is turned on and the TFT 11d is turned on (see also FIG. 1). Then, the reverse bias voltage Vm and E
The voltage is applied to the a terminal of the L element 15. The Vm voltage is a voltage lower than Vs. Vm voltage is 5 (V) or more than Vs 1
It is a low voltage within 5 (V).

Note that the signal line 1 for supplying the reverse bias voltage is
7 is preferably formed parallel to the source signal line 18. Since it can be formed with low resistance wiring and there is no cross with the source signal line 18, the reverse bias signal line and the source signal line 1
Coupling with 8 hardly occurs. Of course,
The signal line 17 for supplying the reverse bias voltage is connected to the gate signal line 1
It may be formed in parallel with 7.

When the EL element 15 is turned on, a high voltage of 5 (V) or more and 15 (V) or less with respect to Vs is applied to the a terminal. That is, the Vm voltage is the EL element 1
Ideally, a voltage whose absolute value is the same and whose polarity is opposite to that of the voltage applied when 5 is turned on is applied. In reality, it is difficult to apply voltages having the same absolute value and opposite polarities, so a voltage of 2-3 times the reverse polarity is applied. By applying the reverse bias as described above, the EL element 15 hardly deteriorates.

Next, as shown in FIG. 52 (b), the TFT
11d is turned off and TFT 11b is turned on. And
The black voltage Vb is written in the capacitor 19. This operation is described in FIG. Next, as shown in FIG. 52C, the TFT 11 is turned on and off in the same state as in FIG. 52B, and the image display voltage (current) from the current source 402 is written in the capacitor 19. This operation is also described in FIG. Finally, as shown in FIG.
b and 11c are turned off, the TFT 11d is turned on, and a current is passed through the EL element 15 to turn on the EL element 15.

The above operation is shown in FIG. 1H period t
The reverse bias voltage Vm is applied to the source signal line 18 for 1 hour, the Vb voltage is applied during the next t2 period, and the image data Vw (Iw) is applied during the t3 period. The other operations have been described with reference to FIG. 52 and the driving method and the like with reference to FIGS.

119 to 121 In the configuration shown in FIG. 52,
When the current of the source signal line 18 is taken into the pixel 16, E
A reverse current flows through the L element 15. Therefore, EL
When the element 15 is an organic electroluminescent element, it becomes possible to delay the electrochemical deterioration due to the redox reaction of organic molecules, as in the case where a reverse voltage is applied.

FIG. 102 shows an energy diagram of a three-layer organic light emitting device composed of anode / hole transport layer / light emitting layer / electron transport layer / cathode. The behavior of the positive and negative carriers during light emission is shown in FIG. The electron is the cathode
More holes are injected into the electron transport layer, and at the same time holes are also injected into the hole transport layer from the anode. Injected electrons,
The holes move to the counter electrode due to the applied electric field. At that time, they are trapped in the organic layer or carriers are accumulated due to the difference in energy level at the interface of the light emitting layer.

When space charges are accumulated in the organic layer, the molecules are oxidized or reduced, and the generated radical anion molecules or radical cation molecules are unstable, resulting in deterioration of the film quality and reduction in brightness. It is known that driving voltage during current driving increases. In order to prevent this, as an example, the device structure is changed and a reverse voltage is applied.

In FIG. 102 (b), since the reverse current is applied, the injected electrons and holes are extracted to the cathode and the anode, respectively. This eliminates the formation of space charges in the organic layer and suppresses the electrochemical deterioration of the molecules, which makes it possible to prolong the life.

Although the three-layer type element is described in FIG. 102, even in the four-layer type or more multilayer type element and the two-layer type or less element, electrons and holes injected from the electrodes cause formation of an organic film. Electrochemical degradation is similar. Therefore, it becomes possible to prolong the life according to this embodiment regardless of the number of layers. It is also effective in a device in which a plurality of materials are mixed in one layer because electrochemical deterioration of molecules similarly occurs.

As described above, the feature of the present invention is to provide the function of preventing the deterioration of organic molecules and the function of supplying the bias current for preventing the waveform distortion due to the stray capacitance parasitic on the source signal line. That is, display is possible without increasing the number of transistors required for a pixel. That is, it is an advantage that the number of transistors for supplying a reverse current does not have to be increased because the aperture ratio of each pixel of the display device does not have to be reduced.

The effect of applying the reverse bias voltage Vm will be described with reference to FIG. FIG. 109 shows the emission luminance of the EL element 15 and the terminal voltage of the EL element when driven with a predetermined current. In FIG. 109, the dotted solid line b indicates the EL element 15
3 shows the terminal voltage of the EL element 15 when the reverse bias voltage Vm is applied to. The alternate long and short dash line c indicates the terminal voltage of the EL element 15 when the reverse bias voltage is not applied to the EL element 15. The solid line a shows the emission luminance ratio of the EL element 15 when the reverse bias voltage is applied to the EL element 15 (dotted line a) (ratio when the initial luminance is 1).

In FIG. 109, specifically, the case where the EL element emits R light and is current-driven at a current density of 100 A / square meter. Sample B continuously applies a current having a current density of 100 A / square meter for time t. The terminal voltage increased at the lighting time of 1500 hours and drastically decreased, and after 2500 hours, only about 15% of the initial luminance was obtained.

Sample A was pulse-driven at 30 Hz, a current density of 200 A / square meter was applied during half the time t2, and a reverse bias voltage of -14 (V) was applied during the latter half time t1 (that is, , And the average emission luminance per unit time is the same in Samples A and B). In the sample A, the terminal voltage of the EL element 15 hardly changed as shown by the dotted line b, and the lighting time at which the luminance was 50% was 4000 hours.

As described above, the application of the reverse bias voltage Vm does not increase the terminal voltage of the EL element 15 and reduces the reduction rate of the emission luminance. Therefore, the EL element 15
It is possible to realize long-life driving.

FIG. 108 shows changes in the reverse bias voltage Vm and the terminal voltage of the EL element 15. The terminal voltage is when the rated current is applied to the EL element 15. Figure 1
08 is the case where the current passed through the EL element 15 has a current density of 100 A / square meter, but the tendency of FIG. 108 is almost the same as the case of the current density of 50 to 100 A / square meter. Therefore, it is estimated that it can be applied in a wide range of current density.

The vertical axis represents the ratio of the initial terminal voltage of the EL element 15 to the terminal voltage after 2500 hours. For example, when the elapsed time is 0 hours, the terminal voltage is 8 (V) when a current density of 100 A / square meter is applied, and the elapsed time is 2500 hours, the current density is 100 A.
/ Terminal voltage when current of square meter is applied is 10
If it is (V), the terminal voltage ratio is 10/8 = 1.25.

The horizontal axis shows the ratio of the rated terminal voltage V0 to the product of the reverse bias voltage Vm and the time t1 when the reverse bias voltage is applied in one cycle. For example, 60Hz (especially 60
However, if the time when the reverse bias voltage Vm is applied is 1/2 (half), t1 = 0.5. Further, at the elapsed time of 0 hours, the current density is 100 A
/ The terminal voltage (rated terminal voltage) when a current of square meter is applied is 8 (V), and the reverse bias voltage Vm is 8
If (V), then | reverse bias voltage × t1 | / (rated terminal voltage × t2) = | −8 (V) × 0.5 | / (8 (V)
× 0.5) = 1.0.

According to FIG. 108, | reverse bias voltage × t
When 1 | / (rated terminal voltage × t2) is 1.0 or more, the terminal voltage ratio does not change (it does not change from the initial rated terminal voltage). The effect of applying the reverse bias voltage Vm is well exhibited. However, when | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 or more, the terminal voltage ratio tends to increase. Therefore, | reverse bias voltage × t1
The magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or the ratio of t1 and t2) may be determined so that | / (rated terminal voltage × t2) is 1.0 or more. Further, preferably, | reverse bias voltage × t1 |
The magnitude of the reverse bias voltage Vm and the application time ratio t are set so that / (rated terminal voltage × t2) becomes 1.75 or less.
You may decide 1 or the like.

However, when the bias driving is performed, it is necessary to alternately apply the reverse bias Vm and the rated current.
When it is attempted to equalize the average brightness per unit time of the samples A and B as shown in FIG. 109, when a reverse bias voltage is applied, it is necessary to instantaneously pass a high current as compared with the case where no reverse bias voltage is applied. . Therefore, the reverse bias voltage V
When m is applied (Sample A in FIG. 109), the terminal voltage of the EL element 15 also becomes high.

However, in FIG. 108, the rated terminal voltage V0 is the terminal voltage satisfying the average luminance (that is, the terminal voltage for lighting the EL element 15) even in the driving method in which the reverse bias voltage is applied (this specification). According to the specific example of the document, the terminal voltage is when the current density of 200 A / square meter is applied, but since it is 1/2 duty, it is 1
The average luminance of the cycle is the luminance at a current density of 200 A / square meter).

The above items assume that the EL element 15 is a white raster display (when the maximum current is applied to the EL elements on the entire screen). However, when displaying an image on the EL display device, it is a natural image, and gradation display is performed. Therefore, the white peak current of the EL element 15 (current flowing at maximum white display; in the specific example of the present specification, average current density of 100 A / square meter of current) does not always flow.

[0923] Generally, when displaying an image, each EL is
The current applied to the element 15 (current flowing) is about 0.2 times the white peak current (current flowing at the rated terminal voltage. According to the specific example of the present specification, current density is 100 A / square meter current). is there.

Therefore, in the embodiment shown in FIG. 108, it is necessary to multiply the value on the horizontal axis by 0.2 when displaying an image. Therefore, | reverse bias voltage × t1 | /
The magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or the ratio between t1 and t2) may be determined so that (rated terminal voltage × t2) is 0.2 or more. Further, preferably, | reverse bias voltage × t1 |
/ (Rated terminal voltage x t2) is 1.75 x 0.2 = 0.3
The magnitude of the reverse bias voltage Vm, the application time ratio t1 and the like may be determined so as to be 5 or less.

That is, on the horizontal axis of FIG. 108 (| reverse bias voltage × t1 | / (rated terminal voltage × t2)), 1.
The value of 0 must be 0.2. Therefore, the image is displayed on the display panel (this state of use will be normal.
It will not display the white raster all the time)
The reverse bias voltage Vm is applied for a predetermined time t1 so that | reverse bias voltage × t1 | / (rated terminal voltage × t2) becomes larger than 0.2. Further, even if the value of | reverse bias voltage × t1 | / (rated terminal voltage × t2) becomes large, the increase in the terminal voltage ratio is not large as shown in FIG. Therefore, considering the white raster display as the upper limit, | reverse bias voltage × t1 | /
The value of (rated terminal voltage × t2) may be set to satisfy 1.75 or less.

The reverse bias method of the present invention will be described below with reference to the drawings. In the present invention, the reverse bias voltage Vm
It is basically applied (current). However, the present invention is not limited to this. For example, the reverse bias voltage Vm may be forcibly applied while a current is flowing through the EL element 15. In this case, as a result, no current will flow through the EL element 15, and the EL element 15 will be in a non-lighting state (black display state). Further, although the present invention is mainly described by applying the reverse bias voltage Vm in the pixel configuration of the current program, the present invention is not limited to this. For example, the TFT 11e is turned off in FIG.
Similarly to the above, if the reverse bias voltage Vm is applied to the anode of the EL element 15, the application of the reverse bias voltage Vm described below can be easily realized even in the pixel configuration of the voltage programming method. Therefore, the effects described with reference to FIG. 108 and the like can be exhibited.

In FIG. 90, a switching TFT 11g for applying a reverse bias voltage Vm is arranged or formed in the pixel configuration of FIG. 1 (a). The gate terminal of the TFT 11g is connected to the control gate signal line 17d. TFT1
By turning on 1 g, the Vm voltage is applied to the anode of the EL element 15.

FIG. 90 is an explanatory diagram of the driving method of the reverse bias voltage applying system of the present invention. First, FIG. 107 (a1)
When the voltage Vgl is applied to the gate signal line 17a as shown in, the TFTs 11b and 11c are turned on. Then, as shown in FIG. 107 (a2), the program current Iw flows from the source driver 14 to the TFT 11c and the like, and the capacitor 19 is current-programmed. Note that the number is not limited to N times, but here, for ease of explanation, N times is set.
It is assumed that the doubled current is programmed and the current Id is supplied to the EL element 15 for a period of 1 F / N.

Next, as shown in FIG. 107 (b1), the voltage Vgh is applied to the gate signal line 17b, and TF is applied.
T11b and 11c turn off. When the voltage Vgl is applied to the gate signal line 17b at the same time (not limited to the same time), the TFT 11d is turned on. Then, FIG.
As shown in (c2), the current Id, which is current-programmed, flows through the TFT 11a from the power supply Vdd to the EL element 15. Therefore, the EL element 15 emits light as shown in FIG. 107 (c1). As for the emission brightness, if the conversion efficiency of the program is 100%, the light emission is about N times as high.

[0930] The light emitting period is 1 F / N. Remaining 1F
During the period (1-1 / N), the TFT 11d is in the off state, and the EL element 15 is not illuminated (black display). In the black display, no current flows through the EL element 15, so that a complete black display can be realized. Further, since the white peak current is large during light emission, the light emission brightness is also high. Therefore, the driving method of the present invention can realize a very high contrast display.

[0931] During the period of 1F, the current of 1 time is applied
When the current is passed through the element 15 (conventional driving method), if black display is realized and used, it is necessary to program the black display current in the capacitor 19. However, in the current driving method, the current value at the time of black display is small, so that there is a problem that the resolution is largely affected by the parasitic capacitance and the resolution is insufficient. Also,
There is also a problem that black floating occurs. In addition, the penetration voltage from the gate signal line 17 is also affected. Due to these problems, the EL element 15 is in a slightly lit state even in the black display portion. Therefore, the contrast becomes very poor.

In the system of the present invention, no current completely flows through the EL element 15 during the period of 1F (1-1 / N). Therefore, perfect black display can be realized. That is, the black floating does not occur. Therefore, high-contrast display can be realized without performing the precharge for black display described in FIG.

Of course, it goes without saying that the method shown in FIG. 90 or the like may be added to the method shown in FIG. 52 or the like. In addition, the fact that high contrast display can be realized is also similarly effective in the pixel configuration of the voltage program shown in FIG. 54, FIG. 67, FIG. By performing 1F / N pulse drive, the period of 1F (1-1 / N) is E
This is because no current flows through the L element 15 and high contrast display can be realized. Of course, good moving image display can be realized by intermittently displaying images.

Also, depending on the pixel configuration, when the punch-through voltage acts in the direction of increasing the current flowing through the EL element 15, the white peak current increases and the contrast feeling of image display increases. Therefore, good image display can be realized.

As shown in FIG. 107 (d1), an on voltage is applied to the gate signal line 17d to turn on the TFT 11g. At this time, the TFT 11d is turned off. T
By turning on the FT 11g, the anode of the EL element 15 (depending on the pixel configuration, the reverse bias voltage V
In some cases, m may be applied to the cathode of the EL element 15. Also, the reverse bias voltage Vm may be a positive voltage.
A reverse bias voltage Vm (also expressed as a reverse bias current Im flows). Since the EL element 15 can be regarded as a capacitor in terms of a circuit, an AC current flows when a reverse bias voltage is applied. This is because the accumulated charge is discharged.). The application time t1 is configured to satisfy the state of FIG. 108 (FIG. 107 (d2)).

[0936] EL is applied during the period in which the reverse bias voltage Vm is applied.
It is preferable to set the period during which the current Id does not flow through the element 15. This is because when Id flows, a reverse bias voltage and a short-circuit state occur (which is not impossible).

In FIG. 107 (d1), the period for applying the reverse bias voltage Vm is set to one of 1F, but the period is not limited to this, and it is not limited to this.
In the period of F, the reverse bias voltage Vm may be applied to the EL element 15 twice or more or three times or more).

This control is easy. Gate signal line 17
This is because the on / off voltage may be applied to the gate signal line 17d at an arbitrary timing during the period in which the off voltage is applied to b. It suffices that the total sum of these ON times is t1 hours described with reference to FIG.

Further, the period of the period 1F (1-1 / N) in which no current flows through the EL element 15 may be divided into a plurality of periods. The division suppresses the occurrence of flicker. The period 1F (1-
When the (1 / N) period is divided into a plurality of periods, the reverse bias voltage Vm may be applied during the period.
However, it is not necessary to apply the reverse bias voltage Vm to all of the divided periods of 1F (1-1 / N) during which no current flows through the EL element 15.

In the driving method in which the reverse bias voltage is not applied and the current does not flow in the EL element 15 as shown in FIG. 109, it is necessary to correct (or supplement) the contents described in FIG. That is, the time t1 described in FIG. 108 is the time when the reverse bias voltage Vm is applied. The time t2 is the time when the current is applied to the EL element 15.

The reverse bias voltage Vm does not have to be a DC fixed value. Vm = −8 (V) is fixed and applied. That is, the reverse bias voltage Vm may be a sawtooth waveform signal or a pulse waveform signal. Alternatively, a sine wave signal waveform may be used. In this case, the reverse bias voltage is an integrated value of the waveform or an effective value. Further, although the application time t1 is unclear, the effective value obtained by integrating the Vm voltage may be a rectangular waveform, and the time when the rectangular waveform is applied may be t1.

For example, the waveform of the reverse bias voltage is shown in FIG.
It is assumed that the voltage waveform (triangular wave) shown in FIG. Maximum amplitude value is 16 (V), application time is t1 = 100
(Μsec). In this case, FIG.
As shown in (b), it is equivalent to a voltage waveform with a maximum amplitude value of 8 (V) and an application time of t1 = 100 (μsec). Further, as shown in FIG. 115 (c), the processing may be performed by assuming that the voltage waveform has a maximum amplitude value of 16 (V) and an application time of t1 = 50 (μsec). The above items also apply to the positive voltage applied to the EL element 15.

The same items apply to the current Id flowing through the EL element 15.
Is also applicable. In other words, the current (voltage) flowing through the EL element 15 may not be a direct current, but may be a sine-shaped current waveform. In this case as well, it may be converted into an effective value of DC and converted into the application period t2 of the rectangular wave.

As shown in FIG. 91 (a), the reverse bias voltage Vm is applied for all periods except the period for applying the ON voltage to the gate signal line 17a (normally, 1H period: program period). The application period of the reverse bias voltage Vm may be set.

[0945] Also, since it is acceptable to apply the reverse bias voltage to the EL element 15 while the current Id is not applied, as shown in Fig. 91 (b), the gate signal line 1
The reverse bias voltage Vm may be applied during a period including a period (program period) in which the ON voltage is applied to 7a (see FIG. 91 (b), a period in which the current Id is applied to the EL element 15 ( The reverse bias voltage Vm is applied except during the period when the ON voltage is applied to the gate signal line 17b).

Note that the matters concerning the application time, the application method, the application timing, etc. of the reverse bias voltage Vm described with reference to FIGS. 91 and 107 are also applicable to the other embodiments.

As described above, the present invention has the non-lighting period 312 in the 1F period. By providing this non-lighting period, the moving image display performance is improved. Further, since the non-lighting time is provided, the reverse bias voltage can be applied to the EL element 15 during the non-lighting period. Therefore, the EL element 15 does not deteriorate and the terminal voltage does not rise. Therefore, the power supply voltage Vdd can also be set low.

In FIG. 91, the reverse bias voltage is applied immediately before the EL element 15. As another configuration, as illustrated in FIG. 92, a configuration in which a reverse bias voltage Vm (current −Im) is applied to the EL element 15 via the TFT 11d is also illustrated.

By applying an on-voltage to the gate signal line 17d, the TFT 11g is turned on and the reverse bias Vm is applied. At the same time, by turning on the TFT 11d as well, a reverse bias voltage can be applied to the EL element 15. In the configuration of FIG. 92, the application of the reverse bias voltage Vm can be controlled by both the TFT 11g and the TFT 11d. Therefore, control becomes easy and flexibility is improved.

As the voltage applied to the gate signal line 17, the ON voltage is applied when the corresponding pixel is selected. The off voltage is applied during the non-selected period. Therefore, as for the voltage applied to the gate signal line, the off voltage is applied in most of the period of 1F. Therefore, the off voltage can be used as the reverse bias voltage.

The off voltage is normally lower than the cathode voltage because it turns off the TFT completely (of course, the opposite is true when the TFT is a P channel). Especially T
When the FT is amorphous silicon, the off voltage is usually set to be quite low.

In the configuration of FIG. 93, the TFTs 11b and 11c connected to the gate signal line 17a are n-channel TFTs.
I am trying. Therefore, at the voltage Vgh, the TFT 11b,
11c is turned on and turned off at the voltage Vgl. The voltage Vgl is applied to the gate signal line 17b during most of 1F. This voltage Vhl is the reverse bias voltage Vm
(Vgl = Vm).

The TFT 11g is also controlled by the voltage applied to the gate signal line 17d as in the previous embodiment. Note that the voltage applied to the gate signal line 17d is TFT1
Since the on / off of 1 g is controlled, the applied voltage is not limited to Vgh and Vgl, and any other voltage can be used.

When the TFT 11g is turned on, the voltage Vgl applied to the gate signal line 17a is applied to the EL element 15. Therefore, the reverse bias voltage Vm can be applied to the EL element 15. In the configuration of FIG. 93,
Since the signal line for supplying the reverse bias voltage Vm as in 2 is unnecessary, the pixel aperture ratio can be improved. Note that in FIG. 93. It may be configured so that the voltage applied to the gate signal line 17b is applied to the EL element 15 (it is necessary to consider the configuration such that the TFT 11d is an n-channel).

FIG. 93 has a configuration in which the voltage of the gate signal line 17 is set to the reverse bias voltage. 94 shows the source signal line 1
In this configuration, the voltage applied to 8 is used as the reverse bias voltage of the EL element 15. The reverse bias voltage Vm is applied to the source signal line 18 at the timing when the TFT 11g is turned on. The voltage Vm applied to the source signal line 18 is EL
It is applied to the element 15. Therefore, the reverse bias voltage Vm can be applied to the EL element 15. The timing and the like have been described with reference to FIG.

The time for applying the reverse bias voltage Vm is E
When it is longer than the period in which the current is applied to the L element 15, as shown in FIG. 95, it is also effective to short the anode and cathode terminals of the EL element 15.
This is because the voltage charged in the EL element 15 is discharged.

[0957] In Fig. 95, when the TFT 11g is turned on, the anode and cathode terminals of the EL element 15 are short-circuited. Due to the short circuit, the holes accumulated in the hole transport layer of the EL element 15 are extracted, and the electrons accumulated in the electron transport layer are also extracted. Therefore, deterioration of the EL element can be suppressed. Needless to say, the matters concerning the application time, the application method, the application timing, etc. of the reverse bias voltage Vm described with reference to FIGS. 91 and 107 are also applicable to the embodiment of FIG.

In FIG. 95, each TFT is composed of p-channel. FIG. 96 shows the configuration of FIG. 95 changed to n channels. In FIG. 96, when the TFT 11g is turned on, the anode and cathode terminals of the EL element 15 are short-circuited. Vdd on the anode and cathode terminals
A voltage is applied. During this period, the holes accumulated in the hole transport layer of the EL element 15 are extracted, and the electrons accumulated in the electron transport layer are also extracted. Therefore, deterioration of the EL element can be suppressed. Note that, as in FIG.
Items such as the application time, the application method, and the application timing of the reverse bias voltage Vm described in FIG.
It goes without saying that this is also applied to the sixth embodiment and the like.

The reverse bias voltage Vm can be applied to the EL element 15 also by changing the control direction in which the current flows. FIG. 97 is a block diagram thereof. In FIG. 97, 402 is a constant current source.

In FIG. 97, when the TFT 11g is on, a current in the same direction as the constant current source 402 flows through the TFT 11g. Therefore, a forward voltage is applied to the EL element 402. When the TFT 11g is off, the EL element 15 and the current source 402 form a loop, so that the direction of the current flowing through the EL element 15 is reversed. That is, by disposing or forming the constant current source 402,
The reverse bias voltage Vm can be easily applied to the EL element 15 by controlling the TFT 11g. Signal line 1 at this time
The timing of No. 7 is shown in FIG. The ON voltage is applied to the gate signal line 17d during a period other than the period in which the gate signal line 17a is selected.

Therefore, the holes accumulated in the hole transport layer of EL element 15 are extracted, and the electrons accumulated in the electron transport layer are also extracted. Therefore, deterioration of the hole transport material due to oxidation and reduction of the electron transport material can be suppressed.

In FIG. 99, the TFT 11g is an n-channel, the TFT 11g is in the off state when the TFT 11d is on, and the TF is when the TFT 11d is off.
In this configuration, T11g is turned on. Therefore, T
The EL element 15 is turned on when the FT 11d is turned on, and the EL element 15 is turned on when the TFT 11g is turned on.
A reverse bias voltage Vm is applied to.

It is effective to set the reverse bias voltage Vm to a voltage lower than the cathode voltage Vk. However, in order to separately generate the reverse bias voltage Vm, a generation circuit is required. To cope with this problem, a flying capacitor is formed in FIG. The flying capacitor circuit 1001 may be arranged (formed) for each pixel, or one circuit may be arranged (formed) on the panel.

The flying capacitor 1001 is operated by controlling the gate signal lines 17e and 17f.
The gate signal line 17e and the gate signal line 17f are operated in opposite phases.

First, an on-voltage is applied to the gate signal line 17e to turn on the TFTs 11i and 11j, and the capacitor 1
The Vdd voltage is applied to 9b. At this time, the gate signal line 1
An off voltage is applied to 7f to charge the capacitor 19b, and then the TFTs 11h and 11k are turned off.

Next, an ON voltage is applied to the gate signal line 17e to turn off the TFTs 11i and 11j, and an ON voltage is applied to the gate signal line 17f to turn on the TFTs 11h and 11k. Then, the voltage Vdd charged in the capacitor 19b has an opposite phase, and the −Vdd voltage is applied to the EL element 15.

With the above-mentioned structure, the Vm voltage (Vm = -Vdd) having the opposite phase can be generated. Therefore, the Vm voltage supply wiring is not required.

Although the above embodiments have been described mainly by exemplifying the pixel configuration of the current programming method described in FIG.
The present invention is not limited to this, and as shown in FIG. 101, even in the pixel configuration of the current mirror, the reverse bias voltage V
It goes without saying that it can be configured so that m can be applied. Note that the operation will not be described because the configuration described in FIG. Also, as shown in FIG. 89,
It goes without saying that the reverse bias voltage can be applied even with the pixel configuration of the voltage program. 54, 67,
The same applies to FIG. 103 and the like. Therefore, even in the pixel configuration of the voltage program, the configuration or method of applying the reverse bias voltage to the EL element 15 at the time of non-lighting can be applied.

In the above embodiments, the present invention has been described as a configuration or system in which a reverse bias voltage is applied to the EL element 15 when it is not lit. This is not limited to displaying the display 21 and applying the reverse bias voltage Vm to the EL element 15 when the EL element 15 is not lit. In the active matrix EL display panel, a configuration in which a reverse bias is constantly applied when the LED is not lit is also within the scope of the present invention.

For example, the reverse bias voltage Vm may be applied to the EL elements 15 of the entire screen 21 for a predetermined period after the use of the EL display panel is finished. Further, the EL element 15 of the entire screen 21 may be sequentially scanned and the reverse bias voltage Vm may be applied for a predetermined period after the use of the EL display panel is completed. In addition, when using the EL display panel (for example, power on
Hour), during a predetermined time. The EL elements 15 of the entire screen 21 may be sequentially scanned to apply the reverse bias voltage Vm. Further, when the EL display panel is not used, the reverse bias voltage may be applied at predetermined time intervals (for example, every 10 hours for every 1 hour). On the contrary, when using the EL display panel, a predetermined time interval (for example, 10 seconds every 1 hour)
Alternatively, a reverse bias voltage may be applied to each.

The above-mentioned embodiments have the configuration in which the reverse bias voltage Vm is applied during the period when no current is applied to the EL element 15. However, the configuration for applying the reverse bias is not limited to this. For example, when the display panel of the present invention is used in a mobile phone, the reverse bias is applied when the mobile phone is not used.

For example, a configuration in which the reverse bias voltage Vm is applied to the EL element 15 for a predetermined period after the power switch of the mobile phone is pressed is illustrated. Further, a configuration in which a reverse bias voltage is applied to the EL element 15 for a predetermined period after using the mobile phone is also exemplified. Alternatively, in the case of a foldable mobile phone, when the folded state is changed to the used state, a reverse bias voltage is applied to the EL element 15 for a predetermined period, and conversely, when the folded state is changed from the used state to the predetermined state. A configuration in which a reverse bias voltage is applied to the EL element 15 during the period is illustrated.

FIG. 321 shows the above embodiment. Figure 32
1 shows one pixel for ease of explanation,
Practically, the pixels are arranged in a matrix like 176 RGB × 220.

In FIG. 321, reference numeral 3211 denotes a voltage detection circuit. The voltage detection circuit 3211 detects that the power button is pressed. When the voltage detection circuit 3211 detects the voltage, it outputs a signal to the gate drive circuit 14b to operate the gate driver circuit 14b.

The gate drive circuit 14b outputs an on voltage to the gate signal line 17d to turn on the TFT 11g. When the TFT 11g is turned on, the reverse bias voltage Vm becomes E.
It is applied to the anode of the L element 15.

As described above, in the configuration of FIG. 321, voltage detection is performed and the reverse bias voltage Vm is applied to the EL element 15 for a certain period. When the reverse bias voltage is applied, the source driver circuit 14 and the like are not operated.

[0977] In FIG. 43, the TFT 11 that constitutes a pixel
Is 5. However, in FIG. 1 (a), it is composed of four pieces. Therefore, the configuration shown in FIG. 1A has the advantages that the number of TFTs 11 constituting the pixel 16 is one less, so that the aperture ratio can be increased and the pixel defect occurrence rate is small.

FIG. 44 also shows the pixel configuration of the current program system. Current programming can be performed by applying an on-voltage to the gate signal line 17a. Further, by applying an off voltage to the gate signal line 17b,
A programmed current can be passed through the EL element 15 by applying an on-voltage to b.

Also in the configuration of FIG. 44, gate signal line 17
By applying an on-voltage or an off-voltage to c, E
The current flowing through the L element 15 can be controlled, and the driving method or display state shown in FIG. 31 or the like can be realized.

Although the TFT 11e is added in FIG. 44, it is possible to realize the image display such as FIG. 31 by deleting the TFT 11e, operating the gate signal line 17b, and controlling the on / off state of the TFT 11d. Needless to say.

FIG. 53 also shows a pixel configuration of a current programming method. Current programming can be performed by applying an on-voltage to the gate signal line 17a. Further, by applying an off voltage to the gate signal line 17b,
A programmed current can be passed through the EL element 15 by applying an on-voltage to b.

Also in the configuration of FIG. 53, gate signal line 17
By applying an on-voltage or an off-voltage to c, T
Since the FT 11d can be turned on and off, the EL element 15
It is possible to control the electric current flowing through the device. Therefore, FIG.
The driving method or display state shown in FIG.

Note that FIG. 54 shows an example of the pixel configuration of voltage programming. The present invention controls the application time of the current flowing through the EL element 15 for a predetermined time of one field or one frame (1F, of course, 2F or more may be considered as one segment), and thereby a predetermined light emission brightness is obtained. Is the way to get. This is a method of obtaining a predetermined brightness by making the current flowing through the EL higher than the predetermined brightness and shortening the ON time for the brightness higher than the predetermined brightness.

FIG. 103 also shows a pixel configuration by voltage programming. In FIG. 103, 19a is a capacitance for detecting a threshold, and 19b is a capacitance (capacitor) for holding an input signal voltage.

In step 1 (section 1), the TFT1
Since the TFTs 11e are all turned on from 1a to turn on the drive transistor once, the deviation of the current value occurs due to the variation of the threshold value.

[0987] In step 2 (section 2), the TFT1
1b, the TFT 11d remains ON, and the TFTs 11c, T
When the FT 11e is turned off, the current value of the drive transistor 11a becomes 0, so that the threshold value of the drive transistor 11a is set to the threshold value detection capacitor 19
a is detected.

In step 3 (section 3), the TFT1
1b, the TFT 11d is turned off, the TFT 11c,
By turning on the TFT 11e, the input signal voltage of the data signal line is changed to the input signal voltage holding capacitor 19b.
At the same time, the signal voltage obtained by adding a threshold value to the input signal voltage is applied to the gate of the drive transistor 11a to current-drive the EL element 15 to emit light.

Since the driving transistor 11a operates in the saturation region, a current proportional to the square of the voltage value obtained by subtracting the threshold value from the gate voltage flows, but the gate voltage has the threshold detecting capacitance 11a. As a result, the threshold value is already applied, so that the threshold value is canceled. Therefore, even if the threshold value of the driving transistor 11a varies, a constant current value always flows through the EL element 15 as shown in the simulation result.

In step 4 (section 4), when the pixel 16 enters the non-selection period, the TFT 11b and the TFT 11d are turned off, the TFT 11e is turned on, and the TFT 11c is turned on.
Even in the FF, since the input signal voltage held in the input signal voltage holding capacitor 19b and the threshold voltage held by the threshold detecting capacitor are applied to the gate of the drive transistor 11a, the EL element The current continues to flow through 15 and continues to emit light.

As described above, in order to detect the threshold value of the driving transistor more accurately, the period of the first step is set to 2 μsec or more and 10 μsec or less, and the period of the second step is set to 2 μsec or more and 10 μsec or less. It is necessary to set. This is to secure sufficient writing or operation time. However, if it is too long, the original voltage programming time becomes short and the stability is lost.

Therefore, it is effective to implement the driving method or the display device of the present invention even in the voltage programming method of FIG. In FIG. 54, the gate signal line 17b
The TFT 11d can be turned on and off by controlling the. Therefore, the current flowing through the EL element 15 can be made intermittent. Further, also in FIGS. 54, 67, and 103, by controlling the gate signal line 17c,
The TFT 11e can be on / off controlled. Therefore, the display states shown in FIGS. 31 and 32 can be realized.

[0992] Further, the driving method of turning on the EL element 15 by N times and controlling the on / off state of the TFT 11e to turn on the light for a period of 1 / N (N
It is clear that the present invention can be realized (not limited to double or 1 / N). That is, the present invention is not limited to only the pixel configuration of the current program shown in FIG. 1, but the driving scheme of the present invention is also realized with the pixel configurations of the voltage program shown in FIGS. 54, 67, 103, 121 and the like. can do. Therefore, the matters described in this specification can be applied to the pixel configuration or device described or illustrated in this specification.

Similarly, FIG. 54, FIG. 67, and FIG. 68 also have pixel configurations for voltage programming. 54, 67, and 68, TF is controlled by controlling the gate signal line 17b.
T11e can be turned on and off. Therefore,
The current flowing through the EL element 15 can be intermittent.
Therefore, the display states shown in FIGS. 31 and 32 can be realized. Therefore, the animation effect can be easily realized. Also, various image displays can be realized. Since other matters and operations are similar or similar to those in FIG. 103, description thereof will be omitted.

Needless to say, the above items can be applied to the reverse bias voltage Vm application method described with reference to FIGS. 52 and 90. The reverse bias voltage Vm may have different voltage values for each of R, G, and B pixels. In that case, a TFT that controls the reverse bias voltage
The number of gate signal lines is increased. EL of each R, G, B
This is because the element 15 has different terminal voltages and applied currents. For example, for the EL element of the R pixel, −15
(V) is applied, and -12 is applied to the EL elements of the G and B pixels.
This is a method of applying (V).

Also, the application time of the reverse bias voltage (current) applied to the R, G, and B EL elements 15 may be different. This is because the terminal voltage and applied current are different for each RGB pixel. For example, the reverse bias voltage Vm is applied to the EL element of the R pixel for 1/2 time of 1F, and the reverse bias voltage Vm is applied to the EL element of the G and B pixels for 1/3 time of 1F. Is the method.

Also, the application time or the application voltage of the reverse bias voltage (current) may be different for each part of the display region 21. This is because, for example, when the Gaussian distribution method for brightening the central portion of the display area is adopted, the EL element in the central portion has a larger current value than the peripheral portion.

As a problem of the method of applying the pulse voltage of N times, there is a problem that the current flowing through the EL element 15 becomes large and the EL element 15 is easily deteriorated. Also, N =
When it is 10 or more, there is a problem that the terminal voltage of the EL element 15 required when a current flows becomes high and the power efficiency becomes poor. However, this task is E
This is a problem that occurs when the current flowing through the L element is large.
This problem is dealt with by taking the pixel configuration of FIG. 1 as an example.
A description will be given with reference to (a).

As shown in FIG. 70 (a), the EL element 1
When the current Idd to 5 is flowing, the Vdd voltage (power supply voltage) is divided by the source-drain voltage (Vsd) of the driving TFT 11a and the terminal voltage (Vd) of the EL element 15. When the Idd current is large, the Vd voltage also becomes high.

When the Vdd voltage is sufficiently high, a current (Idd) equal to the current Iw programmed in the TFT 11a becomes E.
It flows to the L element 15. Therefore, as shown by the solid line in FIG. 81, Iw and Idd have the same or substantially linear relationship (proportional relationship). The linear relationship is established because the capacitor 19 is penetrated by a signal applied to the gate signal line 17 or the like and Idd = Iw is not established.

In the present invention, the Vdd voltage is used at such a low voltage that Idd and Iw cannot maintain a linear (proportional) relationship. That is, the relationship of required Vsd + Vd> Vdd is established. More preferably, it is preferable that Vd> Vdd.

For example, assume that N = 10 and the Iw current required for maximum white display is 2 μA. In this state, if the Idd current is 2 μA, Vd = 14 (V) in the G color EL element. The Vdd voltage at this time is 14
It is (V) or less. Or at this time, Vsd
= 7 (V), Vd + Vsd = 14 (v) +7
That is, (V) = 21 (V) <Vdd = 21 (V).

[1002] When driven in this state, the relationship between Idd and Iw is as shown by the dotted line in FIG. In the maximum white display, the relationship between Iw and Idd is no longer linear (non-linear relationship, range A in FIG. 81). However, in the black display or the gray display (area where the display brightness is relatively low), the linear relationship (range B in FIG. 81) is maintained.

[1003] In the area A, the current flowing through the EL element 15 is limited, and a large current that deteriorates the EL element 15 does not flow. In addition, when the Iw current is increased in the region A, the change ratio is small but the Idd current increases. Therefore, gradation display can be realized. However, gamma conversion is necessary because it is non-linear in the area A. For example, if the image display is 64 gradation display, the input image data 64 gradation data is converted into a table and converted into 128 gradations or 256 gradations and applied to the source driver IC 14.

In the area A, the Vsd voltage of the TFT 11a and the Vd voltage of the EL element 15 are divided to determine the anode voltage Va voltage of the EL element 15. At this time, a noteworthy point is that the EL element 15 is formed uniformly by vapor deposition (or is formed by coating by an inkjet technique or the like), and thus is formed uniformly. Therefore, the EL terminal voltage Va has a uniform value within the surface of the display screen 21. Therefore, the characteristics of the TFT 11a vary and are corrected by the terminal voltage Va of the EL element 15. As a result, by lowering the Vdd voltage as in the present invention, it is possible to absorb the characteristic variation of the TFT 11a, and it is possible to reduce the power consumption by reducing the Vdd voltage. Moreover, even when N is large, a high voltage is not applied to the EL element 15.

[1005] The EL element 15 can be formed not only by the vapor deposition technique and the ink jet technique but also by the stamp technique in which the stamp with the ink is applied to the paper for printing.

[1006] First, a portion to be a stamp is formed. S
A groove pattern of the same shape as the light emitting region of the organic EL element is formed on the i substrate by a semiconductor process, and the groove is formed in
A stamp is made by filling the EL material with the material to be doped. On the other hand, an organic EL material to be an electrode or a light emitting layer is formed on the glass substrate on which the organic EL element is formed.

[1007] Next, the stamp and the glass substrate on which the material to be the organic EL element is attached are exactly overlapped. While maintaining this state, heat treatment is performed at + 100 ° C to + 200 ° C for about 10 minutes. By doing so, the doping material embedded in the groove of the stamp is evaporated and diffused into the light emitting layer of the organic EL element. After that, the stamps in which the doping materials corresponding to the colors are embedded are sequentially applied to the organic EL elements, and RGB stamps are applied.
Paint differently. Using this stamp technology, EL elements 15 with a rectangular pattern of 10 μm or a pattern with a line width of 10 μm
Can be easily formed.

The EL element 1 is set to 1 / N of the 1F period.
The method is to obtain a predetermined brightness by applying a current to No. 5, making the applied current higher than a predetermined brightness, and shortening the ON time for the brightness higher than the predetermined brightness. However, the present invention is a method in which the average of the luminance within a certain period is set to a predetermined value. Therefore, it is not limited to 1F (1 field or 1 frame). For example, in FIG.
The display state of 1) is continuous for 2F, the display state of FIG. 32C2 is continuous for 3F, and the display state of FIG. 32C1 and FIG. 32C2 is continuous.
The state of may be repeated alternately. That is, the driving is performed so that the desired average brightness is obtained at 5F.

Therefore, the technical idea of the present invention is that the EL element 15 is turned on and off within a certain period of time, and the on and off states are alternately repeated.
By repeating this, a predetermined display brightness is obtained. The control is realized by controlling the on / off voltage of the gate signal line 17.

[1010] The source signal line 18 is supplied with a current N times the predetermined current and the EL element 15 is supplied with a current N times the predetermined current for a period of 1 / N, but this cannot be realized in practice. This is because the signal pulse applied to the gate signal line 17 actually penetrates into the capacitor 19 and a desired voltage value (current value) cannot be set in the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set in the capacitor 19. For example, even if driving is performed so as to set a current value of 10 times, only a current of about 5 times is set in the capacitor 19. For example, even when N = 10, the current actually flowing through the EL element 15 is the same as when N = 5. Therefore, the present invention is a method of setting a current value of N times and driving such that a current proportional to or corresponding to N times flows through the EL element 15 (however, FIG. 8).
Since the driving method described in Section 1 is also implemented, it is difficult to limit it).
Alternatively, it is a driving method in which a current larger than a desired value is applied to the EL element 15 in a pulse shape.

[1010] Also, a current (voltage) which is higher than the desired value (a current which becomes higher than the desired brightness when the current is continuously applied to the EL element 15 as it is) is applied to the drive transistor 11a (in the case of exemplifying FIG. 1). Program the EL element 1
By making the current flowing through the LED 5 intermittent, the desired luminance of the EL element can be obtained.

[1012] Also, if FIG. 1 is shown as an example (FIGS. 54 and 5)
7, FIG. 67, FIG. 68, FIG. 89, FIG. 103, and other voltage programming pixel configurations are also effective), and a drive transistor 11a and a signal (current, voltage) path for programming the drive transistor are set. (Constitution, arrangement, connection) First switching element 11
c and the current from the driving transistor 11a is the EL element 1
In the pixel configuration including the second switching element 11d for setting (configuring, arranging, connecting) the flow path of 5, the first switching element 11c is turned on (the path is set). In addition, in the first state in which the second switching element 11d is turned off (the path is cut), the first state in which the current (voltage) is programmed in the drive transistor and the first switching element 11c is turned off (the path is turned off). Disconnect)
The second state in which the second switching element 11d is turned on (path is set) and the first switching element 1 is turned on.
1c is turned off (the path is cut), and the second switching element 11d is turned off (the path is cut).

[1013] In addition, in the active matrix type display panel, the driving transistor 11a to the EL element 15 are connected.
The current path flowing through the line is disconnected or reduced (EL element 1) for a predetermined period of one frame (one field) period.
The waveform of the current flowing through 5 is not limited to a rectangle or DC, and may be a sine waveform. Further, the DC amplitude value may be changed) to reduce the light emission luminance of the EL element 15 in at least one frame (one field).

[1014] In addition, an operation of programming the driving transistor 11a so that the EL element 15 emits light with a luminance higher than a desired value, and the programmed signal (current) is passed through the EL element 15, and at least one frame (1 The operation is performed so that the EL element 15 does not flow during a predetermined period of the field period.

[1015] Alternatively, E is set so that the brightness is equal to or lower than the brightness corresponding to the current programmed in the drive transistor 11a
It is intended to limit the current flowing through the L element 15.

[1016] Further, the EL element 1 has a brightness higher than a desired value.
5 is programmed so that light is emitted, and the average brightness (desired brightness) of one frame (one field) is equal to or less than the desired brightness or at least the desired brightness (programmed brightness (current)). The operation is performed so that the program current does not flow into the EL element 15. Further, it is not limited to completely turning on / off the current flowing through the EL element 15.

[1017] For example, by setting the TFT 11d in the high resistance ON state in FIG. 1 (that is, a current smaller than a predetermined value is flowing in the EL element 15), the EL element 1
5 can be turned off or low-luminance light emission can be performed.
When the EL element 15 emits light with low brightness, it is necessary to understand that the non-lighted area 312 of the display area 21 is replaced with dark (brightness close to gray or black display) instead of completely black display. That is, the non-lighted area 312 may be a display with lower brightness than the normal display. The low-brightness display includes a display state in which an image can be recognized.

[1018] In the above example, the reverse bias voltage is applied during the non-lighting time of the EL element 15 (Fig. 107, Fig. 1).
08), etc.) is effective. Further, it goes without saying that the present invention is also effective for the voltage programmed pixel configurations shown in FIGS. 54, 67, 103 and the like.

[1019] Note that in FIG. 31 and the like, the non-display area 3
12 need not be completely unlit. There is no problem in practice even if there is faint light emission or faint image display. That is, it should be interpreted as an area having lower display brightness than the image display area 311. In addition, the non-display area 31
The term 2 also includes the case where only one or two colors of the R, G, and B image displays are in the non-display state.

[1020] In each pixel configuration (for example, FIGS. 54, 53 (a), 42), even if the gate terminal of the driving TFT 11d can be directly applied with the on / off voltage, the EL element 15 is not formed. It is possible to intermittently operate the current flowing through the. Further, in FIG. 43, the TFT 11e,
The TFT 11a in FIG. 21 and the TF in FIG.
Even if the gate terminal of T11b is configured so that the on / off voltage can be directly applied, the current flowing through the EL element 15 can be operated intermittently. That is, it goes without saying that the display state shown in FIG. 31 and the like can be implemented by controlling the gate terminal of the TFT that applies a current to the EL element 15.

As described above, according to the present invention, the EL element 15 is intermittently displayed by turning on and off the current applied to the EL element 15. To display intermittently,
In the example of FIG. 1, it is necessary to control the TFT 11d to be turned on and off. Therefore, a gate signal line for turning on / off the TFT 11d is required. That is, in order to display the EL element 15 intermittently, a first switching element that forms a path for programming a current flowing through the EL element in the capacitor, and on / off control of the first switching element are provided. The first gate signal line is required.
Further, a second switching element forming a current path flowing through the EL element 15 and a second gate signal line for turning on / off the second switching element are required. That is, two gate signal lines are required for each pixel.

However, if two or more gate signal lines are required for each pixel, this is a problem in the three-side free pixel configuration described with reference to FIG. This is because even if the gate driver 12 is formed by a low temperature polysilicon technique or the like, the number of shift registers becomes large and the circuit configuration becomes complicated. In particular,
The challenge becomes even greater if an amorphous silicon technology is used to realize a three-side free configuration. Because, in the amorphous silicon technology, the driver circuit 12 (14)
This is because it cannot be formed directly on the substrate 82.

[1023] Therefore, if an attempt is made to form a display panel using the amorphous silicon technology, the source driver 14
It is necessary to arrange the gate driver IC 12 on one side of the display area 21. Then, it is necessary to wire all of the gate signal lines 17a and 17b so that they are distributed to the left and right of the display area. If the number of gate signal lines 17 is small, there is still a possibility of being able to cope. However, QCI
Even in F, since the number of vertical pixels is 220 dots, the number of gate signal lines 17 is 220 × 2 = 440.

The above is the case where the display panel is constructed by the amorphous silicon technology, but even when the gate driver 12 is built in by the low-temperature polysilicon technology, if the number of wirings of the gate signal lines 17 is large, the frame cannot be narrowed. Therefore, the product power is lost.

The following inventions solve the above problems. Briefly, a plurality of gate signal lines 17b for turning on / off the EL element 15 are commonly used.
The current flowing through the EL element 15 is turned on / off for each common block.

[1026] Also in the embodiment of FIGS. 87 and 142, E
It is not necessary to control ON / OFF of the L element 15 for each pixel row. Even if each block is turned on / off, the non-lighting area 312 can be formed, and the lighting area 311 can also be formed. The method of performing on / off control in blocks as described above is called block drive. However, since there is an example in which adjacent pixel rows are used as blocks, the concept is broader than the concept of ordinary blocks. However, in the pixel configuration of FIG. 1, the pixel row for which current programming is performed needs to be in a non-lighting state. Therefore, the block including the pixel row selected for the current programming needs to be the non-lighting area 312. But,
Even in the case of FIG. 1, if a slight blurring is allowed in the image, even in the pixel row for which current programming is performed,
It is not necessary to set the non-lighted area 312. In the pixel configuration of the current mirror shown in FIGS. 21, 43, and 71, the non-lighted area 3 is generated even in the pixel row for which the current program is performed.
It does not have to be 12.

The present invention will be described mainly by exemplifying the pixel configuration of the current program shown in FIG. 1. However, the present invention is not limited to this, and the other configurations described with reference to FIGS. 21, 43, 71, etc. It goes without saying that the present invention can also be applied to the current program configuration (pixel configuration of the current mirror). Also, the technical concept of turning on and off in blocks is shown in FIG.
It is needless to say that the present invention can be applied to voltage-programmed pixel configurations such as 4, FIG. 68, and FIG. Further, since the present invention is a method of intermittently flowing the current flowing through the EL element 15, it goes without saying that it can be combined with the method of applying the reverse bias voltage described in FIG. 89 and the like. As described above, the present invention can be implemented in combination with other embodiments.

[1028] FIG. 179 shows an example of block driving.
First, for ease of explanation, the gate driver circuit 12
Will be described as being formed directly on the substrate 49 or having the silicon chip gate driver IC 12 mounted on the substrate 49. The source driver 14 and the source signal line 18 are omitted because the drawing is complicated.

[1029] In FIG. 179, the gate signal line 17a is connected to the gate driver circuit 12. On the other hand, the gate signal line 17b of each pixel is connected to the lighting control line 1791. In FIG. 179, the four gate signal lines 17b are 1
It is connected to one lighting control line 1791.

It is needless to say that blocking with four gate signal lines 17b is not limited to this, and more blocks may be provided. Generally, the display area 21 is preferably divided into at least 5 or more. More preferably, it is preferably divided into 10 or more. Furthermore, it is preferable to divide into 20 or more.
If the number of divisions is small, flicker is easy to see. If the number of divisions is too large, the number of lighting control lines 1791 will increase and the layout of the control lines 1791 will be difficult.

[1031] Therefore, in the case of the QCIF display panel, since the number of vertical scanning lines is 220, it is necessary to block at least 220/5 = 44 or more, and preferably 220/10 = 11 or more. It is necessary to block with. However, when two blocks are formed in the odd-numbered row and the even-numbered row, flicker is relatively small even at a low frame rate, and thus the two blocks may be sufficient.

[1032] In the embodiment of FIG. 179, the lighting control line 179
1a, 1791b, 1791c, and 1791d are sequentially applied with an on-voltage (Vgl) or an off-voltage (Vgl).
gh) is applied to turn on / off the current flowing through the EL element 15 for each block.

[1033] In the embodiment of FIG. 179, the gate signal line 17b and the lighting control line 1791 do not cross each other. Therefore, the gate signal line 17b and the lighting control line 17
The short defect with 91 does not occur. Further, since the gate signal line 17b and the lighting control line 1791 are not capacitively coupled to each other, the lighting control line 1791 to the gate signal line 17b are not connected.
The capacity addition when viewed from the side is extremely small. Therefore, it is easy to drive the lighting control line 1791.

[1034] FIG. 180 illustrates the connection state of FIG. 179 in more detail. A gate signal line 17a is connected to the gate driver 12. A pixel row is selected by applying an on-voltage to the gate signal line 17a, the TFTs 11b and 11c of each selected pixel are turned on, and the current (voltage) applied to the source signal line 18 is applied to the capacitor of each pixel. Program to 19. On the other hand, the gate signal line 17
b is connected to the gate terminal of the TFT 11d of each pixel. Therefore, the on-voltage (Vg
l) is applied, the driving TFT 11a and the EL element 1
5, a current path is formed, and conversely, when an off voltage (Vgh) is applied, the anode terminal of the EL element 15 is opened.

[1035] The control timing of the on / off voltage applied to the lighting control line 1791 and the gate driver circuit 12
Output to the gate signal line 17a by the pixel row selection voltage (Vg
It is preferable that the timing of l) is synchronized with one horizontal scanning clock (1H). However, the present invention is not limited to this. The signal applied to the lighting control line 1791 is simply
It only turns on and off the current to the EL element 15. Further, it does not need to be synchronized with the image data output by the source driver 14. This is because the signal applied to the lighting control line 1791 controls the current programmed in the capacitor 19 of each pixel 16. Therefore, it does not necessarily have to be synchronized with the selection signal of the pixel row. Further, even when synchronized, the clock is not limited to the 1H signal, and may be 1 / 2H or 1 / 4H.

[1036] FIG. 181 shows the case where the pixel configuration is that of the current mirror shown in FIG. However,
As described in the previous embodiment, in order to control the current flowing through the EL element 15, the TFT 11e is formed and the gate signal line 17b for controlling the TFT 11e is formed.
Is added.

[1037] Note that in FIG. 181, the switching T
Although the gate signal line for controlling (turning on / off) the FTs 11c and 11d is common (gate signal line 17a), the present invention is not limited to this and may be a separate gate signal line 17. In this case, the first gate signal line 17 for controlling the TFT 11c and the second gate signal line 17 for controlling the TFT 11d are connected to the gate driver circuit 12.

In FIG. 181, a gate signal line 17a is connected to the gate driver 12. A pixel row is selected by applying an ON voltage to the gate signal line 17a.

[1039] Note that the same applies to FIG. 180 and the like, but the selected pixel row is not limited to one pixel row.
For example, in FIGS. 141, 144, and 146, a plurality of pixel rows are selected. As described above, the present invention is not limited by the number of selected pixel rows.

In FIG. 181, when the selection voltage (Vgl) is applied to the gate signal line 17a, the TFTs 11b and 11d of each selected pixel are turned on, and the source signal line 1 is turned on.
The current (voltage) applied to 8 is applied to the capacitor 19 of each pixel.
To program. That is, the source driver circuit 14 outputs (absorbs) the current (voltage) written in the pixel 16.
On the other hand, the gate signal line 17b is connected to the gate terminal of the TFT 11e of each pixel. Therefore, the lighting control line 1
When the on-voltage (Vgl) is applied to 791, the driving T
A current path is formed between the FT 11b and the EL element 15, and conversely, when an off voltage (Vgh) is applied, the anode terminal of the EL element 15 is opened.

[1041] FIG. 182 is a pixel configuration in which the pixel configuration is a voltage program. However, as described in the previous embodiments, the TFT 11d is formed in order to control the current flowing through the EL element 15 (so that the intermittent operation can be performed), and
A gate signal line 17b for controlling the TFT 11d is added. The gate signal line 17b is connected to the lighting control line 1791 for every plurality of pixel rows.

In FIG. 182, the gate driver 12 is connected to the gate signal line 17a. Gate signal line 1
By applying an on voltage to 7a, the TFT 11b is turned on and a predetermined pixel row is selected.

In FIG. 182, when the selection voltage (Vgl) is applied to the gate signal line 17a, the TFT 11b of each selected pixel is turned on, and the current (voltage) applied to the source signal line 18 is changed. The pixel capacitor 19 is programmed. In other words, the source driver circuit 14 is arranged in the pixel 16
It outputs (absorbs) the current (voltage) written to. On the other hand, the gate signal line 17b is connected to the gate terminal of the TFT 11d of each pixel. Therefore, when the ON voltage (Vgl) is applied to the lighting control line 1791, the driving TFT 11
A current path is formed between a and the EL element 15, and conversely, when the off voltage (Vgh) is applied, the anode terminal of the EL element 15 is opened.

[1044] FIG. 183 shows the pixel configuration of another voltage program, in which the intermittent operation of the current flowing through the EL element 15 is TF.
Performed using T11d. The gate signal line 17d for controlling the TFT 11d is the lighting control line 17d for each plurality of pixel rows.
It is connected to 91.

In the pixel configuration of FIG. 183, two gate signal lines 17a and 17c are required to measure the offset voltage and hold the voltage written in the capacitor 19 for one frame period. Therefore, the two gate signal lines 17a and 17c are connected to the gate driver circuit 12. This configuration is shown in FIG.

[1046] The gate driver circuit 12 includes the gate signal line 1
By applying an on / off voltage to the gate signal line 17c and 7a, the TFT 11c and the TFT 11b are on / off controlled, and the voltage output from the source driver 14 is programmed in the pixel. On the other hand, the gate signal line 17d is connected to the T of each pixel.
It is connected to the gate terminal of the FT 11d. Therefore, when the on-voltage (Vgl) is applied to the lighting control line 1791, a current path between the drive TFT 11a and the EL element 15 is formed, and conversely, when the off-voltage (Vgh) is applied, the EL element 15 is turned on. Open the anode terminal.

As described above, the present invention can be applied regardless of whether the pixel structure is the current program system or the voltage program system. Although the above embodiments have been described by exemplifying the active matrix type display panel, the present invention is not limited to this and can be applied to a simple matrix type display panel. This is because lighting or non-lighting of the EL element 15 for each block can be realized by a simple matrix display panel.

[1048] FIG. 185 shows another embodiment. In the following embodiments, differences from the previous embodiments will be mainly described. Therefore, the pixel configuration and the like in FIG.
Any of 0 to FIG. 183 can be applied.

[1049] In FIG. 185, the gate signal line 17b is commonly used for every two pixel rows, and the lighting control line 17 is provided every four blocks.
The configuration is common to 91. The gate signal line signal line 17b of the first and second pixel rows, and the ninth and tenth pixel signal lines
The gate signal line 17b of the second pixel row is connected to the lighting control line 17
It is common to 91a. Therefore, the lighting control line 17
When the ON voltage (Vgl) is applied to 91a, at least the first, second, ninth, and tenth pixel rows are lit.

Also, the lighting control line 1791b is commonly used for the gate signal line signal line 17b of the third and fourth pixel rows and the gate signal line 17b of the eleventh and twelfth pixel rows. . Therefore, when the ON voltage (Vgl) is applied to the lighting control line 1791b, at least the third, fourth, eleventh and twelfth pixel rows are lit.

[1051] Similarly, the gate signal line signal line 17b of the fifth and sixth pixel rows and the gate signal line 17b of the thirteenth and fourteenth pixel rows are connected to the lighting control line 1791c.
Have in common. Therefore, the lighting control line 1791c
When the on-voltage (Vgl) is applied to, at least the fifth, sixth, thirteenth and fourteenth pixel rows are turned on. In addition, the gate signal line signal line 17b of the seventh and eighth pixel rows and the gate signal line 17b of the fifteenth and sixteenth pixel rows are shared by the lighting control line 1791d. Therefore, when the on-voltage (Vgl) is applied to the lighting control line 1791d, at least the seventh voltage,
The eighth, fifteenth and sixteenth pixel rows are illuminated.

When the gate signal line 17b is connected to the lighting control line 1791 as shown in FIG. 185, small lighting blocks are dispersed and displayed. Therefore, flicker is less likely to occur even at a low rate.

[1053] Fig. 186 shows a configuration in which the gate signal line 17b is connected in common to the lighting control line 1791 by skipping four pixels. The gate signal line signal line 17b of the first, fifth, ninth, and thirteenth pixel rows is the lighting control line 179.
1a is common. Therefore, the lighting control line 17
When the ON voltage (Vgl) is applied to 91a, at least the first, fifth, ninth, and thirteenth pixel rows are lit.

[1054] Also, the second, sixth, tenth,
The gate signal line signal line 17b of the 14th pixel row is shared by the lighting control line 1791b. Therefore, when the on-voltage (Vgl) is applied to the lighting control line 1791b,
At least second, sixth, tenth and first
The fourth pixel row lights up.

[1055] Similarly, the gate control signal lines 17b of the third, seventh, eleventh, and fifteenth pixel rows are shared by the lighting control lines 1791c. Therefore,
When the ON voltage (Vgl) is applied to the lighting control line 1791c, at least the third, seventh, eleventh and fifteenth pixel rows are lit. Also, the 4th and 8th
The gate signal line signal line 17b of the 12th, 16th, and 16th pixel rows is commonly used by the lighting control line 1791d. Therefore, the turn-on voltage (V
gl), at least the 4th, 8th,
The 12th and 16th pixel rows are lit.

When the gate signal line 17b is connected to the lighting control line 1791 as shown in FIG. 186, the pixel rows to be lit are dispersed more than in FIG. 185. Therefore, flicker is less likely to occur even at a low rate.

[1057] FIG. 187 shows the gate signal line 1 of the odd-numbered pixel row.
7b is connected to the lighting control line 1791a, and the gate signal lines 17b of even-numbered pixel rows are connected to the lighting control line 1791b.

[1058] In FIG. 187, the EL element 15 is provided for each pixel row.
Since the lighting can be controlled, flicker is reduced even at a low rate. In addition, the number of lighting control lines 1791 is two, which is small.

[1059] In FIG. 188, the gate signal line 17b is switched to the lighting control line 1791a or the lighting control line 179 every four pixel rows.
1b is connected. In FIG. 188, it is easy to synchronize with the timing of the current (voltage) program to the pixel.

[1060] In the above embodiments, the ON / OFF control is performed for each pixel row by the voltage applied to the lighting control line 1791. The present invention aims at intermittently operating the EL element 15. Therefore, the lighting control line 179
It is not limited to the presence or absence of 1.

For example, in FIG. 189, the lighting control driver circuit 1891 is formed (arranged) on one side of the display area. That is, the gate driver circuit 12 is provided on one side of the display area.
Are formed (arranged), and the lighting control driver circuit 1891 is arranged (formed) on the opposite side of this side.

[1062] The lighting control driver circuit 1891 uses low-temperature polysilicon or high-temperature polysilicon technology,
It may be directly formed on the substrate 49, or may be formed of a silicon chip and mounted on the substrate 49 by using the COG technique or the like. However, as shown in FIG. 189, a plurality of gate signal lines 1
By making 7b common (blocking), the circuit configuration becomes extremely simple. Therefore, even if it is formed directly on the substrate 49, or if it is composed of a silicon chip and stacked on the substrate 49,
Occupies almost no area. Therefore, a narrow frame of the display panel can be realized. The lighting control driver circuit 1
891 is arranged on the same side as the source driver circuit 14,
It goes without saying that a three-side free configuration may be realized.

[1063] In the embodiments up to FIG.
The gate driver circuit 12 has been described as being formed directly on the substrate 49 using low-temperature polysilicon or high-temperature polysilicon technology or formed of silicon chips and mounted on the substrate 49 using COG technology or the like. However, the present invention is not limited to this. For example, FIG.
As shown in FIG. 6, the gate signal line 17a may be wired from the side where the source driver circuit 14 is arranged. That is, both the lighting control line 1791 and the gate signal line 17a are formed at the end of the display area 21. Other configurations are shown in FIG.
The description is omitted because it is similar to 79 or the like.

As shown in FIG. 191, the source driver circuits 14 and the gate driver circuits 12 are arranged (formed) on two sides of the display area, and the gate driver circuits 12 are formed in the central portion of the display area 21. May be connected to the source driver circuit 14. With such a configuration, the routing of the gate signal line 17a is reduced (halved). Therefore, a narrow frame can be realized.

[1065] FIG. 192 is an explanatory diagram in which the source driver circuit 14 and the gate driver circuit 12 are arranged on the panel. In FIG. 192, the source driver circuit 14 is made of a silicon chip and arranged on one side of the substrate 49. The gate driver circuit 12 is formed directly on the substrate 49 by using low temperature polysilicon, CGS technology or high temperature polysilicon technology. The on / off voltage to the lighting control line 1791 is output from the source driver 14.

[1067] FIG. 193 shows a lighting control driver circuit 1891.
In this embodiment, the substrate is directly formed on the substrate 49 by using low temperature polysilicon, CGS technology or high temperature polysilicon technology. Of course, the lighting control driver circuit 18
91 may be made of a silicon chip and mounted on the substrate 49 by using the COG technique or the like.

[1067] FIG. 194 is an example in which the on / off signal to the lighting control line 1791 is output from the controller 101 or the like. By thus configuring the ON / OFF data of the lighting control line 1791 to be output from the controller 103 such as a microcomputer, the specifications of the source driver 14 are simplified, and even if the drive system is changed, the source driver 14 No need to change.

FIG. 195 shows a gate driver circuit 12a and a source driver circuit 14a for driving the display area 21a, and a gate driver circuit 12 for driving the display area 21b.
This is a configuration using b and the source driver circuit 14b. The other structure is similar to that of the previous embodiment, and the description thereof is omitted.

In FIG. 196, an ON / OFF signal to the lighting control line 1791 is output from the controller 101 or the like, and the gate driver circuit 12 and the source driver circuit 14 are provided on the substrate 49 by using low temperature silicon, CGS technology or high temperature polysilicon technology. This is an example directly formed. Of course, the source driver circuit 14, the lighting control driver circuit 1891, and the like are manufactured by a silicon chip, and C is formed on the substrate 49.
You may load using OG technology etc.

In FIG. 197, an ON / OFF signal to the lighting control line 1791 is output from the controller 101 or the like, and a control signal to the gate signal line 17a and image data to the source signal line 18 are realized by the driver circuit 14a.
The driver circuit 14a may be formed directly on the substrate 49 using low temperature silicon, CGS technology or high temperature polysilicon technology. Alternatively, the driver circuit 14a or the like may be manufactured from a silicon chip and mounted on the substrate 49 by using the COG technique or the like.

[1071] The method of applying the reverse bias voltage Vm has been described with reference to Figs. The reverse bias voltage Vm was basically applied to the EL element 15 when no current was applied. On the other hand, FIG.
In the block driving method described in 80 and the like, the non-lighting area 312 and the lighting area 311 are formed for each block.

[1072] Therefore, the non-lit region 3 is driven by the block drive.
The reverse bias voltage Vm can be applied to the 12 EL elements 15. That is, the reverse bias voltage (current) is applied to each block. However, the reverse bias voltage is not limited to being applied to all of the blocks 312. For example, divide any block into multiple,
A configuration in which a reverse bias voltage is applied to each of the divided blocks may be used. Of course, each block has a non-lighting area 31
Two controls may be performed, and the application of the reverse bias voltage may be controlled for each pixel row.

[1073] As described above, by applying the reverse bias voltage Vm to each block, the configuration shown in FIG.
The pixel configuration and the like described in the above are simplified. In addition, control becomes easy. In particular, since the reverse bias voltage Vm is applied to the non-lighting area 312, the logic is simple.

FIG. 211 shows an embodiment of the present invention in the case where the block driving and the reverse bias voltage driving are combined. The pixel configuration of FIG. 211 is the pixel configuration of FIG. This pixel configuration is combined with the block driving described in FIG. The block drive is shown in FIGS. 180 to 197.
It goes without saying that any of the configurations described above can be applied.

[1075] In FIG. 211, by applying the off voltage Vgh to the lighting control line 1791, the corresponding block becomes the non-lighting area 312. At the same time (not limited to the same time, any period may be applied as long as the Vgh voltage is applied to the corresponding lighting control line 1791), and the on-voltage (Vgl) is applied to the reverse bias control line 2111. Then, the reverse bias voltage Vm is applied to the EL element 15 of the block. That is, in terms of logic, the signal of the opposite phase of the lighting control line 1791 is set to the reverse bias control line 21.
It should be 11.

Similarly, FIG. 212 shows a configuration in which a reverse bias drive system is added to the configuration of FIG. 181. In addition, FIG.
FIG. 3 shows a configuration in which a reverse bias drive system is added to the configuration in FIG. 182, and FIG. 214 shows a configuration in which a reverse bias drive system is added to the configuration in FIG. 183. The operation is easy and will not need any explanation.

As described above, it is not necessary to completely synchronize the application of the reverse bias voltage Vm and the block drive. Further, it is not necessary to completely match the scanning cycle.

[1078] The block drive of the present invention will be described below. FIG. 198 is an explanatory diagram of the block driving method of the present invention. Also in the following explanatory diagrams, the pixel configuration will be described as the pixel configuration illustrated in FIG. 1 for ease of description. However, the present invention is not limited to this, and needless to say, other pixel configurations such as FIGS. 21, 43, 71, 22, 54, 68, 103, and 121 are also possible.

In the case of the pixel configuration of FIG. 1, it is necessary to turn off the TFT 11d of the pixel row for which current programming is being performed. That is, in the selected pixel row, the EL element 15 should not be seen from the source signal line 18
Element 15 is not connected). This is to prevent the program current from the source signal line 18 from flowing into the EL element 15. When the program current flows in the EL element 15, a regular current is supplied to the capacitor 19
Because it cannot be programmed to.

Therefore, when the block driving is performed, the block including the selected pixel row needs to be in the non-lighting state 312. In other words, when the pixel row in the block is selected, this block is always kept in the non-lighted area 3
12 On the contrary, other blocks are in the lighting state 311
Any of the non-lighted state 311 may be used. Flicker is suppressed by performing on / off control of blocks other than the selected pixel row.

[1081] FIG. 198 (a) shows 1 of block 1981b.
The pixel row 871a of the book is selected. Therefore, the block 1981b is controlled in the non-lighting state. if,
If the block 1981 is composed of 6 pixel rows, the selected block 1981 is controlled to a non-illuminated display for a period of 6H.

[1082] FIG. 198 (b) is 1H from FIG. 198 (a).
It is a display state later. The selected pixel row 871a is shifted by one pixel row. In FIG. 198 (a), the blocks of the non-lighting display 312 are 1981b, 1918d, and 198.
1f, 1981h, and 1981j. Figure 198 (b)
Then, the blocks of the non-lighting display 312 are 1981a and 1
918b, 1981e, 1981g, and 1981i. That is, in FIGS. 198 (a) and 198 (b), the blocks other than the block 1981b including the selected pixel row 871a are inverted (the non-lighting region 312 and the lighting region 311 are reversed).

[1083] Note that the selected pixel row is not limited to one pixel row. It may be multiple. For example, FIG. 87 and FIG.
8, the method of selecting a plurality of pixel rows as described with reference to FIG. 146 and the block driving of FIG. 198 or FIG.
It can be combined with the reverse bias drive.

[1084] In addition, in FIG. 198, the TFT of the selected pixel row is
11d is turned off and the EL element 15 is not turned on. However, in the case of the current mirror configuration as shown in FIGS. 21, 43 and 71, the source signal line 18 and the EL element 15 are not connected. Therefore, the selected pixel row may be in the display state. However, it is preferable to control the selected pixel row to a non-illuminated state because the image in that period is under programming during programming.

[1085] In FIG. 198, the non-lighting area 312 and the lighting area 311 are inverted in 1H cycle, but the invention is not limited to this and may be 2H or more. . The lighting control may be performed relatively randomly. Further, as a matter of course, the reverse bias voltage Vm may be applied to the non-lighted blocks.

[1086] The non-lighting area 312 and the lighting area 311
It is not necessary to control RGB pixels at the same time. For example, the lighting control may be different for R, G, and B. This is FSC (frame sequential control)
The case of is also included.

In FIG. 198, on / off control is performed for each block, but the present invention is not limited to this. For example, as shown in FIG. 199, two blocks (for example, in FIG. 199 (a), blocks 1981b and 1981c are non-lighting areas 312. Further, block 1981.
The d and 1981e are the lighting region 311. ) May control. Further, after 1H, lighting control may be performed as shown in FIG. 199 (b). Figure 199 (a) and (b)
Then, lighting control is performed by spelling one block at a time. Note that in FIGS. 198, 199, etc., the number of blocks 1981 is very small in order to facilitate the illustration.
The above matters also apply to the other embodiments.

[1088] FIG. 200 shows a method of forming a brightness distribution on the display screen 21 by controlling the lighting of blocks. In order to facilitate the explanation, FIG.
FIG. 200 (b) will be described assuming that it is 1H after the next of FIG. 200 (a). Of course, FIGS. 200 (a) and 200 (b) may be in a state of being separated by a predetermined period.

[1089] As the brightness distribution, a Gaussian distribution is exemplified. In other words, it is a method of brightening the central portion of the display screen and darkening the peripheral portion thereof, thereby visually brightening them and reducing power consumption.

In the present invention, in the horizontal direction of the screen, the data itself is changed by the modulation of the video signal to form the brightness distribution. For example, a line memory for one pixel row is mounted, and this memory holds coefficients required for calculation. For example, if the edge of the screen is 50% of the center,
The coefficient corresponding to% is retained. Hereinafter, the line memory holds coefficients so that the central portion becomes 100% and the Gaussian distribution is satisfied. The applied image data is calculated with the coefficient of this line memory, and the calculated result is applied to each source signal line.

[1091] Note that the non-lighted area 312 is also displayed in the vertical direction of the screen.
It is needless to say that if the pixel is configured to be turned on and off, it is not necessary to change the data itself to form the brightness distribution in the left and right direction of the screen by modulating the video signal. For example, the signal line may be formed so that the TFT 11d in one pixel column can be on / off controlled. That is, TF
T11d can be controlled in a matrix on the display screen.

[1092] The Gaussian distribution is an example. In other words, a luminance distribution state that brightens the vicinity of the central portion of the screen 21 is generated. Therefore, the brightness distribution is not limited to the Gaussian distribution, and may be a sine curve-shaped brightness distribution or a conical brightness distribution. Further, since the present invention controls the TFT 11d and the like to generate the brightness distribution, it is not limited to brightening the central portion of the screen 21. For example,
The central part of the screen may be darkest or the upper part of the screen may be brightest. These brightness distribution states can also be easily realized by controlling the TFT 11d and the like. This is because it can be realized simply by adjusting (changing) the control timing and ON time of the gate signal line 17b.

[1093] Further, the user can freely or automatically change the distribution state of brightness according to the type of image. For example, in the partial display, the partial display position can be displayed particularly brightly.

[1094] The brightness is not limited to the three primary colors of R, G, and B being generated at the same time and changed to the same position (white color moves). For example, the maximum brightness position of only R can be moved. As described above, it is possible to generate a color pattern on the display screen 21 by changing the maximum luminance (minimum luminance) position of each color.

[1095] The formation of the brightness distribution in the vertical direction of the screen 21 is realized by the on / off control of the block 1981. That is, the number of off times of the block 1981 at the center of the screen is reduced, and the number of off times is increased above or below the screen. The screen turns darker as the number of off times increases, and becomes brighter as the number of off times decreases. A Gaussian distribution can be formed in the vertical direction of the screen by controlling this on / off. Therefore,
Brightness is adjusted (controlled) in the horizontal direction of the screen by calculating video data (or the amplitude value may be modulated by analog modulation), and the vertical direction of the screen is controlled by on / off control of block 1981. , Adjust the brightness of the display screen (control).

[1096] Note that in FIG.
Although the brightness distribution is formed by the on / off control of 981, the invention is not limited to this. Block 198
It is needless to say that the brightness distribution can be formed by performing on / off control for each pixel row, not limited to 1. It can also be realized by performing on / off control for each of a plurality of pixel rows. That is, the on / off control in block 1981 is merely the on / off control as a group of a plurality of pixel rows. Therefore, FIG. 200 and the like are one embodiment in which the technical scope of the present invention is limited.

[1097] In FIG. 200 (a), the non-lighting area 312 includes blocks 1981b, 1981d, 1981h, and 1981.
j. In FIG. 200 (b), the non-lighted area 312 includes blocks 1981a, 1981c, 1981i, and 1981k.
Is. Therefore, the central blocks 1981e, 1
In FIGS. 200 (a) and (b), 981f and 1981g are lit. Therefore, the central part becomes bright.

[1098] On the other hand, in FIG.
81a, 1981c, 1981i, and 1981k are in the lighting state 311, but are in the non-lighting state 312 on the contrary in FIG. 200 (b). Therefore, the upper and lower parts of the displayed image are dark.

As described above, the brightness distribution can be formed in the display image by performing the on / off control for each block 1981. In addition, in FIG. 200, blocks 1981e, 1981f, and 1981g in the central portion are shown in FIG.
Although both (a) and (b) are turned on, the brightness can be freely controlled and the occurrence of flicker can be suppressed by performing control such as turning off in the next 1H.

[1100] In FIG. 200, the widths of the blocks 1981 are all the same. However, visually, the central portion of the screen 21 may be made fine and the peripheral portion may be made rough. It implements like FIG. This is because human vision has a high resolution in the central portion of the screen.

[1101] In FIG. 201, the on / off control is performed as shown in FIG.
01 (a) and (b) are alternately performed. In FIG. 201, the blocks 1981f to 1981n in the central portion of the screen 21 are on / off controlled in small block units (1 unit), the upper and lower portions of the central portion are on / off controlled in 2 block units, and the upper and lower portions of the screen are 3 block units. ON / OFF control is performed with. Note that the OFF control of the pixel writing row 871a is performed with reference to FIG.
The method described in 8 is performed. That is, the pixel writing row 87
1a is a non-lighting display 312.

[1102] In Fig. 201, the width of the lighting block 1981 is changed to control the on / off of the central portion of the screen to realize a visually matched display. FIG. 202 realizes a Gaussian distribution on the screen by controlling the number of times of turning on / off in a plurality of unit cycles.
FIG. 202 shows 6 cycles (FIG. 202 (a) → (b) → (c) →
(D) → (e) → (f) → (a) → (b) → (c) →
The screen brightness distribution is formed by (d) → (e) → (f) → (a)). Of course, it is not limited to 6 cycles, and may be 2 cycles or 8 cycles or more. The unit of the cycle may be 1H, 1F, or may be synchronized with another clock. Note that, also in FIG. 202, the Gaussian distribution is performed in the left-right direction of the screen by a video signal or the like. This has been described with reference to FIG. The above items also apply to other inventions.

As shown in FIG. 202, FIG. 202 (b)
In (e), a lighting display area 311 is generated in the center of the screen,
Also in FIGS. 202C and 202F, a large number of lighting display areas are generated near the center of the screen. By controlling in this way, the central part of the screen becomes bright. Therefore, a good Gaussian distribution can be generated.

[1104] FIG. 207 does not generate the Gaussian distribution but changes the position of the lighting block 1981 in a plurality of periods to suppress the occurrence of flicker. In FIG. 207, in FIG. 207 (a), the non-lighting area 312 is generated every two blocks, and in FIG. 207 (b) of the next block, the non-lighting area 3 is generated every three blocks.
12 has been generated. In addition, FIG.
In (c), the non-lighted area 312 is generated every four blocks. As described above, by changing the position of the non-lighted area 312 or the lighted area 311 in a plurality of cycles, it is possible to suppress the occurrence of flicker. In addition, FIG.
A Gaussian distribution can also be generated by combining the methods described in FIG.

[1105] In the above embodiment, the lighting position is changed in units of blocks 1981 as shown in FIG. However, the present invention is not limited to this. For example, the lighting position may be changed by 1/2 block as shown in FIG. That is, in the above-described embodiment, the ON / OFF control is performed in block units, but the present invention is not limited to this. This is because generation of Gaussian distribution and suppression of flicker can be realized without using the block 1981 unit. As described above, the non-lighting control may be performed on a pixel row basis. Of course, the non-lighting control or the lighting control may be performed in units of a plurality of pixel rows.

[1106] Also, the present invention is not limited to the pixel row, and the on / off processing may be performed on the pixel column, or the on / off processing may be performed on both the pixel row and the pixel column. Also,
Pixel rows that are turned on and off are not limited to sequential processing, and random processing may be performed. By randomly controlling the pixel rows (pixel columns) to be turned on and off, it is possible to make the image 21 less visible and to cause flicker. Further, the specific pixel row (pixel column) can be always set to the non-lighting display 312. Further, the screen can be flushed by displaying the whole screen or a part of the screen on / off at a low frame rate (the non-lighting display 312 and the lighting display 311 are alternately repeated). These can be applied as image scramble processing or special effect processing.

[1107] However, the above display state is in the block 19
It goes without saying that the control by 81 units makes the circuit configuration easy, and the panel configuration and the pixel configuration also easy.

[1108] The user can freely or automatically change the distribution state of brightness according to the type of image. For example, in the partial display, the partial display position can be displayed particularly brightly. Moreover, the color of any display portion can be easily changed. In addition, it can be displayed outdoors so that only a necessary portion looks bright.

[1109] As shown in FIG. 215, the lighting area 311
Image is displayed by scanning from the top to the bottom of the screen 21 ((a) → (b) → (c) → (d) → (e) →
(A) → (b) → (c) →). At this time, the brightness distribution (Gaussian distribution or the like) can be realized in the vertical direction of the screen by controlling the scanning clock.

[1110] In FIG. 215, in the display state of (c), when the lighting area 311 is scanned, the scanning speed of the lighting area 311 is decreased. When the lighting area 311 is scanned in the portions (a) and (e), the scanning speed of the lighting area 311 is increased. When the lighting area 311 is scanned in the portions (b) and (d), the scanning speeds of the lighting area 311 are (a) and (c).
At an intermediate speed. The scanning speed is CL applied to the shift register 22 of the gate driver 12 described in FIG.
It can be realized by controlling K *. Also, FIG.
This can be realized by controlling the lighting control line 1791 described above.

[1111] As described above, the lighting area (image display area) 3
By controlling 11, the central part of the screen 21 has the highest brightness and the upper and lower parts of the screen are the darkest. Therefore, a Gaussian distribution or the like can be formed in the vertical direction of the screen 21. Of course, a Gaussian distribution or the like may be formed in the horizontal direction of the screen by controlling in the pixel column direction. It can also be realized by arithmetic processing of video signals.

[1112] In FIG. 215, it is assumed that the scanning speed of the lighting region 311 is changed depending on the screen position to form a luminance distribution such as a Gaussian distribution on the screen. But,
This technical idea is not limited to the EL display device. For example, it is obvious that an LED display device can also be applied. Further, the invention is not limited to the self-luminous display panel (display device). For example, a liquid crystal display device can also be applied.

In the liquid crystal display device, the backlight is improved and realized. As the backlight, one having a plurality of stripe-shaped light emitting regions arranged along the pixel row direction is used. For example, a stripe-shaped white EL element is formed along the pixel row direction. As the white EL element on the stripe, at least 10 or more white EL elements are used. It suffices to light the striped light emitting elements in order from the top. That is, when the striped EL is turned on, the lighting time of the striped EL element 15 corresponding to the central portion of the screen 21 is lengthened. Then, the light emission state of the backlight can be changed to the state shown in FIG. 215.

[1114] Therefore, in the liquid crystal display device, the lighting display state cannot be set as shown in FIG. 215 by itself, but the image display described in FIG. 215 is realized by setting the lighting region of the backlight in the scanning state. it can.
The above matters are shown in FIGS. 218, 219, 220, and 198.
It goes without saying that it can be applied to such cases.

[1115] FIG. 216 shows the drive waveform of the gate signal line 17a. In addition, in order to facilitate the explanation, the MCL
The period of K is 1H (1 horizontal scanning period). However, the present invention is not limited to this. Flexible control can be realized by using a clock faster than 1H.

[1116] The portion indicated by'a 'in FIG. 216 is shown in FIG.
It corresponds to the display state of (a). Similarly, the portion indicated by'b 'in FIG. 216 corresponds to the display state in FIG. 215 (b), and the portion indicated by'c' in FIG. 216 corresponds to the display state in FIG. 215 (c). The part indicated by'd 'in FIG. 216 corresponds to the display state of FIG. 215 (d), and the part indicated by'e' in FIG. 216 corresponds to the display state of FIG. 215 (e).

Note that the pixel configuration will be described by exemplifying the configuration of FIG. Therefore, when the Vgl voltage is applied to the gate signal line 17a, the corresponding pixel row is selected. However, the embodiment of the present invention is not limited to the pixel configuration shown in FIG. 1, and the current mirror configuration shown in FIGS. 21, 43, 71, etc., and the voltage programmed pixel shown in FIGS. 54, 68, 103, etc. It goes without saying that it can be applied to the configuration.

[1118] As shown in FIG. 216, 'a''e'
In the portion of, the pixel row is shifted by the clock of 1H width.
In the part of'b''d ', the pixel row is shifted by the clock of 2H width. Further, in the portion of'c ', the pixel row is shifted by the clock of 3H width. Therefore, the'c 'part is three times slower than the'a' part, and the pixel row shift operation is slow. That is, the'c 'part is 3 compared to the'a' part.
It becomes twice as bright. Therefore, the central part of the screen becomes brightest and the upper and lower parts can be darkest.

[1119] In FIG. 216, the data transfer of the shift register 22 is set to 3 clocks in the central portion of the screen. Further, in the upper and lower parts of the screen, the data transfer of the shift register 22 is one clock. Further, the data transfer of the shift register 22 is set to 2 clocks in the upper and lower parts and the central part of the screen. However, when the clocks are switched in three stages as shown in FIG. 216, the boundaries of the switching are displayed clearly with a difference in brightness. Therefore, it is preferable to reduce the difference between the data transfer clocks and to change the number of changing clocks so that the boundary cannot be seen. That is, FIG. 216 is a diagram for explanation.

For example, in the center part of the screen, the data transfer of the shift register 22 is 5 clocks, in the upper and lower parts of the screen, the data transfer of the shift register 22 is 3 clocks, and in the upper and lower parts and the center part of the screen, the shift register 22 The data transfer of 22 is 4 clocks.

[1121] Also, if the screen is divided into nine or more areas and the first area, the second area, the third area, ... The data transfer of the shift register 22 is set to 15 clocks, and the first area and the ninth area
In the area, the data transfer of the shift register 22 is 11 clocks. The second area and the eighth area are provided in the shift register 22.
The data transfer of is set to 12 clocks. In the third area and the seventh area, the data transfer of the shift register 22 is 13 clocks. The data transfer of the shift register 22 in the fourth area and the sixth area is 14 clocks. As described above, if the screen is divided and the on / off control is optimally performed for each, the boundary between the brightness is not noticed.

[1122] The method of FIG. 217 is also effective for making the boundary of screen brightness invisible. FIG. 217 shows the signal waveform of the gate signal line 17a in the central area of the screen 21.

As shown in FIG. 217, the shift start timing of 3 clocks with respect to the display position is changed in each field (frame) (F). In FIG. 217, the start position is shifted by one clock from 1F to 4F in order to simplify the description. In reality, each F is not shifted by one clock, but one F is shifted by one clock, but another F is not shifted. Further, the number of times the shift of 3 clocks is performed is changed in each F.

For example, in 1F, the start position of 3 clocks in the center of the screen is the pixel row (90) (90th pixel row).
Starting from, the range in which the shift register is transferred in 3 clocks is 20 pixel rows. In the 2nd floor, the start position of 3 clocks in the center of the screen starts from the pixel row (92), and the range to which the shift register is transferred at 3 clocks is 16 pixel rows. Further, in the 3rd F, assuming that the start position of 3 clocks in the central portion of the screen starts from the pixel row (94), the range to which the shift register is transferred at 3 clocks is 12 pixel rows. Further, in the 4th F, assuming that the start position of 3 clocks in the central portion of the screen starts from the pixel row (96), the range to which the shift register is transferred at 3 clocks is 8 pixel rows. By performing the processing as described above, it is possible to make the boundary at which the display brightness at the upper part of the screen changes from the display brightness at the top of the screen to the display brightness at the center part inconspicuous.

[1125] The shift start position is processed in a loop. For example, in FIG. 217, 1F → 2F → 3F → 4
Repeat F → 1F → 2F ... Further, in FIG. 217, the central portion of the screen shifts the pixel rows at 3 clock cycles, but the present invention is not limited to this. As described with reference to FIG. 216, the number of clocks and the display are changed so that the luminance distribution changes smoothly. It goes without saying that the area is adjusted.

It is needless to say that by combining FIG. 216 and FIG. 217, the brightness distribution processing of the screen display can be further omitted and a good display can be realized.

The driving method described with reference to FIGS. 216 and 217 intentionally forms the luminance distribution on the screen 21. However, this technical concept can be applied to other image displays.

[1128] FIG. 218 shows two luminance portions formed (displayed) on the screen 21. In FIG. 218, the lighting area 311a is displayed brighter than the lighting area 311b. In FIG. 218 (a), the display area 311a of the memo 1 is made brighter than the other display areas 311b.

[1129] Displaying the illuminated area 311a brighter than the illuminated area 311b can be easily configured by the method described with reference to FIG. Further, since it is sufficient to control the number of times the display area of each unit is selected, it can be easily realized by another method.

[1130] In FIG. 218, the area selected by the user is displayed brightly (or darkly) to improve the usability of the display device. Of course, it is also preferable to change the color of the selected display area 311. The display method of FIG. 218 is preferably applied to a menu selection screen or the like. This is because the screen display can be switched by the user's operation and the operability is improved. The screen display state of FIG. 218 may be automatically set by the control of a microcomputer or the like. In addition, since the outside light is strong outdoors and the displayed image cannot be seen, it is necessary to strongly light only the particularly necessary portion (lighting area 311a).
You may control. For example, when the brightness of outside light is detected and the detected intensity of the outside light is a certain value or more, the user displays the screen 21 by pressing the power switch.

[1131] As shown in FIG. 219 (a),
The lighting region 311a that lights strongly may be provided in a plurality of places on the screen 21. Moreover, you may make it blink. Blinking means that the display area 311a in FIG.
It is to turn on / off in a cycle of 5 seconds, and to alternately display low brightness and high brightness.

[1132] Also, as shown in FIG. 219 (b), a high-luminance region 311a, a low-luminance region 311b, and a non-lighted region 3
Image display may be performed in combination with 12.

[1133] FIG. 220 shows a screen 21 having a scroll effect. In FIG. 220 (a), a high-brightness lighting area 311a extends up to the central portion of the screen 21.
0 (b) is near the lower edge of the screen 21, and the high-brightness lighting area 3
11a.

[1134] Needless to say, the entire screen 21 can be simultaneously displayed in low brightness. In the present invention, the brightness of the screen 21 is adjusted (controlled) by controlling the lighting control line 1791 or the gate signal line 17b to turn on / off the current flowing through the EL element 15. Therefore, the image data output from the source driver 14 does not change. Therefore, the contrast and gamma curve of the display image are also characterized by being kept constant regardless of the brightness of the display image. Therefore, even if the entire screen 21 is simultaneously displayed in low brightness, the gradation characteristic is maintained as it is (for example, 6).
In the case of 4-gradation display, 64 gradations are maintained even when the screen brightness is halved).

[1135] First, as shown in FIG.
The whole is set as the low-brightness lighting area 311b (set as the low-brightness display), and in order to exert the effect of rewriting the screen, the high-brightness lighting area 311a is moved downward from the top of the screen 21 (high-brightness display). I will). Therefore, one screen 21 is rewritten by performing high-luminance display in the arrow direction of FIG. And
If high-luminance display is continued for a certain period of time, the entire screen 21 is set to low-luminance display from the viewpoint of low power consumption.

[1136] Note that the organic EL display panel requires large power for white raster display. If the power supply circuit for this white raster display is provided, the power supply circuit becomes very large. On the other hand, the normal character display consumes only 1/5 to 1/3 the power of the white raster display. Therefore, it is not preferable from the economical or system size viewpoint to retain the output current of the power supply so that the white raster display can be supported.

To address this problem, in the present invention, when displaying an image that consumes power above a certain value (for example, white raster display), the brightness of the image is reduced and displayed. is doing. For example, if 100 mA of current flows in a white raster, 1/2 of 50 mA
The image data is processed so that the electric current becomes. In other words, the total sum of the data of the input image is obtained, and when the total sum exceeds a certain value, arithmetic processing is performed on the image data to reduce the value of the image data so that the image data can be displayed by the power supply power held.

[1138] Of course, the value of the image data is not limited to a small value, and it is not limited to that shown in FIGS.
By performing the non-lighting control described in 19 etc.,
The brightness of the entire screen 21 can be reduced. It goes without saying that the brightness of only the image display unit can be reduced and the icon parts such as the antenna display and the clock display can be controlled to maintain the conventional brightness (the brightness as it is).

[1139] In the above embodiment, the image display or the different brightness display area is formed (displayed) by scanning the lighting area 311 or the non-lighting area 312 in the vertical direction of the screen. . However, the present invention is not limited to this. For example, in FIG. 218, the brightness distribution can be formed by controlling the number of times each part of the screen 21 is selected.

[1140] For example, in FIG. 218, when the frame rate for displaying the screen 21 is 60 Hz, the display area 31
If the control is performed such that 1b is selected 25 times and the display area 311a is selected 50 times, the display area 311a becomes the display area 31.
It can be displayed with twice the brightness of 1b.

[1141] Similarly, in FIG. 220 (b), screen 2
When the frame rate for displaying 1 is 60 Hz, if the display area 311b is selected 25 times, the display area 311a is selected 50 times, and the non-lighted area 312 is not selected at all, the display area 311a will be displayed. It is possible to display with a brightness twice as high as that of the above, and it is possible to display the area 312 in black.

[1142] Needless to say, the above-described matters can be applied to the block drive described in FIG. 1971 or the like or the reverse bias drive described in FIG. 211.
Further, in block driving, it is preferable that the number of pixel rows forming each block is the number representing one character string. For example, if one character is composed of 16 × 16 dots, 16 pixel rows are set as one block. Further, if one character is composed of 24 × 24 dots, 24 pixel rows are regarded as one block. In this way, by matching the number of dots in the vertical direction forming a character with the number of blocks, the lighting region 311 and the non-lighting region 312 can be controlled for each line in which the character is displayed.

[1143] In the above embodiments, the brightness and the like of the screen 21 is adjusted (changed) by controlling lighting and non-lighting. It is necessary to turn on / off the current flowing through the EL element 15 for brightness adjustment. At this time, a task appears. Hereinafter, this problem, its countermeasure, and the driving method of the present invention will be described. Note that the description will be made on the pixel configuration of FIG. However, as described above, the pixel configuration is not limited to the configuration shown in FIG.
1, FIG. 43, FIG. 71, FIG. 22, FIG. 54, FIG. 67, FIG.
It goes without saying that the present invention can be applied to the pixel configurations described in this specification such as 3.

FIG. 325 (a) is an equivalent circuit diagram when a pixel is selected. The gate signal line 17a receives an on-voltage (Vg
l) is applied and the TFTs 11b and 11c are turned on. At this time, the gate signal line 17b receives an off voltage (Vg
h) The voltage is applied and the TFT 11d is off. Therefore, no current flows through the EL element 15.

[1145] In FIG. 325 (b), when the pixel is in the non-selected state, E
This is a state in which a current is flowing through the L element 15. The off voltage (Vgh) is applied to the gate signal line 17a, and the TFT 11
b, the TFT 11c is off. Gate signal line 17b
ON voltage (Vgl) voltage is applied to the
11d is in an on state.

[1146] FIG. 326 shows a signal waveform applied to the gate signal line 17. The subscripts such as (1), (2), and (3) indicate the pixel row numbers. Note that, for ease of explanation, it is assumed that pixel rows are sequentially selected from the first pixel row. In FIG. 326, HD is a horizontal sync signal.

[1147] In the pixel configuration of FIG. 1, the gate signal line 1
7a is selected for the 1H period. At this time, the off voltage is applied to the gate signal line 17b of the selected pixel row. During this period, a current is programmed from the source signal line 18 to the pixel.

[1148] The gate signal line 17b is
An on-voltage is applied, and a current flows through the EL element 15. As is clear from FIG. 326, the gate signal line 17b has an HD
The ON voltage (Vgl) is applied for a certain period in synchronization with the signal. That is, the on-voltage application time is x / 1H (1H is one horizontal scanning period). In the example of FIG. 326, 1
Since the H period is divided into 16 equal parts, x / 1H = 4H / 1
6 = 1H / 4 (that is, the EL element 15 is lit for a period of 1/4 of 1H).

[1149] Up to this point, the lighting process of the EL element 15 described in the embodiments of the present invention has been controlled with 1H as the minimum unit. FIG. 326 shows a method of subdividing the 1H period and adjusting (changing) the brightness of the screen by the lighting time of the 1H period. Therefore, if the brightness adjustment of 16 steps is taken as an example, the brightness adjustment is as shown in FIG. 328. For the gradation 1 of the brightness, the ON voltage (Vgl) is applied to the gate signal line 17b for each 1H for a period of 1H / 16. For the gradation 2 of the brightness, the ON voltage (Vgl) is applied to the gate signal line 17b every 1H for a period of 2H / 16. Similarly, for the gradation 3 of the brightness, the ON voltage (Vgl) is applied to the gate signal line 17b for every 1H for a period of 3H / 16. Also, the brightness gradation 14
For example, the gate signal line 17b is 14
The on-voltage (Vgl) is applied only during the H / 16 period.
Similarly, for the gradation 15 of the brightness, the ON voltage (Vgl) is applied to the gate signal line 17b every 1H for a period of 15H / 16. The brightness gradation 16 is constantly applied with the on-voltage (Vgl) except for the selected pixel row.

[1150] If brightness of 32 gradations (steps) is required, 1H may be divided into 32 and controlled. Further, in order to control the brightness stepwise above a certain brightness, 1/2 of 1H is always applied to the gate signal line 17b, Vgl voltage is applied, and the remaining 1/2 period of 1H is applied. It may be controlled by dividing it into 32 equal parts.

[1151] FIG. 327 shows the circuit configuration of the display panel. The configuration of FIG. 327 is similar to the configuration of FIG. Therefore, the difference will be mainly described. In FIG. 327, the gate driver 14a for controlling the gate signal line 17a is arranged at the left end of the panel, and the gate driver 14b for controlling the gate signal line 17b is arranged at the right end of the panel. 3271
Is a buffer circuit, which corresponds to the output gate 24, the inverter circuit 22, and the like in FIG. In addition, the inverter 23
Is inserted for the sake of convenience, and is configured so that the ON voltage (Vgl) is output to the gate signal line 17a when the shift register 22 has a positive output (H = 1). Further, when the ON voltage is applied to the gate signal line 17a (a pixel row is selected), the gate signal line 17 of the pixel row is
This is because b is not selected and the logics of the shift register 22a and the shift register 22b are matched.

[1152] The same applies to the gate driver 14b. The input signals (CLK2, ST2) of the shift register 22b of the gate driver 14b are made the same as the input signals (CLK1, ST1) of the shift register 22a of the gate driver. Therefore, ST data is stored in the shift register 2
It is held at the same position in 2a and 22b, and the holding position is shifted in synchronization with the clock. Therefore, FIG.
As shown in FIG. 6, the pixel row selected by the gate signal line 17a is always connected to the gate signal line 17b at the off voltage (Vg
h) is controlled to be output.

[1153] In which period of 1H, the ON voltage (Vgl) is output to the gate signal line 17b depends on E
It is determined by the logic signal applied to the NBL terminal. EN
When the BL signal is L, the output of the OR circuit 3272 is turned on (the on voltage is output to the gate signal line 17b). Therefore, as for the output of the OR circuit 3272, the off voltage is always output to the gate signal line 17b corresponding to the portion where the shift register 22b holds the data (this pixel row is selected by the gate driver 14a and is output to the pixel). Current is programmed). The gate signal line 17b of the selected pixel row is switched on / off by the logic of the ENBL signal line. Therefore, by the ENBL signal line, it is possible to freely adjust (control) the timing of how long the ON voltage is applied during the 1H period. In the circuit configuration of FIG. 327, the gate signal line 17
The control of b is easy. Therefore, the screen brightness can be adjusted freely. Further, the current flowing through the EL element 15 is on / off controlled every 1H. Therefore, since the screen is repeatedly turned on and off at high speed, flicker does not occur.

[1154] However, problems occur depending on the array design state. As illustrated in FIG. 325 (b), since the gate signal line 17b and the source signal line 18 cross each other, a parasitic capacitance 404 is generated between the gate signal line 17b and the source signal line 18. In FIG. 327, on-voltage or off-voltage is simultaneously applied to all the gate signal lines 17b by the ENBL signal. Therefore, the signal applied to the gate signal line 17b causes the potential variation of the source signal line 18 via the parasitic capacitance 404.

[1155] To address this problem, it is effective to apply pulses of opposite polarities to adjacent pixel rows as much as possible, as shown in FIG. That is, pixel 16
That is, the polarity of the on / off signal applied to the gate signal lines 17b of a and 16c is set to the opposite phase to that of the pixel 16b.

However, in reality, applying a signal having a completely opposite phase to the adjacent gate signal line 17b means that
The application time of the current flowing through the EL element 15 differs between adjacent pixel rows. Because the gate signal line 17 of the pixel 16a
When an ON voltage is applied to b for a period of 1H 1/4, light is emitted for a period of 1H 1/4. Gate signal line 17b of pixel 16b
If the phase is opposite to that of the gate signal line 17b of the pixel 16a, the gate signal line 17b of the pixel 16b is 3/4 of 1H.
The ON voltage is applied during the period. Therefore, the pixel 16b emits light for 3/4 period of 1H. That is, the light emission time differs between adjacent pixel rows.

FIG. 332 shows a driving method of the present invention which solves this problem. For easy understanding, the waveforms of the gate signal lines 17b of the pixel row (1) and the pixel row (2) are extracted and shown in the figure. In the example of A, the time for applying the on-voltage (Vgl) of the gate signal line 17b (1) of the pixel row (1) is T
It is the period of 1. Further, the ON voltage (Vg of the gate signal line 17b (2) of the pixel row (2) adjacent to the pixel row (1) is
The time for applying l) is also the period of T1. That is, EL
The time for passing the current through the element 15 is the same in the adjacent pixel rows.
Therefore, the display brightness is the same in the entire display area.

[1158] The waveforms of the gate signal lines 17b of the adjacent pixel rows cancel each other out because they have opposite phases at the point a. b
The points C and C are separated, but the canceling effect is not zero. In reality, in the example (state) of A, almost no screen floating due to coupling occurs.

In the example (state) of B, the time for applying the ON voltage (Vgl) of the gate signal line 17b (1) of the pixel row (1) is the period of T2. The time for applying the on-voltage (Vgl) of the gate signal line 17b (2) of the pixel row (2) adjacent to the pixel row (1) is also the period of T2. That is, the time during which the current is passed through the EL element 15 is the same in the adjacent pixel rows. The waveforms of the gate signal lines 17b of the adjacent pixel rows cancel each other out because they have opposite phases at the point a. The positions of points b and c are quite close. Therefore, the cancellation effect is large.

[1160] In the example (state) of C, the time for applying the on-voltage (Vgl) of the gate signal line 17b (1) of the pixel row (1) is the period of T3. Further, the time for applying the ON voltage (Vgl) of the gate signal line 17b (2) of the pixel row (2) adjacent to the pixel row (1) is also the period of T3. That is, the time during which the current is passed through the EL element 15 is the same in the adjacent pixel rows. The waveforms of the gate signal lines 17b of the adjacent pixel rows cancel each other out because they have opposite phases at the point a. The points a and b are close to each other, and the points c and a are considerably close to each other. Therefore, the cancellation effect is large.

[1161] As described above, in the driving method of FIG.
The state of is the darkest screen brightness, the state of B is the next darkest,
Is the brightest. Further, in any of the states of A, B, and C, the phase of the waveform applied to the gate signal line 17b is changed in the adjacent pixel rows, so that the influence of the parasitic capacitance is canceled between the adjacent pixel rows.

[1162] Note that in FIG. 332, the change positions of the gate signal line 17b of the pixel row (1) and the gate signal line 17b of the pixel row (2) are illustrated to be aligned at the point a and the like; however, the present invention is not limited to this. is not. This is because even if the change positions of the gate signal line 17b of the pixel row (1) and the gate signal line 17b of the pixel row (2) are deviated, the effect of suppressing the potential fluctuation of the source signal line 18 is exhibited. According to the experiment, the changing position is within 30% of 1H (one horizontal scanning period) (for example, if 1H is 100 (μsec), 30 (μse)
Within c)), there was no difference when the changed positions were the same.

[1163] In addition, in FIG. 329 and the like, the signal waveform applied to the gate signal line 17b is different between adjacent pixel rows, but the present invention is not limited to this. For example, in FIG.
As in 30, it may be changed every two pixel rows. Figure 3
In 30, the pixels 16a, 16b and 16e are the same, and the pixels 16c and 16d are the same.

[1164] It is also effective to bring the gate signal lines 17b close to each other in adjacent pixel rows. This embodiment is shown in FIG. The gate signal line 17b1 of the pixel 16a,
It is arranged (formed) close to the gate signal line 17b2 of the pixel 16b.

[1165] In FIG. 330, the signal waveform is made different every two pixel rows, but the signal waveform applied to the gate signal line 17 may be made different every three pixel rows or more. It may also be random. In addition, the brightness may be controlled to be a target value in a plurality of frames (fields). In the above embodiments, the phase relationship of the gate signal line 17b and the timing of the signal waveform are discussed.
The gate signal line 17a is not limited to this, but it is effective to change the phase relationship and the timing of the signal waveform in the adjacent pixel row in the same manner. The same applies to the gate signal line of the TFT 11g that applies a reverse bias voltage.

[1166] In order to change the signal waveform of the gate signal line 17b of the adjacent pixel row as shown in FIG. 332, the circuit configuration of the display panel is as shown in FIG. The configuration of FIG. 333 is similar to that of FIG. Therefore, the difference will be mainly described.

[1167] In which period of 1H, the ON voltage (Vgl) is output to the gate signal line 17b depends on E
It is determined by the logic signal applied to the NBL1 terminal and the ENBL2 terminal. When the ENBL1 signal is L, the output of the OR circuit 3272 corresponding to the even pixel row is turned on (the on voltage is output to the gate signal line 17b). Also, E
When the NBL2 signal is L, the output of the OR circuit 3272 corresponding to the odd pixel row is turned on (an on voltage is output to the gate signal line 17b).

[1168] Therefore, the output of the OR circuit 3272 is
The gate signal line 17b corresponding to the portion where the shift register 22b holds data always outputs the off voltage (this pixel row is selected by the gate driver 14a, and the current is programmed in the pixel). The gate signal line 17b of the selected pixel row has ENBL1 and E
The on / off state is switched by the logic of the NBL2 signal line. Therefore, by the ENBL signal line, it is possible to freely adjust (control) the timing of how long the ON voltage is applied during the 1H period.

Therefore, in FIG. 332, the polarity is opposite to the phase of the gate signal line 17b adjacent at the point a, but the present invention is not limited to this, and the position having the opposite polarity can be freely changed.
Further, the position where the ON voltage (Vgl) is applied to the gate signal line 17b does not have to be continuous in the period of 1H. The ON voltage may be applied multiple times during the 1H period.

[1170] In Fig. 332, the signal waveform is regular at 1H, but the invention is not limited to this. As described with reference to FIG. 326, there is a problem in that the potential fluctuations of the source signal line 18 occur due to the coincidence of the signal waveforms applied to the gate signal line 17b. Therefore, it was the method of the present invention that one of the means for solving the problem is to make the signal waveform applied to the gate signal line 17b different between adjacent pixel rows. For example, as shown in FIG. 337, the signal waveform applied to the gate signal line 17b may be operated in a 2H cycle.

In FIG. 337, the gate signal line 17a for selecting a pixel row is changed in synchronization with the horizontal synchronizing signal (HD) (that is, the pixel row to be selected is shifted pixel by pixel in synchronization with HD. ing). However, the gate signal line 17
b outputs an on-voltage (Vgl) in a 2H cycle. It goes without saying that the brightness of the screen 21 can be adjusted even in this case. Further, since the change in the signal waveform applied to the gate signal line 17b is reduced, the black floating is less likely to occur.

[1173] FIG. 337 can also be restated as being a subdivision of the 1H period into 32. Therefore, taking the 32-step brightness adjustment as an example, the brightness adjustment is as shown in FIG. 338. For brightness gradation 1, the ON voltage (Vgl) is applied to the gate signal line 17b every 2H for a period of 1H / 32. For the gradation 2 of the brightness, the ON voltage (Vgl) is applied to the gate signal line 17b every 2H for a period of 2H / 32. Similarly, for gradation 3 of brightness, the gate signal line 17b is set to 2H.
The on-voltage (Vgl) is applied for each 3H / 32 period. The same applies to the following, and taking the brightness gradation 30 as an example, the ON voltage (Vgl) is applied to the gate signal line 17b every 2H for 30H / 32. Similarly, the brightness gradation 31 is 31H for every 2H on the gate signal line 17b.
The ON voltage (Vgl) is applied only during the period of / 32. As for the brightness gradation 32, the on-voltage (Vgl) is constantly applied except for the selected pixel row.

As another method, as shown in FIG. 335, there is a method of gradually changing the signal waveform applied to the gate signal line 17b. FIG. 335 shows the waveform of the gate signal line 17b from the pixel row (1) to the pixel row (8). The time during which the ON voltage (Vgl) is applied to the gate signal line 17b of each pixel row is constant at T1. Further, the cycle in which the on-voltage (Vgl) and the off-voltage (Vgh) are applied is also constant. Therefore, since the EL element 15 of each pixel row is lit for a predetermined period of time in a predetermined cycle, the brightness of the screen 21 is constant in all pixel rows (of course, in the case of white raster display. Naturally, in a moving image and a natural image. The brightness of each pixel varies depending on the image data).

In each pixel row, gate signal line 17b (1) of pixel row (1) has a1 point (falling direction) and gate signal line 17b (2) of pixel row (2) has a2 point (rise direction). ) And the timing is matched. As described above, the occurrence of coupling to the source signal line 18 is suppressed by matching the rising timing and the falling timing of the two waveforms. Similarly, the timings of the b2 point (falling direction) of the gate signal line 17b (2) of the pixel row (2) and the b3 point (rising direction) of the gate signal line 17b (3) of the pixel row (3) match. I am letting you. Pixel row (3)
The point c3 of the gate signal line 17b (3) (falling direction) and the point c4 of the gate signal line 17b (4) of the pixel row (4) (rising direction) are matched. Also,
Point d4 (falling direction) of the gate signal line 17b (4) of the pixel row (4) and the gate signal line 17b (5) of the pixel row (5)
The timing is the same as the point d5 (the rising direction).

As described above, in the driving method of FIG. 335, since the gate signal lines 17b of the adjacent pixel rows are driven so that the rising timing and the falling timing coincide with each other as much as possible, the coupling to the source signal line 18 is performed. There are few rings.
Therefore, the occurrence of black floating is small, and good contrast can be realized.

[1176] FIG. 336 illustrates the rewriting state of the screen 21 in the driving method of the present invention. FIG. 336 (a)
336 (b) after 1H has passed, and the state in FIG. 336 (c) has further passed after 1H. That is, the screen 21 is divided into a plurality of areas, and a plurality of areas are rewritten at the same time. Of course, it is needless to say that each pixel line may be rewritten.

[1177] Although the driving method of the present invention has been described by exemplifying the configuration of the pixel of the current programming method shown in Fig. 1 and the like, the driving method of the voltage programming method shown in Figs. 54, 68, 103 and 121 is used. It is also effective in the configuration. This is because the gate signal line and the source signal line are caused by the panel structure and are generated in the pixel by the voltage programming method or the current programming method. Therefore, the driving method and the driving circuit of the present invention are applied to all the configurations described in this specification.

In the pixel configuration shown in FIG. 1 or the like, in the selected pixel row, when the ON voltage is applied to the gate signal line 17a, the OFF voltage is applied to the gate signal line 17b and the source signal line 17b is applied. The EL element 15 is made invisible from the 18 side. However, FIG. 21, FIG. 22, and FIG.
In the pixel configuration of the current mirror as shown in FIG. 3 and FIG. 71, there is no direct current path to the source signal line 18 and the EL element 15. Therefore, in the pixel configuration of the current mirror, it is not necessary to satisfy the condition that the off voltage is applied to the gate signal line 17b when the on voltage is applied to the gate signal line 17a. This is shown in FIG.
The same applies to the pixel configuration of the voltage programming method described with reference to FIGS. 67 and 103.

[1179] Also, in FIG. 335, the change positions of the gate signal line 17b of the pixel row (1) and the gate signal line 17b of the pixel row (2) are made to coincide with each other at points a1 and a2. It is not limited. Even if the change positions of the gate signal line 17b of the pixel row (1) and the gate signal line 17b of the pixel row (2) are deviated, the source signal line 1
This is because the effect of suppressing the potential fluctuation of No. 8 is exhibited.
This is remarkable in the current program type panel configuration. According to the experiment, the changing position is within 30% of 1H (1 horizontal scanning period) (for example, 1H is 100 (μse).
In the case of c), within 30 (μsec)), there is no difference when the changed positions match. Also, FIG.
In the above, the change of the gate signal line 17b is set to 1H cycle, but it is not limited to this. All gate signal lines 1
It suffices that 7b is a predetermined period and the period (T1) in which the on-voltage is applied matches. Therefore, it is not necessary to synchronize with HD (horizontal synchronization signal). The gate signal line 17b of each pixel may be operated in free run. The cycle of applying the on-voltage and the off-voltage to the gate signal line 17b is
It may be completely asynchronous with the horizontal synchronizing signal (HD). Further, it may be synchronized with the vertical synchronizing signal (VD). Further, the clock may be synchronized with the clock of the source driver circuit 14.

However, in reality, when the gate signal line 17b is operated completely asynchronously (random state), flicker may occur depending on the type of image or the brightness of the display screen may change due to temperature dependence. is there. Therefore,
It is preferable that the signal application state of each gate signal line 17b has regularity in a predetermined cycle. Further, by providing regularity, the drive circuit can be simplified. Particularly, in the pixel configuration of FIG. 1, there is a restriction that the gate signal line 17b of the selected pixel row applies the off voltage (Vgh). That is, the gate signal line 17a and the gate signal line 17
It is necessary to provide synchronization with b.

In the present invention, the pattern is repeated every 16 cycles. Therefore, pixel row (1)
The signal waveform pattern applied to the gate signal line 17b of the pixel row (16) is made different from the signal waveform pattern applied to the gate signal line 17b of. From the signal waveform pattern applied to the gate signal line 17b of the pixel row (17) to the pixel row (3
The signal waveform pattern applied to the gate signal line 17b in 2) is made different. The signal waveform pattern applied to the gate signal line 17b of the pixel row (1) and the signal waveform pattern applied to the gate signal line 17b of the pixel row (17) are matched and applied to the gate signal line 17b of the pixel row (2). The signal waveform pattern to be applied and the signal waveform pattern applied to the gate signal line 17b of the pixel row (18) are matched.
That is, taking FIG. 335 as an example, the gate signal lines 17b from the pixel row (1) to the pixel row (16) apply a waveform in which the ON voltage application positions are displaced at regular intervals, and the pixel row (1) and the pixel row ( The applied waveforms of the gate signal lines 17b of 17) are the same, and hereinafter, the applied waveforms of the gate signal lines 17b of the pixel row (2) and the pixel row (18) are the same, and the same applies to the pixel row (3).
, And the applied waveforms of the gate signal lines 17b of the pixel row (19) are the same, and the applied waveforms of the gate signal lines 17b of the pixel row (4) and the pixel row (20) are the same ... This means that the applied waveforms of the gate signal lines 17b of the row (16) and the pixel row (32) are the same. Further, since there are 16 patterns, the same signal waveform is applied to the pixel row (1), the pixel row (17) and the pixel row (33).

[1182] Of course, it is not limited to 16 cycles. However, if the period is less than 8, there are many places where the rising or falling timing of the gate signal line 17b coincides with each other in one screen, and black floating easily occurs. On the contrary, if it is longer than 32 cycles, the driving circuit becomes complicated. Therefore, the period is preferably 8 or more and 32 or less.

[1187] FIG. 334 is a circuit configuration diagram for inputting 16 patterns of signals to the gate signal line 17b. Instead of the gate driver circuit 14b described in FIG. 333 and the like, 16 ENBL (0:15) signal lines are used. It should be noted that the 16 ENBL (0:15) signal lines are configured to be able to output voltage amplitudes of on-voltage (Vgl) and off-voltage (Vgh) levels.

[1184] The 16 ENBL (0:15) signal lines are
Each of the 16 gate signal lines 17b is commonly connected. Therefore, when N is an integer other than 0, for example, the signal applied to the ENBL0 signal line is connected to the pixel row (16N-15) and the signal applied to the ENBL1 signal line is connected to the pixel row (16N-14). Connected with
The signal applied to the ENBL2 signal line is the pixel row (16N−
13), the signal applied to the ENBL3 signal line is connected to the pixel row (16N-12), the signal applied to the ENBL4 signal line is connected to the pixel row (16N-11), and to the ENBL5 signal line. The applied signal is the pixel row (16
N-10), the signal applied to the ENBL6 signal line is connected to the pixel row (16N-9), the signal applied to the ENBL7 signal line is connected to the pixel row (16N-8), and the ENBL8 signal is connected. The signal applied to the line is the pixel row (16
N-7), the signal applied to the ENBL9 signal line is connected to the pixel row (16N-6), the signal applied to the ENBL10 signal line is connected to the pixel row (16N-5), and the ENBL11 signal is connected. The signal applied to the line is the pixel row (1
6N-4), and the signal applied to the ENBL12 signal line is connected to the pixel row (16N-3).
The signal applied to the three signal lines is connected to the pixel row (16N-2), and the signal applied to the ENBL14 signal line is connected to the pixel row (16N-1). The signal applied to the ENBL15 signal line is connected to the pixel row (16N).
Therefore, the drive waveform applied to the gate signal line 17b can be freely manipulated in a 16-pixel row cycle.

[1187] In FIG. 334, by controlling ENBL (0:15), the gate signal line 17b is operated to control the current flowing through the EL element 15. In addition, the maximum number of control patterns is 16. In the configuration of FIG. 334, the number of signal lines formed at the end of the display area 21 is as small as 16. Therefore, 3
Suitable for edge-free structure.

However, the number of ENBL (0:15) terminals output from the display panel and the controller is as large as 16, and the control with the gate signal line 17a (on-voltage is applied to the gate signal line 17a is applied). It is somewhat difficult to apply an off voltage to the gate signal line 17b of the pixel row in which it is present.

[1187] Expand the circuits of FIG. 327 and FIG.
If it is 49, control becomes easy. Gate driver 14b
Shift register 22b input signal (CLK2, ST
2) is made the same as the input signal (CLK1, ST1) of the shift register 22a of the gate driver 14a. Therefore, the ST data is held at the same position in the shift registers 22a and 22b, and the holding position is shifted in synchronization with the clock. Therefore, as shown in FIG. 326, the pixel row selected by the gate signal line 17a is always
The gate signal line 17b is controlled to output the off voltage (Vgh).

[1187] In which period the ON voltage (Vgl) is output to the gate signal line 17b is determined by ENBL (0:15).
It is determined by the logic signal applied to the terminal. From the controller, four SEL (0: 3) terminals are the decoder circuit 3
It is connected to 491. The decoder circuit 3491 decodes the data at the SEL terminal to determine which ENBL terminal the on-voltage or the off-voltage is output to.

As for the output of the OR circuit 3272, the off voltage is always output to the gate signal line 17b corresponding to the portion where the shift register 22b holds the data (this pixel row is selected by the gate driver 14a, Current is programmed to). The gate signal line 17b of the selected pixel row is changed by the logic of the ENBL signal line.
The on / off state can be switched. Therefore, by the ENBL signal line, it is possible to freely adjust (control) the timing of how long the ON voltage is applied during the 1H period. The number of signal lines between the controller and the gate driver circuit 14b is 16 ENBL terminals to SEL.
The number of terminals is four, so it is greatly reduced.

As shown in FIG. 339, it is also effective to reverse the signal waveforms applied to the gate signal lines 17b of the adjacent pixel rows. In FIG. 339, the odd-numbered pixel rows have the same waveform, and the even-numbered pixel rows also have the same waveform.
However, in the odd-numbered pixel rows, the on-voltage (Vgl) is applied in the period of T1 in synchronization with the HD signal, and then the off-voltage (Vgl) is applied.
gh) is applied for 1H-T1 period. H for even pixel rows
First, the OFF voltage (Vgh) is 1H- in synchronization with the D signal.
After being applied for the period of T1, the on-voltage (Vgl) changes to T1.
It is applied for a period. Therefore, the order of applying the on-voltage or the off-voltage is opposite in the adjacent pixel rows. EL element 1
All gate signal lines 1 during the period (T1) in which current flows through 5
7b is the same. Since the EL element 15 of each pixel row is lit for a predetermined period of time in a predetermined cycle, the brightness of the screen 21 is constant in all pixel rows (of course, in the case of white raster display. Naturally, in moving images and natural images, image data is displayed. Depending on the brightness of each pixel).

In each pixel row, gate signal line 17b (1) of pixel row (1) has a1 point (falling direction) and gate signal line 17b (2) of pixel row (2) has a2 point (rise direction). ) And the timing is matched. As described above, the occurrence of coupling to the source signal line 18 is suppressed by matching the rising timing and the falling timing of the two waveforms.

[1192] As described above, in the driving method of FIG.
Since the gate signal lines 17b of the adjacent pixel rows are driven such that the rising timing and the falling timing at the point a coincide with each other, the coupling to the source signal line 18 is small. Therefore, the occurrence of black floating is small, and good contrast can be realized. The rising position b1 of the signal waveform of the odd-numbered pixel rows and the falling position b2 of the signal waveform of the even-numbered pixel rows change depending on the lighting time (T1) of the EL element 15. However, it occurs at a position close in time in most of the brightness states. Therefore, the change in the rising position b1 of the signal waveform of the odd pixel row and the change in the falling position b2 of the signal waveform of the even pixel row cancel each other out, and the potential fluctuation to the source signal line 18 is suppressed. Further, when the period of time when the current flows through the EL element 15 is short (T1 is small), the falling position a1 point and the rising position b1 of the signal waveform of the odd-numbered pixel rows are close to each other, and these two changes cancel each other out ( Than
Since the change occurs in a short time, the source signal line 1
8 does not affect the writing to the pixel 16). Similarly, the falling position b2 of the signal waveform of the even pixel row
The point and the rising position a2 are close to each other, and these two changes cancel each other out. Therefore, the influence of the coupling on the source signal line 18 can be suppressed, and the black floating does not occur.

[1193] It is also important to change the signal waveform with the vertical synchronization signal (VD). This is because the rising and falling positions of the signal waveform applied to the gate signal line 17b are dispersed, and the potential fluctuation to the source signal line 18 can be suppressed (in addition, even if the potential fluctuation occurs in the HD cycle, it is suppressed in the VD cycle). Because it will be done). 340 is the same as VD in FIG. 339.
Signals are shown with the signal order reversed. In brief, the signal waveform applied to the gate signal line 17b of the even pixel rows of all frames (fields) is applied to the gate signal line 17b of the odd pixel rows and applied to the gate signal line 17b of the odd pixel rows. The applied signal waveform is applied to the gate signal line 17b of the even pixel row. The other points have been described with reference to FIG.

[1196] In FIG. 340, the signal waveform of the gate signal line 17b in the odd pixel row and the signal waveform of the gate signal line 17b in the even pixel row are interchanged in synchronization with the VD signal. As described above, by changing the signal waveform in synchronization with the VD sync signal (not limited to the VD sync signal, any signal having a period longer than the HD sync signal) can be displayed more. Black floating on the screen 21 is reduced, and high contrast display can be realized. The above items are shown in Fig. 3.
It is not limited to the 39 examples. It is also applied to the driving method described above or the driving method described below. For example, the drive method shown in FIG. 341 is also applied.

[1195] In the driving method shown in Fig. 329, the signal waveform changes with a period of 1H. Therefore, the number of signal changes occurs twice every 1H. The signal change affects the source signal line 18 and the like. Further, if there are many changes in signals, the power consumption of the gate driver 12 also increases. Therefore, the number of signal changes per unit time should be small.

[1196] FIG. 341 shows that, as in FIG. 339, while the period T1 in which current is supplied to the EL element 15 is maintained for the period of 1H,
This is a driving method in which the number of changes of the gate signal line 17b per 1H is set to once. In each pixel row, the period for applying the on-voltage (Vgl) and the period for applying the off-voltage (Vgh) to the gate signal line 17b are set in reverse order for each 1H. For example, in the pixel row (1), the first horizontal scanning period (first
In H), the ON voltage is output during the period T1, and the OFF voltage is output during the period 1H-T1. Second horizontal scanning period (second
In H), the off voltage is output during the period 1H-T1, and the off voltage is output during the period T1. Similarly, in the third horizontal scanning period (third H), the ON voltage is output for the period of T1 and 1H-
The off voltage is output during the period of T1. That is, the period for outputting the on-voltage and the period for outputting the off-voltage are exchanged for each 1H. Further, the odd pixel rows and the even pixel rows are in reverse order.

[1196] Therefore, in the first horizontal scanning period (first H) of the odd-numbered pixel rows, the ON voltage is output for the period of T1 and 1H is output.
The off voltage is output during the period of -T1. In the second horizontal scanning period (second H), the off voltage is output for the period of 1H-T1,
The off voltage is output during the period of T1. Similarly, in the third horizontal scanning period (third H), the ON voltage is output during the period T1,
The off voltage is output during the period of 1H-T1. That is, 1H
The ON voltage output period and the OFF voltage output period are switched for each. In the even-numbered pixel rows, the OFF voltage is output during the 1H-T1 period during the first horizontal scanning period (1st H), and the ON voltage is output during the T1 period. In the second horizontal scanning period (2nd H), the ON voltage is output for 1H during the period of T1.
The ON voltage is output during the period of -T1. Similarly, in the third horizontal scanning period (third H), the OFF voltage is output during the period 1H-T1, and the ON voltage is output during the period T1. Also, FIG.
As described with reference to 40, the signal waveforms applied to the gate signal lines 17b of the odd-numbered pixel rows and the even-numbered pixel rows are switched by the vertical synchronization signal (VD) (see FIG. 343). Note that in FIG. 341, the positions to which the on-voltage and the off-voltage are applied are switched every 1H, but the invention is not limited to this. For example, it may be replaced every 2H or randomly. Also, FIG.
As shown in FIG. 5, the ON voltage application position and the like may be gradually shifted in each pixel row.

In the embodiment of FIG. 344, pixel row (1)
It is paired with (2) and paired with pixel rows (3) and (4). Pixel rows (5) and (6) are paired with pixel row (7)
The signal is applied as a pair with (8). The odd-numbered pixel rows have the same signal waveform, but the pixel row (1) and the pixel row (3) are phase-shifted during the period of 2H / 16. Similarly,
The pixel row (5) and the pixel row (7) are phase-shifted for a period of 2H / 16. The same applies hereinafter. Moreover, even-numbered pixel rows have the same signal waveform, but the pixel rows (2) and (4) are phase-shifted during a period of 2H / 16.
Similarly, the pixel row (4) and the pixel row (6) are phase-shifted for a period of 2H / 16. The same applies hereinafter.

As described above, in the drive system of the present invention, it is not always necessary to synchronize with the HD sync signal and change all the gate signal lines and the like at a predetermined timing from the HD sync signal. The above matters also apply to other inventions.

[1200] The gradation display in FIG. 341 is as shown in FIG. FIG. 342 shows an example in which the 1H period is subdivided into 16 (16
It is possible to adjust the brightness in stages). For the gradation 1 of the brightness, the ON voltage (Vgl) is applied to the gate signal line 17b for each 1H for a period of 1H / 16. Further, the position to which the on-voltage (Vgl) is applied is set in reverse order for each 1H. The brightness gradation 2 is 2H / for every 1H on the gate signal line 17b.
The ON voltage (Vgl) is applied only for 16 periods. Further, the position to which the on-voltage (Vgl) is applied is set in reverse order for each 1H. Similarly, the gradation 3 of the brightness is the gate signal line 17b.
The ON voltage (Vg
l) is applied. Further, the position to which the on-voltage (Vgl) is applied is set in reverse order for each 1H. The same applies hereinafter, and the brightness gradation 15 is 15H for every 1H on the gate signal line 17b.
The on-voltage (Vgl) is applied only for the period of / 16. Further, the position to which the on-voltage (Vgl) is applied is set in reverse order for each 1H. The brightness gradation 16 is always applied with the on-voltage (Vgl) except for the selected pixel row.

[1201] In the driving method described above, the driving waveforms of the gate signal lines in the odd-numbered pixel rows and the even-numbered pixel rows are made different, but the present invention is not limited to this as described in FIGS. 330 and 334. Absent. It goes without saying that they may be different in units of two or more pixel rows. Moreover, you may implement a random drive.

[1202] In the above example, the display image is controlled by controlling the time for applying the on-voltage (Vgl) to the gate signal line 17b (controlling the period in which the current flows through the EL element 15) in the 1H or 2H period. The driving method was to adjust (control) the brightness (brightness) of No. 21. That is, 1
The H or a plurality of H periods are divided into a plurality of periods, and the on-voltage or the off-voltage is applied in the corresponding period of the divided periods.

[1203] In FIG. 345, the brightness of the display image 21 is controlled by controlling the time for applying the on-voltage (Vgl) to the gate signal line 17b in units of 1H period (controlling the period during which current is passed through the EL element 15). Brightness: The present invention is a driving method for adjusting (controlling) gradation. That is, the brightness of the display image 21 is controlled (adjusted) by applying the ON voltage or the OFF voltage to any of the H periods with a plurality of H periods as one unit.

[1204] In FIG. 345, 1H is divided into 1/2, and this 1
The on-voltage (Vgl) is applied to / 2. Further, the ON voltage position of the gate signal line 17b of the even pixel row is made different from the ON voltage position of the gate signal line 17b of the odd pixel row. As can be seen from FIG. 345, the pixel row (1) of the odd pixel rows applies the ON voltage (Vgl) in the first half period of 1H, and the pixel row (2) of the even pixel rows (2) applies the ON voltage in the second half period of 1H. (Vgl) is applied. In this way, the ON voltage and the OFF voltage are alternately applied to the gate signal line 17b. At the point a, the gate signal line 17b of the odd-numbered pixel row changes from the on-voltage (Vgl) to the off-voltage (Vgh) (rise). On the other hand, the gate signal line 17b of the even pixel row changes from the off voltage (Vgh) to the on voltage (Vgl) (falling edge). Therefore, the voltages penetrating the source signal line 18 cancel each other out.

[1205] Gradation display (or rather, brightness (luminance) adjustment of the display screen 21) is as shown in FIG. 345. FIG. 34
Reference numeral 5 is a drive pattern repeated in the 16H period. Therefore, 16 gradations (16 levels of brightness) can be expressed. The phases of the gate signal lines 17b of the odd pixel rows and the gate signal lines 17b of the even pixel rows are shifted by 1H / 2.
Note that in the brightness control of FIG. 345, even at the 16th gradation, EL
The element 15 lights up only for a half period of one frame (one field). Therefore, in order to obtain the brightness as in the conventional case (where the current is constantly applied to the EL element 15), the current applied to the source signal line 18 is twice the predetermined value (N = 2).
Therefore, it is necessary to program each pixel. That is, the N-fold pulse drive described with reference to FIGS. 87 and 88 is performed.

[1206] For the gradation 1 of brightness, the gate signal line 17b is set to 1
The ON voltage (Vgl) is applied only for each H period for 1H / 2 (1/2 of 1H). For the gradation 2 of brightness, the ON voltage (Vgl) is applied to the gate signal line 17b for every 1H for a period of 2H / 2 (twice lighting of 1/2 of 1H). Similarly, for the brightness gradation 3, the gate signal line 17b is changed every 1H for a period of 3H / 2 (1/2 of 1H is lit three times).
An on voltage (Vgl) is applied. The brightness gradation 16 is
The gate signal line 17b is set to 1H every 16H / 2 period (1
ON voltage (Vgl) only for 1/2 of H lighting 16 times)
Is applied. As described above, by controlling the gate signal line 17b, the brightness control of the display screen 21 can be easily realized, and black floating does not occur.

[1207] FIG. 346 shows that the ON voltage (Vgl) application positions are dispersed. For example, gradation 2 in FIG. 345
In the drive method of FIG. 346, the ON voltage is applied continuously for 2H, but the ON voltage is applied to the b position. Since other matters are the same as those in FIG. 345, description thereof will be omitted. By distributing the on-voltage positions (or off-voltage positions) as shown in FIG. 346, it is possible to further reduce the influence on the source signal line 18 and the like. Note that in FIG.
In FIG. 345, 16H (16 horizontal scanning periods) are defined as one segment, but the invention is not limited to this. For example, 8H
However, 32H may be set as one segment.

[1208] In FIG. 345, etc., 1H is divided into ½, and the ON voltage or OFF voltage is applied during this 1H / 2 period. The present invention is not limited to this.
For example, as shown in FIG. 347, all 1H may be controlled to apply the ON voltage or the OFF voltage.

In FIG. 345, ON voltage or OFF voltage is applied to the gate signal line 17b in units of 16H, which is one cycle.
If 16H is one cycle, gradation (brightness can express 16 steps) Further, the ON voltage position of the gate signal line 17b of the even pixel rows is made different from the ON voltage position of the gate signal line 17b of the odd pixel rows. There is.

As can be seen from FIG. 345, in the gradation 1 (brightness level 1), the ON voltage (Vgl) is applied to the gate signal line 17b of the pixel row (1) of the even pixel rows for the period of 1H. After 1H, the ON voltage (Vgl) is applied to the gate signal line 17b of the pixel row (2) of the odd-numbered pixel row during the 1H period. At the point a, the gate signal line 17b of the even pixel row changes from the on-voltage (Vgl) to the off-voltage (Vgh) (rise). On the other hand, the gate signal line 17b of the odd-numbered pixel row changes from the off voltage (Vgh) to the on voltage (Vgl) (falling edge). Therefore, the voltages penetrating the source signal line 18 cancel each other out.

For brightness gradation 1 (brightness level 1), the ON voltage (Vgl) is applied to the gate signal line 17b for a period of 1H. The brightness gradation 2 is 2H for the gate signal line 17b.
The ON voltage (Vgl) is applied during the period. Similarly, for the brightness gradation 3, the ON voltage (Vgl) is applied to the gate signal line 17b for the period of 3H. The final brightness gradation 16 is
The gate signal line 17b is turned on (Vg
l) is applied (the ON voltage is always applied). As described above, by controlling the gate signal line 17b, the brightness control of the display screen 21 can be easily realized, and black floating does not occur.

[1212] The driving waveforms of the gate signal lines in the odd-numbered pixel rows and the even-numbered pixel rows are different from each other.
As described in 34, it is not limited to this. Two
It goes without saying that they may be different in units of pixel rows or more. Moreover, you may implement a random drive.

In the embodiment of FIG. 347, the gate signal line 17
Although the ON voltage (Vgl) is continuously applied from b, the invention is not limited to this. For example, FIG.
As described above, the on-voltage (Vhl) and the off-voltage (Vgh) may be alternately applied to the gate signal line 17b.

In FIG. 356, when each pixel row is selected (the ON voltage is applied to the corresponding gate signal line 17a), the condition that the OFF voltage is applied to the gate signal line 17b of the corresponding pixel row is satisfied. I am letting you. When it is not selected, the ON voltage or the OFF voltage is applied to the gate signal line 17b. In the state illustrated in FIG. 356, the ON voltage is applied to the pixel row (1) during the 4H periods of the 3H, 5H, 7H, and 9H. Since the pixel row (2) is shifted by 1 in the shift register 22, the 4th H and 6th
The on-voltage is applied during the period 4H of H, 8H, and 10H. Similarly, pixel row (3) has shift register 22
Since it has been shifted by 1, the 5H, 7H, 9H,
The on-voltage is applied during the 4H of the 11th H. The same applies hereinafter.

In the configuration of FIG. 356, the ON voltage position can be set by the data input control of the shift register 22 described in FIG. 2, and the ON voltage application position can be changed for each pixel row by the shift control of the shift register. Therefore, the circuit configuration and circuit control are easy. Also, display screen 2
Brightness adjustment of 1 is also easy. This is because it can be easily changed depending on how many ON voltages are applied (this can be controlled by the number of data applied to the shift register 22).

[1216] At the point a, the gate signal line 17b of the pixel row (1) changes from the on-voltage to the off-voltage (rise).
Then, the gate signal line 17b of the pixel row (2) changes (falls) from the off voltage to the on voltage. The same applies to other locations (for example, point b). At the point b, the gate signal lines 17b of the pixel row (1) and the pixel row (3) change (fall) from the off voltage to the on voltage, and the gate signal lines 17b of the pixel row (2) change from the on voltage to the off voltage. Change (rise). Therefore, in the driving method of FIG. 356, the rising and falling edges of the signal waveforms cancel each other in the gate signal lines of the adjacent pixel rows. Therefore, the potential fluctuation of the source signal line 18 and the like due to the applied signal of the gate signal line 17 is suppressed.

In FIG. 356, the on-voltage and the off-voltage are written by skipping one pixel, and the set of the on-voltage and the off-voltage are collectively driven. Further, the data shift is synchronized with the horizontal synchronizing signal (HD). The image display state is such that four sets of display pixel rows 311 and non-display pixel rows 312 (that is, eight pixel rows and other pixel rows are not displayed) are moved downward from the top of the screen. It In the above description, the number of pixel rows is reduced to facilitate the description.
The present invention is not limited to consecutively generating the set of the display pixel row 311 and the non-display pixel row 312. For example, it may be divided as shown in FIG.

[1218] The image display state of FIG.
If there are 4 sets of 11 and non-display pixel rows 312, 2 blocks (that is, 2 sets of 8 pixel rows, other pixel rows are not displayed) are moved downward from the top of the screen. Is displayed. There are 8 pixel rows between blocks.
In the above description, the number of pixel rows is reduced to facilitate the description. By driving so as to generate a plurality of blocks as described above, flicker does not occur in the display image even if the frame rate is extremely slowed.

Note that in FIGS. 356 and 348, the ON voltage is applied during the 1H period and the OFF voltage is applied during the next 1H period, but the invention is not limited to this. For example, 2
The ON voltage may be continuously applied for the H period, the OFF voltage may be applied for the next 2H period, and this may be repeated. What matters is that
That is, the signal waveform applied to the gate signal line 17b or the like is made different between the adjacent pixel rows. It is not limited to only the adjacent pixels. It may be different on the screen 21. Preferably, control is performed so that the number of rising edges and the number of falling edges of the signal waveform are substantially the same at a certain time.

By controlling the ST data applied to the shift register 22 that controls the gate signal line 17b in FIGS. 2, 60, 327, 333, etc., the brightness of the screen 21 can be easily adjusted and the pixel The pattern of line display 311 and non-display 312 can also be freely controlled (changed). If you input a lot of ST data per unit time, screen 2
1 luminance becomes high (when the ST data is H, the ON voltage (Vgl) is applied to the gate signal line 17b).

[1221] If the input data is intermittently input to the ST data and the interval between the input data is short, each pixel row repeats lighting 311 and non-lighting 312 in a short time. Therefore, when a moving image is displayed, moving image blurring easily occurs, but flicker does not occur. On the other hand, if the input data is continuously input to the ST data all at once and the interval for inputting the input data is long, the interval between the lighting 311 and the non-lighting 312 in each pixel row becomes long. Therefore, moving image blur does not occur when displaying a moving image. However, on the other hand, the occurrence of flicker increases. In any case, the present invention can realize brightness adjustment and moving image display adjustment with a simple driving method. Further, by changing the waveform applied to the gate signal line 17 in the adjacent pixel row or the like, the potential fluctuation applied to the source signal line 18 can be made extremely small. Therefore, it is possible to realize a good image display without blackening.

[1222] FIG. 350 shows a data pattern input to the shift register 22. In FIG. 350, black circles are data for controlling the non-display 311. In addition, the white circle is lit 3
This is the data controlled to 11. This data shifts in the shift register 22 and controls whether to output the ON voltage or the OFF voltage to the corresponding gate signal line 17b.

[1223] In Fig. 350 (a), a set of seven black circles and one white circle is continuous. In this pattern, a set of 7 pixel rows not illuminated 312 and 1 pixel row illuminated 311 is continuously displayed, and this pattern is a horizontal synchronization signal (HD).
The screen 21 is scanned from the top to the bottom in synchronization with.

[1224] In FIG. 350 (b), a set of four black circles and four white circles is continuous. In this pattern, a set of 4 pixel rows not illuminated 312 and 4 pixel rows illuminated 311 is continuously displayed, and this pattern is a horizontal synchronization signal (HD).
The screen 21 is scanned from the top to the bottom in synchronization with.

[1225] In FIG. 350 (c), 12 black circles and 12
A set of individual white circles are continuous. In this pattern, 12
A group of pixel rows that are not illuminated 312 and 12 pixel rows that are illuminated 311 is continuously displayed, and this pattern is scanned from the top to the bottom of the screen 21 in synchronization with the horizontal synchronization signal (HD).

In FIG. 350 (d), a set of 21 black circles and 3 white circles is continuous. In this pattern, a set of 21 pixel rows that are not illuminated 312 and 3 pixel rows that are illuminated 311 are continuously displayed, and this pattern is synchronized with the horizontal synchronization signal (HD) to move from the top to the bottom of the screen 21. It will be scanned.

[1227] In FIG. 350 (e), a set of one black circle and one white circle is continuous. In this pattern, a set of non-lighting 312 and lighting 311 is alternately displayed on one pixel row, and this pattern is scanned from the top to the bottom of the screen 21 in synchronization with the horizontal synchronizing signal (HD).

[1228] In FIG. 350 (d), black circles and white circles are randomly input. In this pattern, a random lit pixel row and a non-lit pixel row have a horizontal synchronization signal (HD).
The screen 21 is scanned from the top to the bottom in synchronization with.

In FIG. 350, with the same brightness, FIG. 350 (d) is suitable for displaying a moving image, and FIG. 350 (a) is the most unsuitable (although the actual space between black and white circles is wider).

[1230] FIG. 355 also shows the relationship between the data input to the shift register 22b and the output to the gate signal line 17b. The data initially held in the shift register 22b is the non-selected data (gate signal line 17b
Data (black circle) for applying the off voltage to

[1231] White circles (selection data) are input to the shift register 22b at the first H (1H). Therefore, the gate signal line 17b of the pixel row (1) has a selection voltage (ON voltage (V
gl)) is output. Gate signal line 17 of another pixel row
The off voltage (Vgh) is output to b. Therefore, the pixel row (1) becomes the display 311.

[1232] The next second H (2H) shift register 22
A black circle (non-selected data) is input to b. The shift register 22b shifts by 1 bit in synchronization with CLK (HD). Therefore, the off voltage (Vg
h)) is output, and the selection voltage (ON voltage (Vgl)) is output to the pixel row (2). The off voltage (Vgh) is output to the other pixel rows. Therefore, the pixel row (1) becomes the display 311.

[1233] At the next third H (3H), the shift register 22
A white circle (selected data) is input to b. The shift register 22b shifts by 1 bit in synchronization with CLK (HD). Therefore, the on-voltage (Vgl) is output to the pixel rows (1) and (3), and the non-selection voltage (off-voltage (Vgh)) is output to the pixel row (2). The off voltage (Vgh) is output to the other pixel rows. Therefore, the pixel rows (1) and (3) become the display 311.

[1234] Similarly, a black circle (non-selected data) is input to the shift register 22b at the next 4H (4H). Also,
The shift register 22b shifts by 1 bit in synchronization with CLK (HD). Therefore, the off voltage is output to the gate signal lines 17b of the pixel rows (1) and (3), and the selection voltage (off voltage (Vgh)) is output to the pixel rows (2) and (4). The off voltage (Vgh) is output to the other pixel rows. The pixel rows (1) and (3) are non-display 312, and the pixel rows (2) and (4) are display 31.

[1235] When the above operation is sequentially repeated, the waveform output to the gate signal line 17b becomes a waveform in which the ON voltage and the OFF voltage are alternately output every 1H as shown in FIG. 348.
As described above, according to the data of the shift register 22b,
It is possible to easily control lighting and non-lighting of pixel rows.

In FIG. 355, the switch S is arranged at the output stage of the gate signal line 17b. This is the OR circuit 3272 of FIGS. 334 and 333, or the ENB of FIG. 334.
The L terminal is applicable. By turning this switch on and off, it is possible to control so that the on voltage or the off voltage can be applied to the gate signal line 17b within the period of 1H.
When the switch S is closed, the data of the shift register is output to the gate signal line 17b as it is, and when the switch S is open, the off voltage (Vgh) is output. .

[1237] By controlling the switch S in FIG.
32, FIG. 339, FIG. 340, FIG. 341, FIG. 344, FIG.
Control within 1H such as 45 can be easily realized. Therefore, with the circuit configuration or driving method of FIG.
8 and FIG. 356 and the like in 1H unit control, and FIG.
39, FIG. 340, FIG. 341, FIG. 344, FIG. 345, etc. within 1H can be easily combined and implemented. That is, the flexibility can easily realize the gradation (brightness) control, smoothly, and easily realize the circuit configuration.

[1238] In the above embodiments, the gate signal line 17b has been mainly described. However, it is not only the gate signal line 17b that couples with the source signal line 18. It is also coupled with the gate signal line of the TFT which applies the reverse bias voltage described above. FIG. 357 shows a pixel configuration when a reverse bias voltage is applied. Although the pixel configuration of the current program of FIG. 1 is basically used, the present invention is not limited to the pixel configuration of FIG. 1 as described repeatedly. For example, FIG. 21, FIG. 22, FIG. 47, FIG.
It can also be applied to a pixel configuration of a current mirror such as 1. Further, it goes without saying that the present invention can also be applied to the pixel configuration of the voltage program shown in FIG. 54, FIG. 67, FIG.

The above embodiments deal with the occurrence of black floating due to the coupling between the gate signal line 17b and the source signal line 18. 89 to 101, etc., the characteristic method of the present invention for applying a reverse bias voltage has been described.

However, in order to apply the reverse bias voltage, it is necessary to apply the on / off voltage to the gate terminal of the TFT 11g to which the reverse bias voltage is applied. Therefore, the signal line 17d for applying the on / off voltage and the source signal line 18 may be coupled.

[1241] FIG. 357 shows a configuration in which a reverse bias voltage is applied in the pixel configuration of FIG. In addition, in the following example, FIG.
The pixel configuration of FIG. 21 will be described as an example, but the pixel configuration is not limited thereto, and FIG. 21, FIG. 43, FIG. 54, FIG. 68, and FIG.
It goes without saying that the present invention can be applied to all the pixel configurations or panel configurations of the present invention such as.

[1242] FIG. 357 is an equivalent circuit diagram of a pixel configuration to which the reverse bias voltage Vm is applied. FIG. 357 (a) shows the case where the TFT to which the reverse bias voltage is applied is the P channel. FIG. 357 (b) shows a TFT applying a reverse bias voltage.
Is for N channels.

[1243] Note that the signal line 3571 for transmitting the reverse bias voltage Vm is preferably wired (arranged or formed) in parallel with the source signal line 18. This is because the parasitic capacitance of the gate signal line 17 can be reduced.

[1244] FIG. 359 shows drive waveforms in the case of the pixel configuration of FIG. 357 (a). As described above, the present invention suppresses the coupling between the signal lines, so that the change in the waveform to the applied signal line is reduced, and / or
Apply the applied signal waveforms of adjacent signal lines in opposite phases or cancel each other as much as possible, or (or) observe the waveform applied to the signal lines at any time as the entire display area 21 of the display panel. At this time, the driving is performed so that the signal waveforms of the falling edge and the rising edge of the signal are random or almost the same number.

The embodiment shown in FIGS. 358 and 359 is basically the same as the driving method of the gate signal line 17b described above. The driving concept of the gate signal line 17b is replaced with the control signal line 17d. Therefore, the matters described in the driving of the gate signal line 17b and the like will be described with reference to FIGS.
It can be applied to 59 or the like.

[1246] The drive voltage V of the gate signal lines 17a and 17b
Assuming that gh is 15 (V) and Vgl = 0 (V), FIG.
7 (a), the gate signal line 1 for controlling the TFT 11g
The voltage Vmh (OFF voltage) of 7d is 0 (V) or the vicinity. In addition, the gate signal line 1 for controlling the TFT 11g
The on-voltage Vml of 7d is -15 (V) or the vicinity.

In FIG. 357 (b), the gate signal line 17d for controlling the TFT 11g has a voltage Vmh (off voltage) equal to or near Vgl. Also, TFT 11g
ON voltage Vml of the gate signal line 17d for controlling
It is the same as or close to l.

From the above, as a drive voltage range of the TFT 11g, the method of FIG. 357 (b) is advantageous. However, instead of fixing the voltage applied to the TFT 11g to Vm, it is possible to switch between the high impedance and the Vm voltage.
The constraints of T11g are alleviated.

In FIG. 359 (FIG. 357 (a)), the gate signal line 17b of the pixel row (1) changes (falls) from the off voltage to the on voltage at the point a, and the gate signal line of the pixel row (1) changes. 17d (reverse bias control line) changes (rises) from on-voltage (Vml) to off-voltage (Vmh). Therefore, the change directions of the signal waveforms of the gate signal line 17b and the gate signal line 17d are opposite to each other. Therefore, the punch-through that occurs in the source signal line 18 due to the coupling does not occur (or becomes extremely small).

[1250] When an on-voltage is applied to the gate signal line 17b, the TFT 11d turns on. In addition, the gate signal line 17
When an on-voltage is applied to d, the TFT 11g turns on.
When the TFT 11g and the TFT 11d are turned on at the same time, a short circuit occurs. In order to avoid this situation, the TFT 11d
The timing for switching between ON and OFF of the TFT 11g and the TFT 11g is always controlled so that one of the TFTs is turned on after both are turned off. It is preferable that the off-voltage is applied to the gate signal line 17b and the on-voltage is applied to the gate signal line 17d for a period of 1 μsec or more and 25 μsec or less. Alternatively, it is preferable that the time is 1/100 to 1/4 of 1H. Similarly, an off voltage is applied to the gate signal line 17d, and the gate signal line 1
It is preferable that the ON voltage is applied to 7b for a period of 1 μsec or more and 25 μsec or less. Alternatively, it is preferable that the time is 1/100 to 1/4 of 1H.

At point b in FIG. 359, the gate signal line 17b of the pixel row (1) changes from the on voltage (Vgl) to the on voltage (Vg).
h), the gate signal line 17d (reverse bias control line) of the pixel row (1) is turned off (Vmh).
Changes to the ON voltage (Vml) (falls). In this state, the current flowing from the TFT 11a to the EL element 15 is cut off, and the reverse bias voltage V is applied to the anode of the EL element 15.
m is applied. At the point b, the change directions of the signal waveforms of the gate signal line 17b and the gate signal line 17d are opposite to each other. Therefore, the punch-through that occurs in the source signal line 18 due to the coupling does not occur (or becomes extremely small). Therefore, the potential fluctuation of the source signal line 18 and the like due to the applied signal of the gate signal line 17d is suppressed.

[1252] Also, in FIG. 359, the gate signal line 17d
The signal change position of is shifted for each pixel row. Therefore, the position where the reverse bias voltage is started in synchronization with HD is shifted. Also, the shift is performed in synchronization with the signal waveform of the gate signal line 17b. As mentioned above,
By changing the gate signal lines 17b and 17d in synchronization with each other and shifting the application position, the time for applying the reverse bias voltage to the EL element 15 of each pixel becomes constant. Further, the potential change of the source signal line 18 does not occur. Therefore, it is possible to realize good contrast without blackening.

As described above, the change directions of the signal waveforms of the gate signal line 17b and the gate signal line 17d are opposite to each other (as a matter of course, a period in which both TFTs 11d and 11g are turned off is provided so that both TFTs are turned off. There is a need). Therefore, the source signal line 18 is canceled by the signal waveform. Also, the even-numbered gate signal lines 17d ((2) (4) (6) ...) And the odd-numbered gate signal lines 17d ((1) (3) (5) ... is there. In addition, even-numbered gate signal lines 17b
((2) (4) (6) ...) And the odd-numbered gate signal lines 17b ((1) (3) (5) ... Within the display area 21, the potential fluctuation of the source signal line 18 due to the amplitude of the signal waveform is suppressed as a whole.

[1254] FIG. 358 is similar to FIG. 359. This is the same as the method of driving the gate signal line 17b described above.
The driving concept of the gate signal line 17b is replaced with the control signal line 17d. Therefore, the gate signal line 17b
The matters described in the driving of FIG.

In FIG. 358, at the point a, the gate signal line 17b of the pixel row (1) changes from the off voltage (Vgh) to the on voltage (Vgl) (falls), and the gate signal line 17d of the pixel row (1). (Reverse bias control line) turns on voltage (Vm
The voltage changes from h) to the off voltage (Vml) (falls). Therefore, the gate signal line 17b and the gate signal line 1
The changing directions of the signal waveform of 7d are the same. At the point b, the gate signal line 17b of the pixel row (1) changes (rises) from the on-voltage (Vgl) to the off-voltage (Vgh), and the gate signal line 17d (reverse bias control line) of the pixel row (1) is turned off. The voltage (Vml) changes to the on-voltage (Vmh) (rises). Therefore, the changing directions of the signal waveforms of the gate signal line 17b and the gate signal line 17d are the same. Therefore, there is no effect of canceling the punch-through that occurs in the source signal line 18 due to the coupling.

[1256] Also in the driving method of FIG. 358, as in the case of FIG. 359, the time when the off voltage is applied to the gate signal line 17b and the on voltage is applied to the gate signal line 17d is 1 μsec or more and 25 μsec or less. It is preferable to separate the periods. Or 1/100 or more of 1H and 1/4
It is preferable to be separated for the following time. Similarly, the time period in which the off voltage is applied to the gate signal line 17d and the on voltage is applied to the gate signal line 17b is 1 μsec or more and 25 μs or more.
It is preferable to separate during a period of ec or less. Or 1H
It is preferable that the time is 1/100 or more and 1/4 or less.

[1257] The change directions of the signal waveforms of the gate signal line 17b and the gate signal line 17d of the pixel row (1) are the same. Therefore, there is no effect of canceling the punch-through that occurs in the source signal line 18 due to the coupling. However, the signal waveform of the gate signal line 17b and the signal waveform of the gate signal line 17d of the pixel row (2), and the gate signal line 1 of the pixel row (1)
The signal waveform of 7b and the signal waveform of the gate signal line 17d have opposite phases. Therefore, in the pixel row (1) and the pixel row (2), the effect of canceling the punch-through generated in the source signal line 18 due to the coupling is exerted. That is, in the even-numbered pixel rows and the odd-numbered pixel rows, the effect of canceling the punch-through generated in the source signal line 18 due to the coupling is exhibited by reversing the signal phases applied to the gate signal lines.

[1258] In the above embodiment, the gate signal line 1
Although the phases of the signal waveforms of 7b and the gate signal line 17d are set to be opposite to each other, this does not mean that they are completely opposite. That is, the technical idea of the present invention is to suppress the coupling to the source signal line 18 and the like. Therefore, the gate signal line 17b and the gate signal line 1
The phase relationship of the signal waveform of 7d may be different.

[1259] Also, in FIG. 358, the gate signal line 17d
The signal change position of is shifted for each pixel row. Therefore, the position where the reverse bias voltage is started in synchronization with HD is shifted. Also, the shift is performed in synchronization with the signal waveform of the gate signal line 17b. As mentioned above,
By changing the gate signal lines 17b and 17d in synchronization with each other and shifting the application position, the time for applying the reverse bias voltage to the EL element 15 of each pixel becomes constant. Further, the potential change of the source signal line 18 does not occur. Therefore, it is possible to realize good contrast without blackening.

[1260] In FIG. 358, the change directions of the signal waveforms of the gate signal line 17b and the gate signal line 17d are the same. Therefore, it has been described that there is no effect of canceling the punch-through that occurs in the source signal line 18 due to the coupling. However, as shown in FIG. 367, the off voltage (Vgh) is applied to the gate signal line 17b in the portion where the display region 21 is in the non-lighting state 312. The non-lighting state 312 of the area 312 is maintained for a fixed time. Therefore, FIG.
As shown in FIG. 7, the gate signal line 17d can apply a signal without synchronizing with the gate signal line 17b. Therefore, the even-numbered gate signal lines 17d ((2) (4)
(6) ... ・) and odd-numbered gate signal lines 17d
((1) (3) (5) ... ・) can be in opposite phase. Within the display area 21, the potential fluctuation of the source signal line 18 due to the amplitude of the signal waveform is suppressed as a whole.

[1261] In the driving method described above, the driving waveforms of the gate signal lines in the odd-numbered pixel rows and the even-numbered pixel rows are made different, but the present invention is not limited to this as described with reference to FIGS. 330 and 334. Absent. It goes without saying that they may be different in units of two or more pixel rows. Moreover, you may implement a random drive.

[1262] Also, in the reverse bias driving examples of FIGS. 358, 359, and 367, FIGS.
It is preferable to apply the pixel configuration described in 1. In this case, the gate signal line 17b may be replaced with a gate signal line 17d for controlling the reverse bias application TFT.
Also, FIG. 333, FIG. 327, FIG. 334, FIG. 349, FIG.
The same applies to the panel or array configuration described in 55. Also in this case, the gate signal line 17b is the gate signal line 17d for controlling the reverse bias application TFT.
You can replace it with As described above, it is needless to say that the matters regarding the reverse bias driving described with reference to FIGS. 358, 359, 367, and the like can be combined with other examples in this specification.

[1263] A display method in which odd-numbered pixel rows and even-numbered pixel rows (or a plurality of pixel rows) are switched for each predetermined field (frame) like the display method in FIG. 61 can be applied to a stereoscopic image display device or method. it can. Less than,
The stereoscopic display device of the present invention will be described with reference to FIGS.

[1264] First, according to the display method of the present invention, the display area 311 and the non-display area 3 are basically arranged in pixel row units (pixel row direction).
12 is included. Therefore, when displaying as in FIG. 61, it is necessary to convert the vertical and horizontal directions. This conversion is easy. This is because the rows and columns of the image data stored in the memory may be exchanged. Figure 8 if you convert the vertical and horizontal
5 (a1) is displayed. That is, the scanning direction of the display panel is the direction of the arrow indicated by A, but the image is as shown in FIG.
As shown in, the top of the paper is the screen and the bottom of the paper is the bottom of the screen. Therefore, the user of the display panel looks as if scanning from the top of the screen to the bottom.

[1265] In the display image 21 of the display panel, the right-eye image is displayed in the odd pixel columns (rows) from the left, and the left-eye image is displayed in the even pixel columns (rows). The image display is synchronized with the observation glasses 852 that are synchronized with the display panel. The observation glasses 852 include two liquid crystal panels that function as shutters 851.

[1266] In the first field (first frame), FIG.
5 (a1), the odd-numbered pixel columns from the left (actually odd-numbered pixel rows) become the display region 311, and the even-numbered pixel columns from the left (actually even-numbered pixel rows) become the non-display region 312. Become. Synchronizing the display state of FIG. 85 (a1), the left-eye shutter 851L of the eyeglasses 852 is closed and the right-eye shutter 851R of the eyeglasses 852 is opened. Therefore, the observer sees the image of FIG. 85 (a1) only with the right eye.

In the second field (second frame) next to the first field (first frame), as shown in FIG. 85 (a2), even-numbered pixel columns (actually even-numbered pixel rows) from the left are the display areas. 311 and the odd-numbered pixel columns (actually, odd-numbered pixel rows) from the left become the non-display area 312. Synchronizing the display state of FIG.
The right-eye shutter 851R closes and the left-eye shutter 851L of the eyeglasses 852 opens. Therefore, the observer sees the image of FIG. 85 (a2) only with the left eye.

[1268] By repeating the above operation alternately,
Stereoscopic image display can be realized by allowing the viewer to see alternately the glasses-type shutter 851 used by the viewer and the image display state in synchronism with each other.

In order to realize a stereoscopic image display without using the shutter 851, a prism 861 may be arranged on the light emitting side of the display panel as shown in FIG. The A part of the prism 861 is arranged so as to correspond to the display region 311 at a certain display timing, and the B part of the prism 861 is arranged so as to correspond to the display region 312 at the above-mentioned display timing. By arranging the prism 861 in this way, the image of the odd-numbered pixel rows can enter the right eye of the observer, and the image of the even-numbered pixel rows can enter the left eye of the observer. The prism 8
An optical coupling material 862 such as ethylene glycol is arranged between 61 and the display panel to perform optical coupling.

[1270] Note that in FIG. 85, switching means 852
Was used as glasses, but is not limited thereto. Any one may be used as long as it can control the light incident on the right eye and the light incident on the left eye of the observer. For example, a goggle type is exemplified. Also, switching means 852
An example is one in which the display panel and the display panel are integrated (head-mounted display). It is needless to say that the shutter 851 is not limited to the liquid crystal display panel and may be mechanical such as a shutter of a camera or a rotary filter. In addition, those incorporating a polygon mirror, shutters using PLZT, shutters applying electroluminescence, etc. are also exemplified.

As described above, for example, the right-eye image is displayed on the odd-numbered pixel rows, and the left-eye image is displayed on the even-numbered pixel rows. The eyeglass-type shutter used by the observer and the image display state are synchronized with each other so that the observer can alternately see them.
Alternatively, the prism arranged on the light emission side of the display panel is configured so that the image of the odd pixel rows is incident on the right eye of the observer and the image of the even pixel rows is incident on the left eye of the observer.

As described above, the stereoscopic display can be realized by using the display method of FIG. 61 for the display image of one display panel. Note that the devices or methods of FIGS. 85 and 86 display different images for each of a plurality of pixel rows (columns) or for each of odd-numbered pixel rows (columns) and even-numbered pixel rows (columns). It is not limited to the display only. For example, it goes without saying that it may be used for the purpose of simply displaying two images in an overlapping manner. Needless to say, it is particularly effective to carry out the driving method of the present invention using the EL display device of the present invention.

[1283] The element that drives each pixel is the TFT 11
However, it is not limited to this. For example, the pixel 16 can be configured by combining a thin film diode (TFD), and the current flowing through the EL element 15 can be intermittently operated by operating the voltage level at one terminal of this diode. In this configuration, the cathode electrode is processed (formed) in a horizontal stripe shape as needed. The same applies to switching elements such as varistors and thyristors.

For example, the driving T of the TFT 11a of FIG.
Taking the FT as an example, it may be an N-channel or P-channel bipolar transistor as shown in FIG. Needless to say, it may be an N-channel or P-channel MOS transistor as shown in FIG. 80 (b). Further, it may be a phototransistor or a photodiode as shown in FIG. 80 (c), or a thyristor element as shown in FIG. 80 (d). It goes without saying that this can also be applied to switching elements that form other pixels.

It is needless to say that the TFT element 11 can be used in either P channel or N channel. The position of the EL element 15 is not limited to the position shown in FIG. 1 or FIG. For example, FIG. 79A shows the TFT 11a and the EL element 15 of FIG.
It is a connection state extracted from. As this modification, the configuration of FIG. 79 (b) is also illustrated. Also, the driving TFT
The configurations of FIGS. 79 (c) and (d) in which N is the N channel are also illustrated. These matters apply not only to the driving TFT 11a but also to the switching element 11 that constitutes another pixel.
The same applies to (for example, TFTs 11b, 11c, 11d in FIG. 1). In addition, the drivers 12, 14
It is similarly applied to the elements constituting the.

[1276] Further, it is desirable that the switching element such as TFT is formed of a low temperature polycrystal Si-TFT, but needless to say, it may be an amorphous silicon TFT. In particular, when the current passed through the EL element 15 is 1 μA or less, the characteristics are sufficient because it is formed by the amorphous silicon technique. Also, the gate driver circuit, the source driver circuit, and the like may be formed by elements using amorphous silicon technology.

Also, the configuration of the gate driver 12 shown in FIGS. 2, 60, 74, 84, etc. is not limited to this (in FIG. 2, etc., the shift operation (serial Processing)),
For example, a parallel input that determines the on / off state of each gate signal line at a time may be used (the on / off logic of all gate signal lines is the controller or the gate signal line 1).
For example, a configuration in which the number of 7 is output and determined at one time).

[1278] FIG. 10 is a block diagram of an organic EL module. A control IC 101 and a power supply IC 102 are mounted on the printed circuit board 103. Printed circuit board 103
The array substrate 49 and the array substrate 49 are electrically connected by the flexible substrate 104. The power source voltage, current, control signal, and video data are transferred to the array substrate 49 via the flexible substrate 104.
Are supplied to the source driver 14 and the gate driver 12.

[1279] In this case, the problem is that the gate driver 1
2 control signal. It is necessary to apply a control signal having an amplitude of at least 5 (V) or more to the gate driver 12. However, the power supply voltage of the control IC 101 is 2.
Since it is 5 (V) or 3.3 (V), the control signal cannot be directly applied from the control IC 101 to the gate driver 12.

To solve this problem, the present invention applies the control signal of the gate driver 12 from the power supply IC 102 driven by a high voltage. The power supply IC 102 is the gate driver 12
Since the operating voltage is also generated, it is naturally possible to generate a control signal having an optimum amplitude in the gate driver 12.

[1281] In FIG. 11, the control signal of the gate driver 12 is generated by the control IC, temporarily level-shifted by the source driver 14, and then applied to the gate driver 12. The drive voltage of the source driver 14 is 5 to 8
Since it is (V), the control signal of 3.3 (V) amplitude output from the control IC 101 is supplied to the gate driver 1
It can be converted to a 5 (V) amplitude that 2 can receive.

[1282] FIGS. 14 and 15 are explanatory views of the display module device of the present invention. FIG. 14 shows a structure in which the source driver 14 has a built-in RAM 151. Built-in RAM displays 8 colors (1 bit for each color), 256 colors (3 bits for RG, 2 bits for B), 4096 colors (4 for RGB).
Bit) capacity. These 8 colors, 256 colors or 4
Source driver 1 for 096 color display and still image
The driver controller arranged in 4 has this built-in RA
The image data of M151 is read. Therefore, ultra low power consumption can be realized. Of course, the built-in RAM 151 may be a multicolor RAM having 260,000 colors or more. Further, the image data of the built-in RAM 151 may be used also for a moving image.

[1283] As the image data of the built-in RAM 151, the data after the error diffusion processing or the dither processing may be stored in the memory. By performing error diffusion processing, dither processing, etc., the 260,000-color display data can be converted into 4096 colors, etc., and the capacity of the built-in RAM 151 can be reduced. Error diffusion controller 1 for error diffusion processing
It can be done at 41. Further, the error diffusion process may be further performed after the dither process is performed. The above items also apply to the inverse error diffusion processing.

[1284] Although 14 is described as a source driver in FIG. 14 and the like, not only a driver but also a power supply circuit 102, a buffer circuit 154 (including a circuit such as a shift register), a data conversion circuit, a latch circuit, and a command decoder. , Shift circuit, address conversion circuit, built-in RA
Various functions or circuits for processing the input from M151 and outputting the voltage or current to the source signal line are configured. The same applies to other embodiments of the present invention.

[1283] Needless to say, even in the configuration described with reference to FIG. 14 or the like, the three-side free configuration or the configuration or the drive method described with reference to FIGS. 26 to 30, or 111 to 113, or the like can be applied. .

Also, as shown in FIG. 203, the sealing plate 41 may also serve as a protective cover for a mobile phone or the like.
The protective cover is a transparent plate arranged to protect the front surface of the display panel. Alternatively, in a reflective liquid crystal display panel, the front light serves as a protective cover.

[1287] FIG. 203 shows a configuration example in which the sealing plate (lid) 41 is used as a protective cover for protecting the organic EL element 15 from humidity. A circularly polarizing plate 74 is attached to the sealing plate 41. The circularly polarizing plate 74 may be formed of a thin film. Alternatively, it may be formed by applying a resin to the sealing plate 41 or the like and stretching the resin.

[1288] An EL array substrate 49 is attached to the casing 193 of a mobile phone (an EL display panel is attached). The driver IC (circuit) 12 (14) is arranged (formed) in the sealing plate 41. The driver IC (circuit) 12 (14) also includes the sealing plate 4
Protected by 1. By forming (configuring) as described above, the protective cover can be omitted. Therefore, the overall thickness of the display panel module can be reduced.

[1289] Also, as described with reference to FIG.
In the panel, it is necessary to form the reflective film 46 also as the cathode electrode (or the anode electrode). This electrode is made of aluminum or the like. Therefore, the reflectance is as good as 85% or more.

[1290] Fig. 204 shows a mobile phone configured such that the reflection film 46 can be used as a mirror. In normal use, it is used as shown in FIG. 19 (or see FIG. 205). When the display panel 2046 is used as a mirror, the display panel 2046 is turned upside down around a right or left fulcrum (not shown), and the rear surface mirror 2045 is used.

However, in the above embodiments, the reflective film formed on the back surface of the EL display panel is used as a mirror. Therefore, the target to be used as a mirror is not limited to a mobile phone, but may be a TV, monitor, P
DA may be used. In addition, a mirror is formed on the back surface of the display panel. Therefore, the structure is not limited to the cathode, and a structure in which a mirror is separately formed on the back surface of the display panel may be used. For example, a reflective liquid crystal display panel does not use the back surface. Aluminum or silver may be vapor-deposited on the back surface to form a mirror. In this case, in order to prevent corrosion of aluminum or silver, S on the surface
It is preferable to form an inorganic thin film such as i02. It may also be protected by UV resin or the like.

[1292] In FIG. 204, reference numeral 2041 denotes a speaker that allows the received voice to be heard.
Reference numeral 44 is a microphone for inputting the voice of the user.

[1293] Further, as described with reference to Fig. 35, it is preferable to dispose the display mode changeover switch 465. Further, it is preferable to form (arrange) a changeover switch that realizes the function of changing the screen brightness described with reference to FIG.

[1294] The frame rate is related to the power consumption of the panel module. That is, if the frame rate is increased, the power consumption increases almost in proportion. It is necessary to reduce the power consumption of mobile phones and the like from the standpoint of increasing the standby time. On the other hand, in order to increase the display colors (increase the number of gradations), the driving frequency of the source driver IC 14 and the like must be increased. However, it is difficult to increase the power consumption due to the power consumption problem.

[1295] Generally, in an information display device such as a mobile phone, low power consumption is prioritized over the number of display colors. The power consumption increases because the operating frequency of the circuit that increases the number of display colors increases, or the voltage (current) waveform applied to the EL element changes more often. Therefore, the number of display colors cannot be increased so much. To solve this problem, the present invention displays the image by performing error diffusion processing or dither processing on the image data.

Although not shown in the mobile phone of the present invention described with reference to FIG. 19, a CCD camera is provided on the back side of the housing. The image taken by the CCD camera can be immediately displayed on the display screen 21 of the display panel. The data captured by the CCD camera can be displayed on the display screen 21. Image data of CCD camera is 24 bits (16.7 million colors), 18
Bit (260,000 colors), 16 bits (650,000 colors), 12
Bits (4096 colors) and 8 bits (256 colors) can be switched by key input 265.

[1297] When the display data is 12 bits or more, the error diffusion processing is performed for display. That is, when the image data from the CCD camera exceeds the capacity of the built-in memory, error diffusion processing or the like is performed, and the image processing is performed so that the number of display colors becomes equal to or less than the capacity of the built-in memory 151.

[1298] Now, the source driver IC 14 has 4096
Description will be made assuming that a built-in RAM 151 for one screen is provided for each color (4 bits for each RGB). When the image data sent from outside the module is 4096 colors, it is directly stored in the built-in RAM 151 of the source driver IC 14, the image data is read from this built-in RAM 151, and the image is displayed on the display screen 21.

[1299] Image data has 260,000 colors (G: 6 bits,
In the case of R and B: 5 bits in total (16 bits), as shown in FIGS. 14 and 15, the arithmetic circuit 153 is temporarily stored in the arithmetic memory 152 of the error diffusion controller 141 and simultaneously performs the error diffusion or dither processing. Error diffusion or dither processing is performed. By this error diffusion processing or the like, 16-bit image data is converted into 12-bit which is the number of bits of the built-in RAM 151 and the source driver IC
14 is transferred. The source driver IC 14 outputs image data of RGB each of 4 bits (4096 colors) and displays the image on the display screen 21.

[1300] Also, in the configuration of FIG. 15 or the like, even if the error diffusion processing or the dither processing method is changed for each field or frame by using the vertical synchronization signal VD (the processing method is changed by the vertical synchronization signal VD). Good. For example, in the dither processing, the Bayer type is used in the first frame, and the halftone type is used in the next second frame. By changing and switching the dither processing for each frame in this manner, it is possible to achieve the effect that the dot unevenness caused by the error diffusion processing is less noticeable.

[1301] In addition, the processing coefficient such as the error diffusion processing may be changed between the first frame and the second frame. Alternatively, the error diffusion process may be performed in the first frame, the dither process may be performed in the second frame, and the error diffusion process may be performed in the third frame. In addition, a processing method that includes a random number generation circuit and performs processing for each frame with a random number value may be selected.

[1302] If the information such as the frame rate is described in the transmitted format, the frame rate or the like can be automatically changed by decoding or detecting the described data. In particular,
It is preferable to describe whether the transmitted image is a moving image or a still image. Further, in the case of a moving image, it is preferable to describe the number of frames per second of the moving image. In addition, it is preferable to describe the model number of the mobile phone in the transmission packet. It should be noted that in the present specification, the packet is described as a transmission packet, but it need not be a packet. That is, any data may be used as long as the information (display color number, frame rate, etc.) described in FIG.

[1303] FIG. 17 shows a transmission format sent to the mobile phone or the like of the present invention. Transmission includes both received data and transmitted data. That is, the mobile phone may transmit voice from the handset or an image captured by the CCD camera attached to the mobile phone to another mobile phone or the like. Therefore, matters related to the transmission format and the like described in FIG. 18 and the like are applied to both transmission and reception.

[1304] In the mobile phone or the like of the present invention, data is digitized and transmitted in a packet format. As described in FIG. 16 and FIG. 17, the flag portion (F), the address portion (A), the control portion (C), the information portion (I), the frame check sequence (FCS), and the flag are included in the frame. Part (F). As shown in the figure, the control section (C) has three formats: information transfer (I frame), relation (S frame), and unnumbered system (U frame).

[1305] First, the information transfer format is the format of the control field used when transferring information (data).
Except for some of the non-numbered formats, the information transfer format is the only format that has a data field. A frame in this format is called an information frame (I frame).

[1306] The monitoring format is a format used for a data link monitoring control function, that is, for confirming reception of an information frame and requesting retransmission of an information frame. A frame in this format is a monitoring frame (S frame)
Say.

[1307] Next, the unnumbered format is a format of a control field used to perform other data ring control functions, and a frame in this format is called an unnumbered frame (U frame).

[1308] The terminal and the network manage the information frame to be transmitted / received by the transmission sequence number (S) and the reception sequence N (R). Both N (S) and N (R) are composed of 3 bits,
Eight numbers from 0 to 7 are used as the circulation numbers, and the modulus configuration is such that 0 follows 7. Therefore, the modulus in this case is 8, and the number of frames that can be continuously transmitted without receiving a response frame is 7.

[1309] In the data area, 8-bit data indicating the color number data and 8-bit data indicating the frame rate are described. Examples of these are shown in FIGS. Further, it is preferable to describe the distinction between a still image and a moving image in the number of display colors. Further, it is desirable to describe the model name of the mobile phone, the contents of the image data to be transmitted / received (natural image of a person, a menu screen), etc. in the packet of FIG. The model that received the data decodes the data,
When the data is its own (corresponding model number), the display color, frame rate, etc. are automatically changed according to the described contents. In addition, the described contents are displayed in the display area 2 of the display device.
1 may be displayed. User has screen 2
Looking at the description contents (display color, recommended frame rate) of 1,
Operate the keys etc. to manually change to the optimum display state.

[1310] As an example, in FIG. 18B, the numerical value 3 is described as an example of a frame rate of 80 Hz, but the present invention is not limited to this and indicates a certain range such as 40-60 Hz. It may be. Also, the model of the mobile phone may be described in the data area. This is because the performance etc. varies depending on the model and it is necessary to change the frame rate. It is also preferable to describe information such as whether the image is a cartoon or an advertisement (CM). Also, information such as the viewing fee is written in the packet. Information such as the packet length may be described. The user confirms the viewing fee and determines whether to receive the information. It is also preferable to describe data indicating whether the image data has been subjected to error diffusion processing.

[1311] Also, an image processing method (types such as error diffusion processing and dither processing, types of weighting functions and their data,
Information such as the gamma coefficient) and model number may be described in the transmitted format. Also,
Image data such as data taken by CCD, JPEG
Data, its resolution, MPEG data, BIT
Enter information such as MAP data. By decoding or detecting the described data, it becomes possible to automatically change to the optimum state by a mobile phone or the like.

[1312] Of course, it is preferable to describe whether the transmitted image is a moving image or a still image. Further, in the case of a moving image, it is preferable to describe the number of frames per second of the moving image. It is also preferable to describe information such as the number of playback frames / second recommended by the receiving terminal.

The above items are the same when the transmission packet is a transmission. Further, although it is described as a transmission packet in the present specification, it need not be a packet. That is, any data may be used as long as the information described with reference to FIG.

The error diffusion processing controller 141 preferably adds a function of performing error diffusion processing on the data that has been error-processed and sent, returning the data to the original data, and then performing error diffusion processing again. Whether or not the error diffusion process is performed is included in the packet data of FIG. In addition, the data necessary for the inverse error diffusion process such as the error diffusion (including dither etc.) processing method and format are also listed.

The inverse error diffusion process is performed because the error diffusion process can also correct the gamma curve in the process of the process. In some cases, the gamma curve of the EL display device or the like that has received the data and the sent gamma curve do not match. In addition, the transmitted data may be image data that has already undergone processing such as error diffusion.

[1316] In order to deal with this situation, inverse error diffusion processing is performed to convert the original data to eliminate the influence of gamma curve correction. After that, the received EL display device or the like performs the error diffusion process, and the error diffusion process or the like is performed so as to obtain the optimum gamma curve for the reception display panel and the optimum error diffusion process.

If it is desired to switch the frame rate according to the display color, it may be arranged with a user button on a device such as a mobile phone, and the display color or the like can be switched using the button or the like.

FIG. 19 is a plan view of a mobile phone as an example of the information terminal device. An antenna 191, a numeric keypad 192, and the like are attached to the housing 193. Reference numeral 194 is a display color switching key or a power on / off and frame rate switching key.

[1319] FIG. 20 shows an internal circuit block of a mobile phone or the like.
Shown in. The circuit is mainly composed of blocks such as an up converter 205 and a down converter 204, and a block LO buffer 203 of the duplexer 201.

[1320] When the key 194 is pressed once, the display color is changed to the 8-color mode, when the same key 194 is pressed, the display color is changed to the 256-color mode, and when the key 194 is pressed, the display color is changed to the 4096-color mode. May be assembled. The key is a toggle switch whose display color mode changes each time it is pressed. A change key for the display color may be separately provided. In this case, there are three (or more) keys 194.

The key 194 may be a push switch, another mechanical switch such as a slide switch, or may be switched by voice recognition or the like. For example, by voice inputting 4096 colors to the handset, for example, "high quality display", "256 color mode" or "low display color mode" is input to the handset and displayed on the display screen 21 of the display panel. It is configured so that the display color changes. This can be easily realized by adopting the existing voice recognition technology.

[1322] The display color may be switched by an electrically switching switch or a touch panel for selecting by touching a menu displayed on the display unit 21 of the display panel. Alternatively, the switch may be switched depending on the number of times the switch is pressed, or may be switched by rotation or direction like a click ball.

[1323] Although 194 is a display color switching key, it may be a key for switching the frame rate or the like. Also, it may be a key for switching between a moving image and a still image. Also, a plurality of requirements such as a moving image, a still image, and a frame rate may be switched at the same time. Alternatively, the frame rate may be gradually (continuously) changed when the button is held down.
In this case, it can be realized by changing the resistance R of the capacitor C and the resistance R constituting the oscillator to a variable resistance or an electronic volume. The capacitor can be realized by using a trimmer capacitor. Alternatively, it may be realized by forming a plurality of capacitors on a semiconductor chip, selecting one or more capacitors, and connecting them in parallel in a circuit.

[1324] Note that the technical idea of switching the frame rate according to the display color is not limited to the mobile phone, and is applicable to devices having a display screen such as a palmtop computer, a notebook computer, a desktop computer, and a mobile clock. It can be widely applied. Further, it is not limited to the liquid crystal display device (liquid crystal display panel),
It can also be applied to a liquid crystal display panel, an organic EL display panel, a TFT panel, a PLZT panel, and a CRT.

[1325] In FIG. 204, 2043 is a function switch (FSW). The FSW 2043 is arranged at a position where it can be held by the little finger and the ring finger. Also,
The FSWs 2043a and 2043b are arranged on the left and right. This is because it is configured to be held by the little finger and ring finger of the right hand, and held by the little finger and ring finger of the left hand. The ESW may be arranged on the back surface of the housing 193.

[1326] Whether to enable FSW2043 for the right hand,
Whether to enable the FSW 2043 on the left is set by the command so that the user can switch back. In other words, if the user sets to enable the right side on the menu screen,
FSW2043 for the right hand is enabled, FSW2 for the left hand
043 is invalid. On the contrary, if the user sets to enable the left side on the menu screen, the left hand FSW204
3 becomes valid, and the FSW 2043 on the right becomes invalid.

As shown in FIG. 206 (a), the FSW
When 2043 is not pressed, the key 192 is a numeral input key.

As shown in FIG. 206 (b), FSW2043a
When is pressed, the hiragana input mode is entered. At this time,
The top character of "a, ka, sa, ta, na ..." is designated. In this state, first select "A". Next, FSW
When 2043b is also pressed, five characters including the previously pressed character string are input. When a specific key is pressed in this state, characters are input. Therefore, FSW2
By combining 043 and the key 192, Japanese input can be easily realized. Further, as shown in FIG. 206 (d), if only the FSW 2043b is pressed, the English character input mode is set.

[1329] As described above, in addition to the key 192, the FSW
By arranging 2043, a wide variety of characters can be easily input.

Further, an embodiment adopting the EL display panel or the EL display device or the driving method of the present invention will be described with reference to the drawings.

Reference numeral 45 is a cross-sectional view of the viewfinder in the embodiment of the present invention. However, it is schematically drawn for ease of explanation. In addition, there are some areas that are enlarged or reduced, and some areas are omitted. For example,
In FIG. 45, the eyepiece cover is omitted. The above also applies to other drawings.

[1332] The back surface of the body 451 is dark or black. This is an EL display panel (display device) 82.
This is to prevent the stray light emitted from the diffuse reflection on the inner surface of the body 451 from lowering the display contrast. Further, a phase plate (λ / 4 plate or the like), a polarizing plate 51, etc. are arranged on the light emitting side of the display panel. This is also explained in FIG.

A magnifying lens 453 is attached to the eyepiece ring 452. The observer changes the insertion position of the eyepiece ring 452 in the body 451, and adjusts so that the display image on the display panel is in focus.

If a positive lens 454 is arranged on the light emitting side of the display panel as necessary, the principal ray incident on the magnifying lens 453 can be converged. Therefore, the lens diameter of the magnifying lens 453 can be reduced, and the viewfinder can be downsized.

[1335] FIG. 46 is a perspective view of a video camera. The video camera includes a photographing (imaging) lens unit 461 and a video or camera body 462, and the photographing lens unit 461 and the viewfinder unit 466 are back to back. Also,
An eyepiece cover 464 is attached to the viewfinder (see also FIG. 45) 466. An observer (user) observes the image on the display panel through the eyepiece cover 464.

On the other hand, the EL display panel of the present invention is also used as the display monitor 21. Display 21 has fulcrum 4
The angle can be freely adjusted with 68. When the display unit 21 is not used, it is stored in the storage unit 463.

In FIG. 46, reference numeral 465 is a display mode changeover switch. When the switch 465 is pressed, FIG.
The circuit of No. 5 operates, and the matters described in FIG. 35 are carried out.

The EL display device of this embodiment can be applied not only to a video camera but also to an electronic camera as shown in FIG. The display device drop 82 is the camera body 4
Used as a monitor attached to the 72. Camera body 4
In addition to the shutter 471, a switch 465 is attached to 72.

[1339] Further, it is equipped with a touch panel and has an Internet terminal function capable of operating Web browsing, E-mail and the like with a finger or a pen. Further, it is preferable to mount a compact flash card (with error correction function) of 256 Mbytes or more instead of the hard disk device. The capacity can be reduced by adopting only the basic function part of the Windows (registered trademark) OS. Since there is no HDD, you can secure robustness without worrying about disk crashes. Equipped with two PC card slots.
Modem, ISDN, PIAFS, LAN, wireless LAN
It is preferable to configure so that the above can be used. Built-in antenna for wireless LAN. With the USB / RS232C interface, it is also possible to connect peripheral devices for business use such as bar code readers. In addition to a space-saving design without a keyboard, it can withstand water and dust (JIS drip 2
Conform to the grade). Aiming to improve operability assuming BtoBtoC general user usage, such as adoption of a touch panel, "one-touch key" that can easily start applications, and handwritten E-mail function (including handwritten memo function). ing. The above functions and the like are also mounted on another display device, information terminal, and the like of the present invention.

[1340] The display mode changeover switch 465 is preferably attached to a mobile phone or the like. In addition, it is preferable to add a function for switching the function display brightness of the display mode changeover switch described above in a mobile phone or the like. Hereinafter, a method of digitally changing the display brightness will be described.

As described with reference to FIG. 138, etc., one of the driving methods of the present invention is a method in which an N times larger current is passed through the EL element 15 and the EL element 15 is lit only for a period of 1 / M. The brightness can be digitally changed by changing only the M value of 1 / M to be turned on. For example, N =
4, a four times larger current is passed through the EL element 15. If the lighting period is set to 1 / M and M = 1, 2, 3, 4 is switched,
It is possible to switch the brightness from 1 to 4 times. In addition, you may comprise so that M = 1, 1.5, 2, 3, 4, 5, 6, etc. can be changed.

[1342] The above switching operation displays the display screen 21 very brightly when the power of the mobile phone is turned on,
It is used in a configuration in which the display brightness is lowered in order to save power after a certain time has elapsed. It can also be used as a function of setting the brightness desired by the user. For example, when outdoors, the screen is made very bright. This is because when you are outdoors, the surrounding area is bright and you cannot see the screen at all. However, if the display is continued at high brightness, the EL element 15 deteriorates rapidly. Therefore, when it is made extremely bright, it is configured to restore the normal brightness in a short time. Furthermore, when displaying with high brightness, the user can press the button to increase the display brightness.

[1343] Therefore, it is preferable that the user can switch the button, automatically change the setting mode, or detect the brightness of external light and automatically switch the setting. . In addition, it is preferable that the display brightness can be set to 50%, 60%, and 80% by the user or the like.

[1344] Further, it is preferable that the display screen is a Gaussian distribution display. The Gaussian distribution display is a method in which the brightness of the central part is bright and the peripheral part is relatively dark. Visually, if the central part is bright, it is perceived as bright even if the peripheral part is dark. According to the subjective evaluation, if the peripheral part maintains a luminance of 70% as compared with the central part, it is visually comparable. There is almost no problem even if the luminance is further reduced to 50%.
In the self-emission type display panel of the present invention, the N
Double pulse drive (N times current is passed through EL element 15 and 1F
A Gaussian distribution is generated from the top to the bottom of the screen by using a method of lighting only for 1 / M period).

[1345] Specifically, the value of M is increased in the upper and lower parts of the screen, and the value of M is decreased in the central part. This is realized by modulating the operation speed of the shift register of the gate driver 12. The brightness modulation on the left and right of the screen is generated by multiplying the table data and the video data. By the above operation, when the peripheral brightness (angle of view 0.9) is set to 50%, it is possible to reduce the power consumption by about 20% as compared with the case of 100% brightness. When the peripheral brightness (angle of view 0.9) is 70%, it is possible to reduce the power consumption by about 15% as compared with the case of 100% brightness.

[1346] It is preferable to provide a changeover switch or the like so that the Gaussian distribution display can be turned on and off. This is because, for example, when a Gaussian display is made outdoors, the periphery of the screen becomes completely invisible. Therefore, it is preferable that the user can switch with a button, can be automatically changed in the setting mode, or can be automatically switched by detecting the brightness of external light. Further, it is preferable that the peripheral brightness can be set to 50%, 60%, 80% by the user or the like.

[1347] In a liquid crystal display panel, a fixed Gaussian distribution is generated by the backlight. Therefore, the Gaussian distribution cannot be turned on / off. The fact that the Gaussian distribution can be turned on and off is an effect peculiar to self-luminous display devices.

[1348] Also, when the frame rate is predetermined, flicker may occur due to interference with the lighting state of a fluorescent lamp or the like in the room. In other words, when the fluorescent lamp is lit with an alternating current of 60 Hz, the EL display element 15 has a frame rate of 60 Hz.
When you are operating in, slight interference may occur and you may feel that the screen is blinking slowly. To avoid this, change the frame rate. The present invention adds a frame rate changing function. Further, in N-fold pulse driving (a method in which a N-fold current is passed through the EL element 15 to turn on for 1 / M of 1F), the value of N or M can be changed.

[1349] Needless to say, the above items are not limited to mobile phones, but can be applied to televisions, monitors and the like. In addition, it is preferable to display icons on the display screen so that the user can immediately recognize the display state. The above items also apply to the following items.

[1350] Further, it is preferable to install an "automatic screen adjustment" function for automatically adjusting the clock phase and screen position (horizontal / vertical) and an "auto gain control function" for automatically adjusting black level / contrast.
Adjust the black level contrast to an appropriate value,
It is possible to realize optimal gradation display for each of the RGB colors. Furthermore, it is preferable to have a function of suppressing bleeding that occurs when the VGA mode or the like is reduced or enlarged and displayed. Also, it is preferable to install a "power save mode" in which the backlight automatically turns off when not used for a certain period of time. Further, by using N times pulse driving (a method in which an N times current is passed through the EL element 15 and is turned on for a period of 1 / M of 1F), the value of M is considerably increased and the image is displayed so that the image can be slightly recognized. The brightness may be reduced.
The above matters also apply to the other inventions.

[1351] The above is a case where the display area of the display panel 82 is relatively small, but the display screen 21 is easily bent when the display area is large such as 30 inches or more. As a countermeasure, in the present invention, an outer frame 481 is attached to the display panel 82 as shown in FIG. 48, and a fixing member 482 is mounted so that the outer frame 481 can be hung.
It is attached in. Using this fixing member 482, FIG.
As shown in FIG.
To be installed.

[1352] However, the larger the screen size of the display panel 82, the heavier the weight becomes. Therefore, the display panel 8
The leg mounting portion 484 is arranged on the lower side of
3 allows the weight of the display panel 82 to be held.

[1353] The leg 483 is movable left and right as shown in A, and the leg 483 is retractable as shown in B. Therefore, the display device can be easily installed even in a narrow place.

A plastic film-metal plate composite material (hereinafter referred to as a composite material) is used for the leg 483 or the housing (also in the present invention). The composite material is obtained by strongly adhering a metal and a plastic film via a special surface treatment layer (adhesive layer). The metal plate is preferably 0.2 mm or more and 0.8 mm or less, and the plastic film laminated on the metal plate via the special surface treatment layer has a thickness of 15 μm.
It is preferable that the thickness is not less than m and not more than 100 μm. The special adhesion method provides a strong adhesion between the plastic and the metal plate. By using this composite material, it is possible to color, dye, and print the plastic layer.
It is possible to eliminate the secondary processing steps (hand-attaching the film, plating coating) on the pressed parts. It is also suitable for deep drawing and DI molding, which has been impossible in the past.

[1355] In the television shown in Fig. 48, the surface of the screen is covered with a protective film (or a protective plate) 493. This is one purpose to prevent the surface 21 of the display panel 82 from being hit and damaged. An AIR coat is formed on the surface of the protective film 493, and the surface is embossed to prevent external conditions (external light) from being reflected on the liquid crystal display panel 21.

[1356] By spraying beads or the like between the protective film 493 and the display panel 82, a certain space is arranged. Also, a protective film 493
A fine convex portion is formed on the back surface of the display panel 8 with this convex portion.
A space is maintained between the 2 and the protective film 493. By holding the space in this manner, it is possible to prevent the impact from the protective film 493 from being transmitted to the display panel 82.

[1357] Further, the protective film 493 and the display panel 8
It is also effective to dispose or inject an optical binder such as alcohol or ethylene glycol in a liquid or gel acrylic resin or a solid resin such as epoxy between the two. This is because interface reflection can be prevented and the optical coupling agent functions as a buffer material.

Examples of the protective film 493 include polycarbonate film (plate), polypropylene film (plate), acrylic film (plate), polyester film (plate), PVA film (plate) and the like. It goes without saying that other engineering resin films (ABS, etc.) can be used. It may also be made of an inorganic material such as tempered glass. Instead of disposing the protective film 493, the surface of the display panel 82 is made of epoxy resin, phenol resin, or acrylic resin to be 0.5 m.
Coating with a thickness of not less than m and not more than 2.0 mm has the same effect. It is also effective to emboss the surface of these resins.

It is also effective to coat the surface of the protective film 493 or the coating material with fluorine. This is because stains on the surface can be easily wiped off with a detergent or the like. In addition, the protective film may be formed thick to serve also as the front light.

[1360] The screen is not limited to 4: 3,
A wide display may be used. Resolution is 1280x
It is preferably 768 dots or more. Wide type
By doing so, landscape display of DVD movies, TV broadcasts, etc.
You can enjoy full titles and shows of
It The brightness of the display panel 82 is 300 cd / m²(Kan
(Dela / square meter) is preferable. Even better
More preferably, the brightness of the display panel is 500 cd / m²(Mosquito
Ndella / square meter) is preferred. Also,
Brightness suitable for the Internet and normal PC work
(200 cd / m ²) Switch to display
Is installed.

Therefore, the user can set the brightness of the screen to the optimum depending on the display content or the usage method. Furthermore, only the window displaying the video is 500
in the cd / m ^2, the other parts are also available settings to 200cd / m ^2. It is flexible enough to display TV programs in the corner of the display and check mail. The speaker has a tower shape and is designed to spread the sound not only in the front direction but also in the entire space.

[1362] TV program playback and recording functions are also easier to use. It makes it easy to schedule recordings from i-mode. Conventionally, it was necessary to make a reservation after checking the time and channel on a TV program guide such as a newspaper, but it is possible to make a reservation by checking the electronic program guide in i-mode. This way, you don't have to worry about not knowing the broadcast time. Also,
It also allows short playback of recorded programs. While judging the importance of the presence or absence of telops and voices in news programs and the like, you can skip the parts that you have decided to be unnecessary and see the outline of the program in a short time (1 to 10 minutes for a 30-minute program).

[1363] A hard disk having a disk capacity of 40 GB or more is loaded so that television recording can be performed. In addition to the main body, it is composed of an expansion box that combines the power supply and video input / output terminals. In addition to a personal computer and TV, two types of video equipment can be connected to the expansion box used to connect AV equipment such as video. In addition to the D1 terminal for the BS digital tuner, the video input also has an S terminal input, which can be selected according to the connected device. The terminals for AV are arranged on the front for convenient connection with game consoles.

[1364] In addition, the display screen shows forward bending of 30 degrees or more and backward bending of 1 degree.
90 degrees / 180/270 by setting it to 20 degrees or more
By being configured so that it can be rotated once, it can be installed freely according to the operating environment. For example, the browser screen can be displayed vertically by rotating it 90 degrees. In addition, the screen can be displayed toward the person who sits face-to-face by bending backward by 145 degrees.

[1365] The above protective film 493, housing, configuration,
It goes without saying that matters relating to characteristics and functions are applied to other display devices or information display devices of the present invention.

[1366] In FIG. 69 and the like, one terminal of the capacitor 19 is connected to the Vdd power supply, but the present invention is not limited to this. For example, as shown in FIG.
One terminal may be connected to the gate signal line 17a at the previous stage. The gate signal line 17a in the previous stage (the pixel row immediately before) is 1
The potential is changed before being selected before H, and thereafter, the potential is fixed until it is selected in the next 1F (until the next selection). That is, the gate signal line 17a1 at the previous stage is fixed at the off potential (Vgh). Therefore, it can be used as one electrode of the capacitor 19. Such a configuration in which the gate signal line in the preceding stage is used as the electrode of the capacitor is called a preceding stage configuration.

In FIG. 119, the gate signal line 17a is used as an electrode, but the present invention is not limited to this, and another gate signal line may be used. Further, the technical idea of the former stage configuration is a method of using a fixed potential of a pixel which is not selected. Therefore, in some cases, the gate potential of the latter stage can be used (for example, gate signal line 17b, reverse bias potential Vm, etc.). It goes without saying that the above items can be applied to other pixel configurations.

[1368] Similar items can be applied to the pixel configuration of the voltage program of FIG. As the first stage configuration,
The configuration of FIG. 120 is exemplified. That is, the capacitor 19
One of the potentials is the potential of the gate signal line 17a1. In addition, the pre-stage configuration of FIG. 103 is shown in FIG. 121. By adopting the former-stage configuration as described above, the number of power supply lines formed in the pixel can be reduced. Therefore, high aperture ratio can also be realized.

[1369] As described above, the TFT 11 of FIG.
e, TFT 11e of FIG. 68, TFT 11d of FIG. 69, TFT 11d of FIG. 70, TFT 11e of FIG. 71, TFT 11b of FIG. 72, TFT 11d of FIG. 73, TFT of FIG. 75.
11d, TFT 11e in FIG. 76, TFT 11 in FIG.
d, the TFT 11d in FIG. 78, the TFT 11d in FIG. 82, the TFT 11e in FIG. 83, and the like by controlling the on / off state, and FIGS. 31, 32, 39, 50, 61,
It goes without saying that the driving method or display method or device described with reference to FIGS. 62, 63, 64, 65, 66, 85 and the like can be implemented.

[1370] Also, the switching TFT 11 shown in FIG.
It is preferable that b, 11c and the like are formed by n channels. This is because the penetration voltage to the capacitor 19 is reduced. Further, since the off-leakage of the condenser 19 is also reduced, it can be applied to a low frame rate of 10 Hz or less.

Also, depending on the pixel configuration, when the punch-through voltage acts in the direction of increasing the current flowing through the EL element 15, the white peak current increases and the contrast feeling of image display increases. Therefore, good image display can be realized.

[1372] Conversely, the switching TFT 11b of FIG.
It is also effective to use P channel as the channel 11c to generate more punch-through and improve black display. P
When the channel TFT 11b is turned off, the voltage becomes Vgh voltage. Therefore, the terminal voltage of the capacitor 19 is Vdd
Shift a little to the side. Therefore, the gate terminal voltage of the TFT 11a rises, resulting in a more black display. In addition, since the current value for the first gradation display can be increased (a constant base current can be flown up to gradation 1), the shortage of the write current can be reduced by the current program method.

[1373] In addition, the gate signal line 17a and the TFT 11
A configuration in which a capacitor is positively formed between the gate terminals of a to increase the penetration voltage is also effective (see FIG. 171). The capacity of this capacitor is preferably 1/50 or more and 1/10 or less of the capacity of the capacitor 19. Furthermore, it is preferable to set it to 1/40 or more and 1/15 or less.
Alternatively, the capacitance is set to be 1 to 10 times the source-gate (SG or gate-drain (GD)) capacitance of the TFT 11b. More preferably, it is preferably 2 times or more and 6 times or less the SG capacity. The capacitor may be formed or arranged between one terminal of the capacitor 19 (the gate terminal of the TFT 11a) and the source terminal of the TFT 11d (see FIG. 172). Also in this case, the capacity and the like are the same as the values described above.

The capacity of the capacitor 19b for generating punch-through voltage (capacitance is Cb (pF)) is the capacity of the capacitor 19a for charge retention (capacitance and Ca (pF)).
Then, the gate terminal voltage Vw of the TFT 11a at the time of the white peak current (at the time of the white raster of the display maximum brightness in the image display) is made to flow the current in the black display (the current is basically 0. That is,
Gate terminal voltage V when the image display is black)
b is relevant. These relationships are as follows: Ca / (200Cb) ≤ | Vw-Vb | ≤ Ca
It is preferable to satisfy the condition of / (8Cb). Note that | Vw-V
b | is the absolute value of the difference between the terminal voltage of the driving TFT when displaying white and the terminal voltage when displaying black (that is, the varying voltage width).

[1375] More preferably, Ca / (100Cb) ≤ | Vw-Vb | ≤ Ca
It is preferable to satisfy the condition of / (10Cb).

[1376] The TFT 11b is a P channel, and the P
The channel should be at least a double gate. This is preferably triple gate or higher. More preferably, the number of gates is 4 or more. Then, the source-gate (SG or gate-drain (GD)) of the TFT 11b.
1 times or more of the capacity (the capacity when the TFT is on) 1
It is preferable to form or arrange 0 times or less capacitors in parallel.

The above matters are valid not only in the pixel configuration of FIG. 1 but also in other pixel configurations. For example, in Figure 2.
In the pixel configuration of the current mirror of FIGS. 1, 43, 71, and 22, a capacitor that causes punch-through is arranged or formed between the gate signal line 17a or 17b and the gate terminal of the TFT 11a (see FIGS. 173 and 174). . The n channel of the switching TFT 11c is a double gate or more. Or switching TFT11
c and 11d are p channels, and triple gates or more. In the configuration of the voltage program of FIG. 68, the capacitor 19c for generating the punch-through voltage is formed or arranged between the gate signal line 17c and the gate terminal of the driving TFT 11a (see FIG. 221). In addition, switching TFT
11c is a triple gate or more. The capacitor 19c for generating the punch-through voltage may be arranged between the drain terminal of the TFT 11c (on the side of the capacitor 19b) and the gate signal line 17a. The capacitor 19c for generating the punch-through voltage is connected to the gate terminal of the TFT 11a and the gate signal line 1
It may be arranged between 7a. Further, the capacitor 19c for generating the punch-through voltage may be arranged between the drain terminal (the capacitor 19b side) of the TFT 11c and the gate signal line 17c.

[1379] Also, the capacitance of the charge holding capacitor (19 in FIGS. 1, 21, 43, 71) is Ca, and the switching TFT (11b in FIG. 1, FIG. 21, FIG. 4).
3, the source-gate capacitance Cc (11c or 11d in FIG. 71) (a value obtained by adding the capacitance when there is a capacitor for punch-through), and the high voltage signal (Vgh) applied to the gate signal line, When a low voltage signal (Vgl) applied to the gate signal line is used, good black display can be realized by configuring the following conditions.

[1379] 0.05 (V) ≤ (Vgh-Vgl)
X (Cc / Ca) ≤ 0.8 (V) More preferably, the following conditions are satisfied.

[1380] 0.1 (V) ≤ (Vgh-Vgl) x
(Cc / Ca) ≤ 0.5 (V) The above items are also effective for the pixel configurations of FIGS. 54, 57, 67, 103, and the like. For example, in the voltage-programmed pixel configuration of FIG. 57, a capacitor 19b for generating punch-through voltage is formed or arranged between the gate terminal of the TFT 11a and the gate signal line 17a.

The capacitor 19b for generating the punch-through voltage is formed by the source wiring and the gate wiring of the TFT. However, since the source width of the TFT 11 is widened and overlapped with the gate signal line 17, the TFT 11 may not be clearly separated from the TFT in practical use.

[1382] Also, the switching TFTs 11b and 11c
By forming (in the case of the configuration of FIG. 1) larger than necessary, the capacitor 19b for the punch-through voltage is apparently formed.
The method of constructing is also within the scope of the present invention. Switching T
Channel width W / channel length L for FT11b and 11c
= 6/6 μm in many cases. Increasing this to W also constitutes the capacitor 19b for punch-through voltage. For example, the ratio of W: L is 2: 1 or more and 20:
A configuration in which the number is 1 or less is exemplified. Preferably, the W: L ratio is 3: 1 or more and 10: 1 or less.

[1383] Further, the capacitor 19b for punch-through voltage
It is preferable to change the size (capacitance) of R, G, and B modulated by the pixel (see FIG. 233). R,
This is because the drive currents of the G and B EL elements 15 are different. This is also because the cutoff voltage of the EL element 15 is different. Therefore, the driving TFT 11a of the EL element 15
This is because the voltage (current) to be programmed in the gate terminal of is different. For example, when the capacitor 11bR of the R pixel is 0.02 pF, the capacitors 11bG and 11bB of the other colors (pixels of G and B) are 0.025 pF.
Further, when the capacitor 11bR of the R pixel is 0.02pF, the capacitor 11bG of the G pixel is 0.03p.
F, and the capacitor 11bB of the B pixel is 0.025p
F and so on. In this way, by changing the capacitance of the capacitor 11b for each of the R, G, and B pixels, the offset drive current can be adjusted for each RGB. Therefore, the black display level of each RGB can be set to the optimum value.

In the above description, the capacity of the capacitor 19b for generating the punch-through voltage is changed. However, in the configuration shown in FIG. 233, the punch-through voltage is maintained by the capacitor 19a for holding.
And the capacity of the capacitor 19b for generating the punch-through voltage is relative. Therefore, the capacitor 19b is not limited to being changed for the R, G, and B pixels. That is, the capacitance of the holding capacitor 19a may be changed. For example, when the capacitor 11aR for the R pixel is 1.0 pF, the capacitor 11aG for the G pixel is
And 1.2 pF, and the capacitor 11aB of the B pixel is set to 0.9 pF. At this time, the capacitance of the punch-through capacitor 19b has a common value for R, G, and B.
Therefore, according to the present invention, the capacitance ratio between the holding capacitor 19a and the punch-through voltage generating capacitor 19b is
At least one of the R, G, and B pixels is different from the others. Note that both the capacitance of the holding capacitor 19a and the capacitance of the punch-through voltage generating capacitor 19b may be changed for the R, G, and B pixels.

[1385] Also, the capacitance of the capacitor 19b for punch-through voltage may be changed between the left and right of the screen 21 (Fig. 234).
checking). The pixel 16 a is located near the gate driver 12. In other words, since the pixel 16a is arranged on the signal supply side, the gate signal rises quickly (since the slew rate is high. See the waveform 2341a), so that the punch-through voltage becomes large. Since the pixel 16b is arranged (formed) at the end of the gate signal line 17, the signal waveform is dull (because the gate signal line 17 has a capacity. See the waveform 2341b). This is because the gate signal rises slowly (the slew rate is slow), and the punch-through voltage becomes small. Therefore, the punch-through voltage capacitor 19b of the pixel 16a near the side connected to the gate driver 12 is made small. Further, the end of the gate signal line 17 enlarges the capacitor 19b. For example, the capacitance of the capacitor is changed on the left and right of the screen by about 10%.

As described with reference to FIG. 233, the punch-through voltage generated is determined by the capacitance ratio of the holding capacitor 19a and the punch-through voltage generating capacitor 19b. Therefore, in FIG. 234, the size of the capacitor 19b for generating the punch-through voltage is changed on the left and right of the screen, but the present invention is not limited to this. The punch-through voltage generating capacitor 19b may be constant on the left and right sides of the screen, and the capacitance of the charge holding capacitor 19a may be changed on the left and right sides of the screen.
It goes without saying that both the capacitor 19b for generating the punch-through voltage and the capacitance of the capacitor 19a for holding the charge may be changed on the left and right of the screen.

[1387] In FIG. 234, the capacitance of the capacitors 19a or 19b is changed on the left and right of the screen 21, but when the driver circuit 12 and the like are arranged on the left and right of the screen 21 (for example, power supply from both sides), The capacitors 19a and 19b on the left and right of 21 may have the same capacitance.
However, this time, the signal waveform at the center of the screen may be dull compared to the signal waveforms on the left and right of the screen. Therefore, in this case, the capacitor 19 for generating the punch-through voltage is generated.
b is constant on the left and right of the screen, and a capacitor 1 for holding electric charge
9a and the capacitor 19a for punch-through voltage are the same on the left and right sides of the screen 21, and the capacitor 1 for holding charge is
At least one of the capacitance 9a and the capacity of the capacitor 19a for punch-through voltage is changed at the end and the center of the screen 21.

In FIG. 234, the punch-through voltage or the like may be different even at the same position from the formation position of the gate driver 12 as in the pixel 16a and the pixel 16c. For example, from the relationship of the power supply position or voltage drop of the gate driver 12 and the signal supply position relationship from the source driver 14. Therefore, pixel 16 of FIG.
c makes at least one of the capacitance of the capacitor 19b for generating the punch-through voltage and the capacitance of the capacitor 19a for holding the charge different for the pixel 16a. The same applies to the pixel 16d.

As described above, according to the present invention, at least one of the capacity of the capacitor 19b for generating the punch-through voltage and the capacity of the capacitor 19a for holding the charge is displayed on the display screen 21.
There are parts that have been changed from other parts within.

The configuration for forming (arranging) the capacitor 11b of the present invention as shown in FIGS. 171 and 172 is as follows. In other words, the switching TFT turns on, then
Turn off. At this time, it acts on the capacitor 11a, etc.
TFT 11 for driving the L element 15 (TFT 11a in FIG. 1)
By changing the gate terminal of the above, the configuration is such that the current of the TFT 11 does not flow. That is, FIG. 171, FIG. 172, etc. are for the p channel. It can be applied even in the case of n channels as shown in FIG. Vg for n-channel
The TFT is turned on at h, and the TFT is turned off at Vgl. Therefore, when the n-channel TFT 11b (11c) is turned on (a pixel row is selected) and turned off (the next pixel row is selected), the driving TFT 11a acts in a direction in which no current flows. do it. Therefore, the present invention provides that when the selected TFT is turned off, the EL
The element 15 is configured to operate in a direction in which no current flows.

It will be easier to understand if explained with reference to FIG. 228. First, the source driver circuit 14
A current Iw as image data is drawn in from the source signal line 18. It should be noted that here, for ease of explanation, it is assumed that the source driver circuit 14 operates in a direction in which the program current Iw is absorbed and is programmed in each pixel 16. The operation will be described below with reference to FIGS. 228 and 229. In addition, the description will be given assuming that the pixel row is (1).

As shown in FIG. 228 (a), an on-voltage (Vgl) is applied to the gate signal line 17a (1),
A pixel is selected. At this time, the gate signal line 17b (1)
Is applied with an off voltage (Vgh). Therefore, the switching TFTs 11b and 11c are turned on,
11d is in the off state.

[1395] The source signal line 18 has a program current Iw.
Flows. The program current Iw is supplied by the TFT 11a (current Idd = Iw). This current Id
When d flows, the potential of the source signal line 18 becomes a predetermined voltage, and the gate terminal voltage Vg of the TFT 11a is current-programmed. Current Programmed current is Iw
It is an electric current. That is, the TFT 11a has the program current I
The Vg voltage is set so that w flows. In other words, it can be said that the potential of the source signal line is programmed in the pixel. In other words, it can be said that the operating state of the pixel is that the voltage is programmed.

After 1H (one horizontal scanning period), the off voltage (Vgh) is applied to the gate signal line 17a (1), and TF is applied.
The T11b and the TFT 11c are turned off, and the voltage required to flow the program current Iw in the capacitor 11a is held. Further, the gate signal line 17b (1) has an on-voltage (Vg
l) is applied and the TFT 11d is turned on. Therefore, an Ie (= Iw) current flows through the EL element 15, and the EL element 15 is turned on with the programmed current (Ie) (see FIG. 228 (b)).

[1395] The above is the operation of the current program method described above. However, the present invention differs from the above operation. This is because the current Ie flowing through the EL element 15 is smaller than Iw. The reason for this is that Vg in FIG.
It can be seen by looking at the change in (gate terminal voltage of the TFT 11a).

For ease of understanding, the operation of the P channel of the TFT will be described. P-channel TFT
A larger on-current flows as the gate terminal voltage Vg is on the negative side. It completely turns off at 0 (V). The on-current differs depending on the W / L, mobility, and S value of the TFT. When the W / L of the TFT is 6/12, about -3
Up to (V), the channel current (Idd) is very small. A current of 1 to 5 μA flows at −4 (V) to −4.5 (V).

[1395] FIG. 229 shows a case where the TFT 11a of the pixel (1) is programmed with a current for displaying almost black. First, it is assumed that Vw (white display or the like) is held as the Vg voltage of the pixel (1). When the pixel (1) is selected, the gate signal line 17a (1) changes from Vgh to Vgl, so that the capacitor 19b allows the potential of the gate signal line 17a to penetrate. Vg due to this penetration
The voltage becomes V0.

Next, the TFT 11a passes a current equal to the current Iw absorbed by the source driver circuit 14. But,
In the case of black display, the value of the current passed through the TFT 11a is small.
As an example, it is 30 nA or less. With such a current,
The parasitic capacitance of the source signal line 18 cannot be sufficiently charged / discharged within 1H period. Therefore, the source signal line 18
It is not possible to set the potential of 1 to a predetermined voltage within 1H period.
That is, the Vg voltage is also low, and the originally required voltage Vb cannot be obtained, and becomes the Vc voltage.

Since the Vc voltage is lower than the Vb voltage, T
The FT 11a passes a current larger than that in black display in the EL element 15. Therefore, the EL element 15 emits light brighter than the desired value. Therefore, in the EL display panel, black floating occurs and high contrast display cannot be realized.

However, the operation of the present invention is different from the above operation. This is because the gate signal line 17a (1) changes from the on-voltage (vgl) to the off-voltage (Vgh), so that the punch-through voltage is generated again by the capacitor 19b. Due to this penetration voltage, the Vg voltage is originally
Shift to the required Vb voltage. Therefore, the TFT
11a is programmed to pass no current, or is programmed to pass a desired value of black current. That is, the EL element 15 is programmed so that only a minute current flows. Therefore, the EL display panel of the present invention is free from blackening, and high contrast display can be realized. This Vb voltage is held in one field (one frame), that is, until the pixel is next selected and rewritten.

The present invention makes good use of the penetration voltage,
A good black display is realized. When the corresponding pixel row is selected and the ON voltage is applied to the gate signal line 17a, the V0 voltage penetrates as shown in FIG. 229 and the Vg voltage shifts further toward white display. However, this penetrating voltage is charged in a short time by the voltage from the source signal line 18. In particular, since the gate terminal voltage of the TFT 11a tends to decrease, the TFT 11a
Is more likely to flow current, and is charged in a short time. Therefore, the penetration of the V0 voltage does not pose any problem.

[1402] As the gate terminal voltage Vg of the TFT 11a approaches the target value Vb voltage, the TFT 11a is in the direction in which no current flows. Therefore, the target terminal voltage Vb
It does not reach easily. In particular, the influence becomes more remarkable as the programmed current approaches the black display current.
In FIG. 229, the voltage is not the Vb voltage but the Vc voltage even at the end of the selection period of 1H.

[1403] After the period of 1H, when the corresponding pixel row is unselected and an off voltage is applied to the gate signal line 17a, Vg is applied to the gate signal line 17a as illustrated in FIG. 229.
The h voltage is applied and a punch-through voltage is generated. Due to this punch-through voltage, the gate terminal voltage of the TFT 11a reaches the target Vb voltage.

As described above, according to the present invention, the gate signal line 17
The voltage fluctuation of a is caused by the TFT 11a via the capacitor 11b.
The current supplied to the EL element 15 is controlled.
This control is particularly effective for realizing black display.

[1405] In the above description, the driving TFT 11 is driven by the punch-through voltage of the gate signal line 17a of the selected pixel row.
It controlled a. However, the present invention is not limited to this. For example, as shown in FIG. 230, the punch-through of the gate signal line 17a of the adjacent pixel row may be used.

As described with reference to FIG. 140, this is a method of simultaneously selecting a plurality of pixel rows and shifting the selected pixel rows by one pixel row. The voltage waveform of the applied gate signal line 17 is shown in FIG.

[1407] FIG. 230 shows the gate signal line 1 of the next pixel row.
One terminal of the capacitor 19b is attached to 7a in FIG.
Connected as described in. Further, as shown in FIG. 179, the gate signal line 17b is shared by a plurality of pixel rows (short-circuited at the lighting control line 1791). Also, FIG. 131 and FIG.
As described with reference to 97, the three-side free configuration in which the gate driver IC 12 is arranged on one side of the display screen 21 is adopted.

[1408] In order to reduce the influence of kink variation of the TFT 11a of FIG. 1 and the TFT 11b of FIGS. 21, 43, and 71, it is preferable to fix the potential of the substrate on which the TFT 11 is formed. For example, the TFT may be formed on a metal substrate such as a silicon substrate. Also, T on the glass substrate
Even when the FT is formed, a thin potential stabilizing layer is formed of a metal or the like on the substrate, and the TFT 11 and the like are formed thereon.
Further, one terminal of an element such as a TFT may be grounded on this potential stabilizing layer. As described above, by fixing the potential of the substrate, it is possible to significantly reduce kink variations. In particular,
In the case of a structure in which light is taken out upward, it is not necessary to make the substrate transparent, so that the above structure can be easily adopted.

As can be understood from FIG. 231, the gate signal line 17a of the adjacent pixel row becomes Vgh with a delay of 1H from the gate signal line 17a of the pixel row of interest. Therefore, the punch-through voltage is applied with a delay of 1H. Other operations are the same as the operations described with reference to FIGS. 228 and 229, and therefore description thereof will be omitted.

[1410] FIGS. 228 and 229 show the driving TFT 11a.
Was for the P channel. When the driving TFT 11a has N channels, the driving waveform is as shown in FIG. n
In the case of a channel, the switching TFT 11b and the like are turned on by applying the Vgh voltage, and turned off by applying the Vgl voltage. Therefore, as can be seen from the Vg waveform in FIG. 232, the punch-through voltage occurs when the voltage applied to the gate signal line 17a changes from Vgl to Vgh and from Vgh to Vgl. When a pixel row is selected and not selected, Vg
The voltage is lower. Therefore, the driving TFT1
228 and FIG.
As described in 29, good black display can be realized.

[1411] Note that FIG. 210 is the one in which the P channel and the N channel of the TFT of FIG. 1 are changed. Therefore, the operation is the same as that in FIGS. Since the change of the P channel and the N channel is the same in FIGS. 21, 43, 71, etc., the concept of the capacitor 19b for punch-through voltage of the present invention can be applied to other pixel configurations as it is. .

[1412] Also, the driving TFT 11 (TFT in FIG.
11a, the TFT 11b in FIG. 21) has better control by the punch-through voltage in the N channel than in the P channel in many cases. The reason for this will be described below.

FIG. 270 (a) shows the current output when the drain voltage (D) is set sufficiently lower than the source voltage (S) (saturation region). The horizontal axis represents the gate (G) voltage with respect to the source (S) voltage. When the gate voltage is set to the negative side, a current flows between the source (S) and the drain (D). The vertical axis represents the current between the source (S) and the drain (D).

[1414] Generally, in the TFT formed by the low temperature polysilicon technique, a current flows when the voltage is lower than V0 voltage. The V0 voltage is 3 to 4 (V). In general, the P-channel TFT has a voltage (V0) from which the current starts to flow from 1 to 1.
1 to 10 μA at 1.5 (V) (for example, W / L = 6 /
A current of 9 μm) flows. This voltage width is Vc (V).

[1415] Therefore, in the case of the P channel, when black is displayed, a current starts to flow at the gate (G) voltage V0, and a current of 1 to 10 μA flows at the gate (G) voltage V0 + Vc. FIG. 270 (c) is obtained by extracting the main part of FIG. 1 and writing it in an equivalent circuit diagram. The capacity of the holding capacitor 19a is Ca, the capacity of the punch-through voltage generating capacitor 19b and Cb, and the channel capacity of the TFT 11b are Ct. In addition, the capacity obtained by adding Cb and Ct is C
Let be c. The gate voltage of the TFT 11a is Vg.

[1416] The voltage applied to the gate signal line 17a is
The voltage is divided into Ca and Cc and applied to the gate terminal of the TFT 11a. For example, if Ca: Cc = 3: 2 and the voltage of the gate signal line changes by 10 (V), this voltage is divided into 3: 2 and applied as Vg to the gate terminal. That is, if Vdd = 0 (V), Vg = -4 (V) when the potential of the gate signal line 17a changes from 0 (V) to -10 (V).

The same applies when a predetermined voltage is applied to Vg in advance. The change in voltage applied to the gate signal line 17a is divided into Ca and Cc capacitances and applied. However, the punch-through voltage is due to the change in the potential of the gate signal line 17. Further, Ca and Cc are fixed values.
Therefore, the change in potential is constant because it is determined by Vgh and Vgl. For example, the punch-through voltage is a constant value such as 0.1 (V) regardless of the image display state.

The Vg voltage changes depending on the image. For example, in black display, the Vg voltage is -3 (V). It is -4 (V) in white display (see the solid line a in FIG. 270 (a)). However, the penetration voltage is, for example, 0.1
It is a fixed value such as (V). Therefore, the penetration voltage is 0.1 (V) with respect to Vg = 3 (V) for black display,
Penetration voltage 0.1 against Vg = 4 (V) displayed in white
The contribution is different from (V). That is, the ratio of the punch-through voltage to the black display is higher than that of the white display. Therefore, the effect of the punch-through voltage is large in black display and small in white display.

This operation contributes to the better display of the EL display panel. That is, if the penetration voltage is high in black display, the program current flowing through the source signal line 18 is high in black display. Therefore, the write shortage is resolved. It is better that the effect of punch-through voltage is small in white display.

When the driving TFT 11 is a P channel, the V0 voltage for displaying black is -3 (V) or less, which is a relatively large absolute value. At least a voltage V0 that generates a current (approximately 2 to 50 nA) to flow at the gray level 1 (first gray level) for black display and a current Ii (μ for flowing at the maximum gray level for white display)
The relationship with the voltage V0 + Vc for generating A) preferably satisfies the following equation.

[1421] 1/2 ≤ | (Vc + V0) / V0 | ≤
3 More preferably, it is preferable to satisfy 1 ≦ | (Vc + V0) / V0 | ≦ 2. This is because the effect of the punch-through voltage is remarkable in the black display, good black display can be realized, and the effect of the punch-through voltage in the white display is reduced.

[1422] Also, in FIG. 270 (a), the conventional V
The size of c may be relatively large as compared with V0. That is, the S value is reduced. Also, reduce mobility.

[1432] For the P channel of FIG. 270 (a),
It is preferable to shift the V0 voltage to the 0 potential side as shown by the dotted line b. This shift can be realized by changing the doping amount in the semiconductor layer of the P-channel TFT. The above items also apply to the N channel shown in FIG. 270 (b).

When manufacturing the array, the TFTs constituting the gate driver circuit 12 and the like may be doped in the same manner as in the conventional case, and the doping amount of the TFT 11a of the pixel may be changed. This can be formed by using a mask during doping. In addition, the TFTs forming the gate driver circuit 12 and the like are composed of only N channels, and the TFTs 11a of the pixels are composed of P channels. Conversely, the T of the pixel
When the FT 11a is an N channel, the TFTs and the like forming the gate driver circuit 12 and the like are P channels. The above items can also be applied to the following items.

FIG. 270 shows the current output when the source voltage (S) and the drain voltage (D) of the N-channel TFT are set sufficiently high (saturation region). The horizontal axis represents the gate (G) voltage with respect to the source (S) voltage. When the gate voltage is set to the positive side, a current flows between the source (S) and the drain (D). The vertical axis represents the source (S) -drain (D) current Ii.

[1426] Generally, an N-channel TFT formed by the low temperature polysilicon technique causes a current to flow when the voltage is higher than V0 voltage. The V0 voltage is 1 to 2 (V). Further, generally, in the N-channel TFT, a current of 1 to 10 μA (for example, W / L = 6/9 μm) flows at 1 to 1.5 (V) from the voltage (V 0) at which the current starts to flow. This voltage width is Vc (V).

[1427] Therefore, in the case of the N channel, during black display, a current starts to flow at the gate (G) voltage V0, and a current of 1 to 10 μA flows at the gate (G) voltage V0 + Vc.

The Vg voltage changes depending on the image. For example, in black display, the Vg voltage is 1.
It is 5 (V). It is 2.5 (V) in white display (Fig. 2
70 (b)). However, the punch-through voltage is a fixed value such as 0.1 (V). Therefore, the penetration voltage 0.1 (V) for black display Vg = 1.5 (V) and the penetration voltage 0.1 (V) for white display Vg = 2.5 (V) have different contributions. . That is, the ratio of the punch-through voltage to the black display is higher than that of the white display. Therefore,
The effect of the punch-through voltage is large in black display and small in white display. That is, the V0 voltage in the N channel is lower than that in the P channel. Therefore, the driving TFT 11
As for a, the N channel has a higher punch-through voltage than the P channel, that is, in the black display, and the program current flowing through the source signal line 18 becomes larger in the black display. Therefore, the write shortage is resolved.

It is needless to say that the above items can be applied to the pixel configuration of the voltage program shown in FIGS. 54, 68, 103 and the like. That is, it is possible to prevent the current from flowing through the EL element 15 unless the program voltage exceeds a certain level. Therefore, in black display or the like, when the signal fluctuates due to noise, the noise level is removed (the EL element 15 does not light up to a certain level due to the effect of the punch-through voltage).
Because you can. Further, the white peak luminance is easily produced, and the image quality is improved.

[1430] Also, in the above embodiments, the capacitor 19b is used.
It is assumed that the punch-through voltage is set (set to a desired value) with the capacity of. The value of the punch-through voltage changes depending on the amplitude value of the gate signal line 17. Therefore, the punch-through voltage can be adjusted by adjusting the amplitude value of the gate signal line 17a (in the case of FIG. 1). For example, Vg of the gate signal line
If h = 10 (V) and Vgl = 0 (V), the amplitude value is 10 (V). In this state, the penetration voltage is 0.1
(V). By setting Vgh to 12 (V), the amplitude value becomes 12 (V). Therefore, ideally, the penetration voltage is 0.12 (V). That is, the punch-through voltage can be freely changed by adjusting the amplitude of the gate signal line 17, and the base current can be adjusted.

[1431] This control is easy. This is because the power supply circuit for generating the gate voltage may be set with a command so that the value of Vgh or Vgl can be set. By adjusting this voltage, the punch-through voltage can be finely adjusted.

[1432] A signal applied to the gate signal line 17a (TF
If the slew rate (change in voltage with respect to rise time and fall time) of the T11 on / off signal) is high, the punch-through voltage tends to increase. Conversely, if the slew rate is low, the punch-through voltage will decrease. In other words, slew rate 40
The penetration voltage is higher in (V) / μsec than in 20 (V) / μsec. The slew rate of the gate signal changes depending on the driving capability of the output buffer (inverter circuit, operational amplifier, etc.) of the gate driver 12. The slew rate can be adjusted by controlling the output current of the output buffer. Therefore, the punch-through voltage can be adjusted by controlling the output current of the output buffer. The control of the output current of the output buffer can be realized by adjusting the supply voltage of the output buffer and blunting the waveform applied to the gate terminal. Further, adjusting the supply voltage is easy in terms of circuit configuration. The blunting of the waveform applied to the gate terminal can be realized by reducing the size of the buffer in the previous stage (reducing the capacity). Further, the punch-through voltage can be changed by using an on / off signal applied to the gate signal line 17a as a sine curve or sawtooth signal. The above items are also applied to the control of the voltage control signal line and the common signal line described below.

In FIG. 171, etc., the capacitor 19b for generating punch-through voltage has one electrode as the gate signal line 17 (although it is supposed to be connected to the gate signal line 17), but it is not limited to this. . For example, a voltage control signal line for controlling the capacitor 19b is separately formed to generate the punch-through voltage. One of the two electrodes of the capacitor 19b is connected to the gate terminal of the TFT 11a,
The other may be connected to the separately formed voltage control signal line. In this configuration, a pulse signal (not limited to a rectangular wave, a sine curve or a sawtooth signal) may be applied to the voltage control signal line in synchronization with the selected state of the gate signal line 17a. Further, the punch-through voltage can be easily adjusted by adjusting the pulse amplitude value.

[1434] This configuration is shown in FIG. 235. A punch-through voltage is applied to the gate terminal of the TFT 11a via the capacitor 19b by the pulse voltage applied to the voltage control signal line 17c.

The voltage control signal line 17c is the gate signal line 17
And the operation is the same. As shown in FIG. 236, the voltage control signal line 17c is configured as an output terminal of the gate driver circuit 12. In addition, as described in FIG. 179,
The gate signal line 17b is connected to the lighting control line 1791.

When the signal for generating the punch-through voltage is not supplied from the gate signal line 17a but is supplied from the voltage control signal line 17c as shown in FIG. 237, the control of the punch-through voltage becomes easy. FIG. 237 is an explanatory diagram of signal waveforms for driving the display panel of FIG. 236. For ease of explanation, the pixel row selected is the pixel row number (1).
Will be described.

When the pixel row (1) is selected, the gate signal line 17a (1) changes from Vgh to Vgl, so that the capacitor 19b allows the potential of the gate signal line 17a to penetrate. Due to this penetration, the Vg voltage becomes V0.

Next, the TFT 11a causes a current equal to the current Iw absorbed by the source driver circuit 14 to flow. However, in the case of black display, the value of the current passed through the TFT 11a is small. As an example, it is 30 nA or less. Such a current cannot sufficiently charge and discharge the parasitic capacitance of the source signal line 18 within the 1H period. Therefore, the potential of the source signal line 18 cannot be set to the predetermined voltage within the 1H period. That is, the Vg voltage is also low, and the originally required voltage Vb cannot be obtained, and becomes the Vc voltage.

Next, since the gate signal line 17a (1) changes from the on-voltage (vgl) to the off-voltage (Vgh), the punch-through voltage is generated again by the capacitor 19b. This penetration voltage shifts the Vg voltage from the Vc voltage to the Va voltage.

[1440] Further, the voltage control signal line 17c (1) shifts from the low voltage to the high voltage after a delay of t1. Therefore, a penetration voltage is further generated, and the gate terminal voltage Vg of the TFT 11a shifts to the target voltage Vb. By adjusting the shifting voltage, the punch-through voltage can be freely controlled. That is, in the configurations of FIGS. 228 and 229, the change in voltage (amount of punch-through voltage) is restricted by the amplitude of the gate signal line 17a. However, as shown in FIG. 236, by separately providing the voltage control signal line 17c, it becomes easy to change the amount of punch-through voltage. Further, it is easy to control the slew rate of the applied signal. Further, since there is no restriction on the potential level of the signal applied to the voltage control signal line 17c, the circuit configuration becomes easy.

[1441] Therefore, the TFT 11a is programmed so that no current flows or a black current having a desired value is supplied. That is, the EL element 15 is programmed so that only a minute current flows. Therefore, the EL display panel of the present invention is free from blackening, and high contrast display can be realized. This Vb voltage is held in one field (one frame), that is, until the pixel is next selected and rewritten.

As described above, according to the present invention, the voltage fluctuation of the voltage control signal signal line 17c is controlled by the TF via the capacitor 11b.
It is supplied to T11a. Therefore, the current flowing through the EL element 15 is controlled. This control is particularly effective for realizing black display.

The difference between FIGS. 237 and 238 is that the operation timing t1 of the voltage control signal line 17c is set to 1H. The other points are the same. By adopting the configuration shown in FIG. 238, the gate signal line 17a and the voltage control signal line 17c are
Since the operation clocks of and can be made the same, the circuit configuration becomes easy.

FIG. 236 shows a pixel configuration of the current program shown in FIG. However, the present invention is not limited to the current programming method and can be applied to the pixel configuration of voltage programming. FIG. 239 shows that the technical idea of the present invention is applied to the pixel configuration of the voltage program described with reference to FIG.

[1445] FIG. 239 shows that one terminal of the capacitor 19b is T
It is connected to the drain terminal of the FT 11b and the other terminal is connected to the voltage control signal line 17c. The switching TFT 11b is formed by an N-channel TFT.

FIG. 240 is an explanatory diagram of drive waveforms in the pixel configuration of FIG. 239. When pixel row (1) is selected,
Since the gate signal line 17a (1) changes from Vgl to Vgh, the gate signal line 17a (1) is changed by the capacitor 19b.
The potential of a penetrates. Due to this penetration, the Vg voltage changes from the held Vw to V0.

Next, the TFT 11a causes a current equal to the current Iw absorbed by the source driver circuit 14 to flow. However, the minute current for black display cannot sufficiently charge and discharge the parasitic capacitance of the source signal line 18 within the 1H period.
Therefore, the potential of the source signal line 18 cannot be set to the predetermined voltage within the 1H period. That is, the Vg voltage is also low, and the originally required voltage Vb cannot be obtained, and becomes the Vc voltage.

Next, since the gate signal line 17a (1) changes from the on voltage (vgh) to the off voltage (Vgl), the punch-through voltage is generated again by the capacitor 19b. Due to this penetration voltage, the Vg voltage further decreases from the Vc voltage and shifts to the Va voltage.

Further, after a delay of t1, the voltage control signal line 17c (1) shifts from the low voltage to the high voltage. Therefore, a punch-through voltage is generated, and the gate terminal voltage Vg of the TFT 11a shifts to the target voltage Vb. Therefore, the target voltage Vb can be applied to the gate terminal of the TFT 11a.

The difference between FIG. 240 and FIG. 241 is that the operation timing t1 of the voltage control signal line 17c is set to 1H. The other points are the same. By adopting the configuration shown in FIG. 241, the gate signal line 17a and the voltage control signal line 17c are
Since the operation clocks of and can be made the same, the circuit configuration becomes easy.

The configuration using the voltage control signal line 17c is exemplified by various other configurations. For example, FIG. 242 shows a configuration in which a capacitor 19b is arranged (formed) between the drain terminal of the switching TFT 11c and the voltage control signal line 17c. The configuration of FIG. 242 is not a configuration in which the punch-through voltage is directly applied to the gate terminal of the TFT 11a. But,
The signal waveform applied to the voltage control signal line 17c is applied to the drain terminal of the TFT 11c via the capacitor 19b. The voltage applied to this drain terminal is TF
It is reflected (affected, operated, controlled) on the gate terminal of the TFT 11a via T11b and the like.

[1452] That is, in the pixel configuration of FIG. 242, it is not directly controlled with the drive element 11a that causes a current to flow through the EL element 15. However, it is possible to control the current passed by the drive element 11a. The present invention provides a method of controlling the programmed current to be lower (sometimes higher), such as controlling the white peak current to flow more. is there. Therefore, the configuration of FIG. 242 is also within the technical idea of the present invention.

FIG. 243 shows the voltage control signal line 17c in the pixel configuration of the current mirror shown in FIGS. 21, 43 and 71.
And a capacitor 19b for generating punch-through voltage is formed. No particular explanation will be required for this configuration. Therefore, the description is omitted.

[1454] In FIG. 245, the punch-through voltage generating 11a is not formed. The voltage control signal line 17c is connected to one terminal of the holding capacitor 19. Until now, the TFT 11a has been applied with the voltage applied to the punch-through voltage capacitor 19b.
It is described that the electric potential of the gate terminal is controlled to adjust the current flowing through the TFT 11a.

In FIG. 245, the charge holding capacitor 19 is directly controlled to control the voltage of the gate terminal of the TFT 11a and the current flowing to the TFT 11a. The operation can be applied as it is or by analogy with the operation described in FIG. Figure 2
With the pixel configuration of 45, the capacitor 19 for punch-through voltage
b is unnecessary. Therefore, the pixel configuration becomes easy.

FIG. 266 is an explanatory diagram of drive waveforms in the pixel configuration of FIG. 245. When the gate signal line 17a (1) is selected, the TFT 11c and the TFT 11d are turned on. Next, the TFT 11a causes a current equal to the current Iw absorbed by the source driver circuit 14 to flow. However, the minute current for black display cannot sufficiently charge and discharge the parasitic capacitance of the source signal line 18 within the 1H period. Therefore, the potential of the source signal line 18 cannot be set to the predetermined voltage within the 1H period. That is, the Vg voltage is also low, and the originally required voltage Vb cannot be obtained, and becomes the Vc voltage.

Next, the gate signal line 17a (1) changes from the on-voltage (vgl) to the off-voltage (Vgh). At the same time, the voltage control signal line 17c (1) shifts from the low voltage to the high voltage. Therefore, a penetration voltage is generated, and T
The gate terminal voltage Vg of the FT 11a shifts to the target voltage Vb. Therefore, the target voltage Vb is set to the TFT1.
It can be applied to the gate terminal of 1a.

[1458] Note that in FIG. 266, "gate signal line 17
a (1) is an on-voltage (Vgl) to an off-voltage (Vgh)
Changes to. At the same time, the voltage control signal line 17c (1) shifts from the low voltage to the high voltage. However, the present invention is not limited to this, and the signal waveform may be changed after a period of t1 as shown in FIG. 240 or FIG.

It is needless to say that the pixel configuration shown in FIG. 245 can be applied to the pixel configuration shown in FIG. The voltage control signal line 17c is connected to one terminal of the charge holding capacitor 19 (see FIG. 244). Then, this voltage control signal line 17
The gate terminal voltage of the TFT 11a is changed by the signal applied to c to control (adjust) the current flowing through the TFT 11a.

[1460] Also, in the lower layer of the electrode of the capacitor 19a,
A signal line insulated from the electrode may be formed. what if,
This signal line is called a common signal line. If such a configuration is realized, the second capacitor can be formed by the common signal line, the insulating film, and the electrode of the capacitor. This capacitor can be regarded as the capacitor 19b in FIG. Therefore, by applying the pulse signal to the common signal line in the same manner as above, the same action and effect as above can be exhibited. Although the name is called the common signal line, there is no difference in function and configuration from the voltage control signal line 17c described above. Therefore, the matters and contents described for the voltage control signal line 17c can be applied to the common signal line as they are.

In the above embodiments, one terminal of the punch-through voltage generating capacitor 19b is connected to the gate terminal of the TFT 11a. However, the present invention is not limited to this configuration. For example, as shown in FIG. 267, one terminal of the capacitor 19b may be connected to the middle point of the capacitors 19a and 19c for holding charges. Figure 2
By configuring as shown in 67, the influence of the punch-through voltage on the gate terminal of the TFT 11a is reduced.

[1462] The configuration shown in FIG. 277 is also effective. In FIG. 277, when the pixel is selected, the voltage from the source driver circuit 14 is the drain terminal Vk of the TFT 11b.
Applied to. This voltage (that is, the program current) is divided by the capacitors 19a and 19c and becomes the gate terminal voltage Vg of the driving TFT 11a. Therefore, the gate terminal voltage Vg becomes lower than the programmed voltage Vk. Therefore, TFT11
The current flowing through a (current flowing through the EL element 15) is smaller than the programmed current. Therefore, the program current can be increased and the current flowing through the EL element 15 can be reduced. Therefore, even in black display, insufficient writing is eliminated.

In FIG. 277, the capacitance of the capacitor 19a is Ca, the capacitance of the voltage shift capacitor 19c is Cc, and the high voltage signal (Vg
h), the low voltage signal (Vg
In the case of l), a good black display can be realized by configuring so as to satisfy the following conditions.

[1465] 0.5 ≤ | Vgh-Vgl | x (Ca
/ Cc) ≦ 10 More preferably, the following conditions are preferably satisfied.

[1465] 1 ≦ | Vgh-Vgl | × (Ca / C
c) ≦ 5 Further, based on Vc in FIG. 270, 0.05 ≦ | Vc | × (Ca / Cc) ≦ 1 More preferably, the following conditions are preferably satisfied.

[1466] 0.1 ≤ | Vc | x (Ca / Cc)
<= 5 The above items are also effective for the pixel configurations shown in FIGS. 57, 54, 103 and the like. For example, in the voltage-programmed pixel configuration of FIG. 57, a capacitor 19b for generating punch-through voltage is formed or arranged between the gate terminal of the TFT 11a and the gate signal line 17a.

The above items also apply to the embodiment of FIG. Further, it goes without saying that the present invention can be applied to the pixel configurations described with reference to FIGS. 21, 43, 71, etc. (see FIG. 291). 54, 68, and 103.
It is also applicable to the pixel configuration of voltage programming. TF
The voltage that penetrates T can be compensated. Further, it is possible to operate at the best operating point by shifting the potential.

[1468] FIG. 277 has a configuration in which a capacitor 19b for generating punch-through voltage is added. However, in the configuration of FIG. 277, generally, the P-channel TFT 11b has a low on-resistance, and therefore the channel width W needs to be relatively large. Therefore, the source-gate capacitance is relatively large. Therefore, the parasitic capacitance generated in the TFT 11b can be used as a substitute without adding the capacitor 19b.

As shown in FIG. 277, when both the punch-through voltage capacitor 19b and the operating point shifting capacitor 19c are manufactured, the operating point Vg may vary. To solve this problem, switching TFTs (TFTs 11b and 11c in FIG. 1 that select pixel rows.
1, FIG. 43, and FIG. 71, it is effective to set the TFTs 11c and 11d) to N channels to reduce the punch-through voltage as much as possible. This embodiment is shown in FIG. In FIG. 292, by setting the switching TFT 11b to the N channel, the punch-through voltage is reduced to 1 / th compared to the P channel.
It can be 2 to 1/5. Therefore, the punch-through voltage is unlikely to occur and the Vk voltage shift is unlikely to occur. Therefore, variations in the gate terminal voltage Vg of the TFT 11a are unlikely to occur. Note that in FIG. 292, a TFT 11g (switching means) for applying the reverse bias voltage Vm is added.

The above is the case of the pixel configuration of FIG. 1, but the same as the configurations of FIGS. 21, 22, 43, and 71 (see FIG. 278). When a pixel is selected, the TFT
11d turns on, voltage (current) from the source signal line 18
Is written in one terminal of the capacitor 19a connected to the drain terminal of the TFT 11d. That is, the voltage from the source driver circuit 14 is applied to the drain terminal Vk of the TFT 11b. This voltage (that is, the program current) is divided by the capacitors 19a and 19c and becomes the gate terminal voltage Vg of the driving TFT 11b. Therefore, the gate terminal voltage Vg is smaller than the programmed voltage Vk. Therefore, TFT11
The current flowing through b (the current flowing through the EL element 15) is smaller than the programmed current. Therefore, the program current can be increased and the current flowing through the EL element 15 can be reduced. Therefore, even in black display, insufficient writing is eliminated.

As is apparent, as shown in FIG. 278, each pixel 16 has a reverse bias TFT1.
You may add 1 g. It goes without saying that a capacitor 19b for generating punch-through voltage may be added. Of course, it goes without saying that a TFT 11d for controlling on / off of the current flowing through the EL element 15 may be added. As described above, the present invention can mutually combine the configurations or embodiments or technical ideas described (explained) in the present specification.

The common signal line and the voltage control signal line are formed in parallel with the pixel row. That is, the signal line is formed (arranged) for each pixel row. However, the formation is not necessarily limited to each pixel row. For example, when selecting pixels by two or more pixel rows, the signal line may be formed (or arranged) for each plurality of pixel rows.

[1473] In FIG. 171, etc., 19b is 2
Although the capacitor of the terminal is used, it is not limited to this. For example, a TFT may be used and the source-gate capacitance of the TFT may be used to form a capacitor. That is, the element that generates the punch-through voltage is not limited to the capacitor, and may be any element as long as the gate terminal of the driving TFT 11a of the EL element 15 is insulated and the potential of this terminal can be changed. Of course, it goes without saying that a capacitor can also be configured with the junction capacitance of the diode.

Also, although the capacitor 19b is formed in each pixel, it is not necessarily limited to this. For example, adjacent pixels may form one capacitor 19b.

[1475] In addition, a switching element such as a TFT is arranged (formed) at one end of the capacitor 19b, and the switching element is controlled to be turned on / off.
9b may be separated from the pixel 16.
That is, by disconnecting the capacitor 19b from the pixel 16, the base current can be changed (present or absent). Further, although the capacitor 19b is separated by the switching element, a TFT (switching element) or the like that short-circuits the electrodes of the capacitor 19b is formed (arranged) and the switching element is turned on so that the capacitance of the capacitor 19b becomes zero. You may perform the control.

The target of potential change is not limited to the TFT 11a. Any element may be used as long as it sets the current amount of the EL element 15. That is, the driving amount TFT 11a
This can be configured with MIM, TFD (thin film diode), or the like. By controlling these, the EL element 1
The current flowing in (or flowing through) 5 may be controlled. In this configuration, the cathode electrode is processed (formed) in a horizontal stripe shape as needed.

Also, the reverse bias driving method of preventing deterioration of the EL element 15 by applying the reverse bias voltage Vm has been described with reference to FIGS. 89 to 102 and the like. Needless to say, this reverse bias drive method is combined with the method of controlling the current flowing through the EL element 15 by the punch-through voltage described in FIGS. 222, 223, 224 (called the punch-through drive method). It goes without saying that it is okay.

FIG. 223 shows a TFT1 in which a capacitor 19b for generating punch-through voltage is added to the pixel configuration of the voltage program of FIG. 68 and a reverse bias voltage Vm is applied.
This is a configuration in which 1d is added.

The reverse bias voltage Vm is the same as the TFT 11d.
However, the present invention is not limited to this and may be replaced with a capacitor. That is, like the capacitor for punch-through voltage 19b, the voltage applied to the electrode of the capacitor may be applied to the EL element 15 by punch-through by applying a pulse voltage to one end of the capacitor.

[1480] FIG. 224 shows a configuration in which a reverse bias TFT 11g is added to the current mirror pixel configuration (current programming system) described with reference to FIGS. 21, 43, 71 and the like. Further, FIG. 225 shows a pixel configuration in which a reverse bias TFT 11g is added to the voltage program type pixel configuration described in FIG. In addition, FIG. 226 shows a reverse bias T for the pixel configuration of the pixel configuration (current programming method) of FIG.
This is a pixel configuration in which FT11g is added.

In the above embodiments, the punch-through voltage capacitor 19b has been described as a two-terminal capacitor, but the present invention is not limited to this. For example, in FIG. 227, the capacitor 19b is configured (formed, manufactured) by the channel capacitance of the transistor 2271. Source-drain capacitance may be used.

Similarly, the charge holding capacitor 19a is not limited to a two-terminal capacitor. As described with reference to FIG. 227, the channel capacitance of the transistor may be used. Alternatively, a diode (the transistor 2271 (19b) in FIG. 227 can also be regarded as a diode) may form a capacitor. In addition, any element may be used as long as it can hold an electric charge. It goes without saying that the above items can be applied to other embodiments of the present invention.

[1483] Also, not only the combination of the punch-through driving method and the reverse bias driving but also the block driving method and the N
The present invention described in this specification, such as a double pulse driving method and a multiple pixel row selection method, can be combined with each other.
The above items also apply to the following items.

[1484] Note that the punch-through voltage causes a deviation with respect to the target current. However, as in the present invention,
Program so that double current flows through EL element 15,
Moreover, in the method of intermittently displaying the display image, the deviation from the target value is also about 1 / N. In addition, 1 times the current (normal drive,
Compared with conventional drive), T
Since the FT 11a is operated, the deviation is reduced.
Therefore, better image display can be realized as compared with the conventional case.

[1485] The technical idea of the present invention is to control the current flowing through the EL element 15. Therefore, it is not indispensable that the generation timing of the punch-through voltage is always synchronized with the scanning timing of the gate signal line 17a. Asynchronous control may be possible. The punch-through voltage may be dispersed and applied multiple times.

As shown in FIGS. 122 to 125,
It is assumed that the current output circuit 1222 including the DA converter 1226 outputs a current to the source signal line 18. 171,
In the case of the method of driving by generating the punch-through voltage as in FIGS. 172, 21, 43, 710, etc., it is necessary to add a constant base current and output. For example, when a current of 30 nA is programmed in the pixel 16 at a certain gradation, a current to which the base current due to the punch-through voltage is added is applied to the source signal line 18. If the base current is 40 nA, a current of 30 nA + 40 nA is applied to the source signal line 18
(Absorption from the source signal line 18 toward the circuit 1222). Therefore, it is necessary to configure the circuit so that the base current is applied and flowed. For example, a configuration in which a current mirror circuit for the base current is added is exemplified.

In FIGS. 122 to 125, the current output circuit 1222 including the DA converter 1226 outputs the current to the source signal line 18, but the present invention is not limited to this. For example, one first current mirror circuit that generates a reference current is formed in the IC chip 14 (FIG. 27).
5).

[1488] FIG. 275 illustrates a main portion of the output current circuit 1222 corresponding to each source signal line 18. In addition,
In FIG. 275, the applied image data is 6 bits (RG
The description will be made assuming that B is 64 gradations each. Image data D (0 to 5) corresponds to 6 bits, MSB (most significant bit) is D5, and LSB (least significant bit) is D0.

As shown in FIG. 275, the image data D0
Causes the switching transistor 2752a to turn on,
One child transistor 2754a turns on. Similarly,
Switching transistor 275 according to image data D1
2b turns on and the two child transistors 2754b turn on. Further, the switching transistor 2752c is turned on by the image data D2, and the four child transistors 27
54c turns on. Further, the switching transistor 2752d is turned on by the image data D3, and the eight child transistors 2754d are turned on. Also, the image data D0
The switching transistor 2752e is turned on from 4,
The 16 child transistors 2754e turn on. Also,
Switching transistor 275 according to image data D5
2f is turned on and 32 child transistors 2754f are turned on. Therefore, the current Iw expressing 64 gradations according to the input image data D flows from the source signal line 18. That is, the ON voltage is applied to the gate signal line 17a, and the Id from the TFT 11a (in the case of FIG. 1) of the selected pixel row is changed.
A d (= Iw) current flows.

[1490] In FIG. 275, 1 is included in the driver circuit 14.
One parent transistor 2753 is formed (arranged). The current flowing through the parent transistor 2753 flows through the child transistor 2754. That is, the source signal line 18
If there are 176 (in case of QCIF) books, 176 ×
63 child transistors 2753 are parent transistors 27
It is connected to 53.

However, this is one parent transistor 2
Since there are too many connected to 753, an intermediate transistor may be arranged. For example, if the parent transistor is the first transistor, the second transistor and the third transistor are formed, and the third transistor is in a current mirror relationship with 63 of the child transistors 2754. Therefore, if QCIF is taken as an example (the number of source signal lines is 176), the first transistor is set to 1
Sixteen (transistor) second transistors having a current mirror relationship with each (parent transistor) are formed, and eleven third transistors having a current mirror relationship with the second transistor are formed (arranged). That is, the number of the first to third transistors in the current mirror relationship is 1 × 16 × 11 = 176. In addition, this first
Therefore, the third transistors are densely arranged in the IC chip 14. This is to eliminate the influence of Vt variation of each transistor. In particular, the first transistor and the second transistor need to be arranged very close to each other.

[1494] With the above relationship, the amount of output current of the entire IC chip can be adjusted by adjusting the current passed through the first current mirror circuit (parent transistor 2753). The current flowing through the parent transistor 2753 is configured so that it can be adjusted by an electronic volume. Further, as shown in FIG. 275, an external volume 2751 (bias resistor) is arranged on the chip 14 and the resistance value of this resistor is changed to change the current flowing through the parent transistor (first transistor) 2753. It may be configured so as to allow it. In any case, the parent transistor 27
By adjusting the current flowing through 53, it is possible to easily change the minimum step of the program current Iw and simultaneously change all the source signal lines 18.

Note that in FIGS. 87, 88, 142, etc., a plurality of pixel rows are selected at the same time. Even in this case,
This can be dealt with by changing the current flowing through the parent transistor 2753. That is, as compared with the case where one pixel row is selected, a current that is twice as many as the selected pixel row is supplied to the parent transistor 27.
This is because it can be sent to 53. In addition, as described with reference to FIG. 146, it is easy to deal with the driving method of changing the current flowing in the source signal line 18 (absorbed from the source signal line 18) in the period of 1H or the like. Parent transistor 2753
This is because it is only necessary to change the current flowing to the.

[1494] The brightness and gamma characteristics of the display panel can be adjusted by adjusting the current of the parent transistor 2753. The reference current flowing through the parent transistor 2753 is configured so that it can be adjusted independently for each R, G, B pixel. This is because the RGB gamma curve and applied current are different. This structure is shown in FIG. 276. As shown in FIG. 276, parent transistors 2753 (2753) of respective colors are provided.
The current flowing through R, 2753G, 2753B) can be changed by an electronic regulator or a bias resistor. Of course, the current flowing through the parent transistor 2753 is corrected so as to match the gamma characteristic and the temperature characteristic of the EL element 15.

[1494] Also, in order to suppress black gradation skip (EL
Occurs because the current and brightness are linear. The same applies to PDPs), and image processing is performed by combining both error diffusion and dither processing.

In addition, a configuration is provided in which one (or more than one) transistor 2754 is formed for each of the data D0 to D5 and the current output is changed by changing the current magnification of the current mirror circuit with the parent transistor 2753. But it's okay. For example, the child transistor 2754 corresponding to D0 has a current multiplication factor of 1 times that of the parent transistor 2753, and the child transistor 2754 corresponding to D1.
And the parent transistor 2753 and the current magnification are 2 times.
Similarly, the child transistor 2754 corresponding to D2 has a current multiplication factor of 4 times that of the parent transistor 2753, and the child transistor 2754 corresponding to D3 has a parent transistor 275.
3 and the current magnification is 8 times. Further, the child transistor 2754 corresponding to D4 and the parent transistor 2753 have a current multiplication factor of 16, and the child transistor 2754 corresponding to D5 has a parent transistor 2753 and a current multiplication factor of 32.
It is a double structure.

[1497] As described above, the output current circuit 1222 is
By adopting the configuration of a two-stage or three-stage (first transistor, second transistor, and third transistor) current mirror circuit, each source signal line 1
It is possible to eliminate the variation in current programmed in 8.

When the punch-through voltage capacitor 19b is formed as shown in FIGS. 171, 21, 43, and 710, it is necessary to add a constant base current for output.
Further, even if the capacitor 19b for punch-through voltage is not arranged (formed), the punch-through voltage is generated by the source-gate terminal capacitance of the TFT 11b. For example, when a current of 30 nA is programmed in the pixel 16 at a certain gray scale as before, a current to which the base current due to the punch-through voltage is added is applied to the source signal line 18. If the base current is 40 nA, a current of 30 nA + 40 nA is applied to the source signal line 18 (absorbed from the source signal line 18 toward the circuit 1222). Therefore, it is necessary to configure the circuit so that the base current is applied and flowed. For example, a configuration in which a current mirror circuit for the base current is added separately is exemplified.

In FIG. 293, the base current applying transistors 2752bb and 2754bb are arranged (formed) in the chip 14. The application of the base current can be switched by the logic signal applied to the terminal Dbb. That is, whether or not the base current is applied is configured to be logically controllable.

[1500] It is preferable that the base current can be adjusted independently for each RGB. RGB EL element 1
This is because the gamma curve and the applied current are different for each 5.
Further, it is preferable that the base current can be controlled to be turned on and off. Apply base current (source signal line 18
In some cases, the current may be absorbed by the), so that black floating may occur depending on the image. Therefore, by turning the base current on and off, the optimum adjustment can be made. Further, it is preferable that the on / off of the base current can be independently set for each RGB.

[1501] As described above, the parent transistor 2
The reference current supplied to 753 and the base current supplied to the transistor 2754bb are temperature-compensated. The panel (more precisely, the temperature of the EL element 15) is detected, and the values of the reference current and the base current are changed according to the detected temperature. Generally, the EL element 15 has a reduced luminous efficiency as the temperature rises.
Therefore, the current applied to the EL element 15 is increased when the temperature rises. Further, it is preferable that the compensation values of the reference current and the base current can be set independently for each RGB.

[1502] As described with reference to FIG. 126, a precharge (discharge) function for a black gradation is added.
FIG. 351 is an example thereof. Source driver circuit 14
A precharge circuit 3511 is formed (arranged) therein.

There are two precharge voltages, Vb1 and Vb2. Of course, one type may be used as described in FIG. Further, three or more Vb voltages may be provided (for example, Vb1, Vb2, Vb3, Vb4). FIG. 351
Then, Vb1 is a voltage for completely displaying black in the pixel 16. In the pixel configuration of FIG. 1, the TFT 11a is completely turned off by applying the Vb1 voltage. However, as described with reference to FIG. 126, in this case, gradation skipping occurs completely from the black display to the next first gradation. The occurrence of this jump is suppressed by the precharge voltage Vb2.
Is. When the Vb2 voltage can be applied, in the pixel configuration of FIG. 1, the TFT 11a causes a minute current to flow through the EL element 15.
Therefore, gradation jump is suppressed.

[1504] Whether the Vb1 voltage is applied, the Vb2 voltage is applied, or both are not applied and current programming is performed is determined by the image data D (5: 0).
For example, when the value of D (5: 0) is '0', V
The b1 voltage is applied. When D (5: 0) is 1 or more and 7 or less, the Vb2 voltage is applied. This application condition is configured to be changeable by a command to the driver circuit 14. For example, when the value of the image data D (5: 0) is "0" or "1", the Vb1 voltage is applied, and when D (5: 0) is 1 or more and 15 or less, the Vb2 voltage is applied. And so on. Also, the Vb voltage is 3
When one or more voltages can be applied, the Vb voltage for the input data can be applied accordingly. Although Vb1 and the like are voltages, they are not limited to these and may be replaced with currents.

In the present invention, the Vb1 voltage is applied at least when the value of D (5: 0) is “0”.
By doing this, a very nice black is displayed,
This is because the image quality is remarkably improved. Also, 1 / of all gradations
16, that is, when D (5: 0) is 1 or more and 3 or less,
The Vb2 voltage is applied. This is because the output (input) current from the source driver circuit 14 is small in this range, and insufficient writing to the pixel occurs.

[1506] When the display changes from white display to black display, the change in the potential of the source signal line 18 is slow. Therefore, the target potential cannot be changed (it is difficult to change) in the 1H period. FIG. 352 shows a method (method) for solving this problem.

[1507] FIG. 352 (a) illustrates changes in the potential of the source signal line 18. In each RGB graph, the vertical axis is + (high voltage). The pixel configuration of FIG. 1 is assumed. In the pixel configuration of FIG. 1, the higher the potential, the more TFT
The gate potential of 11a becomes high, and the TFT 11a stops flowing current. Therefore, the EL element 15 does not light up,
It is displayed in black. Further, from the viewpoint of the source driver circuit 14, in the completely black display, the transistors 2754 are all off even in FIG. Therefore, no current flows through the source signal line 18. If no current flows through the source signal line 18, the potential of the source signal line 18 does not change.

[1508] Therefore, the data input to the source driver circuit 14 is white (for example, D (5: 0) = 63).
From 0 to completely black (D (5: 0) = 0), no current flows through the source signal line 18 and insufficient writing occurs in the pixel 16.

[1509] To solve this problem, when changing from white to black, gray level image data is once applied to change the potential of the source signal line 18, and then the final black image data is obtained. It is sufficient to apply a current corresponding to the above to the source signal line 18.

[1510] That is, in gray display, some of the transistors 2754 of the source driver circuit 14 are on. Therefore, a current also flows through the source signal line 18. In addition, a current can be passed through the pixel driving TFT 11a.

Therefore, a current is made to flow from the potential level of the source signal line 18 in white display to the source signal line 18 in accordance with the gray (halftone) level data. Since a current flows, the potential level of the source signal line 18 changes rapidly and changes to a gray (halftone) potential. Then, a black display current is passed through the source signal line 18. At this time, since the flowing current is small, the potential changes little by little. However, since the potential of the source signal line 18 is close to the target value, even if insufficient writing to the pixel 16 occurs, it is visually inconspicuous.

In FIG. 352, a data shift circuit 3521 for shifting the value of the input data D (5: 0) is provided in order to realize the above driving method. The data shift circuit 3521, for example, when the input data D (5: 0) is 4,
Shift 1 bit and change to 8. The shift direction and shift amount are configured to be changeable by command setting. Further, the shift direction is performed in consideration of the value of the data applied to the source signal line 18 of the previous time (1H before).

[1513] White before 1H (for example, D (5: 0))
= 63), and next is displayed in black (for example, D (5: 0) =
In the case of 2), the 1-bit data is shifted to the larger side. That is, D (5: 0) = 4. In this case, the data applied to the source signal line 18 is D before 1H.
The voltage corresponding to (5: 0) = 63 is applied, then the voltage corresponding to D (5: 0) = 4 (referred to as Vb) is applied, and finally (1H / 2 after 1H / 2) ) To D (5:
A voltage (denoted by Va) corresponding to 0) = 2 is applied.
Therefore, as shown in the graph of R in FIG. 352 (a), the potential of the source signal line changes from Vb to Va voltage. Therefore, the potential of the source signal line changes rapidly, and the insufficient writing is eliminated. Note that when D (5: 0) = 0, it is 0 even after shifting. In this case, the precharge voltage Vb1 is applied as described in FIG.

The data shift direction takes into consideration the voltage (that is, data) applied to the source signal line 18 1H before. FIG. 354 shows a case where the black display is changed to the white display. Black is displayed before 1H (for example, D (5: 0) =
2), next is white display (for example, D (5: 0) = 32)
If so, the 1-bit data is shifted to the smaller side. That is, D (5: 0) = 16. In this case, the data applied to the source signal line 18 is D (5:
0) = 2 is applied, then D
A voltage (Va) corresponding to (5: 0) = 16 is applied, and finally D (5: 0) = (after 1H / 2 of 1H) =
A voltage (denoted as Vb) corresponding to 32 is applied.

Therefore, as shown in the graph of R in FIG. 354 (a), the potential of the source signal line changes from Va to Vb voltage. Therefore, the potential of the source signal line changes rapidly, and the insufficient writing is eliminated. Note that D (5:
When 0) = 32, the data of the previous 1H and the next 1H are the same. Therefore, the shift tends to cause insufficient writing of data. Therefore, no data shift is performed. As described above, whether to shift or not and how many bits to shift are determined in consideration of the potential previously written in the source signal line 18. In addition to the previous time, the data shift circuit 35
It goes without saying that the operation of No. 21 may be determined (in some cases, multiple fields are also considered).

[1516] Note that, as illustrated in FIG.
It is also effective to combine with the precharge circuit described in 1. In FIG. 353, first, the precharge voltage Vc closer to black is applied. After that, the Vb voltage is applied from the data shift circuit 3521 to the source signal line, and finally the target voltage Va is applied.

In the above embodiments, the pixel 16 is formed with the capacitor 19b for generating the punch-through voltage, or T
This is a method in which a channel current such as FT11b is used to flow more bias current for black display. The above items can also be realized by shifting the potential of the source signal line 18.

[1518] FIG. 299 is an example thereof.

For example, the voltage applied to switch 1223 is voltage output circuit 1221 in FIG. That is, according to the image data, the switch 1223 is turned on to shift the potential of the source signal line 18 toward the Vdd voltage. Therefore, the potential V of the gate terminal of the TFT 11a
Since g becomes high, the TFT 11a stops passing current. The timing for closing the switch 1223 is immediately before the selected pixel row is deselected. That is, the gate signal line 17
Immediately before the off voltage is applied to a. Therefore, after the current is programmed in the capacitor 19a of the pixel 16 and the potential shift by the source signal line 18 due to the operation of the switch 1223 is superimposed on the capacitor 19a,
The off voltage is applied to the gate signal line 17a, and the corresponding pixel row is deselected.

[1520] Note that "according to image data" means 64
Of the gradations, switch 1 is selected for the lower 8 gradations close to black display.
This means that control is performed to close 223. This is because in black display, the current flowing through the source signal line 18 is small, and thus insufficient writing is likely to occur. That is, the selective precharge described above.

[1521] The current output circuit 1222 in FIG.
2, FIG. 123, FIG. 275, FIG. 276, FIG. 293 and the like. Hereinafter, another current output circuit 1222 of the present invention will be described.

[1522] FIG. 300 is a configuration diagram of a display panel using another current output circuit 1222. Note that in FIG. 300 and the like, the current output circuit 1222 may be formed on the substrate 46 at the same time as the pixel 16. That is, the current output circuit 1222 may be formed by low temperature polysilicon technology. That is, it goes without saying that it may be formed in the same process as the TFT of the pixel, or may be formed in the source driver 14 of the silicon chip and mounted on the substrate 46 by using the COG technique or the like. Further, it may be formed by a high temperature polysilicon technique or an organic material (organic TFT).

[1523] The current output circuit 1222 of FIG.
The EL element 15 is deleted, and the removed EL element is connected to the source signal line 18. That is, the source signal line 18 in FIG. 41 becomes the current program line 3002. The output of the current sampling circuit 3001 is connected to the current program line 3002. The current flowing through the current program line 3002 is the current flowing through the source signal line 18. Therefore, the current sampling circuit 3001
Current flows into the current program line 3002, and this current is programmed into the capacitor 19. Then, the programmed current is applied to the source signal line 18 in synchronization with the 1H clock. Therefore, since it is necessary to apply the current to the source signal lines 18 simultaneously in synchronization with the 1H clock, the current output circuit 12
The output stage of 22 is equipped with a switch that turns on and off in synchronization with the 1H clock.

The current output circuit 1222 may have the current mirror pixel 16 configuration of FIG. The current output circuit 1222 of FIG. 300 has a configuration in which the EL element 15 of FIG. 43 is deleted and the location of the deleted EL element and the source signal line 18 are connected. That is, the source signal line 18 in FIG. 43 becomes the current program line 3002. The output of the current sampling circuit 3001 is connected to the current program line 3002. The current flowing through the current program line 3002 is the current flowing through the source signal line 18. Therefore, the current from the current sampling circuit 3001 flows to the current program line 3002, and this current is programmed in the capacitor 19. Then, the programmed current is applied to the source signal line 18 in synchronization with the 1H clock.

In the configuration of the current mirror of FIG. 43, by setting (configuring) the current magnification, the current sampled and written in the current output circuit 1222 and the current value drawn from the source signal line 18 are made different. be able to. Therefore, the write current from the current sampling circuit 3001 can be increased,
Insufficient writing in the current sampling circuit 3001 can be eliminated. On the contrary, the write current to the source signal line 18 can be increased.

[1526] Note that in FIGS. 300, 301, and the like,
The current output circuit 1222 has been described as a modification of FIGS. 41 and 43, but the present invention is not limited to this. For example, a differential configuration may be used in which a difference between currents flowing in two signal lines (one current is a bias current, the other current is a bias current + a signal (writing) current) is written in the current output circuit 1222. In the differential configuration, insufficient current writing from the current sampling circuit 3001 to the current output circuit 1222 does not occur. However, the current program line 300
Two is required for 2.

[1527] In addition, in FIG. 41 and FIG.
7, the pixel 16 as described in FIG. 224, FIG. 222, and the like.
Bias current can be generated by adding a capacitor 19b for generating punch-through voltage to the structure. Therefore, the current flowing through the source signal line 18 can be increased in the black display state or the like.

In the configuration of FIG. 300, the output from the DA circuit (not shown) that converts digital image data into analog current is subjected to current sampling by the current sampling circuit 3001 and is arranged (formed) on the source signal line 18. Held in the current output circuit 1222 (capacitor 1
9). The held current is applied to the source signal line 18 in synchronization with the 1H clock (the current is absorbed from the source signal line 18) and sequentially written in the pixels 16 in each display region 21. By adopting the above configuration, the operational amplifier described with reference to FIG. 123 or the like becomes unnecessary, and the current mirror circuit described in FIG. 293 or the like becomes unnecessary. Further, since the current output circuit 1222 is easily configured, it can be formed by a low temperature polysilicon technique or the like.

[1529] However, there are problems. The operating frequency of the current sampling circuit 3001 is high, and the current output circuit 1222
This is because there is a shortage of writing to. This can be solved by disposing (forming) two current output circuits (1222a, 1222b) and two current sampling circuits 3001 (3001a, 3001b) as shown in FIG.

[1530] By forming two layers in this way, the first H
The current is applied from the current output circuit 1222a to the source signal line 18, and during that period, the current sampling circuit 30
01b is operated to cause the current output circuit 1222b to hold the write current. In the second H after the first H, a current is applied from the current output circuit 1222b to the source signal line 18, and during that period, the current sampling circuit 3001a can be operated and the current output circuit 1222a can hold the write current. . That is, the current sampling circuit 3
The operation speed of 001 can be halved. The display area is the display area 2 as shown in FIG.
1a and 21b may be divided into two (source signal line 18
Disconnect at the center of the screen).

[1531] The direction in which the current output circuit 1222 described with reference to FIGS. 300 and 301 absorbs the program current Iw or discharges it depends on the pixel 16 configuration. That is, the output current circuit 12 is adapted to the pixel 16 configuration.
22 is set (formed).

In FIG. 301, as described in FIG. 179, the gate signal line 17b is shared by a plurality of signal lines.
That is, the block driving method is implemented. As mentioned above,
The present invention can be combined with other configurations described herein. Further, FIG. 302 shows a lighting control line 179.
A plurality of 1s are formed and a reverse bias voltage is applied. As described above, the present invention can be combined with other configurations described in this specification.

[1533] The EL display device does not require a backlight unlike a liquid crystal display device. Therefore, there is a feature that the module thickness can be reduced. The liquid crystal display device turns on a backlight to display an image. In addition, the power consumption of the backlight is 200 ~ for modules used in mobile phones.
It is as large as 300 (mW). On the other hand, the power consumption used in the liquid crystal display panel is as small as 5 to 10 (mW).
Therefore, when displaying an image, since the backlight is on, there is no difference in the power consumption of the module regardless of which image is displayed.

[1534] The EL display device has a close relationship between the image display state and the power consumption. Power consumption is low in normal natural images. However, the white raster display consumes 3 to 4 times as much current as a natural image. In addition, the current flowing through the module constantly changes depending on the display state of the image.

[1535] If the power supply circuit is configured to follow the white raster display and the image display state, the circuit configuration becomes very large. Also, the power supply capacity is increased. The present invention solves these problems and easily realizes the brightness control of the display image 21.

[1536] FIG. 261 is an explanatory diagram of a display method of a mobile phone according to the present invention as an example of an information display device. FIG. 261
(A) has shown the display screen 21 of a mobile telephone. The display area 21b is a portion for displaying the reception state of the antenna, the time, and the like. That is, it is an area in which necessary information is constantly displayed. Similarly, the display area 21c is an area for displaying information such as operation icons that is constantly required. Display area 21
“A” is an area for displaying a menu, an image, and the like, and is an area where the displayed image constantly changes.

[1537] In FIG. 261, the description of FIG.
It is assumed that the block display method described with reference to FIG. The display area 21b has three blocks 19
The display area 21c has three blocks 1
It corresponds to 981c. The display area 21a corresponds to the remaining blocks 1981a. Therefore, the brightness of the image can be easily adjusted for each block 1981 by controlling the number of selected blocks 1981 and the like. It should be noted that the display areas 21a and 2 are
Brightness adjustments for 1b, 21c, etc., can be made with reference to FIGS.
It is not limited to the block drive described above. Needless to say, the sequential drive described with reference to FIGS. 134, 87, 88 and the like may be used. This is because the brightness can be easily adjusted for each part of the screen 21 by controlling the speed of the clock even in the sequential driving.

[1538] Since the display areas 21b and 21c are the portions which are constantly displayed, it is necessary to maintain a constant display screen brightness. Further, the current consumption is constant. However, in the display area 21a of FIG. 261 (a), it is preferable to control the brightness of the image depending on the type of the image. For example, when a television image is displayed in the display area 21a and the entire screen suddenly changes to white display (white raster), a current suddenly flows from the power supply circuit to the module. Due to this current, there is a risk that the module will generate heat and deteriorate, or defective.
The block 1981a shown in FIG. 261 (b),
1981b and 1981c can individually perform on / off processing (lighting / non-lighting processing), and the brightness of an image can be adjusted. This can be easily realized by controlling the lighting control line 1791.

Therefore, what kind of image is displayed in the display area 21a is monitored, and when the power consumption area is rapidly increased, the image data to be displayed is subjected to arithmetic processing or the like to reduce the overall brightness of the display image 21a. Need to let. For example, when performing white raster display, the size of the image data of the white raster is halved, and the display brightness is reduced to ½. It should be noted that the brightness of the image has a non-display area 312 and a lighting area 311 as described in FIG. 179 and the like.
By changing the ratio of. By doing so, the brightness of the image can be adjusted without changing the size of the image data. Of course, it goes without saying that it may be realized by changing the size of the image data.

[1540] FIG. 262 is a circuit for suppressing a change in power consumption due to image data. The frame (field) memory 2621 is divided into two areas (2621a and 2621b), each of which can hold image data of one screen. The memory 2621a and the memory 2621b are selected alternately. For example, when image data is being read from the memory 2621a to the data conversion circuit 2623,
Image data is written in the memory 2621b from a microcomputer (not shown). Conversely, when the image data is being read from the memory 2621b to the data conversion circuit 2623, the image data is being written to the memory 2621a from a microcomputer (not shown). For ease of explanation, the image data DATA (5: 0) is 6 of D5 to D0.
The description will be made assuming that it is a bit (64 gradations).

[1541] The image data DATA (5: 0) is stored in the memory 2
It is written in 621a and 2621b alternately. The MSB DATA5 is counted by the counter circuit 2622. The count of DATA5 is the image data in which the bits of DATA5 are set, that is, 1/2 of the maximum brightness.
The number of pieces of image data as described above is counted. Therefore, the larger the count value of the counter circuit 2622, the higher the brightness of the image, and the larger the power consumed by the module.

[1542] Now, it is assumed that the image data is written in the memory 2621a and is counted by the counter circuit 2622. At this time, the image data in the memory 2621b is being read.

When the count value of the counter circuit 2622 is greater than or equal to a predetermined value (the predetermined value is configured to be variable by a microcomputer (not shown) or the like), the counter circuit 2
Reference numeral 622 controls the data conversion circuit 2623. This control is processing such as halving the value of the image data from the memory 2622 (shifting to the right by 1 bit). That is, the counter circuit counts image data of one screen (image data is written in the memory 2621a). Then, this image data is read from the memory 2621a and this image data is controlled.

[1544] The count is not limited to D5, but DAT
It can be said that the feature extraction of the image can be more accurately performed by counting A (5: 4) or DATA (5: 3). By accurately performing the feature extraction, the brightness of the display area 21a can be adjusted more appropriately.

[1545] When the image data such as a white raster consumes an extremely large amount of power, the data conversion circuit 2623 performs image data conversion processing to reduce the image data and then applies the converted data to the source driver 14. . If the image is processed frame by frame and the brightness of the display image is adjusted frame by frame, the image will blink (the bright screen and the dark screen are repeated, and the image is in a blinking state). This problem can be dealt with by performing a data conversion control of the data conversion circuit 2623 while delaying the image processing and considering the image change of a plurality of frames.

In FIG. 262, the brightness of the display area 21a is adjusted by converting the image data and applying it to the source driver 14, but the present invention is not limited to this, and the block 1981a in FIG. It goes without saying that it may be realized by controlling the lighting time. Hereinafter, this implementation will be described.

[1550] FIG. 268 is an explanatory diagram of the embodiment. The frame (field) memory 2621 has two areas (2
621a, 2621b), each of which is 1
It can hold the image data of the screen. The memory 2621a and the memory 2621b are selected alternately. For example, when image data is being read from the memory 2621a to the source driver 14, image data is being written to the memory 2621b from a microcomputer (not shown). On the contrary, when the image data is being read from the memory 2621b to the source driver 14, the image data is written in the memory 2621a from a microcomputer (not shown). The above items are the same as in FIG.

The MSB DATA5 of the image data DATA (5: 0) is counted by the counter circuit 2682a. This is for counting the number of pieces of image data having a maximum luminance of ½ or more, as in the embodiment of FIG. Therefore, the larger the count value of the counter circuit 2862a, the more image data the image brightness is high.

[1549] The addition circuit (arithmetic processing circuit) 2682b is
The image 21 is divided into a plurality of blocks, and the average brightness distribution is processed in each block. In addition, the arithmetic processing circuit 2
Reference numeral 682c calculates the distribution state of image data having a predetermined brightness or higher and the distribution state of image data having a predetermined brightness or lower. In other words, adder circuit (arithmetic processing circuit)
2682 analyzes the average brightness distribution of the image 21, the distribution state of the image data, and the like.

[1550] The gate driver control circuit 2683 accumulates the calculation result (processing result) from the calculation processing circuit 2682 over a plurality of frames and applies the ST data to the shift register 22 of the gate driver 12 or the ON / OFF data of the lighting control line 1791. Is sent.

[1551] For example, if the brightness of the screen is adjusted by the control of the shift register 22, it becomes as shown in FIG. When the image is darkened, the number of ST data applied to the shift register 22 is reduced as shown in FIG. Therefore, the proportion of the lighting area 311 in the display area 21 decreases and the display area 21 becomes dark. When the display image 21 is relatively brightened, the width of the lighting area 312 in FIG. 273 (b) is increased or the number of the lighting areas 312 is increased. Further, when the display image 21 is made brighter, the width of the lighting region 312 in FIG. 273 (c) is further increased, or the number of the lighting regions 312 is further increased. Note that the above processing is performed by the block 1981 in FIG. 261.
It is obvious that the selection process can also be realized. Therefore, the description is omitted.

[1552] Also, whether the image data is a moving image or a still image is detected (moving image detection and ID processing are performed), and FIG.
The number of the three lighting areas 312 may be adjusted. That is, in the case of a moving image, the number of lighting regions 312 is reduced to eliminate moving image blur. In the case of a still image, the number of lighting areas 312 is increased and the lighting areas are dispersed in the display area 21 in order to suppress the occurrence of flicker.

[1553] In FIG. 262, the number of pieces of image data having a predetermined brightness or higher is counted to control the brightness of the display screen 21, but as in FIG. 268, the characteristics of the image are extracted and the brightness of the display screen 21 is extracted. May be changed. This embodiment is shown in FIG. 269. It goes without saying that the embodiments of FIGS. 268 and 269 may be combined.

[1554] FIG. 269 is an explanatory diagram of the embodiment. The frame (field) memory 2621 has two areas (2
621a, 2621b), each of which is 1
It can hold the image data of the screen. The memory 2621a and the memory 2621b are selected alternately. For example, when the image data is being read from the memory 2621a to the data conversion circuit 2692, the image data is written to the memory 2621b from a microcomputer (not shown). On the contrary, when the image data is being read from the memory 2621b to the data conversion circuit 2692, the image data is written in the memory 2621a from a microcomputer (not shown). The above items are the same as in FIG. 262 or FIG. 268.

[1555] DATA5 of MSB of image data DATA (5: 0) is counted by the counter circuit 2682a. The larger the count value of the counter circuit 2862a, the more image data the image brightness is high.
As in the case of the addition circuit (arithmetic processing circuit) 2682b, the image 21 is divided into a plurality of blocks, and the average luminance distribution is processed in each block. In addition, the arithmetic processing circuit 26
Reference numeral 82c calculates the distribution state of image data having a predetermined brightness or higher and the distribution state of image data having a predetermined brightness or lower. That is, the adder circuit (arithmetic processing circuit) 2
Reference numeral 682 is for analyzing the average brightness distribution of the image 21, the distribution state of the image data, and the like.

The data control circuit 2691 accumulates the calculation result (processing result) from the calculation processing circuit 2682 over a plurality of frames, controls the data conversion circuit 2692,
Convert image data.

For example, if the brightness of the screen is adjusted, the size of the image data obtained by bit-shifting the data is converted as in the case of FIG. 262. At the same time, based on the analysis result of the image data, optimum gamma conversion processing is performed as shown in FIG.

[1558] FIG. 274 is a gamma table. The horizontal axis represents the gradation number, and the vertical axis represents the relative value of the display brightness. The dotted line in FIG. 274 is a linear case, and the solid line is a case where gradation collapse is generated in the black display area and the white display area. Also, the alternate long and short dash line indicates the case where the gradation collapse occurs only in the black gradation part.

[1558] As described above, the arithmetic processing circuit 2682 extracts the feature of the image, and based on the result, the gamma curve of the display image is selected and the data table conversion is performed. Providing three or more types of gamma tables, select the most suitable one. Then, the converted image data is input to the source driver 14.

Further, as described with reference to FIG. 273, when the image is darkened, the number of ST data applied to the shift register 22 is reduced as shown in FIG. 273 (a).
Therefore, the proportion of the lighting area 311 in the display area 21 decreases and the display area 21 becomes dark. When the display image 21 is relatively brightened, the width of the lighting area 312 in FIG. 273 (b) is increased or the number of the lighting areas 312 is increased.
Further, when the display image 21 is brightened, the display image shown in FIG.
The width of the lighting area 312 in (c) is further increased, or the number of the lighting areas 312 is further increased. In order to make the displayed image appear relatively bright with low power consumption, the maximum brightness of the display brightness is lowered and the minimum brightness is increased (that is, the contrast of the image is decreased).
Moreover, it is preferable to reduce the average brightness of the whole.

[1561] Also, whether the image data is a moving image or a still image is detected (moving image detection and ID processing are performed), and FIG.
The number of the three lighting areas 312 may be adjusted. That is, in the case of a moving image, the number of lighting regions 312 is reduced to eliminate moving image blur. In the case of a still image, the number of lighting areas 312 is increased and the lighting areas are dispersed in the display area 21 in order to suppress the occurrence of flicker.

[1562] In FIG. 261, the display areas are 21a, 21b,
Although the display brightness of the display area 21a is changed to three areas 21c, it is not limited to this, and the display areas 21b and 21c may be changed.

Also, as shown in FIG. 263, display areas 21d and 21e may be provided at the ends of the display area. The display areas 21d and 21e are displayed as a simple frame (that is, a pixel electrode is formed and a dot pattern cannot be displayed). Therefore, the display areas 21d, 21
e is a simple matrix-like display. That is, 21
When a voltage is applied to d and 1e, the entire area is lit.

[1564] As shown in FIG. 265, the lighting control line 1
When a voltage is applied to 791a, the EL film in the region 21d lights up. Further, when a voltage is applied to the lighting control line 1791b, the EL film in the region 21e lights up. Other configurations (189
(1 etc.) has been described previously, and therefore description thereof will be omitted.

As shown in FIG. 264, the planarization film 7 is formed on the gate driver circuit 12 formed by the polysilicon technique.
1 is formed. An electrode 48b made of the same material as the pixel electrode 48a is formed on this, and an EL element is formed on the electrode 48b.
The film 47 is formed. A cathode electrode (or an anode electrode) is formed on the EL film 47. Electrode 48b
By applying a voltage to the areas 21d and 21e, the areas 21d and 21e are turned on.

In the above embodiments, the EL element 15 is R,
It is assumed that G and B are set, but the present invention is not limited to this. For example, cyan, yellow, magenta, or any two colors may be used. Six colors of R, G, B, cyan, yellow, and magenta, or any four or more colors may be used. Further, it may be white monochromatic light, or white monochromatic light may be converted into RGB by a color filter. Further, it is not limited to the organic EL element, and may be an inorganic EL element.

In the liquid crystal display panel of the present invention or the display device using the same, it is preferable that a plurality (a plurality of types) of driver circuits 12 and 14 are integrated. By doing so, it will be possible to display images that come in from any communication network, such as videos and still images downloaded from mobile phone networks or wireless LANs, images that receive terrestrial TV broadcasts, etc. without burdening the MPU. Become. High-definition images are displayed using VGA-compatible 6-bit driver circuits 12 and 14. Switch to QVGA if the definition is reduced, and 1 if text data.
The bit driver circuits 12 and 14 are used. It is also preferable to separately form a driver for NTSC display (interlace, pseudo-interlace scanning) and a driver for progressive display (non-interlace). Needless to say, the drivers 12 and 14 having these plural functions may be formed of silicon chips and mounted by COG technology or the like.

[1568] Note that the active matrix display panel is described as an example in FIGS. 87 and 88, but the present invention is not limited to this. From the source driver IC 14 or the like, N times the predetermined current is applied to (source of) the source signal line 18. In addition, a plurality of pixel rows are simultaneously selected. The concept that a current is passed through the EL element only during a predetermined period and no current is passed during other periods can be applied to a simple matrix display panel.

When there is one type of driver circuit 12, 14,
It is necessary to execute signal conversion processing by the MPU in order to display images with different definition. When preparing a large number of driver circuits 12 and 14 other than the liquid crystal display panel, individually
Since it is necessary to mount, the cost increases and the mounting area increases. In addition, the driver circuit 12,
Panel 8 including not only 14 but also many circuits such as image processing circuits
2 may be integrated in the Si film.

[1570] In addition, the EL element has a large characteristic change in the initial stage of lighting. Therefore, burning and the like are likely to occur. As a countermeasure, it is preferable to perform aging with white raster display for 20 hours to 150 hours after the panel is formed, and then ship the product as a product. In this aging, it is preferable to display with a brightness which is about 2-10 times higher than the predetermined display brightness.

[1571] Note that the present invention is based on FIG. 54, FIG. 67, and FIG.
The pixel configuration described in 3 and the like will be described focusing on the pixel configuration of the voltage program and the pixel configuration of the current program described in FIGS. 1, 21, 43, and 71, and each pixel is synchronized with the 1H period. Then, a signal is supplied from the source driver circuit 14 and written. However, the present invention is not limited to this. For example, one frame or one field may be divided into a plurality of subframes (fields) and driven in combination with time division driving. Also, 1
An area gradation method in which a pixel is divided into a plurality of pixels may be combined.

[1572] FIG. 2, FIG. 35, FIG. 60, FIG. 74, FIG.
31, 32, 56, 61, 89 to 10
The driving (display) method and the driving circuit have been described with reference to FIGS. 1, 104, 105, 106, and the like. A semiconductor chip made of gallium arsenide, silicon, germanium or the like that realizes these technical ideas is also within the scope of the present invention. A display device, an information display device, and the like can be realized by mounting these semiconductor chips on a display panel.

[1573] Also, FIG. 1 (b), FIG. 22, FIG. 75, and FIG.
6, FIG. 77, FIG. 78, and other terminals for applying Vbb are shown in FIG.
By connecting to the gate driver circuit 12b described in 4, it is possible to realize a good image display.

Also, the matters concerning the power supply voltage Vdd described in FIGS. 79 and 80 are also applied to all pixel configurations, display panels, information display devices or driving methods in this specification. In addition, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG.
20, 25, 26, 27, 28, 29, 30, 45, 46, 47, 48, 86 and 8.
9 to 101, 110 to 114, etc., all pixel configurations or driver arrangements in this specification,
It goes without saying that it is applied to a display panel, an information display device, or a driving method.

The driving method and the driving circuit of the present invention described with reference to FIGS. 87, 88, and 134 to 167, and FIGS.
The combination of the method or the configuration of applying a reverse bias to the EL element 15 described with reference to FIGS. In addition, these are shown in FIG. 1, FIG. 21, FIG. 43, FIG. 71, FIG. 22, FIG.
67, 68, 103, 107, 108, and 8
It goes without saying that the present invention can be applied to the pixel configurations described with reference to FIGS. 9 to 101, 115, 171 to 174, FIG. 21, FIG. 43, and 710. Also, with these configurations,
31, 32 to 39, 61 to 67, and FIG.
It is also not necessary to explain that FIG. 4, FIG. 105, FIG. 106, etc. can be realized. It goes without saying that it is also effective to combine the configurations with the three sides free of FIGS. 26 to 30 and 110 to 114. In addition, by using these techniques, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG.
14, FIG. 15, FIG. 18, FIG. 20, FIG. 25, FIG. 26, FIG. 27, FIG. 28, FIG. 29, FIG. 30, FIG.
It is needless to say that the present invention can be applied to the display panel, information display device or driving method of FIGS. 7, 48, 86, 89 to 101, 110 to 114 and the like.

Also, the method or configuration for applying a reverse bias to the EL element 15 described with reference to FIGS. 52, 89 to 102, etc. is also shown in FIGS. 1, 21, 43, 71, 43.
71, 22, FIG. 44, FIG. 31, FIG. 40, FIG. 41, FIG. 42, FIG. 43, FIG. 44, FIG. 53, FIG. 54, FIG.
9, FIG. 60, FIG. 67 to FIG. 78, FIG. 89 to FIG.
103, 119 to 121, and 171 to 17
It goes without saying that the present invention can be applied to the pixel configuration or the array configuration shown in FIG. 4, FIG. 21, FIG. 43, FIG. Further, with these configurations, FIG. 31, FIG. 32 to FIG. 39, and FIG.
It is not necessary to explain that 1 to FIG. 67, FIG. 104, FIG. 105, FIG. 26 to 30, FIG. 110 to FIG. 114, FIG. 179 to FIG. 192, FIG.
It goes without saying that combining with the three-side free configuration of FIGS. 43, 711 to 21, 43, 714 and the like is also effective. In particular, the three-side free structure is effective when the pixel is manufactured by using the amorphous silicon technology. Further, in a panel formed by the amorphous silicon technology, it is preferable to carry out the current drive of the present invention because the process control of the characteristic variation of the TFT element is impossible.

[1577] Furthermore, by using these techniques, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG.
4, FIG. 15, FIG. 18, FIG. 20, FIG. 25, FIG. 26, FIG.
7, FIG. 28, FIG. 29, FIG. 30, FIG. 45, FIG. 46, FIG.
It is needless to say that the present invention can be applied to the display panel, information display device or driving method of FIGS. 7, 48, 86, 89 to 101, 110 to 114 and the like.

[1578] FIG. 107, FIG. 108, FIG. 89 to FIG.
The pixel configuration or the driving method described in FIG. 1, FIG. 115, and the like are not limited to the EL display panel. For example, it can be applied to a liquid crystal display panel. In that case, E
The L element 15 may be replaced with a liquid crystal layer, a light modulation layer such as PLZT or LED. For example, in the case of liquid crystal, TN
(Twisted Nematic), IPS (In-
Plane Switching, FLC (Ferr)
oelectric Liquid Crystal
l), OCB (Optically Compensat)
ory Bend), STN (Super Twis)
ted Nematic), VA (Vertical all)
y Aligned), ECB (Electrical)
ly Controlled Birefringen
ce) and HAN (Hybrid Aligned)
Nematic mode, DSM mode (dynamic scattering mode), and the like. In particular, the DSM can be optically modulated by the applied current, so that it is well matched with the present invention.

[1579] Also, regarding the switching element 11, T
It is not limited to FT. Further, it goes without saying that the present invention is applied to all pixel configurations, driver arrangements, display panels, information display devices or driving methods in this specification.

[1580] FIG. 1, FIG. 21, FIG. 43, FIG. 71, FIG.
44, FIG. 31, FIG. 40, FIG. 41, FIG. 42, FIG. 43, FIG. 44, FIG. 53, FIG. 54, FIG. 58, FIG. 59, FIG.
7 to 78, 89 to 101, 103, and 11
0 to FIG. 114, FIG. 119 to FIG. 121, FIG. 171, FIG. 174, FIG. 21, FIG. 43, FIG.
3, FIG. 710, FIG. 221 to FIG. 260, FIG. 267, FIG.
The pixel configuration or array configuration of 91, FIG. 292, and FIG. 294 is not limited to the EL display panel. For example, it can be applied to a liquid crystal display panel. In that case, the EL element 15 is connected to the liquid crystal layer, PLZT, L
It may be replaced with an optical modulation layer such as ED. The switching element 11 is not limited to the TFT as described above with reference to FIG. 80 and the like.

[1581] Also, FIG. 15, FIG. 19, FIG.
25, FIG. 26, FIG. 28, FIG. 45, FIG. 46, FIG. 47, FIG. 48, FIG. 110 to FIG. 114, FIG. 261, FIG. 264, FIG. 266, FIG. 283 to FIG. The invention is not limited to the one using the display panel. For example, it can be applied to those using a PDP display panel, a PLZT display panel, a liquid crystal display panel and the like.

[1582] Figs. 22, 23, 286 to 288,
1 and 2 by using the manufacturing method of FIG.
1, FIG. 43, FIG. 71, FIG. 22, FIG. 44, FIG. 31, and FIG.
0, FIG. 41, FIG. 42, FIG. 43, FIG. 44, FIG. 53, FIG.
4, FIG. 58, FIG. 59, FIG. 60, FIG. 67 to FIG. 78, FIG.
9 to 101, 103, 119 to 121, 171 to 175, 21, 43, 710 and 2
21 to FIG. 260, FIG. 267, FIG. 283 to FIG. 285,
A display panel having a pixel structure or an array structure as shown in FIGS. 291, 292, and 294 can be easily manufactured. Further, an information display device can be configured using these. Needless to say, the configurations or structures of FIGS. 280 to 285 and 289 can be applied to the display panel or display device of the present invention.

[1583] Further, FIGS. 248 to 255, 309 to 350, 355 to 359, 360, and 36.
1, FIG. 366, and FIG. 367, or the driving method thereof, the pixel structure is as shown in FIGS.
1, FIG. 22, FIG. 44, FIG. 31, FIG. 40, FIG. 41, FIG.
2, FIG. 43, FIG. 44, FIG. 53, FIG. 54, FIG. 58, FIG.
9, FIG. 60, FIG. 67 to FIG. 78, FIG. 89 to FIG.
103, 119 to 121, and 171 to 17
5, FIG. 21, FIG. 43, FIG. 710, FIG. 21, FIG. 43, FIG.
It goes without saying that any of the configurations of FIG. 10, FIG. 221, FIG. 221 to FIG. 260, FIG. 267, FIG. 283 to FIG. 285, FIG. 291, FIG. 292, FIG. 294, FIG.

[1584] Also, the driver I of FIG. 351 to FIG.
It goes without saying that the C circuit can be applied to any of the above pixel configurations or display panels. It is needless to say that the structure or structure of the display panel in FIGS. 362 to 365 can be applied to any of the above pixel structures, and can be applied to any driving circuit and driving method.

1, FIG. 21, FIG. 43, FIG. 71, FIG.
44, FIG. 31, FIG. 40, FIG. 41, FIG. 42, FIG. 43, FIG. 44, FIG. 53, FIG. 54, FIG. 58, FIG. 59, FIG.
7 to 78, 89 to 101, 103, and 11
9 to 121, 171 to 175, 21 and 4
3, FIG. 710, FIG. 221 to FIG. 260, FIG. 267, FIG.
The pixel configuration or array configuration such as 91, FIG. 292, and FIG. 294 is shown in FIG. 203, FIG. 204, FIG. 205, FIG.
It goes without saying that the present invention can be applied to the information display devices shown in FIGS. 265, 261, and 263.

[1586] FIG. 1, FIG. 21, FIG. 43, FIG. 71, FIG. 44, FIG. 31, FIG. 40, FIG.
4, FIG. 53, FIG. 54, FIG. 58, FIG. 59, FIG. 60, FIG.
To FIG. 78, FIG. 89 to FIG. 101, FIG. 103, and FIG.
To FIG. 121, FIG. 171 to FIG. 174, FIG.
3, FIG. 710, FIG. 221 to FIG. 260, FIG. 267, FIG.
83 to FIG. 285, FIG. 291, FIG. 292, and the like have pixel configurations or array configurations shown in FIG.
8, FIG. 25, FIG. 26, FIG. 28, FIG. 45, FIG. 46, FIG.
7, FIG. 48, FIG. 110 to FIG. 114, and FIG. 198 to FIG.
09, FIG. 21, FIG. 43, FIG. 715 to FIG. 220, FIG.
1, FIG. 43, FIG. 710, FIG. 221, FIG.
It goes without saying that it can be adopted in FIG. 7, FIG. 291, FIG. 292, and FIG.

[1587] In addition, the source driver configuration shown in FIGS. 275, 276 and 293 and the current output circuit 1222 shown in FIGS.
1, FIG. 43, FIG. 71, FIG. 22, FIG. 44, FIG. 31, and FIG.
0, FIG. 41, FIG. 42, FIG. 43, FIG. 44, FIG. 53, FIG.
4, FIG. 58, FIG. 59, FIG. 60, FIG. 67 to FIG. 78, FIG.
9 to 101, 103, 119 to 121, 171 to 174, 21, 43, 710, 2
21 to FIG. 260, FIG. 267, FIG. 283 to FIG. 285,
It goes without saying that it can be applied to FIGS. 291, 292, and the like. Similarly, FIG. 229, FIG. 231 to FIG. 232, FIG.
37 to FIG. 238, FIG. 240 to FIG. 241, FIG. 252,
262, 268 to 269, and 271 to 27
It goes without saying that the present invention can be applied to the driving method or the data processing method shown in FIGS. 2 and 273 to 274. The same applies to the driving method and the pixel configuration described with reference to FIGS. 248 to 255. Further, it goes without saying that an information display device or the like can be configured using these.

[1588] FIGS. 23, 24, 286 to 288,
The manufacturing method shown in FIG. 290 is not limited to the manufacturing method of the EL display panel. For example, it goes without saying that it can be applied to a method of manufacturing a liquid crystal display panel. Further, it is needless to say that the configurations or methods shown in FIGS. 26 to 30 and 110 to 114 are not limited to the EL display panel but can be applied to an LED display panel, a liquid crystal display panel and the like. 31 and 3
2 to FIG. 39, FIG. 61 to FIG. 67, FIG. 104, and FIG.
The same applies to the display methods shown in FIG. 5, FIG. 106, FIG. 261, FIG. 263, FIG.

The technical ideas described in the embodiments of the present invention can be applied to a video camera, a projector, a stereoscopic television, a projection television, and the like. Further, it is also applicable to a viewfinder, a mobile phone monitor, a PHS, a personal digital assistant and its monitor, a digital camera and its monitor.

Also, the present invention can be applied to an electrophotographic system, a head mounted display, a direct view monitor display, a notebook personal computer, a video camera, an electronic still camera. Also, monitors of cash drawers, payphones, videophones, personal computers,
It can also be applied to a wristwatch and its display device.

It is needless to say that the present invention can be applied or applied to a display monitor of home electric appliances, a pocket game machine and its monitor, a backlight for a display panel or a lighting device for home or business use. It is preferable that the lighting device is configured so that the color temperature can be changed. In this, the color temperature can be changed by forming RGB pixels in a stripe shape or a dot matrix shape and adjusting the current flowing through these. Further, the present invention can be applied to display devices for advertisements or posters, RGB traffic lights, alarm indicators, etc.

Also, the organic EL panel is effective as the light source of the scanner. The object is irradiated with light using the RGB dot matrix as a light source to read an image. Of course, it is needless to say that it may be a single color. Further, the matrix is not limited to the active matrix, and a simple matrix may be used. If the color temperature can be adjusted, the image reading accuracy will be improved.

[1593] Further, the organic EL display device is also effective for the backlight of the liquid crystal display device. It is possible to change the color temperature and easily adjust the brightness by forming the RGB pixels of the EL display device (backlight) in a stripe shape or a dot matrix shape and adjusting the current flowing through them. In addition, since it is a surface light source, a Gaussian distribution that brightens the central part of the screen and darkens the peripheral part can be easily configured. It is also effective as a backlight for a field-sequential liquid crystal display panel that alternately scans R, G, and B lights. Further, even if the backlight blinks, by inserting black, it can be used as a backlight for a liquid crystal display panel for displaying moving images.

[1594]

EFFECTS OF THE INVENTION The display panel, display device, and the like of the present invention have high image quality, good moving image display performance, low power consumption, and low cost.
A characteristic effect is exhibited according to each structure such as high brightness.

By using the present invention, a low power consumption information display device or the like can be formed, so that power consumption is not performed.
In addition, since the size and weight can be reduced, resources are not consumed. Further, even a high-definition display panel can be sufficiently dealt with.
Therefore, it is friendly to the global environment and space environment.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a display panel of the present invention.

FIG. 2 is a circuit configuration diagram of a display device of the present invention.

FIG. 3 is an explanatory diagram of a display device of the present invention.

FIG. 4 is a sectional view of a display device of the present invention.

FIG. 5 is an explanatory diagram of a display device of the present invention.

FIG. 6 is an explanatory diagram of a display device of the present invention.

FIG. 7 is a cross-sectional view of a display device of the present invention.

FIG. 8 is a sectional view of a display device of the present invention.

FIG. 9 is a sectional view of a display device of the present invention.

FIG. 10 is a configuration diagram of a display device of the present invention.

FIG. 11 is a configuration diagram of a display device of the present invention.

FIG. 12 is a circuit configuration diagram of a conventional display panel.

FIG. 13 is an explanatory diagram of a display panel of the present invention.

FIG. 14 is an explanatory diagram of a display device of the present invention.

FIG. 15 is an explanatory diagram of a display device of the present invention.

FIG. 16 is an explanatory diagram of a data transmission method of the display device of the present invention.

FIG. 17 is an explanatory diagram of a data transmission method of a display device of the present invention.

FIG. 18 is an explanatory diagram of a data transmission method of the display device of the present invention.

FIG. 19 is a plan view of the information display device of the present invention.

FIG. 20 is an explanatory diagram of an information display device of the present invention.

FIG. 21 is an explanatory diagram of a display panel of the present invention.

FIG. 22 is an explanatory diagram of a display panel of the present invention.

FIG. 23 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 24 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 25 is a sectional view of a display panel of the present invention.

FIG. 26 is an explanatory diagram of a display panel of the present invention.

FIG. 27 is an explanatory diagram of a display panel of the present invention.

FIG. 28 is an explanatory diagram of a display panel of the present invention.

FIG. 29 is an explanatory diagram of a display panel of the present invention.

FIG. 30 is an explanatory diagram of a display panel of the present invention.

FIG. 31 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 32 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 33 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 34 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 35 is a circuit block diagram of a display panel of the present invention.

FIG. 36 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 37 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 38 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 39 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 40 is an explanatory diagram of a display panel of the present invention.

FIG. 41 is an explanatory diagram of a display panel of the present invention.

42 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 43 is an explanatory diagram of a display panel of the present invention.

FIG. 44 is an explanatory diagram of a display panel of the present invention.

FIG. 45 is a sectional view of the viewfinder of the present invention.

FIG. 46 is a perspective view of the video camera of the present invention.

FIG. 47 is a perspective view of the electronic camera of the present invention.

FIG. 48 is an explanatory diagram of the television of the present invention.

FIG. 49 is an explanatory diagram of the television of the present invention.

FIG. 50 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 51 is an explanatory diagram of a display panel driving method of the present invention.

52 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 53 is an explanatory diagram of a display panel of the present invention.

FIG. 54 is an explanatory diagram of a display panel of the present invention.

FIG. 55 is an explanatory diagram of a display panel of the present invention.

FIG. 56 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 57 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 58 is an explanatory diagram of a display panel of the present invention.

FIG. 59 is an explanatory diagram of a display panel of the present invention.

FIG. 60 is a circuit block diagram of a display panel of the present invention.

FIG. 61 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 62 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 63 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 64 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 65 is an explanatory diagram of a display panel driving method of the present invention.

66 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 67 is an explanatory diagram of a display panel of the invention.

FIG. 68 is an explanatory diagram of a display panel of the present invention.

FIG. 69 is an explanatory diagram of a display panel of the present invention.

FIG. 70 is an explanatory diagram of a display panel of the present invention.

FIG. 71 is an explanatory diagram of a display panel of the present invention.

FIG. 72 is an explanatory diagram of a display panel of the present invention.

FIG. 73 is an explanatory diagram of a display panel of the present invention.

FIG. 74 is a circuit block diagram of a display panel of the present invention.

FIG. 75 is an explanatory diagram of a display panel of the present invention.

FIG. 76 is an explanatory diagram of a display panel of the present invention.

77 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 78 is an explanatory diagram of a display panel of the present invention.

FIG. 79 is an explanatory diagram of a display panel of the present invention.

FIG. 80 is an explanatory diagram of a display panel of the present invention.

FIG. 81 is an explanatory diagram of a display panel of the present invention.

FIG. 82 is an explanatory diagram of a display panel of the present invention.

FIG. 83 is an explanatory diagram of a display panel of the present invention.

FIG. 84 is a circuit block diagram of a display panel of the present invention.

FIG. 85 is an explanatory diagram of an information display device of the present invention.

FIG. 86 is an explanatory diagram of the information display device of the present invention.

FIG. 87 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 88 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 89 is an explanatory diagram of a display panel of the present invention.

FIG. 90 is an explanatory diagram of a display panel of the present invention

FIG. 91 is an explanatory diagram of a display panel of the present invention.

92 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 93 is an explanatory diagram of a display panel of the present invention

FIG. 94 is an explanatory diagram of a display panel of the present invention

FIG. 95 is an explanatory diagram of a display panel of the present invention.

FIG. 96 is an explanatory diagram of a display panel of the present invention

FIG. 97 is an explanatory diagram of a display panel of the present invention

FIG. 98 is an explanatory diagram of a display panel of the present invention.

99 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 100 is an explanatory diagram of a display panel of the present invention

101 is an explanatory diagram of a display panel of the present invention. FIG.

102 is an explanatory diagram of a display panel of the present invention. FIG.

103 is an explanatory diagram of a display panel of the invention. FIG.

FIG. 104 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 105 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 106 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 107 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 108 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 109 is an explanatory diagram of a display panel driving method of the present invention.

110 is an explanatory diagram of a display panel driving method of the present invention. FIG.

111 is an explanatory diagram of a display panel of the present invention. FIG.

112 is an explanatory diagram of a display panel of the present invention. FIG.

113 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 114 is an explanatory diagram of a display panel of the present invention.

FIG. 115 is an explanatory diagram of a display panel of the present invention.

FIG. 116 is an explanatory diagram of a pixel structure of a display panel of the present invention.

117 is an explanatory diagram of a pixel configuration of a display panel of the present invention. FIG.

FIG. 118 is an explanatory diagram of a pixel structure of a display panel of the present invention.

FIG. 119 is an explanatory diagram of a pixel structure of a display panel of the present invention.

120 is an explanatory diagram of a pixel structure of a display panel of the present invention. FIG.

FIG. 121 is an explanatory diagram of a pixel structure of a display panel of the present invention.

FIG. 122 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 123 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 124 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 125 is an explanatory diagram of a display panel driving method of the present invention.

126 is an explanatory diagram of a display panel driving method of the present invention. FIG.

127 is an explanatory diagram of a display panel of the present invention. FIG.

128 is an explanatory diagram of a display panel of the invention. FIG.

FIG. 129 is an explanatory diagram of a display panel of the present invention.

FIG. 130 is an explanatory diagram of a display panel of the present invention.

131 is an explanatory diagram of a display panel of the invention. FIG.

132 is an explanatory diagram of a display panel of the invention. FIG.

133 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 134 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 135 is an explanatory diagram of a display panel driving method of the present invention

FIG. 136 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 137 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 138 is an explanatory diagram of a display panel driving method of the present invention;

FIG. 139 is an explanatory diagram of a driving method of a display panel of the present invention.

FIG. 140 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 141 is an explanatory diagram of a display panel driving method of the present invention.

142 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 143 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 144 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 145 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 146 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 147 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 148 is an explanatory diagram of a drive circuit of a display panel of the present invention.

FIG. 149 is an explanatory diagram of a drive circuit of a display panel of the present invention.

FIG. 150 is an explanatory diagram of a drive circuit of a display panel of the present invention.

FIG. 151 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 152 is an explanatory diagram of a display panel driving method of the present invention

FIG. 153 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 154 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 155 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 156 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 157 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 158 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 159 is an explanatory diagram of a display panel driving method of the present invention;

160 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 161 is an explanatory diagram of a display panel driving method of the present invention.

162 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 163 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 164 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 165 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 166 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 167 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 168 is an explanatory diagram of a display panel of the present invention.

FIG. 169 is an explanatory diagram of a display panel of the present invention.

170 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 171 is an explanatory diagram of a display panel of the present invention

FIG. 172 is an explanatory diagram of a display panel of the present invention.

FIG. 173 is an explanatory diagram of a display panel of the present invention

FIG. 174 is an explanatory diagram of a display panel of the present invention.

FIG. 175 is an explanatory diagram of a display panel of the present invention.

FIG. 176 is an explanatory diagram of a display panel of the present invention.

FIG. 177 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 178 is an explanatory diagram of a display panel of the present invention.

FIG. 179 is an explanatory diagram of a display panel of the present invention

180 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 181 is an explanatory diagram of a display panel of the present invention

FIG. 182 is an explanatory diagram of a display panel of the present invention.

FIG. 183 is an explanatory diagram of a display panel of the present invention.

FIG. 184 is an explanatory diagram of a display panel of the present invention.

FIG. 185 is an explanatory diagram of a display panel of the present invention.

FIG. 186 is an explanatory diagram of a display panel of the present invention.

FIG. 187 is an explanatory diagram of a display panel of the present invention

FIG. 188 is an explanatory diagram of a display panel of the present invention.

FIG. 189 is an explanatory diagram of a display panel of the present invention

190 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 191 is an explanatory diagram of a display panel of the present invention

FIG. 192 is an explanatory diagram of a display panel of the present invention.

FIG. 193 is an explanatory diagram of a display panel of the present invention

FIG. 194 is an explanatory diagram of a display panel of the present invention.

FIG. 195 is an explanatory diagram of a display panel of the present invention.

FIG. 196 is an explanatory diagram of a display panel of the present invention.

FIG. 197 is an explanatory diagram of a display panel of the present invention

FIG. 198 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 199 is an explanatory diagram of a driving method of a display panel of the present invention.

200 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 201 is an explanatory diagram of a display panel driving method of the present invention.

202 is an explanatory diagram of a display panel driving method of the present invention. FIG.

203 is an explanatory diagram of a display panel of the invention. FIG.

FIG. 204 is an explanatory diagram of an information display device of the present invention.

205 is an explanatory diagram of an information display device of the present invention. FIG.

206 is an explanatory diagram of an information display device of the present invention. FIG.

FIG. 207 is an explanatory diagram of a driving method of a display device of the present invention.

208 is an explanatory diagram of a driving method of a display device of the present invention. FIG.

FIG. 209 is an explanatory diagram of a driving method of a display device of the present invention.

210 is an explanatory diagram of a display panel unit of the present invention. FIG.

211 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 212 is an explanatory diagram of a display panel of the invention.

FIG. 213 is an explanatory diagram of a display panel of the present invention.

FIG. 214 is an explanatory diagram of a display panel of the present invention.

FIG. 215 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 216 is an explanatory diagram of a display panel driving method of the present invention.

217 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 218 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 219 is an explanatory diagram of a driving method of a display panel of the present invention.

220 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 221 is an explanatory diagram of a display panel of the present invention.

222 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 223 is an explanatory diagram of a display panel of the present invention.

[FIG. 224] An explanatory diagram of a display panel of the present invention

FIG. 225 is an explanatory diagram of a display panel of the present invention

FIG. 226 is an explanatory diagram of a display panel of the present invention.

FIG. 227 is an explanatory diagram of a display panel of the present invention

FIG. 228 is an explanatory diagram of a display panel of the present invention.

FIG. 229 is an explanatory diagram of a display panel of the present invention

FIG. 230 is an explanatory diagram of a display panel of the present invention.

FIG. 231 is an explanatory diagram of a display panel of the present invention.

FIG. 232 is an explanatory diagram of a display panel of the present invention.

FIG. 233 is an explanatory diagram of a display panel of the present invention

FIG. 234 is an explanatory diagram of a display panel of the present invention

FIG. 235 is an explanatory diagram of a display panel of the present invention.

FIG. 236 is an explanatory diagram of a display panel of the present invention.

FIG. 237 is an explanatory diagram of a display panel of the present invention

FIG. 238 is an explanatory diagram of a display panel of the present invention.

FIG. 239 is an explanatory diagram of a display panel of the present invention

240 is an explanatory diagram of a display panel of the invention. FIG.

FIG. 241 is an explanatory diagram of a display panel of the present invention

FIG. 242 is an explanatory diagram of a display panel of the present invention.

FIG. 243 is an explanatory diagram of a display panel of the present invention

FIG. 244 is an explanatory diagram of a display panel of the present invention

FIG. 245 is an explanatory diagram of a display panel of the present invention

[FIG. 246] An explanatory diagram of a display panel of the present invention

FIG. 247 is an explanatory diagram of a display panel of the present invention

[FIG. 248] An explanatory diagram of a display panel of the present invention

FIG. 249 is an explanatory diagram of a display panel of the present invention

FIG. 250 is an explanatory diagram of a display panel of the present invention

FIG. 251 is an explanatory diagram of a display panel of the present invention.

FIG. 252 is an explanatory diagram of a display panel of the present invention.

[FIG. 253] An explanatory diagram of a display panel of the present invention

FIG. 254 is an explanatory diagram of a display panel of the present invention.

255 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 256 is an explanatory diagram of a display panel of the present invention.

FIG. 257 is an explanatory diagram of a display panel of the present invention

FIG. 258 is an explanatory diagram of a display panel of the present invention.

FIG. 259 is an explanatory diagram of a display panel of the present invention

260 is an explanatory diagram of a display panel of the present invention. FIG.

[FIG. 261] An explanatory diagram of a display panel of the present invention

FIG. 262 is an explanatory diagram of a display panel of the present invention.

FIG. 263 is an explanatory diagram of a display panel of the present invention.

FIG. 264 is an explanatory diagram of a display panel of the present invention.

FIG. 265 is an explanatory diagram of a display panel of the present invention.

FIG. 266 is an explanatory diagram of a display panel of the present invention.

FIG. 267 is an explanatory diagram of a display panel of the present invention

FIG. 268 is an explanatory diagram of a display panel of the present invention.

FIG. 269 is an explanatory diagram of a display panel of the present invention

FIG. 270 is an explanatory diagram of a display panel of the present invention.

271 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 272 is an explanatory diagram of a display panel of the present invention

[FIG. 273] An explanatory diagram of a display panel of the present invention

[FIG. 274] An explanatory diagram of a display panel of the present invention

FIG. 275 is an explanatory diagram of a display panel of the present invention

[FIG. 276] An explanatory diagram of a display panel of the present invention

FIG. 277 is an explanatory diagram of a display panel of the present invention

FIG. 278 is an explanatory diagram of a display panel of the present invention.

FIG. 279 is an explanatory diagram of a display panel of the present invention

[FIG. 280] An explanatory diagram of a display panel of the present invention

FIG. 281 is an explanatory diagram of a display panel of the present invention

282 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 283 is an explanatory diagram of a display panel of the present invention.

FIG. 284 is an explanatory diagram of a display panel of the present invention.

FIG. 285 is an explanatory diagram of a display panel of the present invention.

FIG. 286 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 287 is an explanatory diagram of the manufacturing method of the display panel of the present invention.

FIG. 288 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 289 is an explanatory diagram of a display panel of the present invention

[FIG. 290] FIG. 290 is an explanatory diagram of the manufacturing method of the display panel of the present invention.

FIG. 291 is an explanatory diagram of a display panel of the present invention

FIG. 292 is an explanatory diagram of a display panel of the present invention.

FIG. 293 is an explanatory diagram of a display panel of the present invention

FIG. 294 is an explanatory diagram of a display panel of the present invention

FIG. 295 is an explanatory diagram of a display panel of the present invention

FIG. 296 is an explanatory diagram of a display panel of the present invention.

FIG. 297 is an explanatory diagram of a display panel of the present invention

FIG. 298 is an explanatory diagram of a display panel of the present invention.

FIG. 299 is an explanatory diagram of a display panel of the present invention

FIG. 300 is an explanatory diagram of a display panel of the present invention

FIG. 301 is an explanatory diagram of a display panel of the present invention

302 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 303 is an explanatory diagram of a display panel of the present invention

FIG. 304 is an explanatory diagram of a display panel of the present invention

FIG. 305 is an explanatory diagram of a display panel of the present invention

FIG. 306 is an explanatory diagram of a display panel of the present invention

FIG. 307 is an explanatory diagram of a display panel of the present invention

[FIG. 308] An explanatory diagram of a display panel of the present invention

FIG. 309 is an explanatory diagram of a display panel of the present invention.

FIG. 310 is an explanatory diagram of a display panel of the present invention.

FIG. 311 is an explanatory diagram of a display panel of the present invention.

FIG. 312 is an explanatory diagram of a display panel of the present invention.

FIG. 313 is an explanatory diagram of a display panel of the present invention.

FIG. 314 is an explanatory diagram of a display panel of the present invention.

FIG. 315 is an explanatory diagram of a display panel of the present invention

FIG. 316 is an explanatory diagram of a display panel of the present invention

FIG. 317 is an explanatory diagram of a display panel of the present invention

FIG. 318 is an explanatory diagram of a display panel of the present invention.

FIG. 319 is an explanatory diagram of a display panel of the present invention

FIG. 320 is an explanatory diagram of a display panel of the present invention

FIG. 321 is an explanatory diagram of a display panel of the present invention

FIG. 322 is an explanatory diagram of a display panel of the present invention.

FIG. 323 is an explanatory diagram of a display panel of the present invention.

FIG. 324 is an explanatory diagram of a display panel of the present invention

FIG. 325 is an explanatory diagram of a display panel of the present invention

FIG. 326 is an explanatory diagram of a method for driving a display panel of the present invention.

FIG. 327 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 328 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 329 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 330 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 331 is an explanatory diagram of a display panel driving method of the present invention

FIG. 332 is an explanatory diagram of a display panel driving method of the present invention;

FIG. 333 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 334 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 335 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 336 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 337 is an explanatory diagram of a driving method of a display panel of the present invention.

FIG. 338 is an explanatory diagram of a driving method of a display panel of the present invention.

FIG. 339 is an explanatory diagram of a driving method of a display panel of the present invention.

FIG. 340 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 341 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 342 is an explanatory diagram of a display panel driving method of the present invention;

FIG. 343 is an explanatory diagram of a driving method of a display panel of the present invention.

FIG. 344 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 345 is an explanatory diagram of a driving method of a display panel of the present invention.

FIG. 346 is an explanatory diagram of a display panel driving method of the present invention;

FIG. 347 is an explanatory diagram of a method for driving a display panel of the present invention.

FIG. 348 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 349 is an explanatory diagram of a display panel driving method of the present invention;

FIG. 350 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 351 is an explanatory diagram of a display panel of the present invention

FIG. 352 is an explanatory diagram of a display panel of the present invention

FIG. 353 is an explanatory diagram of a display panel of the present invention.

FIG. 354 is an explanatory diagram of a display panel of the present invention.

FIG. 355 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 356 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 357 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 358 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 359 is an explanatory diagram of a display panel driving method of the present invention;

FIG. 360 is an explanatory diagram of a display panel of the present invention

FIG. 361 is an explanatory diagram of a display panel of the present invention

FIG. 362 is an explanatory diagram of a display panel of the present invention.

FIG. 363 is an explanatory diagram of a display panel of the present invention

FIG. 364 is an explanatory diagram of a display panel of the present invention.

FIG. 365 is an explanatory diagram of a display panel of the present invention.

FIG. 366 is an explanatory diagram of a display panel of the present invention.

FIG. 367 is an explanatory diagram of a display panel driving method of the present invention.

[Explanation of symbols]

11 TFT 12 Gate Driver 14 Source Driver 15 EL Element 16 Pixel 17 Gate Signal Line 18 Source Signal Line 19 Capacitor (Storage Capacitor, Capacitor) 20 Current Supply Line (Power Supply Line, Voltage Supply Line) 21 Display Area (Display Screen, Effective Display area) 23 Laser irradiation spot 41 Sealing lid (sealing material) 43, 44 Convex portion 45 Sealing material (material) 46 Reflective film 47 Organic EL (EL element) 48 Pixel electrode 49 Array substrate 50 λ / 4 plate (λ / 4 sheet) 51 cathode wiring 52 contact 53 cathode 54 polarizing plate 55 desiccant (drying material, moisture absorbing means) 61, 62 connection terminal 63 anode 71 smoothing film 72 transparent electrode 73 sealing film 74 circularly polarizing plate 81 edge protection film 91 Light shielding film 92 Low resistance wiring (metal film) 101 Control IC 102 Power supply IC 103 Pre Input board 104 Flexible board 105 Data signal 141 Error diffusion controller 151 Built-in display memory 152 Operation memory 153 Operation circuit 154 Buffer circuit 191 Antenna 192 Numeric keypad 193 Case 194 Button 201 Deplexer 202 LNA 203 LO buffer 204 Downconverter 205 Upconverter 206 PA converter Driver 207 PA 241 Glass substrate 242 Positioning marker 251 Convex portion 252 Concavo-convex portion (embossed portion) 14a 1 Chip driver IC 311 Image display area 312 Non-display area 351 Counter circuit 352 Luminance memory 353 CPU 354 Frame (field memory, SRAM) 355 Switching circuit 391 Write pixel row 392 Holding pixel row 401 Voltage source 402 Current source 403 Power supply switching hand 404 Floating capacitance (parasitic capacitance) 451 Body 452 Eyepiece ring 453 Magnifying lens 454 Positive lens 461 Photographing lens 462 Video camera body 463 Storage unit 464 Eyepiece cover 465 Display mode switch 466 Lid 467 Support point 471 Shutter 472 Digital camera (electronic) Camera) Body 481 Outer frame 482 Fixing member 483 Leg 484 Leg mounting portion 491 Wall 492 Fixing metal fitting 493 Protective film (protective plate, protective means) 501 Scanning area 601 ENBL terminal (control terminal) 602 OR circuit 851 Shutter (light shielding means) 852 Glasses (switching means) 871 writing pixel row 1221 voltage output circuit 1222 current output circuit 1223 switching circuit (analog switch) 1224 operational amplifier (output buffer) 1225 adjusting volume (possible) Resistance, adjustment means) 1226 DA converter (digital-analog conversion means (device)) 1227 Output transistor (transistor, FET) 1228 Resistance 1321 Signal wiring 1751 Pixel contact part 1761 Protective film (layer) 1781 Spacer 1791 Lighting control line 1981 Block ( Unit) 2041 Speaker 2043 Function switch (FSW) 2044 Microphone 2045 Mirror (mirror) 2046 Display panel (display device) 2111 Reverse bias control line 2561 Insulation film 2621, 2681 Frame (field) memory 2622 Counter circuit 2623 Data conversion circuit 2682 Addition circuit (Arithmetic processing circuit) 2683 Gate driver control circuit 2691 Data control circuit 2692 Data conversion circuit 2751 Bias resistance (electronic volume, electric Flow change means) 2752 Switch transistor (selection switch) 2753 Parent transistor 2754 Child transistor 2791 Light (trajectory) 2801 Refraction sheet (plate, film) 2802 Refraction part 2861 Transparent film 2862 Roller 2863 Concavo-convex part (concave part) 2871 Convex part 2881 Metal mask 2901 Press plate (pressing means, transfer means) 2902 Light (UV light, visible light) 3001 Current sampling circuit 3002 Current program line 3271 Buffer circuit 3272 OR circuit 3491 Decoder circuit 3511 Precharge circuit 3521 Data shift circuit 3661 Bank 3662 Second pixel electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 622Q 624 624B 641 641D 641E 642 642A 680 680G 680T H05B 33/14 H05B 33/14 AF terms (reference) 3K007 AB02 AB03 AB05 AB17 AB18 BA06 BB05 BB07 DB03 EB00 GA04 5C080 AA06 BB05 CC03 DD05 DD26 DD30 EE28 FF11 FF13 GG11 JJ01 JJ02 JJ03 JJ04 AA A22 A22 A22 A22 A22 A22 A4 A4 A4 A4 DA07 DA09 DA13 DB01 DB04 EA04 EA07 EC03 ED01 FA01 FB01 FB20 GA10

Claims (19)

[Claims] 1. In an EL display device, pixels are arranged in a matrix, an EL element, a drive transistor element for applying a current to the EL element, and a gate terminal voltage of the drive transistor element are provided in each pixel. And a capacitor for holding for a predetermined period,
An EL display device, wherein a switching element that short-circuits both ends of the capacitor is formed. 2. An active matrix type EL display device in which pixels are arranged in a matrix and has a source signal line for transmitting a video signal, wherein an EL element is applied to each pixel and a current is applied to the EL element. Drive transistor element, a first capacitor for holding a gate terminal voltage of the drive transistor element for a predetermined period, a second capacitor connected in series to the capacitor, and a signal of a source signal line is applied to the capacitor. An EL display device comprising: a first switching element; and a second switching element that short-circuits both ends of at least one of the first and second capacitors. 3. An EL display device comprising: an EL element; first and second drive transistor elements for applying a current to the EL element; and a current between the first drive transistor element and the EL element. A first switching element that turns on and off, a second switching element that turns on and off a current between the second drive transistor element and the EL element, a gate terminal of the first drive transistor element, and a second drive transistor in the first half An EL display device, comprising: a gate terminal of the element and a capacitor connected in common. 4. An EL element, first and second drive transistor elements for applying a current to the EL element, and a first switching element for turning on / off a current between the first drive transistor element and the EL element. A second switching element for turning on / off a current between the second driving transistor element and the EL element, a gate terminal of the first driving transistor element and a gate terminal of the second driving transistor element in common. An EL display panel having a capacitor connected thereto, a down converter, an up converter, a receiver, and a speaker, the first drive transistor and the second drive transistor being in synchronization with the field and alternating An information display device characterized by being operated. 5. An EL display device comprising: an EL element; first and second drive transistor elements for applying a current to the EL element; and a current between the first drive transistor element and the EL element. A first switching element that turns on and off, a second switching element that turns on and off a current between the second drive transistor element and the EL element, a gate terminal of the first drive transistor element, and a second drive transistor in the first half A capacitor commonly connected to the gate terminals of the elements, a third transistor having a current mirror circuit relationship with the first driving transistor and the second driving transistor, and a source signal to the gate terminal of the third transistor. An EL display device comprising a switching element for applying a line voltage. 6. A first operation in which the same voltage is written to the gate terminals of the first and second drive transistor elements and the voltage is held for a predetermined period, and the first drive transistor element operates in the first period. A second current is applied to the EL element to cause the EL element to emit light.
And a current applied by the second drive transistor element during the second period is applied to the EL element to cause the EL element to emit light.
And a method of driving an EL display device, wherein the first operation, the second operation, and the third operation are periodically performed. 7. In an EL display device, a first drive transistor in an even pixel row, a second drive transistor in an odd pixel row, and a first switching element that programs the first drive transistor, A second switching element that programs the second driving transistor; a first signal line that controls the first driving transistor; and a second signal line that controls the second driving transistor. A first driving transistor of an even pixel row and a second driving transistor of an odd pixel row are arranged in proximity to each other, and a first signal line and a second signal line are provided between the even pixel row and the odd pixel row. EL characterized in that and are arranged
Display device. 8. A driving method of an EL display device, comprising: in a first field, a first operation of writing the same data into a driving transistor of a first pixel row and a driving transistor of a second pixel row which are adjacent to each other. A second operation for putting the first pixel row in a non-lighting state and a third operation for shifting the pixel row for writing the data by two pixel rows, and a second field next to the first field A first operation of writing the same data to the driving transistor of the first pixel row and the driving transistor of the second pixel row which are adjacent to each other, and a second operation of turning off the second pixel row. A driving method of an EL display device, which comprises performing a third operation of shifting the pixel row for writing the data by two pixel rows at a time. 9. A driving method of an EL display device in which an EL element and a driving transistor are formed in each pixel, wherein a pixel row is programmed in synchronization with a horizontal synchronizing signal, and the pixel row is programmed sequentially. Is shifted, and the current applied to the EL element is turned on / off in a period shorter than the horizontal scanning period. 10. An EL element for each pixel, a drive transistor for applying a current to the EL element, a first switching element forming a path of a program current to the drive transistor, and the drive transistor to the EL element. A second switching element for turning on and off a current flowing through the first switching element, a first gate signal line for transmitting a signal for turning on and off the first switching element, and a signal for turning on and off the second switching element. A second gate signal line; a first shift register that is connected to the plurality of first gate signal lines and shifts an on-voltage position among the plurality of first gate signal lines; A second shift register connected to the gate signal line of the second shift register for shifting the ON voltage position of the plurality of second gate signal lines. E, characterized by comprising
L display device. 11. A driving method of an EL display device, wherein the EL display device comprises an EL element for each pixel, a drive transistor for applying a current to the EL element, and a path of a program current to the drive transistor. A first switching element that constitutes the first switching element, a second switching element that turns on and off a current flowing from the drive transistor to the EL element, and a first gate signal line that transmits a signal that turns on and off the first switching element. A second gate signal line for transmitting a signal for turning on and off the second switching element is formed, and a rising edge of a signal applied to the first gate signal line and a signal applied to the second gate signal line. A driving method of an EL display device, characterized in that the driving is performed so that the trailing edge of the EL display coincides. 12. An EL display device driving method, comprising: an EL element in each pixel, a drive transistor for applying a current to the EL element, and a program current path to the drive transistor. A first switching element that constitutes the first switching element, a second switching element that turns on and off a current flowing from the drive transistor to the EL element, and a first gate signal line that transmits a signal that turns on and off the first switching element. A second gate signal line for transmitting a signal for turning on / off the second switching element is formed, a signal applied to the second gate signal line of the first pixel row, and a signal adjacent to the first pixel row. The driving method of an EL display device, wherein the signal applied to the second gate signal line of the second pixel row has the opposite phase. 13. A driving method of an EL display device, comprising: a first gate signal line for selecting a pixel; and a second gate signal line for cutting off a current to an EL element of the pixel, A first operation of interrupting a current to the EL element by applying an off voltage to the second gate signal line of the pixel to which the selection voltage is applied to the first gate signal line; The second gate signal line of the pixel to which the voltage is not applied is a second gate signal line that alternately applies an on-voltage and an off-voltage.
And the signal rising position of the second gate signal line of the pixel row and the signal falling position of the second gate signal line of the pixel row adjacent to the pixel row are substantially coincident with each other. And a method for driving an EL display device. 14. A driving method of an EL display device, comprising: a first gate signal line for selecting a pixel; and a second gate signal line for cutting off a current to an EL element of the pixel, A first operation of interrupting a current to the EL element by applying an off voltage to the second gate signal line of the pixel to which the selection voltage is applied to the first gate signal line; To the second gate signal line of the pixel to which is not applied, the second operation of applying an ON voltage or an OFF voltage for each horizontal scanning period with the vertical synchronization signal as a reference, and the selection voltage is applied. The second gate signal line of the non-existing pixel performs a third operation of inverting the timing of applying the on-voltage or the off-voltage for each horizontal scanning period for each frame, and the second gate signal line of the second gate signal line Signal is continuous water A method for driving an EL display device, wherein an on-voltage or an off-voltage is applied so as to be continuous during a flat scan period. 15. An EL display device having a second gate signal line for shutting off a current to an EL element of a pixel, wherein one horizontal scanning period is divided into substantially the same first period and second period. , A signal for cutting off the current to the EL element during the first period is applied to the second gate signal line of the even pixel row, and the second gate signal line of the odd pixel row is connected to the second gate signal line. A driving method of an EL display device, wherein a signal for cutting off a current to the EL element is applied in a second period. 16. An EL display device comprising: a second gate signal line for cutting off a current to an EL element of a pixel; and a first gate signal line for applying a reverse bias voltage to the EL element, To the second gate signal line, to the first gate signal line,
A signal for applying a reverse bias voltage is applied to the EL element, a phase of the signal applied to the first gate signal line of the first pixel row, and a second pixel row adjacent to the first pixel row. The driving method of an EL display device, wherein the phase of the signal applied to the first gate signal line is opposite to that of the signal, and is periodically changed. 17. A driving method of an EL display device for performing current programming to a pixel, which corresponds to a first operation of shifting image data and changing a size of the image data, and corresponding to the size of the image data. A second operation of applying a current to the pixel and a third operation of applying a current corresponding to the size of the original image data to the pixel are performed.
Driving method for L display device. 18. An electrode formed on the EL film, a sealing film formed on the electrode, and a concave refraction portion formed on the sealing film and corresponding to a pixel. An EL display device, wherein the concave refraction portion is filled with a refractive index material different from that of the concave refraction portion. 19. A first pixel electrode formed in a matrix, a bank formed between the first pixel electrodes, overlapping with the first pixel electrode so as to be in contact with the first pixel electrode. An EL display device comprising: the second pixel electrode thus formed; an EL film formed on the second pixel electrode; and a common electrode formed on the EL film.