JP4251801B2 - EL display device and driving method of EL display device - Google Patents

EL display device and driving method of EL display device Download PDF

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JP4251801B2
JP4251801B2 JP2001349887A JP2001349887A JP4251801B2 JP 4251801 B2 JP4251801 B2 JP 4251801B2 JP 2001349887 A JP2001349887 A JP 2001349887A JP 2001349887 A JP2001349887 A JP 2001349887A JP 4251801 B2 JP4251801 B2 JP 4251801B2
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current
voltage
pixel
display
signal line
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JP2003150082A (en
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博司 高原
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パナソニック株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3223Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED] combined with dummy elements, i.e. non-functional features
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention mainly relates to an EL display panel that displays an image by self-emission, and an information display device such as a mobile phone using the EL display panel.
[0002]
[Prior art]
Liquid crystal display panels are widely used in portable devices because they are thin and have low power consumption, so they are also used in devices such as word processors, personal computers, and televisions, as well as video camera viewfinders and monitors. Yes.
[0003]
[Problems to be solved by the invention]
However, since the liquid crystal display panel is not a self-luminous device, there is a problem that an image cannot be displayed unless a backlight is used. Since a predetermined thickness is required to configure the backlight, there is a problem that the thickness of the display module increases. In order to perform color display on the liquid crystal display panel, it is necessary to use a color filter. Therefore, there is a problem that the light utilization efficiency is low.
[0004]
[Means for Solving the Problems]
In order to solve this problem, the present invention firstly relates to an active matrix type EL display device in an EL display device, wherein at least one of an upper side and a lower side of the display region emits no light or emits light. A pixel row that is shielded from light is formed or arranged.
[0005]
Secondly, in the driving method of the EL display device, the driving method of the EL display device includes a first operation of simultaneously selecting a plurality of pixel rows and applying the same image data to the selected pixel rows; A second operation for sequentially cysting selected positions of pixel rows and a third operation for selecting pixel rows formed or arranged outside the image display area when selecting the last pixel row are performed. To do.
[0006]
Third, the EL display device includes pixels arranged in a matrix, a gate driver circuit that selects the pixels, and a current output type source driver circuit that outputs image data to be applied to the pixels, The gate driver circuit sequentially selects pixel rows, and when the gate driver circuit does not select a pixel row, the source driver circuit outputs a write current in black display.
[0007]
Fourth, in an EL display device, pixels arranged in a matrix, a gate driver circuit for selecting the pixels, a current output type source driver circuit for outputting image data to be applied to the pixels, and an outside of the display area The gate driver circuit sequentially selects pixel rows, and when the gate driver circuit does not select a pixel row in the display area, the source driver circuit An output current is written in a pixel formed outside the region, or a current is absorbed from the pixel.
[0008]
Fifth, in an EL display device, pixels arranged in a matrix, a gate driver circuit for selecting the pixels, a current output type source driver circuit for outputting image data to be applied to the pixels, and an outside of the display area The pixel electrode of the second pixel is electrically short-circuited with the cathode electrode or the anode electrode of the EL element.
[0009]
Sixth, in an EL display device, pixels arranged in a matrix, a gate driver circuit for selecting the pixels, a current output type source driver circuit for outputting image data to be applied to the pixels, and an outside of the display area The second pixel has a light shielding means for shielding light emitted from the EL element, or an EL element is not formed in the second pixel.
[0010]
Seventh, in the information display device, an EL display panel having pixels arranged in a matrix and second pixels formed outside the display area, a down converter, an up converter, a receiver, a speaker, It is characterized by comprising.
[0011]
Eighth, in the EL display device, the image memory, the counter circuit for counting the number of image data having a predetermined size or more, and the data read from the image memory when the count value of the counter circuit is not less than the predetermined value. And a data conversion circuit for converting the data so as to be small.
[0012]
Ninth, in an EL display device, pixels formed in a matrix, EL elements formed in the pixels, drive transistor elements that supply current to the EL elements, and currents from the drive transistor elements A switching element for controlling the flow to the EL element, a gate driver circuit for sequentially selecting the pixels, a counter circuit for counting the number of image data having a predetermined size or more, and a count value of the counter circuit being a predetermined value In the above-described manner, the control circuit includes a control circuit that controls the switching element.
[0013]
Tenth, in an EL display device, pixels formed in a matrix, EL elements formed in the pixels, drive transistor elements that supply current to the EL elements, and a gate driver circuit that sequentially selects the pixels And an electrode formed on the gate driver circuit and an EL film formed on the electrode.
[0014]
Eleventh, the EL display device is an active matrix EL display device, in which an EL element formed in each pixel, a drive transistor element that supplies current to the EL element, and a gate terminal of the drive transistor element A first capacitor for holding a potential for a predetermined period; a second capacitor connected to one terminal of the first capacitor; and a control signal line connected to the other terminal of the second capacitor. And the potential of the gate terminal is shifted by a voltage applied to the control signal line.
[0015]
Twelfth, in the EL display device, an active matrix EL display device, which is an EL element formed in each pixel, a driving transistor element that supplies current to the EL element, a switching transistor element, and the driving transistor A first capacitor disposed between the gate terminal and the voltage terminal of the element; and a second capacitor disposed between the gate terminal of the driving transistor element and the drain terminal of the switching transistor element, According to the selection, the drain terminal of the switching transistor element and the source terminal of the driving transistor are arranged so as to be short-circuited.
[0016]
Thirteenth, in the EL display device, the active matrix EL display device, wherein the first EL element emitting red light, the second EL element emitting green light, the third EL element emitting blue light, A first driving transistor element for supplying current to the first EL element; a second driving transistor element for supplying current to the second EL element; and a third for supplying current to the third EL element. Drive transistor elements, a first switching element disposed between the first drive transistor element and the first EL element, and a second drive transistor element disposed between the second EL element and the second EL element. A second switching element; a third switching element disposed between the third driving transistor element and the third EL element; the first driving transistor element; A first gate signal line for simultaneously selecting two drive transistor elements and the third drive transistor element, a first control signal line for controlling on / off of the first switching element, and the second switching And a second control signal line for controlling on / off of the element and a third control signal line for controlling on / off of the third switching element.
[0017]
14thly, in the drive method of an EL display apparatus, it is a drive method of an active matrix type EL display apparatus, Comprising: At least one of the period which turns on and off of the 1st EL element which light-emits red, and the time to turn on, It becomes green At least one of the cycle for turning on and off the second EL element that emits light and the time for turning on, and at least one of the cycle for turning on and off the third EL element that emits blue light and the time for turning on are either The EL element is different from the EL element.
[0018]
Fifteenth, in the EL display device, the EL display device, an EL element formed in each pixel, a drive transistor element that supplies current to the EL element, an EL film formed in the pixel, An electrode formed on the EL film, a sealing film for preventing inflow of moisture into the EL film, and a light bending means formed on the sealing film corresponding to the pixel shape, The light bending means is formed or arranged in a hexagonal shape.
[0019]
Sixteenth, in an EL display device, the EL display device is a pixel arranged in a matrix, a current output circuit formed or arranged on each source signal line that outputs a current applied to the pixel, and a digital An analog current conversion circuit that converts image data into an analog current, and a current sampling circuit that samples the current output from the analog current conversion circuit and holds the current in the current output circuit.
[0020]
Seventeenth, in an EL display device manufacturing method, the EL display device manufacturing method includes first forming an EL film and a sealing film for preventing the EL film and an inflow of moisture into the EL film on the substrate. The second step of applying a transparent resin on the sealing film, and pressing the roller having a concavo-convex shape corresponding to the shape of the light bending means against the transparent resin to transfer the concavo-convex shape. A third step and a fourth step of curing the transparent resin are performed.
[0021]
Eighteenth, in the EL display device manufacturing method, the EL display device manufacturing method includes forming an EL film and a sealing film that prevents the EL film and the inflow of moisture into the EL film on the substrate. The second step of forming a convex portion corresponding to the pixel shape on the sealing film, the third step of applying a transparent resin on the convex portion and the sealing film, and the transparent resin. A fourth step of curing is performed.
[0022]
Nineteenth, in an EL display device manufacturing method, the EL display device manufacturing method includes forming an EL film and a sealing film for preventing inflow of moisture into the EL film and the EL film on a substrate. A second step of disposing a mask having an opening corresponding to the pixel shape at a predetermined interval from the sealing film, and a transparent material on the sealing film through the mask. And performing a third step of vapor deposition.
[0023]
20th, in an EL display device manufacturing method, the EL display device manufacturing method includes forming an EL film and a sealing film that prevents the EL film and the inflow of moisture into the EL film on the substrate. The second step of applying a transparent resin on the sealing film, the third step of pressing a press plate having a concavo-convex shape corresponding to the shape of the light bending means to the transparent resin, A fourth step of irradiating the transparent resin with light through a press plate and curing the transparent resin is performed.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
In the present specification, each drawing includes parts that are omitted or enlarged or reduced for easy understanding or drawing. For example, in the cross-sectional view of the display panel in FIG. 5, the sealing film 73 and the like are illustrated to be sufficiently thick. In FIG. 6 and the like, a thin film transistor (TFT) for applying a signal to the pixel electrode is omitted. Further, in the display panel and the like of the present invention, a phase film for phase compensation is omitted, but it is desirable to add it in a timely manner. The same applies to the other drawings. Moreover, the part which attached | subjected the same number or code | symbol has the same material, function, or operation | movement.
[0025]
Note that the contents described in the drawings and the like can be combined with other embodiments and the like without particular notice. For example, by adding a touch panel or the like to the display panel of FIG. 6, an information display device as shown in FIGS. 232 and 243 can be obtained. A viewfinder (see FIG. 239) such as a video camera (see FIG. 162) can also be configured by attaching a magnifying lens. Further, the driving method of the present invention described in FIGS. 49, 297, 50, 60, etc. can be applied to any of the display device and the display panel of the present invention. In addition, the present invention will be mainly described with respect to an active matrix display panel in which a TFT is formed in each pixel. However, the present invention is not limited to this and can be applied to a simple matrix display panel.
[0026]
As described above, the matters, contents, and specifications described in the specification and the drawings can be applied in combination with each other even if not particularly exemplified.
[0027]
(Embodiment 1)
Currently, organic EL display panels configured by arranging a plurality of organic electroluminescence (EL) elements in a matrix form are attracting attention as display panels that have low power consumption and high display quality and can be made thinner. Yes.
[0028]
As shown in FIG. 2, the organic EL display panel has at least one organic EL layer composed of an electron transport layer, a light emitting layer, a hole transport layer, and the like on an array substrate 49 on which a transparent electrode as the pixel electrode 48 is formed. The layer 47 and the reflective film 46 are laminated. By applying a positive voltage to the anode (anode) of the transparent electrode (pixel electrode) 48 and a negative voltage to the cathode (cathode) of the reflective film 46 and applying a direct current therebetween, the organic EL layer 47 emits light. Thus, by using an organic compound that can be expected to have good light emission characteristics for the organic EL layer, the EL display panel can withstand practical use.
[0029]
The cathode electrode, the anode electrode, or the reflective film may be configured by forming an optical interference film made of a dielectric multilayer film on the ITO electrode. The dielectric multilayer film is a multilayer film (dielectric mirror) in which a low refractive index dielectric film and a high refractive index dielectric film are alternately formed. This dielectric multilayer film has a function (filter effect) for improving the color tone of light emitted from the organic EL structure.
[0030]
A large current flows through the wirings 63 and 51 that supply current to the anode or cathode. For example, when the screen size of the EL display device is 40 inches, a current of about 100 A flows. Therefore, the resistance values of these wirings must be made sufficiently low. In response to this problem, in the present invention, first, a wiring such as an anode is formed as a thin film. And the thickness of the conductor is thickly formed in this thin film wiring by the electrolytic plating technique. Further, as necessary, the wiring itself or a metal wiring made of copper thin is added to the wiring.
[0031]
In addition, in order to supply a large current to the anode or cathode wiring, a high voltage and small current power wiring is used from the current supply means to the vicinity of the anode wiring and the like, and a low voltage and high voltage using a DCDC converter or the like. The power is converted into current and supplied. That is, wiring is performed from a power source to a power consumption target using a high voltage, small current wiring, and converted to a large current and low voltage in the vicinity of the power consumption target. Examples of such devices include DCDC converters and transformers.
[0032]
The reflective film 46 is preferably made of a material having a small work function, such as lithium, silver, aluminum, magnesium, indium, copper, or an alloy thereof, particularly an Al-Li alloy. The transparent electrode (pixel electrode) 48 can be made of a conductive material having a high work function such as ITO (tin-doped indium oxide) or gold. In addition, when gold is used as an electrode material, the electrode is in a translucent state. ITO may be other materials such as IZO. The same applies to the pixel electrode.
[0033]
Note that when a thin film is deposited on the pixel electrode 48 or the like, an organic EL film may be formed in an argon atmosphere. Further, by forming a carbon film with a thickness of 20 nm or more and 50 nm or less on ITO as the pixel electrode 48, the stability of the interface is improved, and the light emission luminance and the light emission efficiency are also improved.
[0034]
Moreover, it goes without saying that the organic EL film is not limited to being formed by vapor deposition, but may be formed by inkjet.
[0035]
(Embodiment 2)
Hereinafter, in order to facilitate understanding of the EL display panel structure of the present invention, a method for manufacturing the organic EL display panel of the present invention will be described first.
[0036]
In order to improve heat dissipation, the array substrate 49 may be formed of sapphire glass. Alternatively, a thin film or a thick film having good thermal conductivity may be formed. For example, the use of a substrate on which a diamond thin film is formed is exemplified. Of course, a quartz glass substrate or a soda glass substrate may be used. In addition, a ceramic substrate such as alumina or a metal plate made of copper or the like may be used, or an insulating film coated with a metal film such as vapor deposition or coating may be used. When the pixel electrode is of a reflective type, light is emitted from the surface direction of the substrate as the substrate material. Therefore, a transparent or translucent material such as glass, quartz or resin, or a non-transparent material such as stainless steel may be used. it can. This configuration is illustrated in FIG. In FIG. 5, the cathode electrode is formed of a transparent electrode 72 such as ITO.
[0037]
In the embodiment of the present invention, the cathode or the like is formed of a metal film. However, the present invention is not limited to this, and may be formed of a transparent film such as ITO or IZO. Thus, a transparent EL display panel can be configured by making both the anode and cathode electrodes of the EL element 15 transparent. That is, by increasing the transmittance to about 80% without using a metal film, it is possible to achieve a configuration in which the other side of the display panel can be almost seen through while displaying characters and pictures.
[0038]
The array substrate 49 may be a plastic substrate. Plastic substrates are difficult to break and are lightweight, making them ideal as display panel substrates for mobile phones. The plastic substrate is preferably used as a laminated substrate by attaching an auxiliary substrate to one surface of a base substrate serving as a core material with an adhesive. Of course, these substrates are not limited to plates, and may be films having a thickness of 0.05 mm to 0.3 mm.
[0039]
As a material for the base substrate, an alicyclic polyolefin resin is preferably used. An example of such an alicyclic polyolefin resin is ARTON (single plate having a thickness of 200 μm) manufactured by Nippon Synthetic Rubber. From polyester resin, polyethylene resin or polyethersulfone resin, etc., on which one side of the base substrate is formed with a hard coat layer with heat resistance, solvent resistance or moisture permeability function, and a gas barrier layer with air permeability resistance function An auxiliary substrate (or film or film) is arranged.
[0040]
Thus, when the array substrate 49 is made of plastic, the array substrate 49 is composed of the base substrate and the two auxiliary substrates. Therefore, the hard coat layer and the gas barrier are also formed on the other surface of the base substrate in the same manner as described above. An auxiliary substrate (or film or film) made of a polyethersulfone resin or the like on which a layer is formed is disposed. Note that the base substrate and the auxiliary substrate are attached to each other with an adhesive or a pressure-sensitive adhesive to form a laminated substrate.
[0041]
As the adhesive, it is preferable to use a UV (ultraviolet) curable acrylic resin, and it is preferable to use an acrylic resin having a fluorine group. In addition, an epoxy adhesive or pressure-sensitive adhesive may be used. The refractive index of the adhesive or pressure-sensitive adhesive is preferably 1.47 or more and 1.54 or less. In addition, it is preferable that the difference in refractive index with respect to the refractive index of the array substrate 49 is 0.03 or less. In particular, the adhesive is preferably added with a light diffusing material such as titanium oxide to function as a light scattering layer.
[0042]
When bonding each auxiliary substrate to the base substrate, the angle formed by the optical slow axes of each auxiliary substrate is 45 degrees or more and 120 degrees or less, more preferably 80 degrees or more and 100 degrees or less (approximately 90 degrees). It is good to do. By setting it within this range, the retardation generated in the auxiliary substrate and the polyethersulfone resin as the auxiliary substrate can be completely canceled in the laminated substrate. Therefore, the organic EL display panel plastic substrate can be handled as an isotropic substrate having no phase difference.
[0043]
With this configuration, versatility is significantly increased as compared with a film substrate or a film laminated substrate having a phase difference. That is, it becomes possible to convert linearly polarized light into elliptically polarized light as designed by combining with a retardation film. If there is a phase difference in the array substrate 49 or the like, an error from the design value occurs due to this phase difference.
[0044]
The hard coat layer in the auxiliary substrate can use an epoxy resin, a urethane resin, an acrylic resin, or the like as a material, and also serves as a first undercoat layer of a transparent conductive film having a stripe electrode or a pixel electrode. As the gas barrier layer, SiO2Inorganic materials such as SiOx or organic materials such as polyvinyl alcohol and polyimide can be used. As an adhesive, an adhesive, etc., an epoxy adhesive or a polyester adhesive can be used in addition to the acrylic described above. In addition, although the thickness of an adhesive layer shall be 100 micrometers or less, in order to smooth the unevenness | corrugation of surfaces, such as a board | substrate, it is preferable to set it as 10 micrometers or more.
[0045]
Moreover, it is preferable to use a substrate having a thickness of 40 μm or more and 400 μm or less as the auxiliary substrate and the auxiliary substrate constituting the array substrate 49. In addition, by setting the thickness of each auxiliary substrate to 120 μm or less, unevenness or phase difference at the time of melt extrusion called a die line of polyethersulfone resin can be suppressed low, and the thickness is preferably 50 μm or more and 80 μm or less. And
[0046]
Next, SiOx is formed on the laminated substrate as an auxiliary undercoat layer of the transparent conductive film, and a transparent conductive film made of ITO serving as a pixel electrode is formed by a sputtering technique. The transparent conductive film of the plastic substrate for an organic EL display panel manufactured as described above can realize a sheet resistance value of 25Ω / □ and a transmittance of 80% as its film characteristics.
[0047]
When the thickness of the base substrate is as thin as 50 μm to 100 μm, the organic EL display panel plastic substrate is curled by heat treatment in the manufacturing process of the organic EL display panel. In addition, cracks occur in the ITO that constitutes the striped electrode and the subsequent conveyance becomes impossible. Also, good results cannot be obtained in connection of circuit components. However, when the thickness of the base substrate is 200 μm or more and 500 μm or less with a single plate, the substrate is not deformed and has excellent smoothness, good transportability, and stable transparent conductive film characteristics. Also, connection of circuit components can be carried out without any problem. Furthermore, since it has moderate softness | flexibility and planarity, it is thought that it is good to make thickness into 250 micrometers or more and 450 micrometers or less.
[0048]
When an organic material such as the aforementioned plastic substrate is used as the array substrate 49, it is preferable to form a thin film made of an inorganic material as a barrier layer on the surface in contact with the liquid crystal layer. This barrier layer made of an inorganic material is preferably formed of the same material as the AIR coat. The sealing lid 41 can also be manufactured by the same technique or configuration as the array substrate 49.
[0049]
Further, when the barrier layer is formed on the pixel electrode or the stripe electrode, it is preferable to use a low dielectric constant material in order to reduce the loss of the voltage applied to the light modulation layer as much as possible. For example, an amorphous carbon film (relative dielectric constant: 2.0 to 2.5) to which fluorine is added is exemplified. Other examples include the LKD series (LKD-T200 series (relative permittivity 2.5 to 2.7)) and LKD-T400 series (relative permittivity 2.0 to 2.2)) manufactured and sold by JSR. Is done. The LKD series is a spin coating type based on MSQ (methy-silsesquioxane) and has a low dielectric constant of 2.0 to 2.7, which is preferable. Other organic materials such as polyimide, urethane, acrylic, SiNx, SiO2An inorganic material such as There is no problem even if these barrier layer materials are used for the auxiliary substrate.
[0050]
By using the array substrate 49 or the sealing lid 41 formed of plastic, there is an advantage that it can be pressed, in addition to the advantages that it is not broken and can be reduced in weight. In other words, a substrate having an arbitrary shape can be produced by pressing or cutting (see FIG. 3). Further, it can be processed into an arbitrary shape and thickness by melting or chemical treatment. For example, a circular shape, a spherical shape (curved surface or the like), or a conical shape is exemplified. In addition, by pressing, at the same time as the manufacture of the substrate, the uneven portion 252 can be formed on one substrate surface, and the scattering surface can be formed or embossed.
[0051]
It is also easy to form a backlight or a cover substrate positioning pin into a hole in the array substrate 49 formed by pressing plastic. Further, an electric circuit such as a capacitor or a resistor formed by thick film technology or thin film technology may be formed in the array substrate 49 and the sealing lid 41. Further, a concave portion (not shown) is formed in the sealing lid 41, a convex portion 251 is formed on the array substrate 49, and the concave portion and the convex portion are formed so as to be fitted with each other. The array substrate 49 may be integrated so as to be integrated.
[0052]
When a glass substrate is used, a bank used for depositing an EL element on the periphery of the pixel 16 is formed. The banks (ribs) are formed in a convex shape using a resin material with a thickness of 1.0 μm to 3.5 μm, more preferably 1.5 μm to 2.5 μm. The bank (convex portion) 251 made of this resin can be produced simultaneously with the formation of the sealing lid 41 or the array substrate 49 by press working (see FIG. 3). This is a great effect generated by forming the sealing lid 41 and the array substrate 49 from resin. The bank material may be SOG material in addition to acrylic resin and polyimide resin.
[0053]
In this way, the manufacturing time can be shortened by forming the resin portion simultaneously with the substrate, so that the cost can be reduced. Further, at the time of manufacturing the array substrate 49 and the like, the convex portions 251 are formed in a dot shape in the display region portion. The convex portion 251 is formed between adjacent pixels, thereby holding a predetermined space between the sealing lid 41 and the array substrate 49. The bank shape may be a stripe shape in addition to the square shape surrounding the pixel electrode.
[0054]
In the above embodiment, the convex portion 251 that functions as a bank is formed. However, the present invention is not limited to this. For example, the pixel portion may be dug down (concave portion) by press working or the like. In addition to the formation of the concavo-convex portions 252 and the convex portions 251, a method of forming a concavo-convex by forming a flat substrate first and then pressing by reheating is included.
[0055]
Alternatively, a mosaic color filter may be formed by directly coloring the sealing lid 41 and the array substrate 49. The substrate is coated with a dye or pigment using a technique such as inkjet printing. After infiltration, drying may be performed at a high temperature, and the surface may be coated with a resin such as a UV resin, or an inorganic material such as silicon oxide or nitrogen oxide. Further, the color filter may be formed by a gravure printing technique, an offset printing technique, a semiconductor pattern forming technique in which a film is applied and developed with a spinner. In addition to the color filter, a black matrix (BM) having a complementary color relationship of black or dark color or light to be modulated may be directly formed by coloring using a similar technique. Further, a recess may be formed on the substrate surface so as to correspond to the pixel, and a color filter, BM, or TFT may be embedded in the recess. In particular, it is preferable to coat the surface with an acrylic resin. This configuration also has an advantage that the pixel electrode surface and the like are smoothed.
[0056]
Alternatively, the pixel electrode or the cathode electrode may be configured directly by conducting the resin on the substrate surface with a conductive polymer or the like. Furthermore, a configuration in which a large hole is formed in the substrate and an electronic component such as a capacitor is inserted into the hole is also exemplified. Thereby, the advantage that a board | substrate can be comprised thinly is exhibited.
[0057]
Moreover, you may form a pattern freely by cutting the surface of a board | substrate. Alternatively, the sealing lid 41 and the peripheral portion of the array substrate 49 may be melted. In the case of an organic EL display panel, the periphery of the substrate may be melted and sealed in order to prevent moisture from entering from the outside.
[0058]
As described above, by forming the substrate with a resin, it is easy to make a hole in the substrate. Further, the substrate shape can be freely configured by press working or the like.
[0059]
Further, in order to make the sealing lid 41 and the array substrate 49 usable as a multilayer circuit board or a double-sided substrate, a hole is formed in the sealing lid 41 and the array substrate 49, and a conductive resin or the like is filled in the hole, It is also possible to electrically connect the front and the back.
[0060]
The sealing lid 41 and the array substrate 49 itself may be a multilayer wiring board. For example, a conductive pin or the like can be inserted in place of the conductive resin, a terminal of an electronic component such as a capacitor can be inserted into the formed hole, or a circuit wiring, a capacitor, a coil, or a resistor is formed in the substrate. May be. Multi-layering is configured by bonding thin substrates, and at this time, one or more of the substrates (films) to be bonded may be colored.
[0061]
In addition, dyes and pigments can be added to the substrate material to color the substrate itself and to form a filter. Further, the serial number can be formed simultaneously with the production of the substrate. Further, by coloring only the part other than the display area, it is possible to prevent malfunctions by irradiating light on the mounted IC chip.
[0062]
Also, half of the display area of the substrate can be colored in a different color. This may be achieved by applying resin plate processing techniques (injection processing, compression processing, etc.). In addition, by using the same processing technique, half of the display area can be made to have a different EL layer thickness. In addition, the display portion and the circuit portion can be formed at the same time. It is also easy to change the substrate thickness between the display area and the driver loading area.
[0063]
Further, microlenses can be formed on the sealing lid 41 or the array substrate 49 so as to correspond to the pixels or to correspond to the display area. Further, a diffraction grating may be formed by processing the sealing lid 41 and the array substrate 49. Further, by forming unevenness sufficiently finer than the pixel size, the viewing angle can be improved or the viewing angle can be made dependent. It is to be noted that such arbitrary-shaped processing and fine processing technology can be realized by a stamper technology for forming a microlens developed by OMRON Corporation.
[0064]
Striped electrodes (not shown) are formed on the sealing lid 41 and the array substrate 49. In addition, an antireflection film (AIR coat) is formed on the surface where the substrate comes into contact with air, and when other constituent materials such as a polarizing plate (polarizing film) are affixed, it is reflected on the surface of the constituent material. A prevention film (AIR coat) is formed. Further, when a polarizing plate or the like is not attached to the sealing lid 41 and the array substrate 49, an antireflection film (AIR coat) is directly formed on the sealing lid 41 and the array substrate 49.
[0065]
Although the above embodiment has been described mainly with respect to the sealing lid 41 and the array substrate 49 being formed of plastic, the present invention is not limited to this. For example, even if the sealing lid 41 and the array substrate 49 are a glass substrate or a metal substrate, the concavo-convex portions 252 and the convex portions 251 can be formed or configured by pressing, cutting, or the like. Moreover, it is not limited to a substrate. For example, a film or a sheet may be used.
[0066]
In addition, it is effective to form a thin film made of a fluororesin in order to prevent or suppress the adhesion of dust to the surface of the polarizing plate. In addition, a conductor film such as a thin film having a hydrophilic group, a conductive polymer film, or a metal film may be applied or deposited for preventing static electricity.
[0067]
In addition, the polarizing plate (polarizing film) disposed or formed on the light incident surface or the light emitting surface of the display panel 82 is not limited to linearly polarized light, and may be elliptically polarized light. Alternatively, a plurality of polarizing plates may be bonded together, or a polarizing plate and a retardation plate may be combined or bonded.
[0068]
As the main material constituting the polarizing film, a TAC film (triacetyl cellulose film) is optimal. This is because the TAC film has excellent optical properties, surface smoothness and processability. As for the production of the TAC film, it is optimal to produce it by a solution casting film forming technique.
[0069]
The AIR coat is exemplified by a structure formed of a dielectric single layer film or a multilayer film. In addition, a resin having a low refractive index of 1.35 to 1.45 may be applied. For example, a fluorine-type acrylic resin etc. are illustrated and a thing with a refractive index of 1.37 or more and 1.42 or less is especially good.
[0070]
The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide wavelength band of visible light, and this is called multi-coat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band, and this is called a V coat. Multi-coat and V-coat are used properly according to the use of the display panel. The AIR coat is not limited to two or more layers, and may be a single layer. In this case, magnesium fluoride (MgF2) Is formed by stacking nd1 = λ / 2.
[0071]
In the case of multi-coat, aluminum oxide (Al2OThree) Optical film thickness nd = λ / 4, zirconium (ZrO2) Nd1 = λ / 2, magnesium fluoride (MgF2) Is formed by stacking nd1 = λ / 4. Usually, the thin film is formed as λ = 520 nm or a value in the vicinity thereof.
[0072]
In the case of V coat, silicon monoxide (SiO) is coated with an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF2) Nd1 = λ / 4, or yttrium oxide (Y2OThree) And magnesium fluoride (MgF)2) Is formed by stacking nd1 = λ / 4. Since SiO has an absorption band on the blue side, when the blue light is modulated, Y is2OThreeIt is better to use In addition, SiO2A thin film may be used. Of course, a low refractive index resin or the like may be used for the AIR coating. For example, an acrylic resin such as fluorine is exemplified. These are preferably ultraviolet curable types.
[0073]
In order to prevent the display panel from being charged with static electricity, a hydrophilic resin is applied to the surface of a light guide plate such as a cover substrate or the display panel 82, or the substrate material such as the panel is made hydrophilic. Is preferably made of a good material. In addition, in order to prevent surface reflection, the surface of the polarizing plate 54 may be embossed.
[0074]
In each pixel, a plurality of switching elements or thin film transistors (TFTs) as current control elements are formed. The TFTs to be formed may be the same type of TFT, or may be different types of TFTs, such as P-channel type and N-channel type TFTs. Preferably, both the switching thin film transistor and the driving thin film transistor are used. Those of the same polarity are desirable. The structure of the TFT is not limited to that of a planar type TFT, and may be a staggered type or an inverted staggered type, or may have a impurity region (source, drain) formed using a self-alignment method. A non-self-alignment method may be used.
[0075]
The EL element 15 of the present invention has an EL structure in which ITO serving as a hole injection electrode (pixel electrode), one or more organic layers, and an electron injection electrode are sequentially stacked on an array substrate, The array substrate is provided with TFTs.
[0076]
In order to manufacture the EL device of the present invention, first, an array of TFTs is formed in a desired shape on a substrate. Then, ITO, which is a transparent electrode (pixel electrode) on the smoothing film, is formed and patterned by sputtering. Thereafter, an organic EL layer, an electron injection electrode, and the like are stacked.
[0077]
A normal polycrystalline silicon TFT may be used as the TFT. The TFT is provided at the end of each pixel of the EL structure, and has a size of about 10 to 30 μm. The size of the pixel at this time is about 20 μm × 20 μm to 300 μm × 300 μm.
[0078]
A TFT wiring electrode is provided on the array substrate. The wiring electrode has a low resistance, and also has a function of suppressing the resistance value by electrically connecting the hole injection electrode. Generally, the wiring electrode includes Al, Al and transition metals (except for Ti), Ti or A material containing one or more of titanium nitride (TiN) is used, but the present invention is not limited to this material. The total thickness of the hole injection electrode serving as the foundation of the EL structure and the wiring electrode of the TFT is not particularly limited, but is usually about 100 to 1000 nm.
[0079]
An insulating layer is provided between the wiring electrode of the TFT 11 and the organic layer of the EL structure. The insulating layer is made of SiO2Inorganic materials such as silicon oxide, silicon nitride, etc. formed by sputtering or vacuum deposition, silicon oxide layers formed by SOG (spin on glass), photoresists, polyimides, acrylic resins, etc. Any coating material may be used as long as it has an insulating property, such as a coating film, but polyimide is particularly preferable. The insulating layer also serves as a corrosion / water resistant film that protects the wiring electrode from moisture and corrosion.
[0080]
There may be two or more emission peaks of the EL structure. For example, the green and blue light emitting portions in the EL element of the present invention can be obtained by a combination of a blue-green light emitting EL structure and a green transmission layer or a blue transmission layer. The red light-emitting portion can be obtained by an EL structure that emits blue-green light and a fluorescence conversion layer that converts blue-green light emitted from the EL structure to a wavelength close to red.
[0081]
Next, the EL structure constituting the EL element 15 of the present invention will be described. The EL structure of the present invention includes an electron injection electrode that is a transparent electrode, one or more organic layers, and a hole injection electrode. Each of the organic layers has at least one hole transport layer and a light emitting layer. For example, the organic layer sequentially includes an electron injection transport layer, a light emitting layer, a hole transport layer, and a hole injection layer. Note that the hole transport layer may be omitted. The organic layer of the EL structure of the present invention can have various configurations, and the electron injection / transport layer is omitted, or is integrated with the light emitting layer, or the hole injection transport layer and the light emitting layer are mixed. May be.
[0082]
As a material for the hole injection electrode, the light emitted from the hole injection electrode side is taken out, so ITO (tin doped indium oxide), IZO (zinc doped indium oxide), ZnO, SnO.2, In2OThreeIn particular, ITO and IZO are preferable. The thickness of the hole injection electrode only needs to have a certain thickness or more that can sufficiently inject holes, and is preferably about 10 to 500 nm. In addition, the material for the hole injection electrode needs to have a low driving voltage in order to improve the reliability of the element, but a preferable example is ITO of 10 to 30Ω / □ (film thickness 50 to 300 nm). It is done. In actual use, the film thickness and optical constant of the electrode may be set so that the interference effect due to reflection at the hole injection electrode interface such as ITO sufficiently satisfies the light extraction efficiency and color purity. The hole injection electrode can be formed by vapor deposition or the like, but is preferably formed by sputtering. The sputtering gas is not particularly limited, and an inert gas such as Ar, He, Ne, Kr, or Xe, or a mixed gas thereof may be used.
[0083]
The electron injection electrode is made of a material using a metal, a compound or an alloy having a low work function formed by sputtering or the like, preferably by vapor deposition. For example, K, Li, Na, Mg, La, Ce, Ca, Sr, Ba, Al, Ag, In, Sn, Zn, Zr and other metal elements alone, or two components containing them to improve stability It is preferable to use a three-component alloy system. Examples of alloy systems include Ag · Mg (Ag: 1 to 20 at%), Al·Li (Li: 0.3 to 14 at%), In · Mg (Mg: 50 to 80 at%), Al · Ca (Ca: 5 to 20 at%) and the like are preferable. The thickness of the electron injection electrode thin film may be a certain thickness that can sufficiently inject electrons, and may be 0.1 nm or more, preferably 1 nm or more. Moreover, although there is no restriction | limiting in particular in the upper limit, Usually, a film thickness should just be about 100-500 nm.
[0084]
The hole injection layer has a function of facilitating injection of holes from the hole injection electrode, and the hole transport layer has a function of transporting holes and a function of blocking electrons. Also called transport layer.
[0085]
The electron injecting and transporting layer is provided when the electron injecting and transporting function of the compound used for the light emitting layer is not so high, and prevents the function of facilitating the injection of electrons from the electron injecting electrode, the function of transporting electrons and the holes. It has a function.
[0086]
These hole injection layer, hole transport layer, and electron injection transport layer increase and seal the holes and electrons injected into the light emitting layer, optimize the recombination region, and improve the luminous efficiency. is there. Note that the electron injecting and transporting layer may be provided separately for the layer having an injection function and the layer having a transport function.
[0087]
The thickness of the light emitting layer, the combined thickness of the hole injecting layer and the hole transporting layer, and the thickness of the electron injecting and transporting layer are not particularly limited and vary depending on the forming method, but are usually about 5 to 100 nm. Is preferred.
[0088]
The thickness of the hole injection layer, the hole transport layer, and the thickness of the electron injection / transport layer depends on the design of the recombination / light emitting region, but if it is about the same as the thickness of the light emitting layer or about 1/10 to 10 times Good. The thicknesses of the hole injection layer, the hole transport layer, and the thickness in the case of separating the electron injection layer and the electron transport layer are preferably 1 nm or more for the injection layer and 20 nm or more for the transport layer. At this time, the upper limit of the thickness of the injection layer and the transport layer is usually about 100 nm for the injection layer and about 100 nm for the transport layer. Such a film thickness is the same when two injection transport layers are provided.
[0089]
In addition, by controlling the film thickness while considering the carrier mobility and carrier density (determined by the ionization potential and electron affinity) of the combined light-emitting layer, electron injection transport layer, and hole injection transport layer, the recombination region and light emission region Can be designed freely, and it is possible to design the emission color, control the emission luminance and emission spectrum by the interference effect of both electrodes, and control the spatial distribution of emission.
[0090]
The light emitting layer of the EL element 15 of the present invention contains a fluorescent material which is a compound having a light emitting function. Examples of the fluorescent substance include metal complex dyes such as tris (8-quinolinolato) aluminum (Alq3) as disclosed in Japanese Patent Laid-Open No. 63-264692, and Japanese Patent Laid-Open No. 6-110569 (phenyl). Anthracene derivatives), JP-A-6-114456 (tetraarylethene derivatives), JP-A-6-1000085, JP-A-2-247278, and the like are listed.
[0091]
The EL element 15 that emits blue light may use “DMPhen (Triphenylamine)” having an emission wavelength of about 400 nm as the material of the light emitting layer. At this time, for the purpose of increasing the light emission efficiency, it is preferable to employ a material in which the band gap is the same as that of the light emitting layer for the electron injection layer (Bathocupline) and the hole injection layer (m-MTDATXA). This is because when DMPhen having a large band gap of 3.4 eV is used in the light emitting layer, electrons stay in the electron injection layer and holes stay in the hole injection layer, so that recombination of electrons and holes in the light emitting layer occurs. It is hard to happen. The problem that a light emitting material having an amine group such as DMPhen is unstable in structure and difficult to extend the life can be solved by transferring energy excited in DMPhen to a dopant and emitting light from the dopant.
[0092]
Luminous efficiency can be improved by using a phosphorescent material as the EL material. The fluorescent material has an external quantum efficiency of about 2-3%. The fluorescent light emitting material has an internal quantum efficiency (efficiency at which the energy by excitation is changed to light) is 25%, whereas the phosphorescent light emitting material reaches nearly 100%, so that the external quantum efficiency is high.
[0093]
Further, CBP is preferably used as a host material for the light-emitting layer of the EL element. Here, red (R), green (G), and blue (B) phosphorescent materials are doped. All doped materials contain Ir. It is preferable to use Btp2Ir (acac) for the R material, (ppy) 2Ir (acac) for the G material, and FIrpic for the B material.
[0094]
Examples of the hole injection layer / hole transport layer include, for example, JP-A 63-295695, JP-A 2-191694, JP-A 3-792 and JP-A-5-234681. Various organic compounds described in Kaihei 5-239455, JP-A-5-299174, JP-A-7-126225, JP-A-7-126226, JP-A-8-100192, EP0650955A1, etc. Can be used.
[0095]
In addition, it is preferable to use a vacuum evaporation method for forming these hole injecting and transporting layer, light emitting layer and electron injecting and transporting layer because a homogeneous thin film can be formed.
[0096]
(Embodiment 3)
Hereinafter, the manufacturing method and structure of the EL display panel of the present invention will be described in more detail. As described above, first, the TFT 11 for driving the pixels is formed on the array substrate 49. One pixel is composed of 4 or 5 TFTs. Further, the pixel is current-programmed, and the programmed current is supplied to the EL element 15. Normally, the current programmed value is held in the capacitor 19 as a voltage value. The pixel configuration such as the combination of the TFTs 11 will be described later. Next, a pixel electrode 48 as a hole injection electrode is formed on the TFT 11. The pixel electrode 48 is patterned by photolithography. A light-shielding film is formed or disposed in the lower layer or the upper layer of the TFT 11 in order to prevent image quality deterioration due to a photoconductor phenomenon (hereinafter referred to as a photocon) that occurs when light enters the TFT 11.
[0097]
In order to form a TFT on a plastic substrate, the surface on which the organic semiconductor is formed may be processed to form an electronic thin film using pentacene molecules composed of carbon and hydrogen. This thin film has a size 20 to 100 times that of conventional crystal grains and has sufficient semiconductor properties suitable for electronic device manufacturing.
[0098]
Pentacene molecules tend to adhere to surface impurities when grown on a silicon substrate. This makes the growth irregular and results in crystal grains that are too small to produce a high quality device. In order to grow the crystal grains larger, it is preferable to apply a single layer “molecular buffer” of molecules called cyclohexene on a silicon substrate. This layer covers "sticky sites" on the silicon, creating a clean surface and growing pentacene molecules to very large grains. By applying and using such a new thin film of pentacene molecules with large crystal grains at a low temperature, flexible transistors can be mass-produced.
[0099]
Alternatively, a metal thin film serving as a gate may be formed on a substrate in an island shape, and an amorphous silicon film may be deposited or applied thereon, and then heated to form a semiconductor film. The semiconductor film is crystallized well in the island-shaped portion. Therefore, mobility becomes good.
[0100]
As the organic transistor (TFT), a structure called a static induction transistor (SIT) is preferably employed, and amorphous pentacene is used. Hole mobility is 1 × 10cm2/ Vs and lower than crystallized pentacene. However, the frequency characteristic can be enhanced by adopting the SIT structure. Note that the thickness of pentacene is preferably 100 nm to 300 nm.
[0101]
The organic TFT may be a P-type field effect transistor, and the TFT can be formed on a plastic substrate. In this case, since the entire plastic substrate can be bent, it is preferable that pentacene capable of forming a flexible TFT display panel be in a polycrystalline state. Moreover, it is preferable to use PMMA as a material of the gate insulating film. Naphthacene may be used for the active layer of the organic transistor.
[0102]
Oxygen plasma during cleaning, O2When the asher is used, the smoothing film 71 in the peripheral portion of the pixel electrode 48 is also ashed simultaneously, and the peripheral portion of the pixel electrode 48 is removed. In order to solve this problem, in the present invention, as shown in FIG. 4, an edge protection film 81 made of acrylic resin is formed around the pixel electrode 48. Examples of the constituent material of the edge protective film 81 include the same materials as organic materials such as an acrylic resin and a polyimide resin that constitute the smoothing film 71, and other materials such as SiO.2, Inorganic materials such as SiNx, Al2OThreeEtc. are also exemplified.
[0103]
The edge protection film 81 is formed so as to fill the space between the pixel electrodes 48 after the patterning of the pixel electrodes 48. Of course, the edge protection film 81 may be formed to a height of 2 μm or more and 4 μm or less to serve as a bank of a metal mask (a spacer that prevents the metal mask from being in direct contact with the pixel electrode 48) when the organic EL material is separately applied. Needless to say.
[0104]
(Embodiment 4)
Hereinafter, a method for improving the extraction efficiency of the light generated in the EL display panel will be described. FIG. 301 illustrates a problem of a conventional EL display device. In FIG. 301, 2791 shows the locus of light.
[0105]
The light generated in the organic EL layer 47 is reflected by the reflective film 46 and emitted from the array substrate 49 on which the gate driver 12 (or the source driver 14) is formed. The light 2791 a is incident on the interface between the array substrate 49 and the air at a predetermined angle and is emitted from the array substrate 49. However, the light 2791 b incident at an angle equal to or greater than the critical angle θ is totally reflected within the array substrate 49. The totally reflected light 2791b is diffusely reflected in the array substrate 49, and the display contrast is lowered.
[0106]
The totally reflected light 2791b is lost, and the ratio of the lost light reaches 2/3 of the total luminous flux generated by the EL element 15. Therefore, reducing the generation of light 2791b directly leads to an improvement in light utilization.
[0107]
The configuration for solving this problem is the configuration of FIG. A refractive sheet (a light refracting member or a light refracting plate) is attached (arranged or formed) on the sealing film 73 described with reference to FIG. In the refraction sheet 2801, a refraction portion 2802 is formed on a triangle, polygon, or arc so as to correspond to the pixel 16. The refracting portion 2802 may be entirely constituted by a transparent member, or a reflective film may be formed on the portion indicated by a in FIG. 7 (the inner surface of the refracting portion 2802). The reflection film may be an interference film formed by forming a multilayer of a low refractive index dielectric film and a high refractive index dielectric film in addition to a metal film such as Al or silver. Further, the shape may be set so as to be a total reflection region according to Snell's law.
[0108]
In addition to the configuration in which the refractive sheet 2801 having the refractive portion 2802 formed thereon is attached to the sealing film 73, the refractive portion 2802 may be formed directly on the sealing film 73. Further, in the case of taking out the light, the array substrate 49 itself may be processed to form the refracting portion 2802. Moreover, you may form or arrange | position on a sealing board.
[0109]
The shape of the refracting portion 2802 is not limited to the inclined surface or the arc shape, but may be a polygonal shape or a vertical shape. In addition, a large number of needle-like protrusions may be formed densely. The refraction part 2802 is basically formed around the light emitting part of the pixel 16. That is, if the aperture ratio of the pixel 16 is 30%, the pixel 16 is formed in a non-light emitting portion (that is, a portion of 70%). Of course, it goes without saying that the formation position of the refraction part 2802 may overlap the light emission position.
[0110]
Note that although the refracting portion 2802 is basically formed in the peripheral portion of the light emitting portion of the pixel 16, it is preferable that the refractive portion 2802 be slightly changed in the peripheral portion of the central portion of the display screen 21. In the central part of the display screen 21, the refracting part 2802 is formed so as to be arranged just around the light emitting part of the pixel 16. In the peripheral part of the display screen 21, the refractive part 2802 is formed so as to be shifted outward from the center position of the light emitting part of the pixel 16. Thus, by changing the formation position of the refracting portion 2802 between the central portion and the peripheral portion of the display screen, the occurrence of moire can be suppressed and the occurrence of color unevenness can also be suppressed. In addition, the generation of moire can be suppressed and the occurrence of color unevenness can also be suppressed by forming the position of the refractive portion 2802 somewhat randomly for each pixel.
[0111]
Further, the light emitted from the EL element 15 may pass through the inside of the refraction unit 2802, and may be configured to be refracted by the refraction unit 2802 and emitted to the front surface of the panel. That is, the refraction part 2802 functions as a prism. In this case, the refraction part 2802 needs to be made of a light transmitting material.
[0112]
When the refracting portion 2802 is formed of a light transmitting material, it is effective to color this material. This is because the effect of the color filter that cuts the band of light emitted from the EL element 15 can be exhibited. Therefore, the color purity of the EL display panel is improved and the white balance is also improved. Further, when the EL element 15 emits white light, a color filter is not provided, and this refracting portion 2802 can be used as a color filter. Of course, a color filter may be separately formed, and a colored refracting portion 2802 may be formed or arranged. Further, the refracting portion 2802 or the refracting sheet 2801 may be directly colored, or these may be formed of a coloring material.
[0113]
As the coloring material, a material in which a pigment or pigment is dispersed in a resin may be used, or a material in which gelatin or casein is dyed with an acid dye like a color filter may be used. In addition, a fluorane dye can be used by coloring. In addition, three colors of RGB are not required, and any one or more colors may be used. Further, a natural resin can be dyed with a dye, or a material in which a dye is dispersed in a synthetic resin can be used. The selection range of the pigment may be one appropriate from azo dyes, anthraquinone dyes, phthalocyanine dyes, triphenylmethane dyes, or a combination of two or more thereof.
[0114]
The constituent material of the refractive part 2802 and the refractive sheet 2801 is preferably a polymer. As the polymer, it is preferable to use a photo-curing type resin in view of the ease of the manufacturing process, separation from the liquid crystal phase, and the like. As a specific example, an ultraviolet curable acrylic resin is preferable, and an acrylic monomer or an acrylic oligomer that is polymerized and cured by ultraviolet irradiation is particularly preferable.
[0115]
Among these, a photocurable acrylic resin having a fluorine group has little change with time and good light resistance.
[0116]
Polymer-forming monomers constituting the polymer include 2-ethylhexyl acrylate, 2-hydroxyethyl acrylate, neopentyl glycol acrylate, hexanediol diacrylate, diethylene glycol diacrylate, tripropylene glycol diacrylate, polyethylene glycol diacrylate, trimethylol Propane triacrylate, pentaerythritol acrylate, and the like.
[0117]
Examples of the oligomer or prepolymer include polyester acrylate, epoxy acrylate, polyurethane acrylate and the like.
[0118]
Further, a polymerization initiator may be used in order to perform the polymerization quickly. Examples of this include 2-hydroxy-2-methyl-1-phenylpropan-1-one ("Darocur 1173" manufactured by Merck & Co.), 1- (4-Isopropylphenyl) -2-hydroxy-2-methylpropan-1-one ("Darocur 1116" manufactured by Merck & Co., Inc.), 1-bidoxycyclohexyl phenyl ketone ("Irgacure 184" manufactured by Ciba Gaiky), benzylmethyl ketal ( Ciba Geigy's “Irgacure 651”) and the like. In addition, a chain transfer agent, a photosensitizer, a dye, a crosslinking agent, and the like can be appropriately used as optional components.
[0119]
In addition, the matter regarding the above polymer is mainly applied with the manufacturing method of FIG.13, FIG.14, FIG.15. In the manufacturing method of FIG. 16, the refractive portion 2802 is formed of an inorganic material, but of course, it may be formed of an organic material such as a polymer.
[0120]
The arrangement of the refracting portions 2802 may be hexagonal as shown in FIG. Of course, it may be an octagon or more. A refracting portion 2802 is formed around the light emitting portion of the pixel 16. By adopting the hexagonal shape in this manner, when the EL display panel is observed, even when the viewpoint of viewing the display screen is changed, the occurrence of color unevenness and color shift can be extremely reduced. Further, there is little occurrence of moire due to the positional deviation between the light emission position of the pixel 16 and the refractive portion 2802.
[0121]
FIG. 8 shows an example of a configuration (vertical stripe configuration) in which the same color is arranged in the vertical direction of the display screen 21. However, by forming the pixel color arrangement in a mosaic pattern as shown in FIG. Even when the number of dots constituting the image is relatively small, the resolution in the oblique direction of the image is improved.
[0122]
Further, as illustrated in FIG. 10, a plurality of refractive portions 2802 may be formed or arranged in one pixel 16. In the example of FIG. 10, the pixel 16 has one pixel electrode, and three bent portions 2802 (2802a, 2802b, 2802c) are formed (arranged) with respect to the one pixel electrode. Of course, one pixel 16 may have a plurality of pixel electrodes, and the refractive portions 2802 may be formed (arranged) for each pixel electrode. Note that since a driving or switching TFT or the like is disposed around the pixel electrode, even if the pixel electrode is divided into a plurality of pixel electrodes, the aperture ratio does not decrease much.
[0123]
Of course, as shown in FIG. 11, one refracting portion 2802 may be arranged (formed) in one pixel 16. Further, as shown in FIG. 12A, a plurality of (2 × 6 in FIG. 12A) refracting portions 2802 may be formed in one pixel in two columns. Further, as shown in FIG. 12B, a plurality of polygonal refraction portions 2802 such as hexagons (three in FIG. 12B) may be formed on one pixel electrode.
[0124]
(Embodiment 5)
Hereinafter, a manufacturing method for forming the refraction part 2802 (which may include the refraction sheet 2801) will be described.
[0125]
FIG. 13 shows a first embodiment of the present invention. First, the organic EL layer 47 is formed on the array substrate 49 on which the TFT 11, the pixel 16, the gate driver 12, the source driver 14, and the like are formed. In this formation, a low molecular EL film may be formed by vapor deposition, or a polymer EL film may be formed by an ink jet method. An electrode is formed on the organic EL layer 47, and a sealing film 73 is formed thereon (FIG. 13A). Further, a sealing plate may be attached. Since these items will be described in detail elsewhere, they are omitted here.
[0126]
Moreover, the manufacturing method described in the specification of this invention is applied except the matter demonstrated below. Needless to say, the configuration of the EL element 15, the pixel configuration, the array configuration, the panel configuration, the driving method, the driving circuit, and the like are also applied to the following manufacturing method or manufactured panel. In addition, an information display device, a television, a monitor, a camera, and the like can be configured using a panel manufactured by the following manufacturing method.
[0127]
Next, as shown in FIG. 13B, an uncured polymer material (transparent film 2861) is applied on the sealing film 73. This polymer material 2861 is the material of the refraction part 2802 described above. The coating may be performed by any method (technique) such as offset printing, screen printing, roller coating, or spinner coating.
[0128]
After application of uncured polymeric material 2861, it is placed in an oven and pre-dried. Alternatively, the fluidity of the polymer material 2861 is suppressed by irradiating the polymer material 2861 with weak light (which may be ultraviolet light (UV) or visible light). Thereafter, the roller 2862 having the shape of the refracting portion 2802 is pressed against the transparent film (polymer material) 2861 while rotating. Thus, the uneven shape of the roller 2862 is transferred to the transparent film 2861 (FIG. 13C). By this transfer, an uneven portion (concave portion) 2863 corresponding to the refractive portion 2802 is formed in the transparent film 2861. After the formation of the concavo-convex portion (concave portion) 2863, the entire transparent film 2861 is irradiated with UV or visible light to completely cure the transparent film 2861.
[0129]
Temperature control when polymerizing the transparent film 2861 is important. Heating should be 40 degrees or more and around 60 degrees. Ultraviolet rays (UV) depend on spectral distribution, but 20-30mW / cm2Irradiate at a moderate intensity for 2 to 8 seconds. These temperature and ultraviolet irradiation conditions must be determined in consideration of the additive of the transparent film 2861 and the like. When the conditions are inappropriate, the surface becomes cloudy or has fine irregularities. In the present invention, an ultrahigh pressure mercury lamp is used as a light source at a temperature of 50 ° C., and the transparent film 2861 is irradiated with ultraviolet rays (irradiation intensity on the substrate surface: 30 mW / cm2) For 6 seconds to cure the transparent film 2861.
[0130]
Note that an ultraviolet (UV) 2902 light source may be disposed inside the roller 2862, and the transparent film 2861 may be irradiated with UV as the roller 2862 progresses to be cured sequentially. Further, a UV 2902 generation source may be provided separately from the roller 2862, and the transparent film 2861 may be irradiated with UV from the generation source in accordance with the progress of the roller 2862, and may be cured sequentially. Further, a reflective film or the like is formed on a necessary portion of the refracting portion 2802. The configuration of the reflective film has been described with reference to FIG.
[0131]
Further, the refractive portion 2802 may be formed by the manufacturing method of FIG. Since FIGS. 14A and 14B are the same as FIGS. 13A and 13B, description thereof is omitted. In FIG. 14C, a press plate 2901 made of a transparent material is used. The press plate 2901 is formed with irregularities opposite in shape to the refracting portion 2802. The press plate 2901 is made of a transparent material such as quartz glass. By pressing the press plate 2901 against the transparent film 2861, the unevenness of the press plate 2901 is transferred to the transparent film 2861.
[0132]
As described above, by transferring the uneven shape of the press plate 2901 to the transparent film 2861, an uneven portion (concave portion) 2863 corresponding to the refracting portion 2802 is formed in the transparent film 2861. After the formation of the concavo-convex portion (concave portion) 2863, the entire transparent film 2861 is irradiated with UV or visible light 2902 through a press plate 2901 to completely cure the transparent film 2861.
[0133]
It is preferable to form a thin film having good releasability made of an olefin-based material on the uneven surface of the press plate 2901. By forming such a thin film having good releasability, the releasability between the transparent film 2861 and the press plate 2901 becomes good, and the production efficiency is improved. Note that temperature management is also important for both the press plate 2901 and the transparent film 2861. The press plate 2901 is preferably kept at a temperature lower by about 5 to 15 degrees than the transparent film 2861. Depending on the type of the transparent film 2861, the releasability may be improved when the temperature is reversed. Therefore, it is necessary to carry out experiments sufficiently and set conditions.
[0134]
Examples of the release film include silicon resin films, fluororesin films, olefin-based resin films such as polyethylene and polypropylene, and those obtained by applying silicon resin and fluororesin to the surface of the resin film. . In addition, anything is acceptable as long as it transmits ultraviolet rays and has a certain degree of flexibility. For example, a glass substrate or the like can be used.
[0135]
14D, after removing the press plate 2901, the entire transparent film 2861 is irradiated with UV (visible light) to completely cure the uncured resin component. This is the same when the transparent film 2861 is a thermosetting type or the like.
[0136]
In the manufacturing method described with reference to FIGS. 13 and 14 and the like, the transparent film 2861 is an ultraviolet curing type, but the present invention is not limited to this. For example, a resin material such as a thermoplastic resin material, a thermosetting resin material, and a two-component room-temperature curable resin material that begins to cure by mixing two liquids can also be used. In the above case, the polymer material (transparent film) 2861 does not need to be a transparent material. The selection range of the polymer material 2861 is also widened, and an epoxy resin, a phenol resin, or the like can be used. In this case, after forming the concavo-convex portion (concave portion) 2863, the refractive portion 2802 is formed by heating, leaving, or the like. Of course, the press plate 2901 may be cured while being pressed against the transparent film 2861. Further, a reflective film or the like is formed on a necessary portion of the refracting portion 2802. The configuration of the reflective film has been described with reference to FIG.
[0137]
FIG. 15 shows another embodiment of the present invention. The description up to FIG. 15A is the same as in the other embodiments, and a description thereof will be omitted.
[0138]
In FIG. 15B, a convex portion 2871 is formed on the sealing film 73. The formation position of the convex part 2871 is made to coincide with the formation position of the refractive part 2802. That is, it is the peripheral portion of the pixel peripheral portion or the light emitting portion of the pixel. In the liquid crystal display panel, it is the formation position of the black matrix (BM). The convex portion 2871 is made of SiO.2And using an inorganic material such as SiNx. Further, an organic material such as a transparent film 2861 may be used. As a method for forming the convex portion 2871, an inorganic thin film or an organic thin film is deposited or applied in a thickness of 0.5 to 3 μm on the sealing film 73 or the sealing plate. A mask is formed thereon, and negative or positive etching is performed using the mask (FIG. 15B).
[0139]
Next, as illustrated in FIG. 15C, a transparent film 2861 is applied to the entire display screen 21. The coating may be performed by any method (technique) such as offset printing, screen printing, roller coating, or spinner coating.
[0140]
The resin to be applied preferably has a viscosity of 5 cp to 40 cp. That is, a material having a relatively low viscosity is used. The transparent film 2861 is smoothly formed along the convex portion 2871. As described above, in FIG. 15, the refracting portion 2802 is formed by the convex portion 2871 and the transparent film 2861. Further, a reflective film or the like is formed on a necessary portion of the refracting portion 2802. The configuration of the reflective film has been described with reference to FIG.
[0141]
In FIG. 15C, the transparent film is applied to the entire display screen 21, but the present invention is not limited to this, and a thin film made of an inorganic material may be deposited. By depositing an inorganic material, the refracting portion 2802 is formed by the unevenness of the convex portion 2871.
[0142]
FIG. 16 shows another embodiment of the present invention. The description up to FIG. 16A is omitted because it is similar to the other embodiments. In FIG. 16B, a metal mask 2881 is disposed on the sealing film 73 or the sealing lid. The opening of the metal mask 2881 has a wide opening on the sealing film 73 side and a narrow side on the other surface side.
[0143]
The metal mask 2881 described with reference to FIG. 16 does not directly touch the sealing film 73 (or does not contact the sealing film 73 as much as possible), so that the back surface of the metal mask 2881 or the sealing film 73 is used. Alternatively, a protrusion having a height of 1.5 to 3 μm is formed on the surface of the sealing lid. The protrusion is formed at a location where the organic EL layer 47 is not deposited, for example, between adjacent pixels.
[0144]
As illustrated in FIG. 16B, the SiO 2 is interposed through the metal mask 2881.2And depositing an inorganic material such as SiNx. The deposition location is where the refractive portion 2802 is formed. Further, an organic material such as a transparent film 2861 may be used instead of the inorganic material. As described above, the refractive portion 2802 can be formed using the metal mask 2881.
[0145]
FIG. 7 is an illustration of a bent portion (or light reflecting portion) 2802 having a prism shape or the like. However, the present invention is not limited to this. For example, as shown in FIG. 17, a microlens-shaped refracting portion 2802 may be formed corresponding to the pixel 16. The microlens is preferably in a sine curve shape. Moreover, although it is preferable to form in circular arc shape, it is not limited to this, A bowl shape may be sufficient. The height of the microlens is preferably 15 μm or more and 3100 μm or less. Microlenses are formed by stamper technology. For this stamper technology, a method used by OMRON as a method for forming a microlens, a method used by Matsushita Electric as a method for forming a microlens with a CD pickup lens, and the like are applied. Further, the refraction part 2802 in FIG. 17 can also be formed of a diffraction grating. Since other matters are the same as those in FIG.
[0146]
As the vacuum deposition apparatus, an apparatus obtained by modifying a commercially available high vacuum deposition apparatus (manufactured by Nippon Vacuum Technology Co., Ltd., EBV-6DA type) is used. The main exhaust device is a turbo molecular pump (TC 1500, manufactured by Osaka Vacuum Co., Ltd.) with an exhaust speed of 1500 liter / min, and the ultimate vacuum is about 1 × 10e.-6Torr (133.322e-6Pa) or less, and all vapor deposition is 2-3 × 10e.-6Torr (266.644-399.966e-6Pa). All vapor deposition may be performed by connecting a DC power source (manufactured by Kikusui Electronics Co., Ltd., PAK10-70A) to a resistance heating vapor deposition boat made of tungsten.
[0147]
A carbon film of 20 to 50 nm is formed on the array substrate arranged in the vacuum layer in this way. Next, 4- (N, N-bis (p-methylphenyl) amino) -α-phenylstilbene is formed to a thickness of about 5 nm at a deposition rate of 0.3 nm / s as a hole injection layer.
[0148]
As a hole transport layer, N, N′-bis (4′-diphenylamino-4-biphenylyl) -N, N′-diphenylbenzidine (manufactured by Hodogaya Chemical Co., Ltd.) and 4-N, N-diphenylamino-α -Phenylstilbene is co-evaporated at a deposition rate of 0.3 nm / s and 0.01 nm / s, respectively, to form a film thickness of about 80 nm.
[0149]
As the light-emitting layer (electron transport layer), tris (8-quinolinolato) aluminum (manufactured by Dojin Chemical Co., Ltd.) is formed to a film thickness of about 40 nm at a deposition rate of 0.3 nm / s.
[0150]
Next, as an electron injection electrode, only Li at a low temperature from an Al-Li alloy (manufactured by High Purity Chemical Co., Ltd., Al / Li weight ratio 99/1) is deposited at a film thickness of about 1 nm at a deposition rate of about 0.1 nm / s. Then, the temperature of the Al-Li alloy is further raised, and from the state where Li is exhausted, only Al is formed at a deposition rate of about 1.5 nm / s to a film thickness of about 100 nm, and a stacked electron An injection electrode was obtained.
[0151]
The organic thin film EL device thus prepared leaks the inside of the vapor deposition tank with dry nitrogen, and then, in a dry nitrogen atmosphere, the sealing lid 41 made of Corning 7059 glass is used as the sealing agent 45 (trade name, manufactured by Anelva Corporation). : Super back seal 953-7000) to obtain a display panel. A desiccant 55 is disposed in the space between the sealing lid 41 and the array substrate 49. This is because the organic EL film is sensitive to humidity, so that moisture that permeates the sealant 45 is absorbed by the desiccant 55 to prevent the organic EL layer 47 from deteriorating.
[0152]
In order to suppress the penetration of moisture from the sealing agent 45, it is a good measure to lengthen the path from the outside. For this reason, in the display panel of the present invention, fine concave portions 43 and convex portions 44 are formed in the peripheral portion of the display area. The convex portions 44 formed on the peripheral portion of the array substrate 49 are formed at least double. The distance between the protrusions (projection pitch) is preferably 100 μm or more and 500 μm or less, and the height of the protrusions is preferably 30 μm or more and 300 μm or less. This convex portion is formed by a stamper technique.
[0153]
On the other hand, a recess 43 is also formed in the sealing lid 41. The formation pitch of the recesses 43 is the same as the formation pitch of the projections 44. In this way, by making the formation pitch the same, the convex portion 44 fits exactly into the concave portion 43, and no positional deviation occurs between the sealing lid 41 and the array substrate 49 during the manufacture of the display panel. A sealing agent 45 is disposed between the concave portion 43 and the convex portion 44. The sealing agent 45 adheres the sealing lid 41 and the array substrate 49 and prevents moisture from entering from the outside.
[0154]
As the sealant 45, it is preferable to use a UV (ultraviolet) curable resin made of an acrylic resin, and it is preferable to use an acrylic resin having a fluorine group. In addition, an epoxy adhesive or pressure-sensitive adhesive may be used. The refractive index of the adhesive or pressure-sensitive adhesive is preferably 1.47 or more and 1.54 or less. In particular, as the sealing adhesive, fine powder of titanium oxide, fine powder of silicon oxide or the like is added at a ratio of 65% to 95% by weight, and the average particle diameter of the fine powder is 20 μm to 100 μm. It is preferable. This is because the effect of suppressing the entry of humidity from the outside increases as the weight ratio of the fine powder increases. However, if the amount is too large, bubbles or the like are likely to enter, and on the contrary, the space becomes larger and the sealing effect is lowered.
[0155]
The weight of the desiccant is desirably 0.04 g or more and 0.2 g or less, particularly 0.06 g or more and 0.15 g or less per 10 mm of the seal length. This is because when the amount of the desiccant is too small, the moisture prevention effect is reduced and the organic EL layer is immediately deteriorated. On the other hand, if the amount is too large, the desiccant becomes an obstacle when sealing, and good sealing cannot be performed.
[0156]
Although it is the structure sealed using the glass sealing lid 41 in FIG. 2, the sealing using a film may be sufficient as FIG. For example, as the sealing film, it is exemplified that a film of an electrolytic capacitor on which DLC (diamond-like carbon) is deposited is used. Since this film has extremely poor moisture permeability (moisture resistance), it can be used as the sealing film 73. Moreover, the structure which vapor-deposits a DLC film directly on the surface of the transparent electrode 72 may be sufficient. The thickness of the thin film is calculated by n · d (where n is the refractive index of the thin film, and when a plurality of thin films are stacked, the refractive indexes thereof are combined (calculating n · d of each thin film). When the plurality of thin films are laminated, their refractive indexes are calculated together.) Is preferably equal to or less than the emission main wavelength λ of the EL element 15. By satisfying this condition, the light extraction efficiency from the EL element 15 becomes twice or more as compared with the case of sealing with a glass substrate. Further, an alloy or a mixture or a laminate of aluminum and silver may be formed.
[0157]
Half of the light generated from the organic EL layer 47 is reflected by the reflective film 46 and is transmitted through the array substrate 49 and emitted. However, since the reflective film 46 reflects external light, reflection occurs, and the display contrast is lowered. For this measure, a λ / 4 plate 50 and a polarizing plate 54 are arranged on the array substrate 49. When the pixel is a reflective electrode, the light generated from the organic EL layer 47 is emitted upward. Therefore, the λ / 4 plate 50 and the polarizing plate 54 must be disposed on the light emitting side. The reflective pixel is obtained by forming the pixel electrode 48 from aluminum, chromium, silver or the like. Further, by providing the surface of the pixel electrode 48 with projections (or projections and depressions), the interface with the organic EL layer 47 is widened, the emission area is increased, and the emission efficiency is improved.
[0158]
One or a plurality of phase films (phase plate, phase rotation means, phase difference plate, phase difference film) are disposed between the array substrate 49 and the polarizing plate (polarizing film) 54. Polycarbonate is preferably used as the phase film. This phase film generates a phase difference between incident light and outgoing light, and contributes to efficient light modulation.
[0159]
In addition, as the phase film, an organic resin plate or an organic resin film such as a polyester resin, a PVA resin, a polysulfone resin, a vinyl chloride resin, a ZEONEX resin, an acrylic resin, or a polystyrene resin may be used. In addition, crystals such as quartz may be used. The phase difference of one phase plate is preferably 50 nm to 350 nm, more preferably 80 nm to 220 nm in a uniaxial direction.
[0160]
As shown in FIG. 5, a circularly polarizing plate 74 (circularly polarizing film) in which a phase film and a polarizing plate are integrated may be used.
[0161]
The λ / 4 plate (phase film) 50 is preferably colored with a dye or a pigment to have a function as a color filter. In particular, since the organic EL layer has poor red (R) purity, the colored λ / 4 plate 50 cuts a certain wavelength range to adjust the color temperature. The color filter is generally provided with a pigment dispersion type resin as a dyeing filter, and the pigment absorbs light in a specific wavelength band and transmits light in a wavelength band not absorbed.
[0162]
As described above, a part or the whole of the phase film may be colored, or a part or the whole may have a diffusion function. Further, the surface may be embossed or an antireflection film may be formed to prevent reflection. In addition, it is preferable to form a light-shielding film or a light absorption film at a location that is not effective or unhindered for image display so as to increase the black level of the display image or to exhibit a contrast enhancement effect by preventing halation. Further, by forming irregularities on the surface of the phase film, microlenses may be formed in a kamaboko shape or a matrix shape. The microlenses are arranged so as to correspond to one pixel electrode or three primary color pixels, respectively.
[0163]
As described above, since the phase difference can be generated by rolling or photopolymerization when forming the color filter, the color filter may have the function of the phase film. In addition, the phase difference may be given by photopolymerizing the smoothing film 71 of FIG. If comprised in this way, it will become unnecessary to comprise or arrange | position a phase film out of a board | substrate, the structure of a display panel will also become simple and cost reduction can be expected. The above matters can be applied to the polarizing plate 54.
[0164]
The polarizing plate 54 is exemplified by a resin film in which iodine or the like is added to polyvinyl alcohol (PVA) resin. The polarizing plates of the pair of polarization separation means perform polarization separation by absorbing a polarized light component in a direction different from a specific polarization axis direction in incident light, so that light use efficiency is relatively poor. Therefore, a reflective polarizer that performs polarization separation by reflecting a polarized component (reflective polarizer) in a direction different from a specific polarization axis direction of incident light may be used. If comprised in this way, the utilization efficiency of light will increase with a reflective polarizer, and a brighter display will be attained rather than the above-mentioned example using a polarizing plate.
[0165]
In addition to such polarizing plates and reflective polarizers, the polarization separation means of the present invention is a combination of a cholesteric liquid crystal layer and a (1/4) λ plate, and reflective polarization using the Brewster angle. It is also possible to use a polarization beam splitter (PBS), etc.
[0166]
Although not shown in FIG. 2, the surface of the polarizing plate 54 is provided with an AIR coat.
[0167]
Although the TFT is connected to the pixel electrode 48, the present invention is not limited to this. In the active matrix, as a switching element, a thin film transistor (TFT), a diode system (TFD), a varistor, a thyristor, a ring diode, a photodiode, a phototransistor, an FET, a MOS transistor, a PLZT element, and the like are possible. That is, any of those constituting the switching element and the driving element can be used.
[0168]
In addition, it is preferable to adopt an LDD (low doping drain) structure for the TFT. Note that TFT means all elements that perform transistor operations such as switching, such as FETs. Further, the structure of the EL film, the panel structure, and the like can be applied to a simple matrix display panel. In this specification, an organic EL element (OEL, PEL, PLED, OLED) is described as an example of the EL element, but the present invention is not limited to this, and the present invention is also applicable to an inorganic EL element.
[0169]
There are two active matrix methods used for organic EL display panels: (1) a specific pixel can be selected and necessary display information can be given, and (2) current can flow through the EL element over one frame period. The condition must be met.
[0170]
In order to satisfy these two conditions, in the conventional organic EL element configuration shown in FIG. 302, the first TFT 11a is a switching thin film transistor for selecting a pixel, and the second TFT 11b is for supplying current to the EL element 15. Driving thin film transistor.
[0171]
Here, compared with the active matrix system used for the liquid crystal, the switching TFT 11a is necessary for the liquid crystal, but the driving TFT 11b is necessary for lighting the EL element 15. This is because in the case of liquid crystal, the on state can be maintained by applying a voltage, but in the case of the EL element 15, the lighting state of the pixel 16 cannot be maintained unless a current is continuously supplied.
[0172]
Therefore, in order to keep the current flowing in the organic EL display panel, the driving TFT 11b must be kept on. First, when both the scanning line and the data line are turned on, charges are accumulated in the capacitor 19 through the switching TFT 11a. Since the capacitor 19 continues to apply a voltage to the gate of the driving TFT 11b, the current continues to flow from the current supply line 20 even when the switching TFT 11a is turned off, and the pixel 16 can be turned on for one frame period.
[0173]
When displaying gradation using this configuration, it is necessary to apply a voltage corresponding to the gradation as the gate voltage of the driving TFT 11b. Therefore, the variation in the on-current of the driving TFT 11b appears in the display as it is.
[0174]
The on-current of a transistor is extremely uniform if it is a single crystal transistor, but in a low-temperature polycrystalline transistor formed by low-temperature polysilicon technology with a formation temperature of 450 degrees or less that can be formed on an inexpensive glass substrate. Since the threshold value varies in a range of ± 0.2 V to 0.5 V, the on-current flowing through the driving TFT 11b varies correspondingly, and display unevenness occurs. These irregularities are caused not only by variations in the threshold voltage but also by the mobility of the TFT and the thickness of the gate insulating film. The characteristics also change due to the deterioration of the TFT 11.
[0175]
Therefore, in the method of displaying gradation in an analog manner, it is necessary to strictly control the device characteristics in order to obtain a uniform display. In the current low-temperature polycrystalline polysilicon TFT, this variation is suppressed within a predetermined range. I can not meet the specifications. In order to solve this problem, there are four transistors in one pixel, and a method of obtaining a uniform current by compensating for variations in threshold voltage with a capacitor, or a constant current circuit for each pixel to make the current uniform A method for achieving this can be considered.
[0176]
However, in these methods, since the programmed current is made through the EL element 15, the transistor that controls the drive current becomes a source follower to the switching transistor connected to the power supply line when the current path changes, and the drive margin Becomes narrower. Therefore, there is a problem that the drive voltage becomes high.
[0177]
In addition, it is necessary to use a switching transistor connected to a power source in a low impedance region, and there is a problem that this operation range is affected by fluctuations in characteristics of the EL element 15. In addition, when the kink current occurs in the voltage-current characteristics in the saturation region, or when the threshold voltage of the transistor varies, there is a problem that the stored current value varies.
[0178]
In the EL element structure of the present invention, the TFT 11 that controls the current flowing through the EL element 15 does not have a source follower configuration and the influence of the kink current is minimized even if the transistor has a kink current. In this configuration, the variation of the stored current value can be reduced.
[0179]
Specifically, as shown in FIG. 6A, the EL element structure of the present invention is formed by a plurality of TFTs 11 and EL elements 15 each having at least four unit pixels. Note that the pixel electrode is configured to overlap the source signal line. That is, an insulating film or a smoothing film made of an acrylic material is formed on the source signal line 18 for insulation, and a pixel electrode is formed on the insulating film. The configuration in which the pixel electrode is overlaid on the source signal line 18 in this way is called a high aperture (HA) structure.
[0180]
By making the first gate signal line (first scanning line) 17a active (ON voltage applied), the first TFT (or switching element) 11a and the third TFT (or switching element) 11c are passed through. The second TFT 11b activates the first gate signal line 17a (applies an ON voltage) so that a current value to be passed through the EL element 15 is passed and the gate and drain of the first TFT 11a are short-circuited. The gate voltage (or drain voltage) of the first TFT 11a is stored so that the current value flows through the capacitor 19 connected between the gate and source of the first TFT 11a.
[0181]
Note that the capacitor 19 that is the source-gate capacitance of the first TFT 11a is preferably set to have a capacitance of 0.2 pF or more. As another configuration, there is an example in which the capacitor 19 is separately formed. That is, this is a configuration in which a storage capacitor is formed from the capacitor electrode layer, the gate insulating film, and the gate metal. From the standpoint of preventing luminance reduction due to leakage of the M3 transistor 11c and stabilizing the display operation, it is preferable to form a separate capacitor in this way. The size of the capacitor 19 is preferably 0.2 pF or more and 2 pF or less, and more preferably 0.4 pF or more and 1.2 pF or less.
[0182]
The capacitor 19 is preferably formed in a non-display area between adjacent pixels. Generally, when creating a full-color organic EL layer, since the organic EL layer is formed by mask vapor deposition using a metal mask, there is a risk that the position of the organic EL layer is shifted and the organic EL layers of the respective colors overlap. There is. Therefore, the non-display area between adjacent pixels of each color must be separated by 10 μm or more, and this part does not contribute to light emission. Therefore, forming the capacitor 19 in this region is an effective means for improving the aperture ratio.
[0183]
Next, the first gate signal line 17a is inactive (OFF voltage is applied), the second gate signal line 17b is active, and the current flow path is connected to the first TFT 11a and the EL element 15. 4 is switched to a path including the TFT 11 d and the EL element 15, and the stored current is supplied to the EL element 15.
[0184]
This circuit has four TFTs 11 in one pixel, the gate of the first transistor M1 is connected to the source of the second transistor M2, and the gates of the second transistor M2 and the third transistor M3. Are connected to the first gate signal line 17a, the drain of the second transistor M2 is connected to the source of the third transistor M3 and the source of the fourth transistor M4, and the drain of the third transistor M3 is connected to the source signal line 18. It is connected. The gate of the fourth transistor M4 is connected to the second gate signal line 17b, and the drain of the fourth transistor M4 is connected to the anode electrode of the EL element 15.
[0185]
In FIG. 6, all TFTs are configured by P-channel. The P-channel is somewhat less mobile than the N-channel TFT, but is preferable because it has a high breakdown voltage and is unlikely to deteriorate. However, the present invention is not limited to the EL element configuration configured by the P channel. You may comprise only N channel (refer FIG. 158, FIG. 159, FIG. 85, etc.), and you may comprise using both N channel and P channel.
[0186]
The third and fourth transistors are preferably configured with the same polarity and configured with an N channel, and the first and second transistors are preferably configured with a P channel. In general, P-channel transistors have features such as higher reliability and less kink current compared to N-channel transistors. For EL elements that obtain the desired light emission intensity by controlling the current. If the first TFT 11a is a P channel, the effect is increased.
[0187]
(Embodiment 6)
Hereinafter, the EL element configuration of the present invention will be described with reference to FIG. The EL device configuration of the present invention is controlled by two timings. The first timing is a timing for storing a necessary current value. When the TFT 11b and the TFT 11c are turned on at this timing, an equivalent circuit is shown in FIG. Here, a predetermined current I1 is written from the signal line, the TFT 11a is connected to the gate and the drain, and the current I1 flows through the TFT 11a and the TFT 11c. Therefore, the voltage between the gate and the source of the TFT 11a becomes V1 so that the current I1 flows.
[0188]
The second timing is a timing at which the TFT 11a and the TFT 11c are closed and the TFT 11d is opened, and the equivalent circuit at that time is shown in FIG. In this case, since the TFT 11a of M1 always operates in the saturation region, the current I1 becomes constant, and the voltage V1 between the source and gate of the TFT 11a remains held.
[0189]
The gate of the TFT 11a and the gate of the TFT 11c are connected to the same gate signal line 17a. However, the gate of the TFT 11a and the gate of the TFT 11c may be connected to different gate signal lines 17b (so that SA1 and SA2 can be individually controlled). That is, there are three gate signal lines for one pixel (the configuration in FIG. 6 is two). By individually controlling the ON / OFF timing of the gate of the TFT 11a and the ON / OFF timing of the gate of the TFT 11c, the current value variation of the EL element 15 due to the variation of the TFT 11 can be further reduced.
[0190]
When the first gate signal line 17a and the second gate signal line 17b are made common and the third and fourth transistors have different conductivity types (N channel and P channel), the driving circuit is simplified, and the pixel The aperture ratio can be improved. With this configuration, the write path from the signal line is turned off as the operation timing of the present invention. That is, when a predetermined current is stored, if there is a branch in the current flow path, an accurate current value is not stored in the source-gate capacitance (capacitor) of M1. The third transistor M3 and the fourth transistor M4 have different conductivity types, and by controlling the threshold values of each other, the M4 can be turned on after the M3 is always turned off at the switching timing of the scanning lines. However, in this case, attention must be paid to the process because it is necessary to accurately control each other's threshold values.
[0191]
Although the circuit described above can be realized with at least four transistors, the TFT 11e (M5) is configured as shown in FIG. 6B to control the timing more accurately or to reduce the mirror effect as will be described later. The operation principle is the same even if the total number of transistors is 4 or more by cascade connection. As described above, by adding the TFT 11e, the current programmed through the third transistor M3 can be supplied to the EL element 15 with higher accuracy.
[0192]
In the configuration of FIG. 6, it is more preferable that the current value Ids in the saturation region of the first TFT 11a satisfies the following formula. In the following expression, the value of λ satisfies the condition of 0.01 or more and 0.06 or less between adjacent pixels.
[0193]
Ids = k * (Vgs−Vth)2(1 + Vds * λ)
In the present invention, the operating range of the TFT 11a is limited to the saturation region, but generally the transistor characteristics in the saturation region deviate from the ideal characteristics and are affected by the source-drain voltage (mirror effect).
[0194]
Consider a case where a threshold value shift of ΔVt occurs in each TFT 11a in an adjacent pixel. In this case, the stored current values are the same. If the threshold shift is ΔL, approximately ΔV × λ corresponds to a shift in the current value of the EL element 15 due to a change in the threshold of the TFT 11a. Therefore, in order to suppress the current deviation to x (%) or less, λ must be 0.01 × x / y or less, where y (V) is the threshold shift allowable amount between adjacent pixels. I understand. This tolerance varies depending on the brightness of the application. Brightness is 100 cd / m2~ 1000cd / m2In the luminance region up to, if the fluctuation amount is 2% or more, the human recognizes the fluctuating boundary line. Therefore, it is necessary that the variation amount of the luminance (current amount) is within 2%. Brightness is 100 cd / cm2If it is higher, the luminance change amount of adjacent pixels is 2% or more. When the EL display element of the present invention is used as a display for a portable terminal, the required luminance is 100 cd / m.2Degree. Actually, when the pixel configuration of FIG. 6 was prototyped and the fluctuation of the threshold was measured, it was found that the maximum value of the fluctuation of the threshold was 0.3 V in the TFT 11a of the adjacent pixel. Therefore, λ must be 0.06 or less in order to keep the luminance variation within 2%. However, since humans cannot recognize the change, it is not necessary to make it 0.01 or less. Further, in order to achieve this variation in threshold value, it is necessary to make the transistor size sufficiently large, which is unrealistic.
[0195]
Further, it is preferable that the current value Ids in the saturation region of the first TFT 11a satisfies the following formula. Note that the variation of λ is 1% or more and 5% or less between adjacent pixels.
[0196]
Ids = k * (Vgs−Vth)2(1 + Vds * λ)
Even if there is no change in threshold between adjacent pixels, if there is a change in λ in the above equation, the value of the current flowing through the EL element will change. In order to suppress the fluctuation within ± 2%, the fluctuation of λ must be suppressed to ± 5%. However, since humans cannot recognize changes, it is not necessary to make it 1% or less. In order to achieve 1% or less, the transistor size needs to be considerably increased, which is unrealistic.
[0197]
Further, according to experiments, array trial manufacture, and examination, it is preferable that the channel length of the first TFT 11a is 10 μm or more and 200 μm or less, and further 15 μm or more and 150 μm or less. This is considered to be because when the channel length L is increased, the electric field is relaxed by increasing the grain boundaries contained in the channel, and the kink effect is suppressed to a low level.
[0198]
Further, the TFT 11 constituting the pixel is formed of a polysilicon TFT formed by a laser recrystallization method (laser annealing), and the channel direction in all transistors is the same direction as the laser irradiation direction. Is preferred.
[0199]
An object of the present invention is to propose a circuit configuration in which variations in transistor characteristics do not affect display. For this purpose, four or more transistors are required. When determining circuit constants based on these transistor characteristics, it is difficult to obtain appropriate circuit constants if the characteristics of the four transistors are not aligned. When the channel direction is horizontal and vertical with respect to the major axis direction of laser irradiation, the threshold value and mobility of transistor characteristics are different. In both cases, the degree of variation is the same. Since the mobility and the average value of the threshold values are different between the horizontal direction and the vertical direction, it is desirable that the channel directions of all the transistors constituting the pixel are the same.
[0200]
Further, when the capacitance value of the capacitor 19 is Cs and the off-current value of the second TFT 11b is Ioff, it is preferable that the following equation is satisfied.
[0201]
3 <Cs / Ioff <24
More preferably, it is preferable to satisfy the following formula.
[0202]
6 <Cs / Ioff <18
By setting the off-state current of the TFT 11b to 5 pA or less, it is possible to suppress the change in the current value flowing through the EL element to 2% or less. This is because when the leakage current increases, the electric charge stored between the gate and the source (both ends of the capacitor) cannot be held for one field in the voltage non-writing state. Therefore, if the storage capacity of the capacitor 19 is large, the allowable amount of off-current is also large. By satisfying the above equation, the fluctuation of the current value between adjacent pixels can be suppressed to 2% or less.
[0203]
In addition, it is preferable that the transistor constituting the active matrix is a p-ch polysilicon thin film transistor and the TFT 11b has a multi-gate structure having a dual gate structure or more. Since the TFT 11b functions as a switch between the source and the drain of the TFT 11a, a characteristic having a high ON / OFF ratio is required as much as possible. In order to satisfy this requirement, a high ON / OFF ratio characteristic can be realized by making the gate structure of the TFT 11b a multi-gate structure.
[0204]
The transistors constituting the active matrix are composed of polysilicon thin film transistors, and the (channel width W) * (channel length L) of each transistor is 54 μm.2The following is preferable. There is a correlation between (channel width W) * (channel length L) and variations in transistor characteristics. The cause of variations in transistor characteristics is often caused by variations in energy due to laser irradiation, and in order to absorb this, the laser irradiation pitch (generally a few tens of μm) is increased as much as possible in the channel. It is desirable to have a structure that includes it. Therefore, the (channel width W) * (channel length L) of each transistor is 54 μm.2By making the following, a thin film transistor with uniform characteristics can be obtained without variation due to laser irradiation. If the transistor size is too small, characteristic variation due to area occurs. Therefore, (channel width W) * (channel length L) of each transistor is 9 μm.2Or more, and 16 μm2More than 45μm2It is preferable to be as follows.
[0205]
Further, it is preferable that the mobility variation of the first TFT 11a in adjacent unit pixels is 20% or less. This is because the charging capability of the switching transistor is deteriorated due to insufficient mobility, and the capacity between the gate and the source of the first transistor M1 cannot be charged before a necessary current value is passed in time. Therefore, by suppressing the variation in movement to within 20%, it is possible to reduce the luminance variation between pixels below the recognition limit.
[0206]
As described above, FIG. 6 is described as a pixel configuration, but these can also be applied to the configurations illustrated in FIGS. 19 and 20. Hereinafter, the pixel configuration in FIG. 19 will be described.
[0207]
When setting the current to flow to the EL element 15, the signal current to flow to the conversion TFT 11a is set to Iw, and as a result, the gate-source voltage generated in the conversion TFT 11a is set to Vgs. At the time of writing, since the gate and drain of the conversion TFT 11a are short-circuited by the TFT 11d, the conversion TFT 11a operates in the saturation region. Therefore, the signal current Iw is given by the following equation.
[0208]
(Equation 1) Iw = μ1 · Cox1 · W1 / L1 / 2 (Vgs−Vth1)2
Here, Cox is a gate capacitance per unit area, and is given by Cox = ε0 · εr / d. Vth is the TFT threshold, μ is the carrier mobility, W is the channel width, L is the channel length, ε0 is the vacuum mobility, εr is the relative dielectric constant of the gate insulating film, and d is the thickness of the gate insulating film. is there.
[0209]
Assuming that the current flowing through the EL element 15 is Idd, the current level of Idd is controlled by the driving TFT 11 b connected in series with the EL element 15. In the present invention, since the voltage between the gate and the source coincides with Vgs in the equation (1), the following equation is established if it is assumed that the driving TFT 11b operates in the saturation region.
[0210]
(Equation 2) Idrv = μ 2 · Cox 2 · W 2 / L 2/2 (Vgs−Vth 2)2
The conditions for an insulated gate field effect thin film transistor (TFT) to operate in the saturation region are generally given by the following equation, where Vds is the drain-source voltage.
[0211]
(Equation 3) | Vds |> | Vgs−Vth |
Here, since the conversion TFT 11a and the driving TFT 11b are formed close to the inside of a small pixel, they are approximately μ1 = μ2 and Cox1 = Cox2, and it is considered that Vth1 = Vth2 unless particularly devised. Then, at this time, the following formula is easily derived from the formula (1) and the formula (2).
[0212]
(Formula 4) Idrv / Iw = (W2 / L2) / (W1 / L1)
The point to be noted here is that in the equations (1) and (2), the values of μ, Cox, and Vth themselves usually vary from pixel to pixel, from product to product, or from production lot to production lot. Since the equation (4) does not include these parameters, the value of Idrv / Iw does not depend on these variations. If W1 = W2 and L1 = L2 are designed, Idrv / Iw = 1, that is, Iw and Idrv have the same value, and the drive current Idd flowing through the EL element 15 is accurate regardless of variations in TFT characteristics. Since it becomes the same as the signal current Iw, the light emission luminance of the EL element 15 can be accurately controlled as a result.
[0213]
As described above, since the threshold value Vth1 of the conversion TFT 11a and the threshold value Vth2 of the driving TFT 11b are basically the same, when a signal voltage having a cut-off level is applied to the gate at a common potential in both TFTs, Both the conversion TFT 11a and the driving TFT 11b should be non-conductive. However, in practice, Vth2 may be lower than Vth1 due to factors such as parameter variations within the pixel. At this time, since a sub-threshold level leakage current flows through the driving TFT 11b, the EL element 15 emits slight light emission. This slight light emission reduces the contrast of the screen and impairs display characteristics.
[0214]
In the present invention, in particular, the threshold voltage Vth2 of the driving TFT 11b is set not to be lower than the threshold voltage Vth1 of the corresponding conversion TFT 11a in the pixel. For example, the gate length L2 of the driving TFT 11b is made longer than the gate length L1 of the conversion TFT 11a so that Vth2 does not become lower than Vth1 even if the process parameters of these thin film transistors fluctuate. Leakage can be suppressed. The above matters also apply to the relationship between the conversion TFT 11a and the TFT 11d in FIG.
[0215]
As shown in FIG. 19, the pixel circuit is controlled by controlling the first scanning line scanA (SA) in addition to the driving TFT 11b for controlling the driving current flowing in the light emitting element including the conversion TFT 11a and the EL element 15 through which the signal current flows. Of the conversion TFT 11a, the switching TFT 11d for short-circuiting between the gate and the drain of the conversion TFT 11a during the writing period by the control of the second scanning line scanB (SB). A capacitor 19 for holding the gate-source voltage even after the writing is completed, an EL element 15 as a light emitting element, and the like. As described above, since the gate signal line is two pixels, the configuration, function, operation, and the like of the entire specification of the present invention based on FIG. 6 described above can be applied.
[0216]
The capture TFT 11c in FIG. 19 is composed of an N-channel MOS (NMOS), and the other transistors are composed of a P-channel MOS (PMOS), but this is an example, and this is not necessarily the case. One terminal of the capacitor 19 is connected to the gate of the conversion TFT 11a and the other terminal is connected to Vdd (power supply potential). However, the capacitor 19 is not limited to Vdd, and may be any constant potential. The cathode (cathode) of the EL element 15 is connected to the ground potential. Therefore, it goes without saying that the above items also apply to FIG.
[0217]
The terminal voltage of the EL element 15 also changes depending on the temperature. Usually, it is high when the temperature is low, and decreases as the temperature increases. This tendency is linear. Therefore, it is preferable to adjust the Vdd voltage by the external temperature (more precisely, by the temperature of the EL element 15). The external temperature is detected by the temperature sensor, and the Vdd voltage is changed by applying feedback of the Vdd voltage generator. The Vdd voltage is a change of 10 ° C. and is preferably 2% to 8%, and more preferably 3% to 6%.
[0218]
Note that the Vdd voltage in FIG. 6 and the like is preferably lower than the off voltage of the TFT 11. Specifically, Vgh (gate off voltage) should be at least higher than Vdd-0.5V. If it is lower than this, off-leakage of the TFT occurs, and laser annealing shot unevenness becomes conspicuous. On the other hand, if it is too high, the amount of off-leakage increases, so it should be lower than Vdd + 4V. Therefore, the gate off voltage Vgh, that is, the Vdd power supply voltage in FIG. 6 should be −0.5 V or more and +4 V or less, more preferably 0 V or more and +2 V or less. The TFT off voltage applied to the gate signal line is To be off enough. When the TFT has an N channel, Vgl is an off voltage, and therefore Vgl is preferably in the range of −4 V to 0.5 V, more preferably −2 V to 0 V with respect to the GND voltage.
[0219]
The current program pixel configuration of FIG. 6 has been described above, but the present invention is not limited to this, and it is needless to say that the present invention can also be applied to the voltage program pixel configurations of FIG. 85, FIG. The Vt offset cancellation of the voltage program is preferably compensated individually for each of R, G, and B.
[0220]
The configuration of FIG. 19 includes data including a scanning line driving circuit that sequentially selects the scanning lines scanA and scanB, and a current source CS that generates a signal current Iw having a current level according to luminance information and sequentially supplies it to the data line data. A line driving circuit; and a plurality of pixels including current-driven EL elements 15 that are arranged at intersections of the scanning lines scanA and scanB and the data lines data and emit light upon receiving a driving current. .
[0221]
As a feature, the pixel configuration shown in FIG. 19 includes a receiving unit (specifically, a capturing TFT 11c) that captures a signal current Iw from the data line data when the scanning line scanA is selected. A conversion unit that once converts the current level of the captured signal current Iw into a voltage level and holds it, and a driving current having a current level corresponding to the held voltage level, corresponding to the light-emitting element OLED (EL, OEL, PEL and PLED).
[0222]
The conversion unit includes a conversion TFT 11a having a gate, a source, a drain, and a channel, and a capacitor 19 connected to the gate. The conversion TFT 11a and the signal current Iw taken in by the receiving unit are passed through the channel to generate a converted voltage level at the gate, and the voltage level generated in the capacitor 19 is held.
[0223]
The converter includes a switching TFT 11d inserted between the drain and gate of the conversion TFT 11a. The switching TFT 11d becomes conductive when the current level of the signal current Iw is converted to a voltage level, and the drain and gate of the conversion TFT 11a are electrically connected to generate a voltage level based on the source at the gate of the conversion TFT 11a. Close. The switching TFT 11d is cut off when the voltage level is held in the capacitor 19, and the gate of the conversion TFT 11a and the capacitor 19 connected thereto are separated from the drain of the conversion TFT 11a.
[0224]
The driving unit includes a driving TFT 11b having a gate, a drain, a source, and a channel. The driving TFT 11b receives the voltage level held in the capacitor 19 at the gate, and a driving current having a current level corresponding to the voltage level flows to the EL element 15 through the channel. The gate of the conversion TFT 11a and the gate of the driving TFT 11b are directly connected to form a current mirror circuit so that the current level of the signal current Iw and the current level of the driving current are in a proportional relationship.
[0225]
The driving TFT 11b operates in a saturation region, and a driving current corresponding to the difference between the voltage level applied to its gate and the threshold voltage is supplied to the EL element 15.
[0226]
The driving TFT 11b is set so that its threshold voltage does not become lower than the threshold voltage of the corresponding conversion TFT 11a in the pixel. Specifically, the driving TFT 11b is set so that its gate length is not shorter than the gate length of the conversion TFT 11a. Alternatively, the driving TFT 11b may be set so that the gate insulating film thereof is not thinner than the gate insulating film of the corresponding conversion TFT 11a in the pixel.
[0227]
Further, the driving TFT 11b may be set so that the threshold voltage does not become lower than the threshold voltage of the corresponding conversion TFT 11a in the pixel by adjusting the concentration of impurities injected into the channel. If the threshold voltages of the conversion TFT 11a and the driving TFT 11b are set to be the same, when the signal voltage of the cut-off level is applied to the gates of both of the commonly connected thin film transistors, the conversion TFT 11a and the driving TFT 11b Should both be off. However, in reality, there are slight variations in process parameters within the pixel, and the threshold voltage of the driving TFT 11b may be lower than the threshold voltage of the conversion TFT 11a.
[0228]
At this time, since the weak current of the sub-threshold level flows to the driving TFT 11b even with a signal voltage equal to or lower than the cut-off level, the EL element 15 emits light slightly and the contrast of the screen appears. Therefore, the gate length of the driving TFT 11b is made longer than the gate length of the conversion TFT 11a. Thereby, even if the process parameter of the thin film transistor varies within the pixel, the threshold voltage of the driving TFT 11b does not become lower than the threshold voltage of the conversion TFT 11a.
[0229]
In the short channel effect region A where the gate length L is relatively short, the TFT threshold Vth increases as the gate length L increases. On the other hand, in the suppression region B where the gate length L is relatively large, regardless of the gate length L, the threshold value Vth of the TFT is substantially constant. Using this characteristic, the gate length of the driving TFT 11b is made longer than the gate length of the conversion TFT 11a. For example, when the gate length of the conversion TFT 11a is 7 μm, the gate length of the drive TFT 11b is set to about 10 μm.
[0230]
The gate length of the conversion TFT 11a may belong to the short channel effect region A, while the gate length of the drive TFT 11b may belong to the suppression region B. Thereby, the short channel effect in the driving TFT 11b can be suppressed, and the threshold voltage reduction due to the process parameter variation can be suppressed. As described above, the sub-threshold level leakage current flowing through the driving TFT 11b can be suppressed, so that the light emission of the EL element 15 can be suppressed and the contrast can be improved.
[0231]
A method for driving the pixel circuit shown in FIG. 19 will be briefly described. First, at the time of writing, the first scanning line scanA and the second scanning line scanB are selected. By connecting the current source CS to the data line data in a state where both scanning lines are selected, the signal current Iw corresponding to the luminance information flows through the conversion TFT 11a. The current source CS is a variable current source that is controlled according to luminance information. At this time, since the gate and the drain of the conversion TFT 11a are electrically short-circuited by the switching TFT 11d, Expression (3) is established, and the conversion TFT 11a operates in the saturation region. Therefore, a voltage Vgs given by the equation (1) is generated between the gate and the source.
[0232]
Next, the first scanning line scanA and the second scanning line scanB are brought into a non-selected state. More specifically, first, the second scanning line scanB is set to a low level, and the switching TFT 11d is turned off. As a result, the voltage Vgs is held by the capacitor 19. Next, the pixel circuit and the data line data are electrically disconnected by setting the first scanning line scanA to a high level to be in the off state, and thereafter, the pixel line and the data line data are electrically disconnected from each other. Can write. Here, the data output as the current level of the signal current by the current source CS is valid at the time when the second scanning line scanB is not selected, but after that any level (for example, writing of the next pixel) Data).
[0233]
Since the driving TFT 11b has a gate and a source connected in common with the conversion TFT 11a and is formed close to the inside of a small pixel, if the driving TFT 11b operates in the saturation region, the driving TFT 11b The flowing current is given by the equation (2), that is, the driving current Idd flowing through the EL element 15. In order to operate the driving TFT 11b in the saturation region, a sufficient power supply potential may be applied to the Vdd voltage so that the formula (3) is satisfied even when the voltage drop in the EL element 15 is taken into consideration.
[0234]
As in FIG. 6B and the like, TFTs 11e and 11f may be added as shown in FIG. 20 for the purpose of increasing the impedance, thereby realizing better current drive. . The other items are described in FIG.
[0235]
A DC voltage is applied to the EL display element described in FIG. 6 and FIG.2Were continuously driven at a constant current density of. In the EL structure, 7.0 V, 200 cd / cm2Of green light (maximum light emission wavelength λmax = 460 nm) was confirmed. In the blue light emitting part, the luminance is 100 cd / cm.2And the color coordinates are x = 0.129, y = 0.105, and in the green light emitting part, the luminance is 200 cd / cm.2In the case where the color coordinates are x = 0.340, y = 0.625, and the red light emitting part, the luminance is 100 cd / cm.2Thus, an emission color having color coordinates of x = 0.649 and y = 0.338 was obtained.
[0236]
(Embodiment 7)
Hereinafter, a display device, a display module, an information display device, a driving circuit, a driving method, and the like using FIGS. 6, 19 and 20 will be described.
[0237]
In full-color organic EL display panels, improvement of the aperture ratio is an important development issue. This is because increasing the aperture ratio increases the light utilization efficiency, leading to higher brightness and longer life. In order to increase the aperture ratio, the area of the TFT that blocks light from the organic EL layer may be reduced. A low-temperature polycrystalline Si-TFT has a performance 10 to 100 times that of amorphous silicon, and further has a high current supply capability, so that the size of the TFT can be very small. Therefore, in the organic EL display panel, it is preferable that the pixel transistor and the peripheral drive circuit are manufactured by a low temperature polysilicon technique. Of course, it may be formed by amorphous silicon technology, but the pixel aperture ratio becomes considerably small.
[0238]
By forming a driving circuit such as the gate driver 12 or the source driver 14 on the array substrate 49, it is possible to reduce a resistance that is particularly problematic in a current-driven organic EL display panel. That is, the connection resistance of TCP is eliminated, and the lead-out line from the electrode is shortened by 2 to 3 mm as compared with the case of TCP connection, and the wiring resistance is reduced. Furthermore, there is an advantage that the process for TCP connection is eliminated and the material cost is reduced.
[0239]
(Embodiment 8)
Next, the EL display panel or EL display device of the present invention will be described. FIG. 21 is an explanatory diagram focusing on the circuit of the EL display device. Pixels 16 are arranged or formed in a matrix. Each pixel 16 is connected to a source driver 14 that outputs a current for current programming of each pixel. A current mirror circuit corresponding to the number of bits of the video signal is formed at the output stage of the source driver 14. For example, in the case of 64 gradations, 63 current mirror circuits are formed for each source signal line, and a desired current can be applied to the source signal line 18 by selecting the number of these current mirror circuits. It is configured. Note that the minimum output current of one current mirror circuit is preferably 10 nA to 50 nA, particularly 15 nA to 35 nA. This is to ensure the accuracy of the transistors constituting the current mirror circuit in the source driver 14.
[0240]
A precharge or discharge circuit for forcibly releasing or charging the source signal line 18 is incorporated. The voltage (current) output value of this circuit is preferably configured so that it can be set independently for R, G, and B because the threshold values of the EL elements 15 are different for RGB.
[0241]
As described above, it goes without saying that the pixel configuration, array configuration, panel configuration, and the like described so far are applied to the configuration, method, and apparatus described later.
[0242]
It is known that an organic EL element has a large temperature dependency characteristic (temperature characteristic). In order to adjust the light emission luminance change due to the temperature characteristics, a non-linear element such as a thermistor or a posistor that changes the output current is added to the current mirror circuit, and the temperature characteristics change is adjusted by the thermistor as an analog reference. Create a current. In this case, since it is uniquely determined by the EL material to be selected, there is often no need for a microcomputer or the like for software control. That is, it may be fixed to a certain shift amount or the like by a liquid crystal material. What is important is that the temperature characteristics differ depending on the luminescent color material, and it is necessary to perform optimum temperature characteristics compensation for each luminescent color (R, G, B).
[0243]
Needless to say, it is preferable that the R, G, and B EL elements 15 have no temperature characteristics, but the temperature characteristics of each EL element must be within a certain range. At least the temperature characteristic directions of R, G, and B are the same or not changed. Further, the change is a change of 10 ° C. for each color, and it is preferably 2% or more and 8% or less, more preferably 3% or more and 6% or less.
[0244]
Alternatively, temperature compensation may be performed by a microcomputer. The temperature of the EL display panel is measured with a temperature sensor, and is changed by a microcomputer (not shown) or the like according to the measured temperature. Further, the reference current or the like may be automatically switched by microcomputer control or the like at the time of switching, or control may be performed so that a specific menu can be displayed. Moreover, it may be configured to be switched by using a mouse or the like, or by switching the display screen of the EL display device to a touch panel and displaying a menu and pressing a specific portion.
[0245]
In the present invention, the source driver 14 is formed of a semiconductor silicon chip, and is connected to the terminal of the source signal line 18 of the array substrate 49 by a glass-on-chip (COG) technique. For wiring of signal lines such as the source signal line 18, metal wiring such as chromium, aluminum, and silver is used. This is because a low resistance wiring with a narrow wiring width can be obtained. Since the process can be simplified when the pixel is of a reflective type, the metal wiring is preferably formed simultaneously with the reflective film by using a material constituting the reflective film of the pixel.
[0246]
The present invention is not limited to the COG technology, and the above-described source driver 14 and the like may be mounted on the chip-on-film (COF) technology and connected to the signal line of the display panel. Further, the source driver 14 may have a three-chip configuration by separately manufacturing the power supply IC 102.
[0247]
A TCF tape may be used. A film for TCF tape can be thermocompression bonded without using an adhesive to a polyimide film and a copper (Cu) foil. In addition to the film for TCP tape, in addition to this, a method of casting a melted polyimide on a Cu foil and a method of casting Cu on a metal film formed by sputtering on a polyimide film by plating or vapor deposition There is. Any of these methods may be used, but a method using a TCP tape for attaching Cu to a polyimide film without using an adhesive is most preferable. For the lead pitch of 30 μm or less, a Cu-laminated laminate without using an adhesive is used. Among the methods for forming a Cu-clad laminate without using an adhesive, a method of forming a Cu layer by plating or vapor deposition is suitable for thinning the Cu layer, which is advantageous for miniaturization of the lead pitch.
[0248]
On the other hand, the gate driver 12 is formed by the same process as the TFT of the pixel by a low temperature polysilicon technology. This is because the internal structure is easier and the operating frequency is lower than that of the source driver 14. Therefore, it can be formed easily even by low-temperature polysilicon technology, and a narrow frame can be realized. Of course, the gate driver 12 may be formed of a silicon chip and mounted on the array substrate 49 using COG technology or the like. In addition, switching elements such as pixel TFTs, gate drivers, and the like may be formed by high-temperature polysilicon technology or may be formed by an organic material (organic TFT).
[0249]
The gate driver 12 includes a shift register 22a for the gate signal line 17a and a shift register 22b for the gate signal line 17b. Each shift register 22 is controlled by positive and negative phase clock signals (CLKxP, CLKxN) and a start pulse (STx). In addition, it is preferable to add an enable (ENABL) signal for controlling the output and non-output of the gate signal line and an up / down (UPDWM) signal for reversing the shift direction up and down. In addition, it is preferable to provide an output terminal for confirming that the start pulse is shifted to the shift register and output. Note that the shift timing of the shift register is controlled by a signal from a control IC (not shown). A level shift circuit for performing level shift of external data and an inspection circuit are incorporated.
[0250]
Since the buffer capacity of the shift register 22 is small, the gate signal line 17 cannot be driven directly. Therefore, at least two or more inverter circuits 23 are formed between the output of the shift register 22 and the output gate 24 that drives the gate signal line 17.
[0251]
The same applies to the case where the source driver 14 is formed directly on the array substrate 49 by polysilicon technology such as low-temperature polysilicon, and between the gate of an analog switch such as a transfer gate that drives the source signal line and the shift register 22 of the source driver. A plurality of inverter circuits 23 are formed. The following items (the output of the shift register and the output stage that drives the signal line (related to the inverter circuit arranged between the output stages such as the output gate or transfer gate)) are common to the source driver and the gate driver circuit. 21, for example, the output of the source driver 14 is illustrated as being directly connected to the source signal line 18, but in reality, a multistage inverter circuit 23 is connected to the output of the shift register 22 of the source driver. The output of the inverter circuit is connected to the gate of an analog switch such as a transfer gate.
[0252]
The inverter circuit 23 includes a P-channel MOS transistor and an N-channel MOS transistor. As described above, the inverter circuit 23 is connected in multiple stages to the output terminal of the shift register 22 of the gate driver 12, and its final output is connected to the output gate 24. Note that the inverter circuit 23 may be composed of only the P channel. However, in this case, it may be configured as a simple gate circuit instead of an inverter circuit.
[0253]
An inverter close to a shift register, where the channel width of the P-channel or N-channel TFT constituting each inverter circuit 23 is W and the channel length is L (in the case of a double gate or more, the width or channel length of the constituting channel is added) Is 1 and the order of the inverter near the display side is N (Nth stage).
[0254]
If the number of connected stages of the inverter circuit 23 is large, characteristic differences of the connected inverter circuits 23 are multiplexed (stacked), and a difference occurs in transmission time from the shift register 22 to the output gate 24 (delay time variation). For example, in an extreme case, in FIG. 21, the output gate 24a is turned on after 1.0 μsec (starting from the output of the pulse from the shift register) (the output voltage is switched), but the output gate 24b is A state occurs in which the output is turned on (output voltage is switched) after 1.5 μsec (starting from the output of the pulse from the shift register).
[0255]
Therefore, the number of inverter circuits 23 formed between the shift register 22 and the output gate 24 should be small, but the gate width W of the TFT channel constituting the output gate 24 should be very large. Further, since the gate drive capability of the output stage of the shift register 22 is small, it is impossible to drive the output gate 24 directly by a gate circuit (NAND circuit or the like) constituting the shift register. Therefore, it is necessary to connect the inverters in multiple stages. For example, the size of W4 / L4 (channel width of P channel / channel length of P channel) of the inverter circuit 23d in FIG. 21 and the size of W3 / L3 of the inverter circuit 23c. If the ratio is large, the delay time becomes long, and the characteristics of the inverter also vary greatly.
[0256]
FIG. 22 shows the relationship between delay time variation (dotted line) and delay time ratio (solid line). The horizontal axis is indicated by (Wn-1 / Ln-1) / (Wn / Ln). For example, in FIG. 21, if the channel length L of the inverter circuit 23d and the inverter circuit 23c is the same and 2W3 = W4, (W3 / L3) / (W4 / L4) = 0.5. In the graph of FIG. 22, the delay time ratio is 1 when (Wn−1 / Ln−1) / (Wn / Ln) = 0.5, and the time variation is 1 as well as the delay.
[0257]
FIG. 22 shows that as (Wn−1 / Ln−1) / (Wn / Ln) increases, the number of connection stages of the inverter circuit 23 increases and the delay time variation also increases. Further, it is shown that the delay time from the inverter circuit 23 to the inverter circuit 23 at the next stage becomes longer as (Wn−1 / Ln−1) / (Wn / Ln) becomes smaller. From this graph, it can be seen that it is advantageous in design that the delay time ratio and the delay time variation are within two. Therefore, what is necessary is just to satisfy the conditions of following Formula.
[0258]
0.25 ≦ (Wn−1 / Ln−1) / (Wn / Ln) ≦ 0.75
The P channel W / L ratio (Wp / Lp) and the N channel W / L ratio (Ws / Ls) of each inverter circuit 23 must satisfy the following relationship.
[0259]
0.4 ≦ (Ws / Ls) / (Wp / Lp) ≦ 0.8
Furthermore, the number n of stages of the inverter circuit 23 formed between the output terminal of the shift register and the output gate (or transfer gate) satisfies the following equation, and therefore, the variation in delay time is small and good.
[0260]
3 ≦ n ≦ 8
Mobility μ also has challenges. When the mobility μn of the N-channel transistor is small, the sizes of the TG and the inverter are increased, and the power consumption and the like are increased. In addition, the driver formation area increases and the panel size also increases. On the other hand, if the mobility μn is large, the characteristics of the transistor are likely to be deteriorated. Therefore, the mobility μn is preferably in the following range.
[0261]
50 ≦ μn ≦ 150
The slew rate of the clock signal in the shift register 22 is set to 500 V / μsec or less. This is because when the slew rate is high, the N-channel transistor is severely deteriorated.
[0262]
In FIG. 21, the inverter circuit 23 is connected in multiple stages to the output of the shift register, but it may be a NAND circuit. This is because an inverter can also be configured with a NAND circuit. That is, the number of connection stages of the inverter circuit 23 may be considered as the number of gate connection stages. Also in this case, the relationship such as the W / L ratio described so far is applied. Further, the matters described with reference to FIGS. 21 and 22 are also applied to FIGS. 66, 67, 69, and the like.
[0263]
Further, in FIG. 21 and the like, when the switching transistor of the pixel is a P channel, the output from the final stage inverter is the ON voltage Vgl applied to the gate signal line 17 and the OFF voltage Vgh applied to the gate signal line 17. . Conversely, when the pixel switching transistor is N-channel, the output from the final stage inverter is applied with the off voltage Vgl applied to the gate signal line 17 and the on voltage Vgh applied to the gate signal line 17.
[0264]
In the above embodiment, the gate driver is manufactured at the same time as the pixel 16 using high-temperature polysilicon or low-temperature polysilicon technology. However, the present invention is not limited to this. For example, as shown in FIG. 23, the source driver 14 and the gate driver 12 made of a semiconductor chip may be separately mounted on the display panel 82.
[0265]
When the display panel 82 is used for an information display device such as a mobile phone, the source driver 14 and the gate driver 12 are preferably mounted on one side of the display panel as shown in FIG. The configuration in which the driver IC is mounted on the display area is referred to as a three-side free configuration (structure), where the gate driver 12 is mounted on the X side of the display area and the source driver 14 is mounted on the Y side). This is because it is easy to design the center line of the display screen 21 to be the center of the display device, and it is easy to mount the driver IC. Note that the gate driver circuit may be manufactured as a three-side free configuration using high-temperature polysilicon or low-temperature polysilicon technology (that is, at least one of the source driver 14 and the gate driver 12 in FIG. 23 is polysilicon). Directly formed on the array substrate 49 by a technique).
[0266]
The three-side free configuration is not limited to a configuration in which an IC is directly stacked on or formed on the array substrate 49, but a film (TCP, TAB technology, etc.) on which the source driver 14, the gate driver 12, etc. are attached A configuration in which a side (or almost one side) is pasted is also included. In other words, it means a configuration, arrangement, or all similar to that where no IC is mounted or attached to two sides.
[0267]
As shown in FIG. 23, when the gate driver 12 is disposed beside the source driver 14, the gate signal line 17 needs to be formed up to the display screen 21 along the side C (see FIG. 24 and the like).
[0268]
Note that the pitch of the gate signal lines 17 formed on the C side is 5 μm or more and 12 μm or less. This is because if it is less than 5 μm, noise will be applied to the adjacent gate signal line due to the influence of parasitic capacitance. According to the experiment, the influence of the parasitic capacitance is remarkably generated at 7 μm or less, and when it is less than 5 μm, the image noise such as a beat is generated intensely on the display screen. In particular, the occurrence of noise differs between the left and right sides of the screen, and it is difficult to reduce image noise such as a beat. On the other hand, if the reduction exceeds 12 μm, the frame width D of the display panel becomes too large to be practical.
[0269]
In order to reduce the image noise described above, a grant pattern (a conductive pattern whose voltage is fixed to a constant voltage or set to a stable potential as a whole) is disposed in the lower layer or upper layer of the portion where the gate signal line 17 is formed. Can be reduced. Further, a separately provided shield plate (shield foil (conductive pattern fixed to a constant voltage or set to a stable potential as a whole)) may be disposed on the gate signal line 17.
[0270]
The gate signal line 17 on the C side in FIG. 24 may be formed of an ITO electrode. However, in order to reduce the resistance, it is preferable to form a stacked layer of ITO and a metal thin film or a metal film. When laminating with ITO, a titanium film is formed on ITO, and an aluminum or aluminum / molybdenum alloy thin film is formed thereon. Alternatively, a chromium film is formed on ITO. In the case of a metal film, it is formed of an aluminum thin film or a chromium thin film. The above matters are the same in other embodiments of the present invention.
[0271]
In FIG. 24 and the like, the gate signal lines 17 and the like are arranged on one side of the display area. However, the present invention is not limited to this and may be arranged on both sides. For example, the gate signal line 17a may be arranged (formed) on the right side of the display screen 21 and the gate signal line 17b may be arranged (formed) on the left side of the display screen 21. The above matters are the same in other embodiments.
[0272]
In FIG. 25, the source driver 14 and the gate driver 12 are integrated into one chip (one-chip driver IC 14c). If one chip is used, only one IC chip needs to be mounted on the display panel 82. Therefore, the mounting cost can be reduced. Various voltages used in the one-chip driver IC 14c can be generated at the same time.
[0273]
The source driver 14, the gate driver 12, and the one-chip driver IC 14c are made of a semiconductor wafer such as silicon and mounted on the display panel 82. However, the present invention is not limited to this, and the low-temperature polysilicon technology and the high-temperature polysilicon technology are used. May be formed directly on the display panel 82.
[0274]
In FIG. 26, the gate drivers 12a and 12b are mounted (or formed) at both ends of the source driver 14, but the present invention is not limited to this. For example, as shown in FIG. 23, one gate driver 12 may be arranged on one side adjacent to the source driver 14. In FIG. 26 and the like, a portion indicated by a thick solid line indicates a portion where the gate signal lines 17 are formed in parallel. Therefore, the gate signal lines 17 corresponding to the number of scanning signal lines are formed in parallel in the portion b (lower screen), and one gate signal line 17 is formed in the portion a (upper screen).
[0275]
As shown in FIG. 26, when two gate drivers 12a and 12b are used, the number of gate signal lines 17a formed in parallel with the C side in FIG. 26 becomes 1/2 of the number of scanning lines (on the left and right sides of the screen). This is because half the number of gate signal lines can be arranged). Therefore, the frame has a feature that it is uniform on the left and right of the screen.
[0276]
The present invention is also characterized by the scanning direction of the gate signal line 17 and the screen division. For example, in FIG. 26, the gate driver 12a is connected to the gate signal line 17b at the top of the screen. The gate driver 12b is connected to the gate signal line 17a at the bottom of the screen. The scanning direction of the gate signal line 17 is also from the top to the bottom of the screen as indicated by the arrow A. The source signal line 18 is common to the upper part of the screen and the lower part of the screen.
[0277]
In FIG. 27, the gate driver 12a is connected differently from the adjacent gate signal line 17 at the top of the screen. The gate driver 12a is connected to the odd-numbered gate signal line 17b. The gate driver 12b is connected to the even-numbered gate signal line 17a. The scanning direction of the gate signal line is the direction from the top to the bottom of the screen (arrow A). The gate signal line 17a is from the bottom to the top of the screen (arrow B). In this way, by connecting the gate signal line 17 to the gate driver 12 and by setting the scanning method of the gate signal line to a predetermined direction, the display screen 21 is not inclined in luminance and flicker is also generated. Can be suppressed. The source signal line 18 is common to the upper part of the screen and the lower part of the screen. However, it goes without saying that it may be divided at the top and bottom of the screen. The above matters also apply to other embodiments.
[0278]
In FIG. 25, which is made into one chip, the gate driver 12a is connected to the gate signal line 17b at the top of the screen. The gate driver 12b is connected to the gate signal line 17a at the bottom of the screen. As indicated by the arrow A, the scanning direction of the gate signal line 17b is from the top to the bottom of the screen. As indicated by an arrow B, the scanning direction of the gate signal line 17a is from the bottom to the top of the screen. The source signal line 18 is common to the upper part of the screen and the lower part of the screen. In this way, by connecting the gate signal line 17 to the gate driver 12 and by setting the scanning method of the gate signal line to a predetermined direction, the display screen 21 is not inclined in luminance and flicker is also generated. Can be suppressed.
[0279]
The one-chip driver IC 14c is made of a semiconductor wafer such as silicon and mounted on the display panel 82. However, the present invention is not limited to this, and the one-chip driver IC 14c is formed directly on the display panel 82 by low-temperature polysilicon technology or high-temperature polysilicon technology. May be. In addition, a driver IC that drives the upper part of the screen may be arranged on the upper side of the display screen, and a driver IC that drives the lower part of the screen may be arranged on the lower side of the display screen (that is, the mounted IC has two chips). The above matters also apply to other embodiments of the present invention.
[0280]
In FIGS. 25 and 26, the screen is expressed as being divided at the center, but the present invention is not limited to this. For example, in the case of FIG. 26, the display screen 21a may be reduced and the display screen 21b may be increased. This display screen 21a is used as a partial display area (see FIG. 28), and mainly displays time and date and is used in the low power consumption mode. 25 and 26, the display screen 21a is displayed by the gate signal line 17b, and the display screen 21b is displayed by the gate signal line 17a.
[0281]
28 and the like, as shown in FIG. 29, the display screen 21a may have a three-side free configuration, and the display screen 21b may have a configuration in which the conventional source driver 14 and the gate driver 12 are arranged on separate sides. . That is, the gate signal line 17a and the source signal line 18a are output from the one-chip driver IC 14c.
[0282]
Further, as shown in FIG. 30, the display screen 21 may be divided into two screens 21a and 21b, and the source driver 14 and the gate driver 12 corresponding to each screen may be arranged. In FIG. 30, the writing time of the video signal output from each source driver 14 is twice as long as that of the other embodiments, so that the signal can be sufficiently written to the pixel. Further, as shown in FIG. 31, there may be one display screen 21, and the source drivers 14 may be arranged one by one above and below the screen. This can be similarly applied to the gate driver 12.
[0283]
In the above embodiment, the gate signal lines 17 are formed in parallel and wired to the pixel region. However, the present invention is not limited to this. As shown in FIG. Needless to say, the wiring may be arranged parallel to the side.
[0284]
In FIG. 28, FIG. 29, FIG. 30, etc., changing the frame rate (drive frequency or the number of screen rewrites per unit time (one second)) on the display screens 21a and 21b is also an effective means for reducing power consumption. It is. Further, changing the number of display colors or the display colors on the display screens 21a and 21b is also effective for reducing power consumption.
[0285]
In the configuration illustrated in FIG. 6, the cathode of the EL element 15 is connected to the Vs1 potential. However, there is a problem that the driving voltage of the organic EL constituting each color is different. For example, when a current of 0.01 A is applied per unit square centimeter, the terminal voltage of the EL element is 5 V in blue (B), but 9 V in green (G) and red (R). That is, the terminal voltage differs between B, G, and R. Therefore, the source / drain voltages (SD voltage) of the TFTs 11c and 11d held by B, G and R are different, and the off-leak current between the source-drain voltages (SD voltage) of the transistors is different for each color. When off-leakage current is generated and the off-leakage characteristic is different for each color, flickering occurs when the color balance is shifted, and the gamma characteristic is shifted in correlation with the emission color.
[0286]
In order to cope with this problem, in the present invention, as shown in FIG. 33, the potential of one cathode electrode of at least R, G, and B colors is made different from the potential of the cathode electrode of the other color. Yes. Specifically, in FIG. 33, B is the cathode electrode 53a, and G and R are the cathode electrodes 53b. In addition, although FIG. 33 assumes the bottom extraction which takes out light from a glass surface, it may be an upper extraction. In this case, the cathode and the anode are reversed.
[0287]
Needless to say, the terminal voltages of the R, G, and B EL elements 15 are preferably matched as much as possible. At least the white peak luminance is displayed, and it is necessary to select a material or a structure so that the terminal voltage of the R, G, and B EL elements is 10 V or less in the color temperature range of 6000 K to 9000 K. Further, among R, G, and B, the difference between the maximum terminal voltage and the minimum terminal voltage of each EL element needs to be within 2.5V, more preferably 1.5V or less. In the above embodiment, the color is RGB, but is not limited to this. This will be explained later.
[0288]
In addition, color unevenness correction is also necessary. This color unevenness is caused by variations in film thickness and characteristics because different colors of EL materials are applied separately. In order to correct this, white raster display is performed at a luminance of 30% to 70%, and the in-plane distribution of each color in the display screen 21 is measured. The in-plane distribution is measured one point at least every 30 pixels. The measurement data is stored in a table made of memory, and the stored image is used to correct the input image data and display it on the display screen 21.
[0289]
The pixels are three primary colors of R, G, and B, but are not limited to this, and may be three colors of cyan, yellow, and magenta. Moreover, two colors of B and yellow may be used, and of course, a single color may be used. Also, six colors of R, G, B, cyan, yellow, and magenta may be used, or five colors of R, G, B, cyan, and magenta may be used. These are natural colors and the color reproduction range is expanded, and a good display can be realized. In addition, four colors of R, G, B, and white may be used, and eight colors of R, G, B, cyan, yellow, magenta, black, and white may be used. Alternatively, white light emitting pixels may be formed (manufactured) on the entire display screen 21 to display three primary colors using a color filter such as RGB, and light emitting materials of each color may be stacked on the EL layer. Further, one pixel may be painted separately as B and yellow. As described above, the EL display device of the present invention is not limited to one that performs color display with the three primary colors RGB.
[0290]
In addition to the three primary colors, a white light emitting pixel 16W may be formed as shown in FIG. The white light emitting pixel 16W is manufactured (formed or configured) by stacking R, G, and B light emitting structures, and one set of pixels includes the three primary colors of RGB and the white light emitting pixel 16W. Thus, by forming pixels emitting white light, white peak luminance can be easily expressed, and a bright image display can be realized.
[0291]
Even when the three primary colors of RGB are used as one set of pixels, it is preferable that the areas of the pixel electrodes of the respective colors are made different as shown in FIG. Of course, if the luminous efficiency of each color is well balanced and the color purity is well balanced, the same area may be used. However, when the balance of one or more colors is poor, it is preferable to adjust the pixel electrode (light emission area), and the electrode area of each color may be determined based on the current density. That is, when the white balance is adjusted within a color temperature range of 6000 K (Kelvin) to 9000 K, the difference in current density between the colors may be within ± 30%, and more preferably within ± 15%. For example, if the current density is 100 A / square meter, the three primary colors are all set to 70 A / square meter to 130 A / square meter, more preferably 85 A / square meter to 115 A / square meter.
[0292]
Also, as shown in FIG. 36, it is preferable to arrange the three primary colors differently in adjacent pixel rows. For example, if the even-numbered row has an arrangement of R, G, B from the left, the odd-numbered row has an arrangement of B, G, R. By arranging in this way, the resolution in the oblique direction of the image is improved even with a small number of pixels. Further, the first row from the left is arranged R, G, B, R, G, B, the second row is arranged G, B, R, G, B, R, the third row is B, R, The pixel arrangement may be different in three or more pixel rows so as to have the arrangement of G, B, R, and G.
[0293]
The cathode electrode 53a is formed using a metal mask technique in which organic EL of each color is separately applied. The metal mask is used because organic EL is weak to water and cannot be etched. Using a metal mask (not shown), a cathode electrode 53a is deposited and simultaneously connected to the contact hole 52a. The contact hole 52a can be electrically connected to the B cathode wiring 51a.
[0294]
Similarly, the cathode electrode 53b is formed using a metal mask technique in which organic ELs of different colors are separately applied. Using a metal mask (not shown), a cathode electrode 53b is deposited and simultaneously connected to the contact hole 52b. The contact hole 52b can be electrically connected to the RG cathode wiring 51b. Note that the aluminum film thickness of the cathode electrode is preferably 70 nm to 200 nm.
[0295]
With the above configuration, different voltages can be applied to the cathode electrodes 53a and 53b. Therefore, even if the Vdd voltage in FIG. 6 is common to each color, the voltage applied to at least one color EL element of RGB is set. Can be changed. In FIG. 33, RG is the same cathode electrode 53b. However, the present invention is not limited to this, and R and G may be different cathode electrodes.
[0296]
With the configuration described above, it is possible to prevent the occurrence of an off-leakage current between the source-drain voltage (SD voltage) of the transistor and the kink phenomenon in each color. Therefore, no flicker occurs, and a good image display can be realized without a gamma characteristic being shifted in correlation with the emission color.
[0297]
Further, Vs1 in FIG. 6 is set as the cathode voltage, and the cathode voltage is made different for each color. However, the present invention is not limited to this, and the anode voltage Vdd may be made different for each color. For example, the V pixel voltage of the R pixel may be 8V, G may be 6V, and B may be 10V. These anode voltage and cathode voltage are preferably configured to be adjustable within a range of ± 1V.
[0298]
Even when the panel size is about 2 inches, a current of nearly 100 mA is output from the anode connected to the Vdd voltage. Therefore, it is essential to reduce the resistance of the anode wiring (current supply line) 20. In order to cope with this problem, in the present invention, as shown in FIG. 37, the anode wiring 63 is supplied from the upper side and the lower side of the display area (both ends feeding). By supplying power at both ends as described above, the occurrence of a luminance gradient at the top and bottom of the screen is eliminated.
[0299]
In order to increase the light emission luminance, the pixel electrode 48 is preferably roughened. This configuration is shown in FIG. First, fine irregularities are formed at a location where the pixel electrode 48 is to be formed using a stamper technique. When the pixel is a reflection type, the pixel electrode 48 is formed by forming a metal thin film of about 200 nm of aluminum by sputtering. A convex portion is provided at a location where the pixel electrode 48 is in contact with the organic EL element, and the surface is roughened. In the case of a simple matrix display panel, the pixel electrode 48 is a striped electrode. Moreover, a convex part is not limited only to convex shape, A concave shape may be sufficient. Moreover, you may form a concave and a convex simultaneously.
[0300]
The size of the protrusions is about 4 μm in diameter, the average distance between adjacent points is 10 μm, 20 μm, and 40 μm, and the unit area density of the protrusions is 1000 to 1200 / mm, respectively.2, 100-120 pieces / mm2600-800 pieces / mm2As a result of the luminance measurement, it has been found that the emission luminance increases as the unit area density of the protrusions increases. Therefore, it was found that by changing the unit area density of the protrusions on the pixel electrode 48, the light emission luminance can be adjusted by changing the surface state of the pixel electrode. According to the study, the unit area density of protrusions is 100 / mm.2800 pieces / mm or more2Good results could be obtained with the following.
[0301]
Organic EL is a self-luminous element. When light emitted by this light emission enters a TFT as a switching element, a photoconductor phenomenon (photoconversion) occurs. “Photocon” refers to a phenomenon in which leakage (off leakage) increases when a switching element such as a TFT is turned off by photoexcitation.
[0302]
In order to cope with this problem, in the present invention, as shown in FIG. 38, a light shielding film 91 is formed below the gate driver 12 (or the source driver 14 in some cases) and below the pixel TFT 11. The light shielding film 91 is formed of a metal thin film such as chromium, and the film thickness is 50 nm or more and 150 nm or less. This is because if the film thickness is thin, the light-shielding effect is poor, and if it is thick, unevenness is generated, making it difficult to pattern the upper TFT 11.
[0303]
A smoothing film 71a made of an inorganic material having a thickness of 20 nm to 100 nm is formed on the light shielding film 91. Alternatively, one electrode of the capacitor 19 may be formed using the layer of the light shielding film 91. In this case, it is preferable to make the smoothing film 71a as thin as possible and increase the capacitance value of the capacitor. Alternatively, the light shielding film 91 may be formed of aluminum, a silicon oxide film may be formed on the surface of the light shielding film 91 using an anodic oxidation technique, and the silicon oxide film may be used as a dielectric film of the capacitor 19. A pixel electrode having a high aperture (HA) structure is formed on the smoothing film 71b.
[0304]
The gate driver 12 and the like should suppress light from not only the back surface but also the front surface. This is because it malfunctions due to the influence of the photocon. Therefore, in the present invention, when the cathode electrode is a metal film, the cathode electrode is also formed on the surface of the gate driver 12 or the like, and this electrode is used as a light shielding film.
[0305]
However, if a cathode electrode is formed on the gate driver 12, a malfunction of the driver due to an electric field from the cathode electrode or an electrical contact between the cathode electrode and the driver circuit may occur. In order to cope with this problem, in the present invention, at least one layer, preferably a plurality of layers of organic EL films are formed on the gate driver 12 and the like simultaneously with the formation of the organic EL film on the pixel electrode. Since the organic EL film is basically an insulator, by forming the organic EL film on the gate driver, the cathode and the gate driver are isolated, and the above-described problems can be solved.
[0306]
In the pixel, when the terminals of one or more TFTs 11 or the TFT 11 and the signal line are short-circuited, the EL element 15 may be constantly lit and become a bright spot. Since these bright spots are visually conspicuous, it is necessary to make them black (not lit). As a countermeasure, the corresponding pixel 16 is detected, and the capacitor 19 is irradiated with laser light to short-circuit the terminals of the capacitor. Then, the capacitor 19 can no longer hold electric charge, and the TFT 11 can no longer pass current.
[0307]
At this time, it is desirable to remove the cathode film corresponding to the position where the laser beam is irradiated. This is to prevent the terminal electrode of the capacitor 19 and the cathode film from being short-circuited by laser light irradiation.
[0308]
The structure illustrated in FIG. 39 is also illustrated. FIG. 39 shows an example of a lower extraction structure for extracting light from the array substrate 49 side. Also in FIG. 39, a light shielding film is formed below the gate driver 12 (or the source driver 14 in some cases) and below the pixel TFT 11.
[0309]
However, since malfunction occurs due to the influence of the photo converter, the gate driver 12 (or the source driver 14) and the like should suppress the entrance of light from the front surface as well as the back surface. Therefore, in the present invention, the cathode electrode 46 is used as a light shielding film.
[0310]
On the other hand, when the cathode (or anode) electrode is a transparent electrode, that is, the light extraction structure (extracting light from the array substrate 49 side) in which the pixel electrode is a reflection type and the common electrode is a transparent electrode (ITO, IZO, etc.). In the case of taking out light from the bottom and taking out light from the EL film deposition surface), the sheet resistance value of the transparent electrode becomes a problem. This is because the transparent electrode has a high resistance, but it is necessary to pass a current at a high current density to the cathode of the organic EL. Therefore, when the cathode electrode is formed of a single layer of ITO film, it becomes heated due to heat generation, or an extreme luminance gradient occurs on the display screen.
[0311]
In order to cope with this problem, a low resistance wiring 92 made of a metal thin film is formed on the surface of the cathode electrode. The low resistance wiring 92 has the same configuration as the black matrix (BM) of the liquid crystal display panel (chrome or aluminum material with a thickness of 50 nm to 200 nm) and the same position (between the pixel electrodes, above the gate driver 12, etc.) It is. However, the function of the organic EL is completely different because it is not necessary to form a BM. The low resistance wiring 92 is not limited to the surface of the transparent electrode 72 but may be formed on the back surface (surface in contact with the organic EL film). Further, as the metal film formed in a BM shape, an alloy such as Mg · Ag, Mg · Li, Al·Li, or a laminated structure such as aluminum, magnesium, indium, copper, or an alloy of each may be used. In order to prevent corrosion and the like, ITO and IZO films are further laminated on the BM, and SiNx, SiO2An inorganic thin film such as polyimide or an organic thin film such as polyimide is formed.
[0312]
In the case where light is extracted from the vapor deposition surface of the EL film (upper extraction), it is preferable to form an Mg—Al film on the organic EL layer 47 and to form an ITO or IZO film thereon. Alternatively, it is preferable that an Mg—Al film is formed on the organic EL layer 47 and a black matrix (a black matrix such as a liquid crystal display panel) is formed thereon. This black matrix is formed of chromium, Al, Ag, Au, Cu, etc.2It is preferable to form a protective film 1761 made of an inorganic insulating film such as SiNx or an organic insulating film such as polyester or acrylic. Further, it is preferable to form an antireflection film (AIR coat) on the protective film 1761. Note that the minimum film thickness of the protective film 1761 is 1 μm or more.
[0313]
Further, even in the case of taking out the bottom, it is also effective to increase the transmittance of the reflective film 46 of the cathode electrode. In this configuration, even if the display image is viewed from the array substrate 49 side, the reflection of the reflective film 46 is high, so that the reflection is reduced and the circularly polarizing plate 74 is not necessary. Therefore, the light extraction efficiency may be improved compared to the upper extraction. The transmittance of the reflective film 46 is preferably 60% or more and 90% or less, particularly preferably 70% or more and 90% or less. This is because if it is 60% or less, the sheet resistance value of the cathode electrode is lowered, while the reflection is increased. On the contrary, if it is 90% or more, the sheet resistance value of the cathode electrode becomes high, and the luminance gradient of the display image becomes large.
[0314]
In order to increase the transmittance of the reflective film 46, the Al film is formed as thin as 20 nm to 100 nm in thickness. An ITO or IZO film is preferably formed thereon. Alternatively, it is preferable to form a black matrix on the Al film.
[0315]
As shown in FIG. 40, the light emission area of the organic EL layer 47 is widened by making the pixel electrode 48 arc-shaped. Therefore, the current density is reduced and the life of the EL element 15 can be increased. Further, since the terminal voltage of the EL element 15 is also reduced, the power efficiency is also improved.
[0316]
FIG. 41 is an explanatory diagram of a method for manufacturing the EL display panel described in FIG. As illustrated in FIG. 41A, the TFT 11, the gate driver 12, and the like are formed on the array substrate 49.
[0317]
Next, as shown in FIG. 41B, a smoothing film 71 made of an organic material such as acrylic resin is applied on the array substrate 49. The smoothing film 71 may be an inorganic material such as SOG. The film thickness is preferably 1.5 μm or more and 3 μm or less. Next, a mask 1771 is formed on the smoothing film 71. The mask 1771 is formed using a metal material so that the formation position thereof corresponds to the pixel 16. Next, etching is performed. Etching is wet etching, O2Any of dry etching such as plasma may be used. Since the smoothing film 71 is etched from between the masks 1771, the smoothing film 71 has an arc shape as shown in FIG.
[0318]
Further, as shown in FIG. 41 (d), a mask (not shown) is formed on the smoothing film 71 to form a contact hole 1772. Alternatively, the contact hole 1772 is also formed at the same time in the etching process of FIG.
[0319]
Next, as shown in FIG. 41E, a pixel electrode 48 is formed using a transparent electrode such as ITO or IZO. The pixel electrode 48 and the TFT 11 are connected by a pixel contact portion 1751. This contact hole electrically connects the pixel electrode 48 made of ITO and the drain terminal.
[0320]
Next, a carbon film having a thickness of 50 nm to 150 nm is thinly deposited on the pixel electrode 48, and an organic EL layer is formed thereon. The organic EL layer 47 is coated on the entire surface in the case of a single color and separately using a metal mask in the case of RGB (see FIG. 41 (f)).
[0321]
After the formation of the organic EL layer 47, an Al film (reflection film) 46 to be a cathode electrode is formed (FIG. 41 (g)). Further, a protective film 1761 is formed on the Al film (reflection film) 46 (FIG. 41 (h)).
[0322]
The protective film 1761 may be a protective layer using a film. For example, as the protective layer, use is made of a film of an electrolytic capacitor obtained by vapor-depositing DLC (diamond-like carbon). Since this film has extremely low moisture permeability (moisture-proof), it can be used as the protective layer 1761. Further, the thickness of the protective layer 1761 is calculated by n · d (n is the refractive index of the thin film, and when a plurality of thin films are stacked, the refractive indexes thereof are totaled (calculating n · d of each thin film)). D is calculated by summing up the film thickness of the thin film and, when a plurality of thin films are laminated, the refractive index of the thin films).
[0323]
The organic EL layer 47 or the pixel electrode 48 is not limited to a circular arc shape, and may be a triangular pyramid shape, a conical shape, a sine curve shape, or a structure in which these are combined. Further, a configuration in which a fine arc, a triangular pyramid shape, a conical shape, or a sine curve shape is formed in one pixel, a combination thereof, or random unevenness may be formed. In FIG. 40, a convex arc shape is used, but a concave arc shape is the same as described above.
[0324]
FIG. 42 is a configuration diagram (cross-sectional view) in a panel form. Note that although the same applies to other drawings, in the present specification, each drawing is omitted or enlarged or reduced for easy understanding or drawing. Also in the cross-sectional view of the display panel of FIG. 42, the smoothing film 71 and the like are shown to be sufficiently thick. However, the thickness of the array substrate 49 is very thin. Further, TFTs and the like are omitted.
[0325]
42, a spacer 1781 is disposed between the sealing lid 41 and the array substrate 49 so that the protective film 1761 or the reflective film 46 or the organic EL layer 47 and the sealing lid 41 are not in direct contact with each other. Yes. The desiccant is disposed or filled around the display area. The spacer is cylindrical or spherical. The height is preferably 10 μm or more and 100 μm or less. Alternatively, the protective film 1761 can be processed to form a spacer. In other words, a part or all of the protective film 1761 is processed or formed into a protrusion shape, a column shape, or a stripe shape, thereby providing a spacer function. A configuration in which the spacer 1781 is a desiccant is also preferable.
[0326]
In the pixel shown in FIG. 19, the driving TFT 11b and the conversion TFT 11a are in a current mirror relationship, and their characteristics (threshold value Vt, S value, mobility μ, etc.) must match. In addition, it goes without saying that the characteristics of the TFTs are preferably the same in the pixel of FIG.
[0327]
The semiconductor film constituting the TFT 11 of the pixel 16 is generally formed by laser annealing in the low temperature polysilicon technology. Variations in the laser annealing conditions result in variations in TFT 11 characteristics. However, if the characteristics of the TFTs 11 in one pixel 16 match, the current programming method shown in FIGS. 6 and 19 can be driven so that a predetermined current flows through the EL element 15. This is an advantage not found in voltage programming.
[0328]
In response to this problem, in the present invention, as shown in FIG. 43, a laser irradiation spot 230 at the time of annealing is irradiated in parallel with the source signal line 18. Further, the laser irradiation spot 230 is moved so as to coincide with one pixel column. Of course, the present invention is not limited to one pixel column, and for example, the RGB in FIG. 43 may be irradiated with a unit of one pixel 16 (in this case, it is a three pixel column). In particular, the pixels are made of three pixels of RGB and have a square shape. Accordingly, each of the R, G, and B pixels has a vertically long pixel shape. Therefore, the arrangement of the TFTs 11 formed in the pixels 16 is arranged in the vertical direction as shown in FIG. 34 (conversion TFT 11a, driving TFT 11b). Therefore, by making the laser irradiation spot 230 vertically long and annealing, it is possible to prevent variation in characteristics of the TFT 11 within one pixel.
[0329]
In general, the length of the laser irradiation spot 230 is a fixed value such as 10 inches. Since the laser irradiation spot 230 is moved, it is necessary to arrange the panel so that one laser irradiation spot 230 can be moved within the movable range (that is, the laser irradiation spot at the center of the display screen 21 of the panel). 230 do not overlap).
[0330]
In the configuration of FIG. 44, three panels are formed vertically within the range of the length of the laser irradiation spot 230. The annealing apparatus that irradiates the laser irradiation spot 230 recognizes the positioning markers 242a and 242b of the glass substrate 241 and moves the laser irradiation spot 230. The positioning marker 242 is recognized by a pattern recognition device. An annealing device (not shown) recognizes the positioning marker 242 and determines the position of the pixel column. Then, annealing is sequentially performed by irradiating the laser irradiation spot 230 so as to overlap the pixel row position.
[0331]
The laser annealing method (method of irradiating a linear laser spot parallel to the source signal line 18) described with reference to FIGS. 43 and 44 is particularly preferably employed in the current programming method of the organic EL panel. This is because the parallel characteristics of the source signal lines and the characteristics of the TFTs 11 match (the characteristics of the pixel TFTs adjacent in the vertical direction are approximate). Therefore, there is little change in the voltage level of the source signal line at the time of current driving, and current writing shortage hardly occurs (for example, in the case of white raster display, the current passed through the conversion TFT 11a of each adjacent pixel is almost the same. There is little change in the current amplitude output from the driver 14).
[0332]
In addition, the method of simultaneously writing a plurality of pixel rows described with reference to FIGS. 45 and 46 can realize uniform image display (since display unevenness mainly due to variations in TFT characteristics is unlikely to occur). In FIG. 45 and the like, a plurality of pixel rows are selected at the same time. Therefore, if the TFTs of adjacent pixels are uniform, uneven TFT characteristics in the vertical direction can be absorbed by the source driver 14.
[0333]
As shown in FIG. 6, the gate signal line 17a becomes conductive during the row selection period (here, since the TFT 11 in FIG. 6 is a P-channel transistor, it becomes conductive at a low level), and the gate signal line 17b is in the non-selection period. It becomes conductive.
[0334]
When the state of the source signal line is the gradation 0 display state, when the current value for gradation 1 is applied and the row selection period is operated at 75 μsec, the source signal is shown as indicated by the solid line a in FIG. When the parasitic capacitance of the line 18 increases, the current value output to the EL element 15 decreases.
[0335]
The dotted line b in FIG. 47 shows a case where the current value for gradation 1 is 10 times that of the solid line a, and the decrease rate of the current value output to the EL element 15 with respect to the increase in the parasitic capacitance of the source signal line 18. Becomes smaller. Since a variation of about 10% cannot be observed as a luminance difference for the human eye with respect to a predetermined current value, if a decrease of about 10% is recognized, the allowable source capacitance is 2 pF or less for the solid line a and 25 pF for the dotted line b. It becomes as follows.
[0336]
The time t required to change the current value of the source signal line 18 is t = C · V / I, where C is the size of the stray capacitance, V is the voltage of the source signal line, and I is the current flowing through the source signal line. Therefore, the fact that the current value can be increased by 10 times indicates that the time required for the current value change can be shortened to nearly 1/10, or that the current value can be changed to a predetermined current value even when the source capacitance becomes 10 times. Therefore, in order to write a predetermined current value within a short horizontal scanning period, it is effective to increase the current value.
[0337]
When the input current is increased 10 times, the output current is also increased 10 times, and in order to obtain a predetermined luminance so that the luminance of the EL element becomes 10 times, the conduction period of the switching TFT 11d in FIG. The predetermined brightness is displayed by setting the period to 1/10. That is, in order to sufficiently charge and discharge the parasitic capacitance of the source signal line 18 and to program a predetermined current value to the conversion TFT 11a of the pixel 16, it is necessary to output a relatively large current from the source driver 14. There is. However, when such a large current flows through the source signal line 18, this current value is programmed in the pixel, and a large current flows through the EL element 15 with respect to a predetermined current. For example, if programming is performed with 10 times the current, naturally 10 times the current flows through the EL element 15, and the EL element 15 emits light with 10 times the luminance. That is, in order to obtain a predetermined light emission luminance, the time required to flow through the EL element 15 may be reduced to 1/10. By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained.
[0338]
It should be noted that although the current value of 10 times is written in the pixel conversion TFT 11a (more precisely, the terminal voltage of the capacitor 19 is set) and the on-time of the EL element 15 is reduced to 1/10, this is an example. . In some cases, a 10 times larger current value may be written into the pixel conversion TFT 11a, and the on-time of the EL element 15 may be reduced to 1/5. On the other hand, there may be a case where 10 times the current value is written to the pixel conversion TFT 11a and the on-time of the EL element 15 is doubled. The present invention is characterized in that the pixel write current is set to a value other than a predetermined value and the current flowing through the EL element 15 is driven intermittently. In this specification, for ease of explanation, it is assumed that a current value of N times is written in the TFT 11 of the pixel and the ON time of the EL element 15 is 1 / N times. However, the present invention is not limited to this, and it goes without saying that a current value of N1 times may be written to the TFT 11 of the pixel, and the ON time of the EL element 15 may be 1 / N2 times (different from N1 and N2). The intermittent interval is not limited to an equal interval.
[0339]
For ease of explanation, it is assumed that 1F is set to 1 / N on the basis of 1F (one field or one frame). However, there is a time during which one pixel row is selected and the current value is programmed (usually one horizontal scanning period (1H)), and an error occurs depending on the scanning state. This is only a matter of convenience for the purpose, and is not limited to this.
[0340]
The organic (inorganic) EL display device also has a problem in that the display method is basically different from a display that displays an image as a set of line displays with an electron gun, such as a CRT. That is, in the EL display device, the current (voltage) written to the pixel is held for a period of 1F (1 field or 1 frame). For this reason, when a moving image is displayed, there is a problem that the outline blur of the display image occurs.
[0341]
In the present invention, a current is passed through the EL element 15 only during the period of 1F / N, and no current is passed during the other period (1F (N-1) / N). Consider the case where this driving method is implemented and a point on the screen is observed. In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is a temporal display (intermittent display) state. When the moving image data display is viewed in this intermittent display state, the outline of the image is not blurred and a good display state can be realized. That is, a moving image display close to a CRT can be realized. Although intermittent display is realized, the main clock of the circuit is not different from the conventional one. Therefore, the power consumption of the circuit does not increase.
[0342]
In the case of a liquid crystal display panel, image data (voltage) for light modulation is held in the liquid crystal layer, and it is necessary to rewrite the data applied to the liquid crystal layer when performing black insertion display. For this reason, the operation clock of the source driver 14 is increased, and the image data must be applied to the source signal line 18 alternately with the black display data, so that black insertion display (intermittent display such as black display) is to be realized. It is necessary to raise the main clock of the circuit. In addition, an image memory for performing time axis expansion is also required.
[0343]
However, in the pixel configuration of the EL display panel of the present invention, FIGS. 6, 159, 162, 184, 81, 85, 86, 72 to 76, 83, 67, 79, FIG. As shown in FIG. 80, FIG. 182 and the like, the image data is held in the capacitor 19, and a current corresponding to the terminal voltage of the capacitor 19 is passed through the EL element 15. Therefore, the image data is not held in the light modulation layer like the liquid crystal display panel.
[0344]
In the present invention, the current flowing through the EL element 15 is controlled only by turning on or off the switching TFT 11d or the TFT 11e. That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is held in the capacitor 19 as it is. Therefore, if the switching element is turned on at the next timing and a current flows through the EL element 15, the flowing current is the same as the previously flowing current value. In the present invention, it is not necessary to increase the main clock of the circuit even when black insertion display (intermittent display such as black display) is realized. In addition, since it is not necessary to perform time axis expansion, an image memory is also unnecessary. In addition, the organic EL element 15 has a short response time from application of current to light emission and a high-speed response. Therefore, it is suitable for moving image display, and further, intermittent display can solve the problem of moving image display, which is a problem of conventional data holding type display panels (liquid crystal display panel, EL panel, etc.).
[0345]
As shown in FIG. 48, the gate signal line 17b has a conventional conduction period of 1F (when the current program time is 0, the normal program time is 1H, and the number of pixel rows of the EL display device is at least 100 or more. 1F, the error is 1% or less), and if N = 10, according to FIG. 47, if the source capacitance is about 20 pF from gradation 0 to gradation 1, which takes the longest time to change, 75 μm It can change in about seconds. This indicates that a frame frequency of 60 Hz can be driven with an EL display device of about 2 type.
[0346]
Further, when the source capacity is increased in a large display device, the source current may be increased 10 times or more. In general, when the source current value is increased N times, the conduction period of the gate signal line 17b (TFT 11d) may be set to 1 F / N. Accordingly, the present invention can be applied to a television, a monitor display device, and the like.
[0347]
Hereinafter, it will be described in more detail with reference to the drawings. First, the parasitic capacitance 404 in FIG. 6 is generated by the coupling capacitance between the source signal lines, the buffer output capacitance of the source driver 14, the cross capacitance between the gate signal line 17 and the source signal line 18, and the like. This parasitic capacitance 404 is usually 10 pF or more. In the case of voltage driving, a voltage is applied from the source driver 14 to the source signal line 18 with a low impedance, so that there is no problem in driving even if the parasitic capacitance 404 is somewhat large.
[0348]
However, in the current drive, it is necessary to program the capacitor 19 of the pixel with a minute current of 5 nA or less, particularly in the case of black level image display. Therefore, when the parasitic capacitance 404 is generated with a magnitude greater than or equal to a predetermined value, the time for programming to one pixel row (usually within 1H, but is not limited to within 1H since two pixel rows may be written simultaneously). The parasitic capacitance cannot be charged or discharged inside. If charging / discharging is not possible in the 1H period, writing to the pixel is insufficient and no resolution is obtained.
[0349]
In the pixel configuration of FIG. 6, as shown in FIG. 18A, the program current I <b> 1 flows through the source signal line 18 during current programming. V1 of the capacitor 19 is set (programmed) so that the current I1 flows through the conversion TFT 11a and the current through which the program current I1 flows is maintained. At this time, the switching TFT 11d is in an open state (off state).
[0350]
Next, the TFT 11 operates as shown in FIG. That is, the off voltage Vgh is applied to the gate signal line 17a, and the conversion TFT 11a and the take-in TFT 11c are turned off. On the other hand, the on voltage Vgl is applied to the gate signal line 17b, and the switching TFT 11d is turned on.
[0351]
Assuming that the program current I1 is N times the current (predetermined value) that flows originally, the current flowing through the EL element 15 in FIG. 18B is also I1. Therefore, the EL element 15 emits light with a brightness N times the predetermined value.
[0352]
Therefore, if the switching TFT 11d is turned on only for a period of 1 / N of the time for which the switching TFT 11d is originally turned on (about 1F) and the other period (N-1) / N is turned off, the average brightness of the entire 1F becomes a predetermined brightness. Become. This display state approximates that the CRT is scanning the screen with an electron gun. The difference is that the range in which the image is displayed is 1 / N of the entire screen (the whole screen is 1) is lit (in CRT, the lit range is one pixel row (strictly Is one pixel)).
[0353]
In the present invention, this 1 / N image display area moves from the top to the bottom of the display screen 21 as shown in FIG. In the present invention, current flows through the EL element 15 only during the 1F / N period, and no current flows during the other period (1F · (N−1) / N). Therefore, although the image is intermittently displayed, the image is retained by the afterimage to the human eye, so that the entire screen appears to be displayed uniformly.
[0354]
In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is a temporal display (intermittent display) state. In a liquid crystal display panel (an EL display panel other than the present invention), since data is held in pixels for a period of 1F, even if image data changes in the case of moving image display, the change cannot be followed. The video was blurred (outline of the image). However, since the image is intermittently displayed in the present invention, the outline of the image is not blurred and a good display state can be realized. That is, a moving image display close to a CRT can be realized.
[0355]
Further, in the EL display device, since the black display is completely unlit, there is no contrast reduction as in the case where the liquid crystal display panel is intermittently displayed. Further, as shown in FIG. 18, intermittent display can be realized only by turning on and off the switching TFT 11d. This is because the image data is stored in the capacitor 19. That is, the image data is held in each pixel 16 during the period of 1F. Whether or not a current corresponding to the held image data is supplied to the EL element 15 is realized by controlling the switching TFT 11d.
[0356]
Accordingly, there is no change in the number of TFTs 11 constituting one pixel in the case where the intermittent display is realized or not. That is, the current configuration is realized by removing the influence of the parasitic capacitance 404 of the source signal line 18 while maintaining the pixel configuration. In addition, a moving image display close to a CRT is realized.
[0357]
In addition, since the operation clock of the gate driver 12 is sufficiently slower than the operation clock of the source driver 14, the main clock of the circuit is not increased. Further, it is easy to change the value of N.
[0358]
As shown in FIG. 50, the image display direction (image writing direction) is downward from the top of the screen in the first field (FIG. 50A), and upward from the bottom of the screen in the second field. It is good also as (FIG.50 (b)). That is, FIG. 50 (a) and FIG. 50 (b) may be repeated alternately.
[0359]
Further, as shown in FIG. 51, in the first field, the screen is directed downward from the top (FIG. 51 (a)), and once the entire screen is displayed in black (non-display area) 312 (FIG. 51 (b)). )), In the next second field, the screen may be shifted upward from the bottom of the screen (FIG. 51 (c)), and the entire screen may be temporarily displayed in black (non-display area) 312 (FIG. 51 (d)). That is, what is necessary is just to repeat the state of FIG. 51 (a) to FIG.51 (d) alternately.
[0360]
In FIG. 50, FIG. 51, etc., the screen writing method is set from the top to the bottom or from the bottom to the top. However, the present invention is not limited to this. The above matters are the same in other embodiments of the present invention.
[0361]
49A, the image display area 311 is set to 1 / N, and the non-display area 312 is set to (N−1) / N (however, this is an ideal state. This is different because there is a penetration due to the source-gate (SG) capacitance of the TFT 11a). That is, this is a case where the image display area 311 is single. As indicated by the arrow, the image display area 311 moves downward from the top of the screen (FIG. 49 (a1) → FIG. 49 (a2) → FIG. 49 (a3) → FIG. 49 (a1) →). However, the movement of the image display area 311 is not limited to the downward movement from the top of the screen, and may be the upward movement from the bottom of the screen. The first frame (first field) is scanned (operated) so that it moves downward from the top of the screen, and the second frame (second field) moves upward from the bottom of the screen. Needless to say, it is good. Further, scanning (operation) may be performed from the right to the left of the screen or from the left to the right of the screen.
[0362]
FIG. 48 shows operation timing waveforms. As described above, one screen is displayed in the period of 1F, and the current is programmed in the period of 1H. FIG. 48 (a) shows the timing waveform of the gate signal line 17a in FIGS. 6 (a) and 6 (b). FIG. 48B shows the timing waveform of the gate signal line 17b. Basically, when the gate signal line 17b becomes the ON voltage Vgl, the switching TFT 11d is turned on (period is 1 F / N), and the EL element 15 has a peak current N times the predetermined current I1, and the EL The element 15 emits light with a luminance (N · B) N times the predetermined luminance B. During the period of 1F / (N−1) / N, the switching TFT 11d is turned off. The control of the gate signal line can be easily realized by controlling the two shift registers (22a, 22b) in the gate driver 12, as shown in FIG. This is because the shift register 22a may hold (scan) the control data of the gate signal line 17a, and the shift register 22b may hold (scan) the control data of the gate signal line 17b.
[0363]
FIG. 52 shows the waveform of the gate signal line 17b. If FIG. 52A is the voltage waveform of the gate signal line 17b of the first pixel row, FIG. 52B shows the voltage waveform of the gate signal line 17b of the second pixel row adjacent to the first pixel row. Show. Similarly, FIG. 52C shows the voltage waveform of the gate signal line 17b of the next third pixel row, and FIG. 52D shows the voltage waveform of the gate signal line 17b of the fourth pixel row.
[0364]
As described above, the waveform of the gate signal line 17b is made the same in each pixel row, and the application is performed by shifting at an interval of 1H. By scanning in this manner, it is possible to shift the pixel rows that are sequentially lit while prescribing the time during which the EL element 15 is lit to 1 F / N, so that the waveform of the gate signal line 17b in each pixel row can be changed. It is easy to make them identical and shift. This is because it is only necessary to control ST1 and ST2 which are data applied to the shift registers 22a and 22b in FIG. For example, if the ON voltage Vgl is output to the gate signal line 17b when the input ST2 is L level, and the OFF voltage Vgh is output to the gate signal line 17b when the input ST2 is H level, the gate signal line 17b is output. ST2 to be applied to is input at the L level for the period of 1F / N and is set to the H level for the other periods. The input ST2 is simply shifted by the clock CLK2 synchronized with 1H.
[0365]
Similarly, it is easy to create the waveform of the gate signal line 17a shown in FIG. This is because ST1 that is input data of the shift register 22a in FIG. For example, if the ON voltage Vgl is output to the gate signal line 17a when the input ST1 is L level, and the OFF voltage Vgh is output to the gate signal line 17a when the input ST1 is H level, the gate signal line 17a is output. ST1 to be applied to is input at the L level for the period of 1H, and is set to the H level for the other periods. This input ST1 is simply shifted by the clock CLK1 synchronized with 1H.
[0366]
FIG. 49B shows an example in which the image display area 311 is set to 1 / (2N), and the two image display areas 311a and 311b are moved downward from the top of the screen as indicated by arrows (FIG. 49B1). ) → FIG. 49 (b2) → FIG. 49 (b3) → FIG. 49 (b1) →). However, the movement of the image display areas 311a and 311b is not limited to moving from the top to the bottom of the screen, and may be moved from the bottom to the top of the screen. The first frame (first field) is scanned (operated) so that it moves downward from the top of the screen, and the second frame (second field) moves upward from the bottom of the screen. Needless to say, it is good. Further, scanning (operation) may be performed from the right to the left of the screen or from the left to the right of the screen.
[0367]
Further, FIG. 49C shows an example in which the image display area 311 is set to 1 / (3N), and the three image display areas 311a, 311b, and 311c are moved downward from the top of the screen as indicated by arrows ( 49 (c1) → FIG. 49 (c2) → FIG. 49 (c3) → FIG. 49 (c1) →).
[0368]
As shown in FIGS. 49B and 49C, the more the image display area 311 is divided, the more the frame rate of the entire image display (the number of times the screen is written per second, for example, the frame rate 60 is 1 Rewriting the screen 60 times per second). If the frame rate is lowered, the operation clock of the circuit can be lowered accordingly, so that power consumption can be reduced. That is, the light emission period of the EL element 15 is shortened, the apparent instantaneous luminance is increased, and the image display area 311 and the non-display area 312 are repeated at high speed, and flicker is reduced. Therefore, the frame rate can be reduced.
[0369]
By driving as described above, the number of times of lighting in one frame (one field) can be increased and flicker can be reduced. When the EL element is turned on, the frequency component is increased by increasing the number of times of lighting, so that it is difficult to be observed by human eyes. For example, when the lighting period per time is set to 1/7 and lighting is performed seven times in one frame, display without flicker can be realized even at a frame frequency of 30 Hz.
[0370]
  By controlling on / off of the switching TFT 11d, the luminance of the image can be adjusted (variable). For example, in the case of FIG. 49A (when there is one image display region 311), the brightness of the display screen 21 changes by changing the area of the non-display region 312 (FIG. 53A).353 (a2) is darker than FIG. 53 (a2), and FIG.1) Is darker).
[0371]
  Similarly, in the case of FIG. 49B (when there are two image display areas 311), FIG.353 (b2) is darker than FIG. 53 (b2), and FIG.1) The display brightness of the display screen 21 becomes darker. The same applies to the case of FIG. 49C (when there are three image display areas 311, that is, three or more).is there.
[0372]
In FIG. 49, the image display area 311 is scanned on the display screen 21, but the present invention is not limited to this. As shown in FIGS. 53 (c1) and 53 (c2), one frame (one field) is shown. The entire screen may be the non-display area 312 for the eyes, and the entire screen may be the image display area 311 for the next two frames (two fields). That is, the entire screen is alternately switched between the image display state and the non-lighting state. However, the image display time and the non-lighting time are not limited to the same time. For example, the image display time may be 1F / 4, and the non-lighting time may be 3F / 4. Thus, the display brightness of the image can be changed (adjusted) by changing the ratio between the image display time and the non-lighting time.
[0373]
In any case, as shown in FIG. 54, by changing the value of N, the display luminance B of the image can be changed linearly. Further, the brightness of the image can be easily changed by simply controlling the value of N.
[0374]
FIG. 55 is a block diagram of a circuit for adjusting (controlling) display luminance according to the present invention. The frame memory (field memory) 354 stores video data input from the outside. The CPU 353 performs calculation using the accumulated video data. The calculation uses at least one of the maximum luminance, optimum luminance, average luminance, and luminance distribution of the video data. In addition, the maximum luminance, optimum luminance, average luminance, luminance distribution, and change rate of each frame of continuous video data are also considered.
[0375]
The calculated result is stored in the luminance memory 352. The luminance memory 352 is data obtained by correcting the brightness of an image. For example, on a bright screen such as a beach, the average luminance of the image is corrected to be bright, and when there is a relatively dark portion in the image data, the image data is converted to image data that is darker than the actual value. On the night screen or the like, since the image is entirely dark, a relatively bright part is corrected more brightly.
[0376]
The counter circuit 351 counts how much the N value in FIG. 54 is made. The N value is changed in real time in the waveform of the gate signal line 17b. Since the N value is time, it can be easily changed by counting with a counter, and the brightness of the image can be changed.
[0377]
The switching circuit 355 is a circuit for switching a voltage Vgl for turning on the TFT 11 of the pixel 16 and a voltage Vgh for turning it off (when the pixel TFT 11 is in the P channel and vice versa in the N channel). That is, based on the output of the counter circuit 351, the period of 1F / N shown in FIG. Therefore, the brightness of the display screen 21 can be easily changed in real time.
[0378]
The display brightness is controlled in real time according to the video signal data. By controlling in this way, the dynamic range of the brightness expression can be expanded substantially three times or more. Further, the EL display device is completely black (non-lighted) when no current is passed through the EL element, so that no black floating occurs in the image display. That is, the contrast is also increased. In particular, in the case of current programming, since the current value programmed in the pixel is as small as 10 nA in black display, the parasitic capacitance 404 cannot be charged and discharged sufficiently, and it is difficult to realize complete black display. Further, power is supplied to the source signal line 18 by a pulse applied to the gate signal line 17 (punch-through voltage), and black floating occurs.
[0379]
The present invention forcibly turns off the switching TFT 11d and stops supplying current to the EL element 15. Therefore, the EL element 15 is completely turned off. Therefore, good contrast can be realized. In addition, it is necessary to adjust the output timing of data applied to the source signal line 18 and the timing of the gate signal lines 17a and 17b. In particular, it is preferable that the output of Vgl (the voltage for turning on the TFTs 11b and 11c in FIG. 6) of the gate signal line 17a for selecting a pixel row be shorter than 1H. This will also be described with reference to FIG.
[0380]
In FIG. 55, the brightness of the image is changed in real time based on the video data of the video signal. However, the present invention is not limited to this. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume, this change is detected and the counter value of the counter circuit 351 is changed to change the brightness (or contrast or dynamics) of the display screen 21. Range) may be changed. Alternatively, brightness such as outside light may be detected by a photo sensor, and the brightness of the display screen 21 may be automatically changed based on the detected data. Further, it may be configured to change manually or automatically depending on the contents and data of the image to be displayed.
[0381]
The brightness adjustment can be realized by turning on and off the TFT on the EL element 15 side (switching TFT 11d in FIG. 6). In this case, since the program current (voltage: voltage programming method) output from the source driver 14 is a fixed value (the program current is not changed), the circuit configuration of the source driver can be simplified. That is, it is not necessary to change the output current (voltage) or the like corresponding to the brightness of the display screen. For example, the conventional liquid crystal display panel uses the 64th gradation of the maximum brightness when displaying 64 gradations. When the brightness is lowered by brightness adjustment, for example, up to the 32nd gradation is used. When the circuit is configured in this way, the number of gradation displays decreases when the screen brightness is low.
[0382]
Further, even when the TFT 11 on the EL element 15 side is turned on / off (the current flowing through the EL element 15 is intermittently displayed), the brightness can be freely adjusted by adjusting the off period. At that time, the brightness adjustment according to the present invention can be maintained even in the brightness change of gamma adjustment and linearity. Since the power supply voltage Vdd is also a fixed value, it is advantageous in terms of configuration.
[0383]
Further, by controlling the on / off state of the switching TFT 11d from the top to the bottom of the screen, the luminance of the screen can be easily distributed. Almost no calculation function is required for control. This method will be described later.
[0384]
Note that the cycle of turning on and off the EL element 15 needs to be 0.5 msec or more. When this period is short, the image is not completely displayed due to the afterimage characteristics of the human eye, and the image becomes blurred, as if the resolution is lowered. Alternatively, the display state of the data holding type display panel is set. However, when the on / off cycle is set to 100 msec or more, it appears to blink. Therefore, the on / off period of the EL element should be 0.5 msec or more and 100 msec or less, and further 2 msec or more and 30 msec or less. More preferably, the on / off cycle should be 3 msec or more and 20 msec or less.
[0385]
When the number of divisions of the black screen (non-display area) 312 is one, good moving image display can be realized, but since the flickering of the screen is easily seen, it is preferable to divide the black insertion portion into a plurality. However, if the number of divisions is too large, moving image blur occurs, so the number of divisions should be between 1 and 8. Further, it is preferably 1 or more and 5 or less.
[0386]
  It should be noted that the number of divisions of the black screen is preferably configured so that it can be changed between a still image and a moving image. With N = 4, 75% is a black screen and 25% is an image display. At this time, the division number is 1 to scan the 75% black display portion in the vertical direction of the screen in the 75% black belt state. The number of divisions is 3 which scans in 3 blocks of a 75% black screen and a 25/3% display screen. Increase the number of divisions for still images and decrease the number of divisions for moving images. Switching may be performed automatically (moving image detection or the like) according to the input image, or may be performed manually by the user. You can also input video from the display devicecontentWhat is necessary is just to comprise so that it may switch according to.
[0387]
For example, in a mobile phone or the like, the number of divisions is set to 10 or more on the wallpaper display and input screen (extremely, it may be turned on / off every 1H). When displaying NTSC moving images, the number of divisions is set to 1 or more and 5 or less. It should be noted that the number of divisions is preferably configured so that it can be switched to multiple stages of 3 or more. For example, no division number, 2, 4, 8, etc.
[0388]
Further, the ratio of the black screen to the entire display screen is 0.2 or more and 0.9 or less (1.2 or more and 9 or less if displayed in N), where the area of the entire screen is 1, especially 0. It is preferably 25 to 0.6 (indicated by N, 1.25 to 6). This is because if it is 0.20 or less, the improvement effect in moving image display is low. Further, if it is 0.9 or more, the luminance of the display portion increases, and it is easy to visually recognize that the display portion moves up and down.
[0389]
The number of frames per second is preferably 10 or more and 100 or less (10 Hz or more and 100 Hz or less), and more preferably 12 or more and 65 or less (12 Hz or more and 65 Hz or less). This is because when the number of frames is small, the flickering of the screen becomes conspicuous, and when the number of frames is too large, writing from the source driver 14 etc. becomes difficult and the resolution deteriorates.
[0390]
In any case, as described above with reference to FIGS. 48 and 55, the present invention may be performed by controlling the gate signal line 17 or changing the current (voltage) applied to the source signal line 18. However, both may be combined.
[0390]
Needless to say, the above items can also be applied to the pixel configuration of the voltage program shown in FIGS. For example, in FIG. 85, the TFT 11e may be controlled on and off.
[0392]
As shown in FIG. 56, the time when the gate signal line 17b is turned on for the ON voltage Vgl is 1F (not limited to 1F, and may be a unit period) as shown in FIG. Good. This is because a predetermined average luminance is obtained by turning on the EL element 15 for a predetermined period of the unit period. However, immediately after the programming period (1H) of FIG. 56 (a), it is less affected by the retention characteristic of the capacitor 19 of FIG. 6 if the gate signal line 17b is set to the ON voltage Vgl to cause the EL element 15 to emit light. It will be good. Further, in the period of 1F / N, the position may be changed as indicated by symbols A and B and arrows in FIG. 56 (b). If the configuration is such that the timing of data to be applied to ST in FIG. 21 (when it becomes L level in 1F) can be adjusted or varied, this change can also be realized easily.
[0393]
  In addition, as shown in FIG. 57, the period (1F / N) during which the gate signal line 17b is turned on may be divided into a plurality of division numbers (K). That is, the period during which the ON voltage Vgl is set is 1F / (K ・ N) Is performed K times. With this control, the image display state is as shown in FIG. 49 (b) (K = 2) and FIG. 49 (c) (K = 3). In this way, by dividing the image portion (image display area 311) to be lit into a plurality of portions, the occurrence of flicker can be suppressed and an image display with a low frame rate can be realized. Further, it is preferable that the number of divisions of the image is variable. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume, the change is detected and the value of K is changed manually. Or you may comprise so that it may change automatically.
[0394]
In this way, if it is configured to be able to adjust or vary the timing of data to be applied to ST in FIG. 21 (when it becomes L level when 1F), the value of K (the number of divisions of the image display area 311). It is also easy to change the value.
[0395]
  In FIG. 57, the period (1F / N) in which the gate signal line 17b is set to the on voltage Vgl is divided into a plurality (division number K), and the period in which the on voltage Vgl is set is 1F / N.(K ・ N)Although the period is implemented K times, the present invention is not limited to this. 1F /(K ・ N)The period may be implemented L (L ≠ K) times. In other words, the present invention displays the display screen 21 by controlling the period (time) flowing through the EL element 15, so that 1F /(K ・ N)It is included in the technical idea of the present invention to implement the period of L (L ≠ K) times. Further, the luminance of the display screen 21 can be changed digitally by changing the value of L. For example, when L = 2 and L = 3, the luminance (contrast) changes by 50%. These controls can also be easily realized with the circuit configurations of FIGS. 21, 55, 66, 67 and the like.
[0396]
Further, when the image display region 311 is divided, the period during which the gate signal line 17b is set to the on voltage Vgl is not limited to the same period. For example, as shown in FIG. 58, the period during which the ON voltage Vgl is set may be a plurality of periods such as t1 and t2.
[0397]
In FIG. 48, the adjacent pixel rows are sequentially turned on (displayed), but the present invention is not limited to this. As shown in FIG. 59, interlace scanning may be performed. In the interlaced scanning, an image is written in an odd-numbered pixel row in the first field (FIG. 49A), and an image is written in an even-numbered pixel row in the next second field (FIG. 48B). Line 391) An image display method. The pixel row not to be written holds the image data of the previous field (holding pixel row 392). In this way, flicker can be reduced by performing interlaced scanning with an EL display device.
[0398]
With the driving method of FIG. 59, all (or plural) even pixel row gate signal lines 17b can be shared, and all (or plural) odd pixel row gate signal lines 17b can be shared. Therefore, the number of gate signal lines 17 can be greatly reduced. Further, when the entire screen is displayed alternately between the image display area 311 and the non-display area 312, all the gate signal lines 17 b can be shared. These configurations are particularly effective in a three-side free configuration as shown in FIG.
[0399]
In the interlace scanning, an image is written in an odd-numbered pixel row in the first field and an image is written in an even-numbered pixel row in the next second field. However, the present invention is not limited to this. For example, in the first field, an image may be written every two pixel rows by skipping two pixel rows, and an image may be written in every two pixel rows not written in the first field in the next second field. Further, every three pixel rows or four pixel rows may be used. In the first field, an image may be written every two pixel rows from the second row of the screen (see FIG. 60A), and in the next second field, an image may be written every two pixel rows from the first row (see FIG. (See FIG. 60 (b)). In addition, as illustrated in FIG. 60, the pixel row to be written or the pixel row to be written may be controlled to be the non-display area 312. Further, an image may be written from the top to the bottom of the screen in the first field, and an image may be written from the bottom to the top of the screen in the second field. These are all included in the concept of interlaced scanning.
[0400]
Interlaced scanning can also be easily realized by implementing the method described with reference to FIGS. This is because the pixel row corresponding to the non-display area 312 that is not lit is only required to turn off the switching TFT 11d shown in FIG.
[0401]
Naturally, as shown in FIG. 61, the non-display area 312 and interlaced scanning can be combined. In FIG. 61A, the scanning region 501 including the writing pixel row 391 and the holding pixel row 392 is sequentially shifted. In FIG. 61A, an image is written from the first line. Similarly in FIG. 61B, the scanning region 501 including the writing pixel row 391 and the holding pixel row 392 is sequentially shifted. In FIG. 61B, an image is written from the second line.
[0402]
The above embodiment has mainly described the configuration of the pixel 16 of FIG. However, the present invention is not limited to this. For example, it can be realized by the pixel 16 of FIG. 19 or FIG.
[0403]
In the pixel configuration of FIG. 19, the current value applied to the source signal line 18 is programmed in the capacitor 19 by applying the ON voltage Vgl to the gate signal line 17 a. As shown in FIG. 62, data corresponding to the video signal is applied to the source signal line 18 from the power supply switching means 403 in the source driver 14. When the current mirror efficiency is 1, the programmed current flows to the driving TFT 11 b and this current is applied to the EL element 15. This relationship (timing waveform etc.) can be diverted from the matters shown in FIG. However, when current programming is performed, it may be necessary to individually control the on / off timing of the capture TFT 11c and the switching TFT 11d. In this case, the gate terminal for turning on and off the take-in TFT 11c and the switching TFT 11d must be another gate signal line 17.
[0404]
In order to implement the display method of FIG. 49 and the like, it is necessary to cut off the current flowing through the EL element 15. For this purpose, a TFT 11e is added as shown in FIG. A current is applied to the EL element 15 by setting the gate terminal of the TFT 11e to the on voltage Vgl, and a current to the EL element 15 is blocked by setting the gate terminal of the TFT 11e to the off voltage Vgh (non-lighting state).
[0405]
Therefore, by applying the signal waveforms of the gate signal lines 17a and 17b described in FIG. 48 and the like, the image display described in FIG. 49 and the like can be realized.
[0406]
In the image display area 311 and the non-display area 312, as shown in FIG. 63, the odd pixel row and the even pixel row may be switched for each frame (field). If odd-numbered pixel rows are displayed in FIG. 63A and even-numbered pixel rows are not displayed, odd-numbered pixel rows are not displayed in the next frame (field) (see FIG. 63B), and even-numbered pixel rows are displayed. Is displayed.
[0407]
Thus, if the non-display area and the display area are displayed repeatedly for each pixel row, the occurrence of flicker is greatly suppressed.
[0408]
In FIG. 63, the non-display pixel row and the display pixel row are set for each pixel row. However, the present invention is not limited to this, and the non-display pixel row and the display are displayed for every two pixel rows or more. It may be a pixel row.
[0409]
For example, if there are two rows, if the first pixel row and the second pixel row are display pixel rows and the third pixel row and the fourth pixel row are non-display pixel rows in the first field (frame), 5 The pixel row and the sixth pixel row are display pixel rows. In the next second field (frame), if the first and second pixel rows are non-display pixel rows, and the third and fourth pixel rows are display pixel rows, the fifth and sixth pixel rows The eyes are non-display pixel rows. In the next third field (frame), as in the first field, the first and second pixel rows are display pixel rows, and the third and fourth pixel rows are non-display pixel rows. The fifth and sixth pixel rows are display pixel rows.
[0410]
In this specification, the terms “field” and “frame” are used synonymously or separated. In general, in NTSC interlaced driving, one frame is composed of two fields. However, in progressive driving, one frame is one field. Thus, although the field and the frame are properly used in the world of the video signal, the image displayed on the display panel in the present invention can be applied to either progressive or interlace. Therefore, it is expressed that either is acceptable. Conceptually, it is a unit of time for completing a series of screens in both fields and frames.
[0411]
The display method of FIG. 64 is also effective. For ease of explanation, FIG. 64A shows the first field (first frame), FIG. 64B shows the second field (second frame), and FIG. 64C shows the third field (first frame). 3 frames) and FIG. 64D are the fourth field (fourth frame).
[0412]
In the first field (frame), the first pixel row and the second pixel row are non-display pixel rows, the third pixel row and the fourth pixel row are display pixel rows, the fifth pixel row and the sixth pixel row are display pixels. Line. In the second field (frame), odd pixel rows are display pixel rows, and even pixel rows are non-display pixel rows. In the third field (frame), the first pixel row and the second pixel row are display pixel rows, and the third pixel row and the fourth pixel row are non-display pixel rows. In the fourth field (frame), odd pixel rows are non-display pixel rows and even pixel rows are display pixel rows. Thereafter, the display is repeated sequentially from the display state of the first field (first frame).
[0413]
In the driving method shown in FIG. 64, one field has four fields (frames). In this way, by performing image display in a plurality of fields (a plurality of frames), the occurrence of flicker is often suppressed as compared with FIG.
[0414]
In the embodiment of FIG. 64, in the first field (frame), the second pixel row is set as a non-display pixel row, and in the second field (frame), the first pixel row is set as a non-display pixel row. It is not limited. In the first field (frame), four pixel rows are set as non-display pixel rows, in the second field (frame), two pixel rows are set as non-display pixel rows, and in the third field (frame), one pixel is set. In the fourth field (frame), the fourth pixel row is a non-display pixel row, and in the fifth field (frame), the second pixel row is a non-display pixel row, and the sixth field. In (frame), the non-display pixel rows may be set for each pixel row.
[0415]
The driving method of the present invention can easily realize display effects (such as animation effects). FIG. 65 shows a display method in which the display area appears in the order of FIG. 65 (a) → FIG. 65 (b) → FIG. 65 (c) → FIG. 65 (d). An animation effect can be realized by slowly scrolling the non-display area 312. These controls can be easily realized with the circuit configurations of FIG. 21, FIG. 66, FIG. This does not write a black display state as an image and easily realizes an animation effect by controlling the gate signal line 17b and the like.
[0416]
A display panel that holds data for one field (one frame) in a pixel such as a liquid crystal display panel has a problem in that motion blur occurs. However, since a CRT or the like is only displayed momentarily by an electron gun, there is no problem of moving image blur.
[0417]
An effective means for solving this problem is black insertion. The present invention can easily realize a black insertion method close to a CRT that displays a moving image.
[0418]
FIG. 68 shows that the letter F moves from the top to the bottom of the screen. As shown in FIG. 68, the non-display state (FIGS. 68B, 68D, and 68F) is inserted between the image displays (FIGS. 68A, 68C, and 68E). Yes. Therefore, the image is displayed in a flying manner. As a result, no moving image blur occurs and a good moving image display can be realized.
[0419]
In this way, the circuit configuration of FIG. 66 may be employed to make the entire screen a non-display area. The difference from FIG. 21 is that an ENBL terminal 601 is provided. The ENBL terminal 601 is connected to one terminal of the OR circuit 602 in which the gate signal line 17 is formed. By setting the ENBL terminal to the L level, the Vgh level is output to all the gate signal lines 17b, the switching TFT 11d or the TFT 11e that supplies current to the EL element 15 is turned off, and the entire screen is connected to the non-display area 312. Become. When the ENBL terminal is at H level, normal operation is performed.
[0420]
21, 66, 67, and 69, the data input to the ST terminal is described as being sequentially shifted with the clock (serial operation). However, the present invention is not limited to this. For example, it may be a parallel input that determines the ON / OFF state of each gate signal line at once (a configuration in which ON / OFF logic of all the gate signal lines is output and determined at a time for the number of controllers or gate signal lines 17. Such).
[0421]
The example of FIG. 68 is a moving image display, but it is also easy to implement an animation effect such as flashing for each of R, G, and B (see FIG. 70). 70A, FIG. 70A is an image of red display 311R, FIG. 70C is an image of green display 311G, and FIG. 70E is an image of blue display 311B. A non-display state (FIGS. 70B, 70D, and 70F) is inserted between the images of FIGS. 70A, 70C, and 70E. If this operation is performed slowly from FIG. 70 (a) to FIG. 70 (f), the images of R, G, and B can be displayed as if they are flashing.
[0422]
Also, as shown in FIG. 71, it is easy to implement an animation effect such as flashing for each different image. 71, FIG. 71 (a) is a first image 311a, FIG. 71 (c) is a second image 311b, and FIG. 71 (e) is a third image 311c. A non-display state (FIGS. 71B, 71D and 71F) is inserted between the images of FIGS. 71A, 71C and 71E. If the operation from FIG. 71A to FIG. 71F is performed slowly, the first, second, and third images can be displayed as if they are flashing.
[0423]
In the above embodiment, a current N times as large as a predetermined value of the source signal line 18 is conceptually passed, and a current N times as long as 1 / N is passed through the EL element 15 to obtain a desired luminance. Method
(Configuration). This way
(Configuration) solves the problem of insufficient writing due to the presence of the parasitic capacitance 404.
[0424]
Note that the light emission efficiency of the N-fold drive method is higher than that of the 1-time drive (conventional drive method). This is the influence of the punch-through voltage of the driving TFT 11b (capacitor 19 side) in FIG. 6, and the influence of the punch-through voltage can be reduced by increasing the N times. The N multiple is suitably 1.5 times or more and 8 times or less. If it is more than this, the luminous efficiency of the EL element is lowered, and the overall efficiency is also lowered. Therefore, the N multiple is preferably 2 to 6 times. Here, N times means that the light emission period is 1 / N. Therefore, when the N multiple is set to 2 times or more and 6 times or less, the light emission period is set to 1/2 or more and 1/6 or less (in normal brightness).
[0425]
In the present invention, the switching TFT 11d is turned off, the current to the EL element 15 is interrupted, and then the switching TFT 11d is turned on again, whereby the current can be passed through the EL element 15 in the same manner as before. In the present invention, this principle is applied well, and a current is passed in a period of 1 / N to obtain a predetermined luminance. The reason why it can be driven in this way is that the current value to be passed is held in the capacitor 19 for each pixel 16. That is, it can be said that the present invention has successfully applied the pixel configuration peculiar to the EL display panel while maintaining the current value flowing through the EL element 15.
[0426]
(Embodiment 9)
The configuration of FIG. 72 is a method for solving the problem of insufficient writing due to the presence of the parasitic capacitance 404 by forming a driving TFT 11an having a driving capability N-1 times that of the driving TFT 11a.
[0427]
The difference between FIG. 72 and FIG. 6A is that, in addition to the driving TFT 11a, an N-1 times driving TFT 11an-1 and a switching TFT 11f are added. The difference between FIG. 6 and FIG. 72 will be mainly described. The reason why the driving TFT 11an-1 is selected is that the driving TFT 11an-1 and the driving TFT 11a are configured to be N times as long as the currents of the driving TFT 11an-1 and the driving TFT 11a are added. That is, the channel width W2 of the driving TFT 11an-1 is set to N-1 times the channel width W1 of the driving TFT 11a. For example, if N = 10 and the channel width W1 of the driving TFT 11a is 1, the channel width W2 of the driving TFT 11an-1 is nine times. Therefore, theoretically, if the driving TFT 11a allows a current of 1 to flow, the driving TFT 11an-1 has a capability of flowing a current 9 times as large.
[0428]
In FIG. 72, the driving current of the driving TFT 11an-1 is set to N-1. In the configuration of FIG. 72, when the N-fold current is supplied to the source signal line 18, the driving current is supplied to the EL element 15. This is because a current that is one time that of the TFT 11a is added. In the configuration of FIG. 73, since the current of the driving TFT 11b that passes current to the EL element 15 does not flow to the source signal line 18, the driving current of the TFT 11n needs to be increased N times.
[0429]
For ease of explanation, if the driving TFT 11a passes a current I1, and the driving TFT 11an-1 passes an In-1 current, then I1 + In-1 = Iw (in this case, Iw is the EL element 15). The current I1 is N times as large as the current I1 to be applied.
[0430]
In the current program period, the gate signal line 17a is applied to the ON voltage Vgl, and the driving TFT 11b, the switching TFT 11f, and the capturing TFT 11c are turned on. Further, the off voltage Vgh is applied to the gate signal line 17b, and the switching TFT 11d is turned off. Therefore, a voltage corresponding to the program current Iw is programmed in the capacitor 19. That is, a current of I1 + In−1 = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15) flows through the source signal line 18.
[0431]
Next, in a period in which a current flows through the EL element 15, the off voltage Vgh is applied to the gate signal line 17a, and the driving TFT 11b, the switching TFT 11f, and the take-in TFT 11c are turned off. Therefore, the source signal line 18 and the pixel 16 are separated. Further, the on voltage Vgl is applied to the gate signal line 17b, and the switching TFT 11d is turned on. Therefore, a current I1 corresponding to 1 / N of the program current Iw flows through the EL element 15.
[0432]
By driving as described above, the source signal line 18 can be supplied with a current N times as large as a desired value (current flowing through the EL element). Therefore, the influence of the parasitic capacitance 404 is excluded, and the current program can be sufficiently performed on the capacitor 19. On the other hand, a desired value of current can be applied to the EL element 15.
[0433]
In FIG. 72, the driving TFT 11an-1 having a current capability of N-1 is manufactured in one pixel, but the present invention is not limited to this. As shown in FIG. 74, a plurality of TFTs (TFT 11n1 to TFT 11n6 in FIG. 74) may be manufactured. Since the operation is the same as that in FIG.
[0434]
The configuration of FIG. 72 can also be developed in the current mirror system shown in FIG. As shown in FIG. 73, a TFT 11n having N times driving capability may be formed. However, in the current mirror configuration, the switching TFT 11f is not necessary.
[0435]
In FIG. 73, the ratio of the channel width W2 of the TFT 11n to the channel width W1 of the driving TFT 11b is N: 1. For ease of explanation, if the driving TFT 11b passes a current I1, and the TFT 11n passes an In current, then In = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15). ).
[0436]
During the current program period, the ON voltage Vgl is applied to the gate signal line 17a, and the capturing TFT 11c and the switching TFT 11d are turned on. Therefore, a voltage corresponding to the program current Iw is programmed in the capacitor 19. That is, a current of In = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15) flows through the source signal line 18. Note that it is preferable to control the on / off state of the take-in TFT 11c and the switching TFT 11d with a slight shift in timing. In this case, the gate signal line for controlling the take-in TFT 11c and the gate signal line for controlling the switching TFT 11d are required to be separately controlled.
[0437]
Next, in a period in which a current flows through the EL element 15, the off voltage Vgh is applied to the gate signal line 17a, and the take-in TFT 11c and the switching TFT 11d are turned off. Therefore, the source signal line 18 and the pixel 16 are disconnected, and a current I1 corresponding to 1 / N of the program current Iw flows through the EL element 15.
[0438]
By driving as described above, the source signal line 18 can be supplied with a current N times as large as a desired value (current flowing through the EL element). Therefore, the influence of the parasitic capacitance 404 is excluded, and the current program can be sufficiently performed on the capacitor 19. On the other hand, a desired value of current can be applied to the EL element 15.
[0439]
As described with reference to FIG. 62, the gate signal line 17b and the TFT 11e are provided in order to control the current to flow through the EL element 15 only during non-image display or 1 / N period as shown in FIG. Therefore, in the configuration of FIG. 73, the problem of insufficient writing due to the parasitic capacitance 404 is eliminated at all by flowing N times more current and driving the current flowing through the EL element 15 in a 1 / N period. Further, black insertion display can be easily realized, and good moving image display can be realized.
[0440]
The configuration of FIG. 73 is very effective. For example, if N = 10 is to be realized with the configuration of FIG. 6 alone, it is necessary to apply a pulsed current 10 times higher than the desired value to the EL element 15. In this case, since the terminal voltage of the EL element 15 becomes high, it is necessary to design the Vdd voltage high, and the EL element 15 may be deteriorated.
[0441]
However, in the configuration of FIG. 73, if the channel width W2 of the TFT 11n is 5 times that of the driving TFT 11b and programmed with a current that is twice as high, 5 × 2 = 10 is obtained. This can be realized by applying only a half period. Therefore, there is no problem that the EL element 15 deteriorates, and it is not necessary to increase the Vdd voltage almost.
[0442]
On the other hand, if N = 10 is to be realized only by the TFT 11n, the channel width W2 of the TFT 11n needs to be 10 times that of the driving TFT 11b in the configuration of FIG. When the magnification is 10 times, the formation area of the TFT 11n occupies most of the area of the pixel. Therefore, the pixel aperture ratio becomes extremely small or cannot be realized. However, in the configuration of FIG. 73, it is only necessary to make the channel width W2 of the TFT 11n five times that of the driving TFT 11b, so that a sufficient pixel aperture ratio can be realized.
[0443]
There are many ways to achieve N = 10. For example, the channel width W2 of the TFT 11n is twice that of the driving TFT 11b, and a current five times higher is applied to the EL element 15 for a period of 1/5, or the channel width W2 of the TFT 11n is four times that of the driving TFT 11b. For example, a method in which a current five times higher is applied to the EL element 15 for a period of 1 / 2.5. That is, the multiplication may be set to 10 in consideration of the design of the TFT 11n (channel width W2), the current flowing through the EL element 15 and the period thereof. Thus, the value of N can be designed freely.
[0444]
In FIG. 73, the TFT 11n having the current capability of N is manufactured in one pixel, but the present invention is not limited to this. As shown in FIG. 75, a plurality of TFTs (TFT 11n1 to TFT 11n5 in FIG. 75) may be manufactured. The operation is the same as in FIG.
[0445]
There are many ways of realizing N = 10 in the configuration of FIG. The channel width W2 of the driving TFT 11an-1 is four times that of the driving TFT 11a, and a current twice higher is applied to the EL element 15 for a period of half, or the channel width W2 of the driving TFT 11an-1 is set to the driving TFT 11a. For example, a method of applying a current 5 times higher to the EL element 15 for a period of 1/5. That is, the multiplication may be set to 10 in consideration of the design of the driving TFT 11an-1 (channel width W2), the current flowing through the EL element 15 and the period thereof. Thus, the value of N can be designed freely.
[0446]
It is clear that the items described above can be applied to FIGS. 72, 74, and 76 to 78. That is, according to the present invention, a driving TFT having a large channel width is formed in each pixel, and the current for driving the source signal line 18 is increased. In addition, as described with reference to FIG. 49 and the like, the current or current flowing through the EL element 15 is increased and the current flowing through the EL element 15 is set to a predetermined period.
[0447]
Further, the display described with reference to FIGS. 25 and 49 can be realized by controlling on / off of the switching TFT 11d or TFT 11e. With this display, the moving image display can be improved and the brightness can be adjusted. Therefore, in the present invention, a current that is N times or proportional to N is applied to the EL element 15, but the present invention is not limited to this. A configuration in which a current that is a predetermined one or less is supplied to the EL element 15 may be employed. This is because even in this case, the moving image display can be improved and the brightness can be easily adjusted.
[0448]
6 and 72 are the same, but when the switching TFT 11d is turned on, the characteristic variation due to the kink phenomenon of the driving TFT 11a can be suppressed by increasing the resistance value. This has been described with reference to the configuration of FIG. By disposing the TFT 11e of FIG. 6B and applying a Vbb voltage (Vgl <Vbb <Vgh) to the gate terminal of the TFT 11e, variation in the current flowing through the driving TFT 11a is reduced.
[0449]
6 and 72, it is preferable to apply the Vbb voltage to the gate signal line 17b to turn on the switching TFT 11d. In other words, the switching TFT 11d is applied with the off voltage Vgh in the off state and applied with the Vbb voltage in the on state.
[0450]
This control is easy if the circuit is configured as shown in FIG. If the off-state voltages Vgh and Vbb are used as power supplies, the output stage inverter of the shift register 22b can apply the off-voltage Vgh to the gate signal line 17b in the off state and the Vbb voltage to the gate signal line 17b in the on state. It is.
[0451]
Although the ON / OFF control of the gate signal line 17 is based on the data held in the shift register 22, the present invention is not limited to this, and each gate signal line 17 is independently controlled without providing the shift register 22. The method may be used. For example, an arbitrary gate signal line 17 that outputs an ON voltage may be selected by a multiplexer circuit. Alternatively, all the gate signal lines may be drawn in parallel so that an on voltage or an off voltage can be freely applied to each gate signal line. In this way, by configuring so that an arbitrary gate signal line 17 can be selected regardless of the data held in the shift register 22, FIGS. 49, 53, 45, 46, 210, 213, and 218. 221, FIG. 223, FIG. 248, etc., it becomes easy to turn on / off the display screen 21 or process the intensity distribution.
[0452]
Similarly to FIG. 6B, as shown in FIG. 76, a TFT 11e to which a Vbb voltage is applied may be separately formed or arranged. The same applies to the current mirror configuration. For example, as shown in FIGS. 79 and 80, a switching TFT 11f for applying a Vbb voltage may be separately formed or arranged. The same applies to the pixel configuration of FIG.
[0453]
In FIG. 82, by separating the driving TFT 11a into the TFT 11a1 and the TFT 11a2 and connecting the gate terminals in cascade, the kink phenomenon can be suppressed and the characteristic variation can also be suppressed. The same applies to the driving TFT 11a in FIG. 6, the driving TFT 11b in FIG. 19, the driving TFT 11a in FIG. 72, the driving TFT 11b in FIG. 73, and the like (preferably employed as the configuration of the driving TFT).
[0454]
74 and 75, the TFT 11n and the like are divided into a plurality of parts. As another configuration, the gate signal line 17c determines whether or not the divided TFTs 11n1 and 11n2 as shown in FIG. It may be controlled by the potential (Vgh or Vgl) applied to. When the TFT 11f2 is turned off, the current flowing through the source signal line 18 is ½ that when the TFT 11n1 and TFT 11n2 are operating. These controls may be determined from the viewpoint of image display data of the display panel and power consumption.
[0455]
The difference between FIG. 76 and FIG. 77 is that the gate terminal of the switching TFT 11f is connected to the gate signal line 17c. That is, the on / off state of the switching TFT 11f is not affected by the potential state of the gate signal line 17a, and unique control can be realized. When the switching TFT 11f is constantly in an off state, the TFT 11n is separated from the pixel, and the pixel configuration of FIG. 6A is obtained. If the gate signal line 17c and the gate signal line 17a are logically shorted and used, the configuration shown in FIG. 76 is obtained.
[0456]
The problem of FIG. 76 here is that if a characteristic shift such as the threshold value Vt between the TFT 11n and the driving TFT 11a occurs for each pixel, the current flowing in the EL element 15 varies for each pixel. When variation occurs in the current, a feeling of roughness appears in the displayed image even in a uniform display such as a white raster. In this respect, this problem does not occur in the configuration of FIG.
[0457]
Therefore, when the screen size of the display panel is small and the influence of the parasitic capacitance 404 is small, the switching TFT 11f is constantly used in the off state. Further, when the screen size of the display panel is large and the influence of the parasitic capacitance 404 cannot be eliminated only by the operation of the driving TFT 11a, the gate signal line 17c is short-circuited with the logic of the gate signal line 17a to realize the pixel configuration of FIG. Then, it is good to drive.
[0458]
FIG. 69 shows a circuit block for driving the pixel configuration of FIG. A shift register 22c for driving the gate signal line 17c is formed, and the gate signal line 17c is driven. When driving with the pixel configuration of FIG. 6, the control is performed so that the data of ST3 is constantly set to L and the Vgh off-voltage is continuously output to the gate signal line 17c. When used in the configuration of FIG. 77, the data input states (timing, logic, etc.) of the shift registers 22c and 22a may be the same.
[0459]
The configuration of FIG. 77 can also be realized by a configuration of a current mirror. FIG. 78 shows the pixel configuration. As shown in FIG. 78, whether or not the divided driving TFT 11a and TFT 11n are operated for improving the driving current may be controlled by the potential (Vgh or Vgl) applied to the gate signal line 17c. When the switching TFT 11f is turned off, only the driving TFT 11a is operated by the current flowing through the source signal line 18.
[0460]
Therefore, similarly to the pixel configuration of FIG. 77, when the screen size of the display panel is small and the influence of the parasitic capacitance 404 is small, the switching TFT 11f is constantly used in the OFF state. When the screen size of the display panel is large and the influence of the parasitic capacitance 404 cannot be eliminated only by the operation of the driving TFT 11a, the gate signal line 17c is short-circuited with the logic of the gate signal line 17a, and the driving current is increased to drive. As described above, the circuit block of FIG. 69 can also be applied to the pixel configuration of FIG.
[0461]
In the configuration of FIG. 69, a shift register 22c for controlling the gate signal line 17c is newly formed and operated. However, it is not limited to this configuration. Since only the Vgl or Vgh voltage is applied to the gate terminal of the switching TFT 11f, the control logic of the gate signal line 17c is easy. When the TFT 11n is not operated, the off voltage Vgh may be applied to the gate terminals of all the switching TFTs 11f in the display screen 21. When the TFT 11n is operated, the potential of the gate signal line 17a may be applied to the gate signal line 17c. Therefore, it is not necessary to separately use the shift register 22c as shown in FIG. That is, the data of the shift register 22a may be output to the gate signal line 17c as it is, or a gate circuit may be added so that the potentials of all the gate signal lines 17c become the off voltage Vgh.
[0462]
(Embodiment 10)
The driving method of the present invention will be described below. By multiplying the current flowing through the source signal line 18 by N, the influence of the parasitic capacitance 404 is eliminated, and a good image display with resolution can be realized. FIG. 45 is an explanatory diagram of another embodiment for increasing the current flowing in the source signal line. The driving method of the present invention in FIG. 45 basically selects a plurality of pixel rows at the same time, charges and discharges the parasitic capacitance of the source signal line with a current that combines the plurality of pixel rows, and greatly reduces current writing shortage. It is a way to improve. With this driving method, since a plurality of pixel rows are simultaneously selected, the driving current per pixel can be reduced, and the current flowing through the EL element 15 can also be reduced. Here, for ease of explanation, as an example, N = 10 will be described (the current flowing through the source signal line is multiplied by 10).
[0463]
In the present invention described with reference to FIG. 45 and the like, K pixel rows are simultaneously selected as the pixel rows. A current N times the predetermined current is applied to the source signal line 18 from the source driver IC. Each pixel is programmed with a current N / K times the current flowing through the EL element. In order to make the EL element have a predetermined light emission luminance, the time for flowing through the EL element is set to K / N time of one frame. By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and good resolution and predetermined light emission luminance can be obtained.
[0464]
That is, current flows through the EL element only during the K / N period of one frame, and no current flows during the other period (1F (N−1) K / N). In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F, and the image data display is in a state of skipping in time (intermittent display). Accordingly, the outline blurring of the image is eliminated and a good moving image display can be realized. Further, since the source signal line 18 is driven by N times the current, it is not affected by the parasitic capacitance and can be applied to a high-definition display panel.
[0465]
First, in order to facilitate understanding, a method of selecting one pixel row and programming an N-fold current as described above will be described with reference to a drive waveform and the like. FIG. 84 is an explanatory diagram thereof. Note that in FIG. 84, the screen is illustrated horizontally, but the screen is not limited to this, and the screen may be vertically long or another shape such as a circle.
[0466]
FIG. 84A illustrates a state of writing on the display screen 21. In FIG. 84A, reference numeral 871 denotes a writing pixel row. Note that in FIG. 84A, one pixel row is written in the 1H period. In the following embodiments, the pixel configuration of FIG. 6 will be described as an example, but the present invention is not limited to this, and the pixel configuration of a current mirror as shown in FIG. 19 may be used. Needless to say, the present invention can also be applied to voltage programming pixel configurations such as those shown in FIGS. 85, 86, and 87.
[0467]
In FIG. 84A, when the gate signal line 17a is selected, the current flowing through the source signal line 18 is programmed into the conversion TFT 11a. At this time, an off voltage is applied to the gate signal line 17b, and no current flows through the EL element 15. This is because, when the switching TFT 11d on the EL element 15 side is in an on state, the capacitance component of the EL element 15 can be seen from the source signal line 18, and a sufficiently accurate current program cannot be performed on the capacitor 19 due to this capacitance. Because. Therefore, as shown in FIG. 84B, the pixel row in which current is written becomes a non-display region 312. Since the switching TFTs 11d in the other pixel rows are in the on state, the image display area 311 is formed. In the pixel configuration of the current mirror shown in FIG. 19 and the like, the EL element 15 cannot be seen from the source signal line 18 even when a current flows through the conversion TFT 11a that performs current programming. Therefore, it is not necessary to set the non-lighting state as shown in FIG. That is, as shown in FIG. 84B, it is not an essential condition of the invention to set the writing pixel row as the non-display area 312.
[0468]
FIG. 88 shows voltage waveforms applied to the gate signal line 17. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level). The lower row of FIG. 88 shows the number of the selected pixel row. Also, (1) and (2) in the figure indicate the selected pixel row number.
[0469]
88, the gate signal line 17a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the conversion TFT 11a of the selected pixel row toward the source driver. This program current is N times a predetermined value (for ease of explanation, it is assumed that N = 10. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. .) Therefore, the capacitor 19 is programmed so that 10 times the current flows through the conversion TFT 11a. When the pixel row (1) is selected, the off voltage Vgh is applied to the gate signal line 17b (1) in the pixel configuration of FIG. 6, and no current flows through the EL element 15.
[0470]
After 1H, the gate signal line 17a (2) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the conversion TFT 11a of the selected pixel row toward the source driver 14. This program current is N times a predetermined value (in order to facilitate explanation, explanation will be made assuming that N = 10). Therefore, the capacitor 19 is programmed so that 10 times the current flows through the conversion TFT 11a. When the pixel row (2) is selected, in the pixel configuration of FIG. 6, the off voltage Vgh is applied to the gate signal line 17b (2), and no current flows through the EL element 15. However, the off voltage Vgh is applied to the gate signal line 17a (1) of the previous pixel row (1), and the on voltage Vgl is applied to the gate signal line 17b (1). .
[0471]
After the next 1H, the gate signal line 17a (3) is selected (Vgl voltage), the off voltage Vgh is applied to the gate signal line 17b (3), and a current is applied to the EL elements 15 in the pixel row (3). Not flowing. However, the off voltage Vgh is applied to the gate signal lines 17a (1) and (2) of the previous pixel rows (1) and (2), and the on voltage Vgl is applied to the gate signal lines 17b (1) and (2). Is applied, so that the lighting state is established.
[0472]
The above operation is displayed in synchronization with the 1H synchronization signal. However, in the driving method of FIG. 88, 10 times the current flows in the EL element 15. Therefore, the display screen 21 is displayed with about 10 times the luminance. Of course, in order to perform a predetermined luminance display in this state, it goes without saying that the program current may be set to 1/10. However, if the current is 1/10, insufficient writing occurs due to parasitic capacitance or the like. Therefore, it is the basic gist of the present invention to program at a high current and obtain a predetermined luminance by inserting the non-display area 312. .
[0473]
However, the method of FIG. 84 is also within the scope of the present invention. That is, the concept is that a current higher than a predetermined current flows through the EL element 15 and the parasitic capacitance of the source signal line 18 is sufficiently charged and discharged. According to this, it is not necessary to flow N times the current through the EL element 15. For example, a current path is formed in parallel with the EL element 15 (a dummy EL element is formed, and a light shielding film is not formed on the EL element to emit light), and the current is divided and distributed between the dummy EL element and the EL element 15. May be flushed. That is, when the signal current is 0.2 μA, the program current is set to 2.2 μA, and 2.2 μA is passed through the conversion TFT 11a. Of this current, a signal current of 0.2 μA is passed through the EL element 15 and 2 μA is passed through the dummy EL element.
[0474]
With the configuration described above, by increasing the current flowing through the source signal line 18 by N times, it is possible to program the current to flow through the conversion TFT 11a so that N times the current flows, and to the current EL element 15. Can pass a current sufficiently smaller than N times. In the above method, as shown in FIG. 89 and the like, the entire display screen 21 can be made the image display area 311 almost or completely as shown in FIG. 84 without providing the non-display area 312.
[0475]
However, all the programmed currents flow theoretically to the EL element 15 unless a special process such as forming a dummy EL element is performed. Therefore, in FIG. 84, the display screen emits light with N times the luminance. In order to emit light with a predetermined luminance, a non-display area 312 may be provided as shown in FIG. FIG. 89 is an explanatory diagram of this method.
[0476]
FIG. 89A shows a state of writing on the display screen 21. In FIG. 89A, reference numeral 871a denotes a writing pixel row. A program current is supplied from the source driver 14 to each source signal line 18. Note that in FIG. 89 and the like, one pixel row is written in the 1H period. However, it is not limited to 1H, and it may be 0.5H period or 2H period. Although the program current is written to the source signal line 18, the present invention is not limited to the current program method, and a voltage program method of writing a voltage to the source signal line 18 may be used.
[0477]
In FIG. 89A, as in FIG. 84, when the gate signal line 17a is selected, the current flowing through the source signal line 18 is programmed into the conversion TFT 11a. At this time, an off voltage is applied to the gate signal line 17b, and no current flows through the EL element 15. This is because, when the switching TFT 11d on the EL element 15 side is in an on state, the capacitance component of the EL element 15 can be seen from the source signal line 18, and a sufficiently accurate current program cannot be performed on the capacitor 19 due to this capacitance. Because. Therefore, taking the configuration of FIG. 6 as an example, a pixel row in which current is written becomes a non-display region 312 as shown in FIG.
[0478]
Now, assuming that the current is programmed with N times (N = 10 as described above), the screen brightness will be 10 times, so 90% of the display screen 21 is not displayed. The region 312 may be used. Therefore, if the horizontal scanning lines of the image display area are 220 QCIF (S = 220), 22 should be the image display area 311 and 220-22 = 198 should be the non-display area 312. Generally speaking, if the horizontal scanning line (number of pixel rows) is S, the S / N area is the image display area 311, and the image display area 311 emits light with N times the luminance, and the vertical direction of the screen , The S (N−1) / N area becomes the non-display area 312. This non-display area is black display (non-light emission). The non-display area 312 is realized by turning off the switching TFT 11d. Although it is assumed that the light is lit at N times the luminance, it is natural that the N times value must be adjusted by brightness adjustment and gamma adjustment.
[0479]
In the previous embodiment, if the current is programmed with 10 times the current, the screen brightness will be 10 times, and the 90% range of the display screen 21 may be set as the non-display area 312. However, this is not limited to the common non-display area 312 for RGB pixels. For example, R pixel is 1/8 non-display area 312, G pixel 1/6 non-display area 312, and B pixel 1/10 non-display area 312. You may change with each color. Further, the non-display area 312 (or the image display area 311) may be individually adjusted with the RGB color. To realize these, the individual gate signal lines 17b for R, G, and B are provided. I need it. However, by enabling individual adjustment of RGB as described above, it is possible to adjust white balance, and color balance adjustment is facilitated at each gradation.
[0480]
As shown in FIG. 89B, the pixel row including the writing pixel row 871a is set as a non-display area 312 and the S / N range above the writing pixel row 871a is set as an image display area 311 (writing scanning). Is from the top to the bottom of the screen, and vice versa when scanning the screen from bottom to top). In the image display state, the image display area 311 has a band shape and moves from the top to the bottom of the screen.
[0481]
FIG. 90 shows voltage waveforms applied to the gate signal line 17. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level). The lower row of FIG. 90 describes the number of the selected pixel row. Also, (1), (2), (3), and (4) in the figure indicate the selected pixel row number.
[0482]
90, the gate signal line 17a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the conversion TFT 11a of the selected pixel row toward the source driver. This program current is N times a predetermined value (for ease of explanation, it is assumed that N = 10. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. .) Therefore, the capacitor 19 is programmed so that 10 times the current flows through the conversion TFT 11a. When the pixel row (1) is selected, the off voltage Vgh is applied to the gate signal line 17b (1) in the pixel configuration of FIG. 6, and no current flows through the EL element 15.
[0483]
After 1H (for ease of explanation and not limited to 1H), the gate signal line 17a (2) is selected (Vgl voltage) and the source from the conversion TFT 11a of the selected pixel row A program current flows through the source signal line 18 toward the driver 14. This program current is N times a predetermined value (in order to facilitate explanation, explanation will be made assuming that N = 10). Therefore, the capacitor 19 is programmed so that 10 times the current flows through the conversion TFT 11a. At this time, the ON voltage Vgl is applied to the gate signal line 17b (1). The period during which the ON voltage is applied is an S / N period according to the embodiment of FIG. Thereafter, the off voltage Vgh is applied to the gate signal line 17b (1), and no current flows through the EL elements 15 in the pixel row (1).
[0484]
When the pixel row (2) is selected, the off voltage Vgh is applied to the gate signal line 17b (2) in the pixel configuration of FIG. 6, and no current flows through the EL element 15. However, the off voltage Vgh is applied to the gate signal line 17a (1) of the previous pixel row (1), and the on voltage Vgl is applied to the gate signal line 17b (1). . The period during which the ON voltage is applied is an S / N period according to the embodiment of FIG. Thereafter, the off voltage Vgh is applied to the gate signal line 17b (2), and no current flows through the EL elements 15 in the pixel row (2).
[0485]
After the next 1H, the gate signal line 17a (3) is selected, the off voltage Vgh is applied to the gate signal line 17b (3), and no current flows through the EL elements 15 in the pixel row (3). However, the off voltage Vgh is applied to the gate signal lines 17a (1) and (2) of the previous pixel rows (1) and (2), and the on voltage Vgl is applied to the gate signal lines 17b (1) and (2). Is applied, so that the lighting state is established. The above operation is repeated to realize the display state of FIG.
[0486]
In the display of FIG. 89, one image display area 311 moves downward from the top of the screen. When the frame rate is low, it is visually recognized that the image display area 311 moves. In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.
[0487]
To solve this problem, the image display area 311 may be divided into a plurality of parts as shown in FIG. In FIG. 91 (b), the non-display area 312 is divided into five. If the area obtained by adding these five areas has an area of S (N-1) / N, it is equivalent to the brightness of FIG. On the other hand, when viewed from the image display area 311, the image display area (lighting area) 311 is divided into six parts, and the portion obtained by adding these six divided areas substantially matches S / N. If it is configured (driven), it becomes equivalent to the display luminance of FIG.
[0488]
Note that the divided image display areas 311 do not have to be equal as illustrated in FIG. Further, the divided non-display areas 312 need not be equal.
[0489]
As described above, dividing the image display area 311 into a plurality reduces the flickering of the screen, prevents occurrence of flicker, and realizes a good image display. The division may be finer, but the moving image display performance decreases as the division is performed.
[0490]
FIG. 92 shows voltage waveforms applied to the gate signal line 17. The difference between FIG. 92 and FIG. 90 is the operation of the gate signal line 17b. The gate signal line 17b operates on and off (Vgl and Vgh) by the number corresponding to the number of divisions of the screen. The other points are the same as in FIG.
[0491]
In the above embodiment, the pixel row selected simultaneously is one pixel row. FIG. 46 shows a method for simultaneously selecting a plurality of pixel rows. In FIG. 46, for ease of explanation, it is assumed that the selection is made at the same time as the five pixel rows. However, when the number of pixel rows selected at the same time increases, the dispersion absorbing effect of the conversion TFT 11a is reduced.
[0492]
In the following embodiments, the pixel configuration of the current program in FIG. 6 will be described as an example, but the present invention is not limited to this. Needless to say, the current mirror of FIG. 19 is also effective. This is because the number of simultaneously selected pixel rows facilitates charging / discharging of the source signal line parasitic capacitance 404 and the like. Further, the pixel configuration of the voltage program shown in FIGS. 86 and 87 is also effective. This is because when the number of pixel rows selected at the same time increases, adjacent pixel rows can be precharged and can be applied to a high-definition display panel.
[0493]
Here, in order to facilitate the explanation, the current that flows from the source driver 14 to the source signal line 18 (or the current that the source driver 14 sinks from the source signal line 18 and the current that the conversion TFT 11a flows into the source signal line 18). Is described as 10 times the predetermined value (N = 10). Therefore, if the simultaneously selected pixel rows are five pixel rows (K = 5), the five conversion TFTs 11a operate. That is, 10/5 = 2 times of current flows through the conversion TFT 11a per pixel. If the simultaneously selected pixel rows are two pixel rows, the two conversion TFTs 11a operate. That is, a current of 10/2 = 5 times flows to the conversion TFT 11a per pixel.
[0494]
If the pixel rows to be selected at the same time are five pixel rows (K = 5), the program current of the five conversion TFTs 11a is added. For example, if the current to be written is originally set to Id and N = 10 in the write pixel row 871a, a current of Id × 10 is passed through the source signal line 18. A write pixel row 871b adjacent to the write pixel row 871a (871b is a pixel row used auxiliary to increase the amount of current to the source signal line 18. Therefore, a pixel (row) for writing an image is 871a, A pixel (row) 871b is used as an auxiliary to write to 871a).
[0495]
Ideally, each of the conversion TFTs 11a of five pixels passes a current of Id × 2 to the source signal line 18, and the capacitor 19 of each pixel 16 is programmed with a double current. However, since the characteristics of the TFTs 11 of the five pixels are shifted in reality, the current programmed in the capacitor 19 of each pixel varies. For example, the write pixel row 871a is programmed with a current of 1.8 times, and the four write pixel rows 871b are programmed with a current of 2.2 times, 2.0 times, 1.6 times, and 2.4 times, respectively. In this example, 1.8 times the current is programmed in the write pixel row 871a, and an error of (2.0−1.8) /2.0=10% occurs. However, the sum of these currents is maintained at a specified value of 10 times.
[0496]
In other words, the current programmed from the source driver 14 flows through the source signal line 18 as prescribed, whereas the current according to the characteristic variation flows through the selected pixel. Therefore, as the characteristic variation of the conversion TFT 11a of each pixel increases, the target program current deviates from the set value. However, since the adjacent conversion TFTs 11a have substantially the same characteristics, uniform display can be realized even if the number of pixel rows to be selected simultaneously is increased as shown in FIG.
[0497]
45 and 46 are more effective for a display panel in which the TFT 11 is formed by amorphous silicon technology than in a display panel in which the TFT 11 is formed by low temperature polysilicon technology. This is because the characteristics of adjacent TFTs in the amorphous silicon TFT 11 are substantially the same. Therefore, even when driving with the added current, the driving current of each TFT is almost the target value.
[0498]
In FIG. 46, when K rows (K = 5) are simultaneously written in the image data of the writing pixel row 871a, the K row ranges (871a, 871b) are displayed in the same manner. When the same display is made in this way, the resolution is naturally reduced. In order to cope with this, the portion of the writing pixel row 871 is set as a non-display area 312 as shown in FIG. As a result, no resolution reduction occurs.
[0499]
After the next 1H, the same operation is performed with the position shifted by one pixel row as the writing pixel row 871a, and the non-display area 312 is also shifted by one pixel (row), so that the pixel (row) that is current-programmed with the previous 1H is displayed. Is done.
[0500]
When driven as described above, the write pixel row 871b in which current data different from the original display data is written is not displayed, and a complete image display can be realized by shifting the above operation one row at a time. Further, due to the effect of the writing pixel row 871b used as an auxiliary, charging / discharging of the parasitic capacitance 404 can be realized within a sufficiently 1H period.
[0501]
FIG. 93 is an explanatory diagram of drive waveforms for realizing the drive method of FIG. As in FIG. 88, the voltage waveform has an off voltage of Vgh (H level) and an on voltage of Vgl (L level). The lower row of FIG. 93 shows the number of the selected pixel row. (1), (2), (3)... (6) indicate the selected pixel row number. The number of rows is 220 in the case of the QCIF display panel and 480 in the case of the VGA panel.
[0502]
In FIG. 93, the gate signal line 17 a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the conversion TFT 11 a of the selected pixel row toward the source driver 14. Here, for ease of explanation, first, it is assumed that the writing pixel row 871a is the pixel row (1) -th.
[0503]
The program current flowing through the source signal line 18 is N times a predetermined value (for ease of explanation, N = 10 will be described. Of course, since the predetermined value is a data current for displaying an image, white raster display is performed. It is not a fixed value unless it is). Further, description will be made assuming that five pixel rows are simultaneously selected (K = 5). Therefore, ideally, the capacitor 19 of one pixel is programmed so that twice the current flows through the conversion TFT 11a.
[0504]
When the writing pixel row is the (1) pixel row, as shown in FIG. 93, (1), (2), (3), (4), (5) are selected for the gate signal line 17a. ing. That is, the driving TFT 11b and the capturing TFT 11c in the pixel rows (1), (2), (3), (4), and (5) are in the on state. Further, since the gate signal line 17b is in an opposite phase to the gate signal line 17a, the switching TFT 11d in the pixel rows (1), (2), (3), (4), and (5) is in an OFF state. The current does not flow through the EL elements 15 in the corresponding pixel row, and the non-display area 312 is formed.
[0505]
Ideally, the conversion TFTs 11 a of 5 pixels each pass a current of Id × 2 to the source signal line 18. A double current is programmed in the capacitor 19 of each pixel 16. Here, for ease of understanding, description will be made assuming that the characteristics (Vt, S value) of the conversion TFTs 11a are the same.
[0506]
Since five pixel rows (K = 5) are selected at the same time, the five conversion TFTs 11a operate. That is, 10/5 = 2 times of current flows through the conversion TFT 11a per pixel. A current obtained by adding the program currents of the five conversion TFTs 11a flows through the source signal line 18. For example, a current to be originally written is Id in the write pixel row 871a, and a current of Id × 10 is supplied to the source signal line 18. A write pixel row 871b for writing image data after the write pixel row (1) is a pixel row used auxiliary to increase the amount of current to the source signal line 18. However, there is no problem in the writing pixel row 871b because normal image data is written later.
[0507]
Accordingly, since the writing pixel row 871b is displayed in the same manner as the writing pixel row 871a during the 1H period, the writing pixel row 871a and the writing pixel row 871b selected for increasing the current are at least the non-display area 312. is there. However, the current mirror pixel configuration as shown in FIG. 19 and the voltage programming pixel configuration as shown in FIG.
[0508]
After the next 1H, the gate signal line 17a (1) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (1). At the same time, the gate signal line 17 a (6) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the conversion TFT 11 a of the selected pixel row (6) toward the source driver 14. By operating in this way, regular image data is held in the pixel row (1).
[0509]
After the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (2). At the same time, the gate signal line 17 a (7) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the conversion TFT 11 a of the selected pixel row (7) toward the source driver 14. By operating in this way, regular image data is held in the pixel row (2). One screen is rewritten by performing the above operation and scanning while shifting one pixel row at a time.
[0510]
As in FIG. 84, in the driving method of FIG. 93, since each pixel is programmed with twice the current (voltage), the light emission luminance of the EL element 15 of each pixel is ideally doubled. . Therefore, the brightness of the display screen is twice the predetermined value.
[0511]
In order to obtain a predetermined luminance, as shown in FIG. 45, a non-display area 312 may be included that includes a writing pixel row 871 and a half of the display screen 21. This has been described with reference to FIG.
[0512]
As the area of the black display area (non-display area) 312 occupying the display screen 21 is increased, the moving image display performance is improved. Therefore, as shown in FIG. 94, the image display area 311 may be reduced and the area of the non-display area 312 may be increased.
[0513]
As shown in FIG. 45, when the current programmed in each pixel is doubled and the area of the image display region 311 is 1/2 of the display screen 21, a predetermined display luminance can be obtained. However, when the image display area 311 is smaller than ½ of the display screen 21 as shown in FIG. 94, the screen becomes dark. Therefore, in order to obtain a predetermined luminance, the current programmed for each pixel may be increased. For example, if the image display region (lighting region) 311 is 1/5 of the area of the display screen 21 and five pixel rows are selected simultaneously (K = 5), the current (voltage) programmed in one pixel row May be five times the predetermined value. The current flowing through the source signal line 18 is 5 × 5 pixel rows = 25 times.
[0514]
In any case, in the embodiment of the present invention, the program current (voltage) can be adjusted by changing the current (voltage) flowing through the source signal line 18. That is, the current flowing through the source signal line 18 can be adjusted only by adjusting the reference current (voltage) of the source driver 14. Whether to turn on two pixel rows at the same time, turn on five pixel rows at the same time, or select only one pixel row depends on whether the ST * terminal applied to the shift register 22 of the gate driver 12 shown in FIG. Can be set with data. Therefore, the specification of the source driver 14 does not depend on the number of pixels to be selected. Further, since the brightness of the screen can also be adjusted by turning on / off the gate signal line 17b, the output current from the source driver 14 is not changed by adjusting the brightness of the display screen 21. Therefore, the gamma characteristic of the EL element 15 may be determined for one current. Therefore, the configuration of the source driver 14 is extremely easy and highly versatile. The above matters can be applied to other embodiments of the present invention.
[0515]
In the above embodiment, one selected pixel row is arranged (formed) for each pixel row. However, the present invention is not limited to this, and one selected pixel in a plurality of pixel rows. A gate signal line may be arranged (formed).
[0516]
FIG. 95 shows an example thereof. In order to facilitate the description, the pixel configuration will be described mainly using the case of FIG. In FIG. 95, the selection gate signal line 17a in the pixel row simultaneously selects three pixels (16R, 16G, 16B), and sets each pixel in a data writing state. Note that the symbol R represents a red pixel relationship, the symbol G represents a green pixel relationship, and the symbol B represents a blue pixel relationship.
[0517]
The pixel 16R writes data from the source signal line 18R to the capacitor 19R, the pixel 16G writes data from the source signal line 18G to the capacitor 19G, and the pixel 16B writes data from the source signal line 18B to the capacitor 19B.
[0518]
The TFT 11d of the pixel 16R is connected to the gate signal line 17bR, the TFT 11d of the pixel 16G is connected to the gate signal line 17bG, and the TFT 11d of the pixel 16B is connected to the gate signal line 17bB. Accordingly, the EL element 15R of the pixel 16R, the EL element 15G of the pixel 16G, and the EL element 15B of the pixel 16B can be separately controlled on and off. That is, the EL element 15R, the EL element 15G, and the EL element 15B can individually control the lighting time and the lighting cycle by controlling the gate signal lines 17bR, 17bG, and 17bB.
[0519]
In order to realize this operation, in the configuration of FIG. 21, the shift register 22 that scans the gate signal line 17a, the shift register 22 that scans the gate signal line 17bR, and the shift register 22 that scans the gate signal line 17bG It is appropriate to form (place) four shift registers 22 that scan the gate signal line 17bB.
[0520]
FIG. 96 illustrates the arrangement of the pixels 16. In FIG. 96, pixels are formed in a horizontal stripe shape (in the conventional configuration, it is generally a vertical stripe shape). By arranging the pixels in a horizontal stripe shape, the connection between the gate signal line 17 and the switching element is facilitated, and the pixel layout is facilitated. Further, in the case of an EL element made of a polymer material, it can be easily produced by ink jet.
[0521]
95 and 96, the pixels are formed in a horizontal stripe shape, but may be formed in a vertical stripe shape as in the conventional case. In addition, the reverse bias voltage application method, block drive method, control method using Vbb voltage, a configuration in which each RGB voltage is made separate, a method using the punch-through voltage of the TFT 11b, and the method shown in FIG. Needless to say, it is appropriate to combine a configuration in which dummy pixel rows are added with other embodiments in this specification.
[0522]
FIG. 97 shows operation waveforms of the pixel configuration of FIG. For ease of explanation, it is assumed that one pixel row is selected (of course, if counting in RGB, it will be three pixel rows). However, as described in FIGS. 45, 46, 116, etc., it is needless to say that a driving method for simultaneously selecting a plurality of pixel rows can be realized. In addition, as described with reference to FIG. 110, it is necessary to control the timing of the gate signal line even within the range of the 1H period. Here, for ease of explanation, the pixel row of the gate signal line 17a is controlled. The selection will be described as being a 1H period. The above matters are also applied to other driving methods and panel configurations described in this specification.
[0523]
In FIG. 97, when the writing pixel row is the (1) pixel row, the gate signal line 17a selects the pixel 16 block (it is easier to understand if it is considered as one pixel row) (FIG. 95). See also). That is, the pixel 16R, the pixel 16G, and the pixel 16B are selected, and the switching TFT 11b and the TFT 11c in the pixel row (1) 16R, the pixel row (1) 16G, and the pixel row (1) 16B are turned on.
[0524]
The pixel 16R in the pixel row (1) writes image data from the source signal line 18R to the capacitor 19R, and the pixel 16G in the pixel row (1) writes image data from the source signal line 18G to the capacitor 19G. ) Pixel 16B writes the image data from the source signal line 18B into the capacitor 19B.
[0525]
For ease of explanation, in FIG. 97, each pixel is programmed such that N times (N = 2) current flows in the EL element 15 in a 1 / N period of one frame (one field). Will be described. As described in this specification, the present invention can be applied to other embodiments. Needless to say, by increasing the N value, the influence of the parasitic capacitance 404 of the source signal line 18 can be ignored, and image data can be easily written to the pixel 16. That is, it is not limited to N = 2. N is not limited to an integer, and can be realized by a value such as 2.5. The selection time of the gate signal line 17a is not limited to 1H, and may be 2H or more.
[0526]
The gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB in the pixel row (1) are in opposite phases to the gate signal line 17a. Therefore, at least the switching TFTs 11d of the pixel 16R, the pixel 16G, and the pixel 16B in the pixel row (1) are in the off state, and no current flows through the EL elements (15R, 15G, 15B) in the corresponding pixel row. It becomes a display area 312.
[0527]
After the next 1H, the gate signal line 17a (1) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b. At the same time, the gate signal line 17a (2) is selected (Vgl voltage), and the source signal line 18 (from the TFT 11a of the pixel 16R, pixel 16G, and pixel 16B of the selected pixel row (2) toward the source driver 14 ( Program currents flow through 18R, 18G, and 18B, respectively. By operating in this way, image data is held in the pixel 16R, the pixel 16G, and the pixel 16B of the pixel row (1).
[0528]
Further, after the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (2). At the same time, the gate signal line 17 a (3) is selected (Vgl voltage), and a program current flows from the TFT 11 a in the selected pixel row (3) toward the source driver 14 through the source signal line 18. By operating in this way, image data is held in the pixel row (2). One screen is rewritten by scanning the above operation while shifting one pixel row at a time.
[0529]
Next, the operation of the gate signal line 17b in FIG. 97 will be mainly described. A gate signal line 17bR is connected to the pixel 16R. A gate signal line 17bG is connected to the pixel 16G. A gate signal line 17bB is connected to the pixel 16B. Therefore, the pixel 16R can perform on / off control of the current flowing through the EL element 15R through the gate signal line 17bR. Similarly, the pixel 16G can perform on / off control of the current flowing through the EL element 15G by the gate signal line 17bG, and the pixel 16B can perform on / off control of the current flowing through the EL element 15B by the gate signal line 17bB.
[0530]
In FIG. 97, the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB have the same waveform in each pixel row. Accordingly, the EL elements 15R, 15G, and 15B are turned on / off (lighted or not lighted) at the same time. In FIG. 97, the EL element 15 is turned on and off every 4H, but is not limited to this. It may be every 1H or more. In principle, the EL element 15 may be turned on and off at a cycle of 1H or less.
[0531]
However, if the on / off cycle is too fast, moving image blur occurs in the moving image display. Therefore, the interval from when the EL element 15 is turned on until it is turned off and then turned on needs to be 0.5 msec or more. When this period is short, the image is not completely displayed due to the afterimage characteristics of the human eye, and the image becomes blurred, as if the resolution is lowered. Further, the display state of the data holding type display panel is set. However, when the on / off period is set to 100 msec or more, it looks like a blinking state. Therefore, the on / off period of the EL element should be 0.5 μsec or more and 100 msec or less, and more preferably 2 msec or more and 30 msec or less. More preferably, it should be 3 msec or more and 20 msec or less.
[0532]
From the above relationship, the number of insertions of the non-display area 312 for turning on / off the screen is determined from the time required for one frame (one field) and the cycle or number of signals (Vgh, Vgl) applied to the gate signal line 17b. When one non-display area 312 is provided, a good moving image display can be realized. However, since flickering of the screen is easily seen, it is preferable to divide the non-display area 312 insertion portion into a plurality. However, if the number of divisions is excessively large, moving image blur occurs, so that the number of divisions is preferably 1 or more and 8 or less, and more preferably 1 or more and 5 or less.
[0533]
In the present invention, even if the current flowing through the EL element 15 is cut off by turning off the TFT 11d, when the TFT 11d is turned on again, the same current as the current that has flowed previously can be passed through the EL element 15. . This is because the current value to be passed is stored in the pixel capacitor 19 (analog memory). This matter is a major feature of the present invention. That is, it means that the control for turning on and off the current flowing through the EL element 15 can be freely performed.
[0534]
In FIG. 97, the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB have the same waveform in each pixel row, and the selection of the pixel row is performed by sequentially shifting the selected pixel row every 1H. The light emission positions of 15R, 15G, and 15B move from the top to the bottom of the display screen 21 at high speed. The on / off control, the insertion ratio of the non-display area 312 and the number of non-display areas 312 can be easily realized by controlling the ST data to the shift register 22 described with reference to FIG. Of course, it goes without saying that the Vgh data applied to the gate signal line 17b may be controlled in parallel.
[0535]
Further, although the signal applied to the gate signal line 17 is a periodic signal, the signal is not limited to this and may be an aperiodic signal. However, if the total time for turning on or off the EL element 15 is different, the brightness of the screen changes or a color balance shift occurs. Therefore, the EL element 15 is turned on or off in one frame (one field) period. It is necessary to set the total sum of turning off time to a constant value. Note that as a special case, there is a case where the total time for which the EL element 15 is turned on or off in a period of two frames (two fields) or more may be a constant value. One frame (field) is very fast and the other is FSC (frame sequential control) drive.
[0536]
In FIG. 98, the waveform applied to the gate signal line 17bR is changed in a 2H cycle, the waveform applied to the gate signal line 17bG is changed in a 3H cycle, and the waveform applied to the gate signal line 17bB is changed in a 4H cycle. . Other items are the same as those in FIG.
[0537]
Note that the synchronous change pattern in FIG. 98 is for ease of drawing, and is not limited to 2H, 3H, or the like. A signal applied to at least one gate signal line 17b among at least the gate signal line 16bR connected to the pixel 16R, the gate signal line 16bG connected to the pixel 16G, and the gate signal line 16bB connected to the pixel 16B. The waveform is different from that of the other gate signal line 17b.
[0538]
When driven as shown in FIG. 98, the light emission positions of the EL elements 15R, 15G, and 15B move from the top to the bottom of the display screen 21 at high speed. At this time, the on / off (lighting / non-lighting) cycle of the EL element 15R, the on / off (lighting / non-lighting) cycle of the EL element 15G, and the on / off (lighting / non-lighting) cycle of the EL element 15B are different. In this way, the occurrence of flicker is less noticeable by changing the lighting cycle of the EL element 15.
[0539]
The on / off control, the insertion ratio of the non-display area 312 and the number of non-display areas 312 can be easily realized by controlling the ST data to the shift register 22 described with reference to FIG. Of course, it goes without saying that the signal (Vgh, Vgl) data applied to the gate signal line 17b may be controlled in parallel.
[0540]
In FIG. 99, the Vgl period applied to the gate signal line 17bR is shorter than the other gate signal lines 17b. Therefore, the lighting time of the EL element 15R connected to the gate signal line 17bR becomes long (the period during which the TFT 11d of the pixel 16R is turned on becomes long). Accordingly, the R emission luminance of the display screen 21 is increased.
[0541]
As described above, by individually controlling the signals applied to the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB, that is, by controlling the time, timing, and cycle of turning on the EL element 15, The color balance and flicker generation on the screen 21 can be suppressed.
[0542]
In FIG. 99, the waveform applied to the gate signal line 17bG is changed in a 3H cycle, and the waveform applied to the gate signal line 17bB is changed in a 4H cycle. This is for ease of drawing. It is not limited to 2H, 3H, etc. At least the gate signal line 16bR connected to the pixel 16R, the gate signal line 16bG connected to the pixel 16G, and the gate signal line 16bB connected to the pixel 16B are applied to one or more gate signal lines 17b. Among the signal waveforms to be applied, the application time of the signal for turning on (or turning off) the TFT 11d is different from that of the other gate signal line 17b.
[0543]
When driven as shown in FIG. 99, the light emission positions of the EL elements 15R, 15G, and 15B move from the top to the bottom of the display screen 21 at high speed. At this time, the ON (lighting) time of the EL element 15R, the ON (lighting) time of the EL element 15G, and the ON (lighting) time of the EL element 15B can be made different, so that the color balance of the screen can be adjusted. In addition, the occurrence of flicker is less noticeable. Such color balance adjustment is preferably configured so that the user can adjust the color balance while viewing the display screen 21. This adjustment is easy because the ON number of ST data input to the shift register 22 shown in FIG. 21 may be increased or decreased. The on / off control, the insertion ratio of the non-display area 312 and the number of the fertilizer temple areas 312 can be easily realized by controlling the ST data to the shift register 22 described with reference to FIG. Of course, it goes without saying that the signal (Vgh, Vgl) data applied to the gate signal line 17b may be controlled in parallel.
[0544]
95 to 99 have been described by exemplifying the pixel configuration of FIG. However, it goes without saying that the above embodiments can be applied to other pixel configurations. For example, FIG. 19, FIG. 20, FIG. 86, FIG. That is, the technical idea described in FIGS. 95 to 99 can be applied to other configurations.
[0545]
The driving method described in FIG. 46, FIG. 45, FIG. 93, and the like is a method of selecting a plurality of pixel rows at the same time. This drive method requires attention in the following points. In conclusion, it is preferable to provide (form) pixels (rows) (dummy pixels (rows)) that do not contribute to display. The reason for this will be described below.
[0546]
FIG. 100 is an explanatory diagram of a driving method for selecting two pixel rows at the same time. In FIG. 100, a state where the pixels 16a and 16b are selected is illustrated. The TFT 11a of the pixel 16a and the TFT 11a of the pixel 16b pass a current Idd to the source signal line 18, respectively.
[0547]
Here, for ease of explanation, it is assumed that there is no variation in the current flowing through the TFT 11a of each pixel, and 2 × Idd = Iw. That is, the source driver 14 absorbs the current Iw from the source signal line 18 and a current obtained by dividing the current Iw into two equal parts is programmed in the capacitor 19 of each pixel. For example, if Idd = 15 nA, Iw = 30 nA.
[0548]
As shown in FIG. 1A, two write pixel rows 871 (871a and 871b) are selected and sequentially selected from the upper side to the lower side of the display screen 21. However, as shown in FIG. 1B, when the pixel reaches the lower side of the screen, the writing pixel row 871a exists, but the 871b disappears. That is, only one pixel row is selected. Therefore, all the current Iw applied to the source signal line 18 is written to the write pixel row 871a. Therefore, Iw = Idd, and twice the current is programmed in the pixel as compared with the write pixel row 871a in FIG.
[0549]
To deal with this problem, the present invention forms (places) a dummy pixel row 2471 on the lower side of the display screen 21 as shown in FIG. When selected, the last pixel row and the dummy pixel row 2471 on the display screen 21 are selected. Therefore, a prescribed current of Idd = Iw / 2 is written in the write pixel row of FIG.
[0550]
FIG. 101 shows the state of FIG. As is clear from FIG. 101, when the selected pixel rows are selected up to the pixel 16b row on the lower side of the display screen 21, the last pixel row and the dummy pixel row 2471 on the display screen 21 are selected. Further, as illustrated in FIG. 102, a dummy pixel row 2471 is formed (arranged) outside the display screen 21. That is, the dummy pixel row 2471 is configured not to be lit, not to be lit, or not to be displayed as a display even when lit.
[0551]
101 and 102, even if the dummy pixel row 2471 is formed (arranged), the lighting control line 1791 is shared by the gate signal line 17b and the like as described in FIG. Can be implemented. It can also be combined with reverse bias driving (see FIG. 103).
[0552]
In FIG. 1, the dummy pixel row 2471 is provided on the lower side of the display screen 21. However, the present invention is not limited to this. For example, as shown in FIG. 104A, when scanning from the lower side to the upper side of the screen (upside down scanning), dummy pixels are also formed on the upper side of the display screen 21 as shown in FIG. Row 2471 should be formed. That is, the dummy pixel row 2471 is formed (arranged) on each of the upper side and the lower side of the screen 21 (see FIG. 105). With the configuration described above, it is possible to cope with upside down scanning of the screen.
[0553]
In the above embodiment, two pixel rows are selected simultaneously. The present invention is not limited to this. For example, a method of simultaneously selecting five pixel rows may be used.
[0554]
FIG. 106 is an explanatory diagram of a driving method for simultaneously selecting five pixel rows. As shown in FIG. 106, dummy pixel rows 2471 for four pixels are formed on the upper and lower sides of the screen.
[0555]
FIG. 107 is an explanatory diagram of a method for driving the display panel of FIG. In the following description, it is assumed that a current of Iw = 5 × Idd is output (or absorbed) from the source driver 14. The current Idd is a current written into each pixel (programmed current), and it goes without saying that the current Idd varies depending on the display image.
[0556]
In the driving method of simultaneously selecting five pixel rows, the source driver 14 outputs a current that is five times the current Idd that is written to the pixels. In FIG. 107A, only the top pixel on the display screen 21 is selected. However, since Iw = 5 × Idd in this state, a current five times the predetermined value is written in the write pixel row 871.
[0557]
To deal with this problem, in the present invention, as shown in FIG. 107A, dummy pixel rows 2471a for four pixels are simultaneously selected. That is, four dummy pixel rows 2471a and one display region write pixel row 871 are simultaneously selected. Therefore, since Iw = 5 × Idd, a predetermined current Idd is programmed in the write pixel row 871 selected in FIG.
[0558]
In FIG. 107 (b), two write pixel rows 871 on the display screen 21 are selected, and one dummy pixel row 2471a is selected instead of three. Therefore, the total number of selected pixel rows is 5. Therefore, since Iw = 5 × Idd, a predetermined current Idd is programmed in the two write pixel rows 871 selected in FIG.
[0559]
Similarly, in FIG. 107C, three write pixel rows 871 on the display screen 21 are selected, and two dummy pixel rows 2471a are not selected but two are selected. Therefore, the total number of selected pixel rows is 5. Therefore, since Iw = 5 × Idd, a predetermined current Idd is programmed in the two write pixel rows 871 selected in FIG. 107 (c).
[0560]
Similarly, in FIG. 107D, four write pixel rows 871 on the display screen 21 are selected, and three dummy pixel rows 2471a are not selected but one is selected. In FIG. 107 (e), five write pixel rows 871 on the display screen 21 are selected, and the dummy pixel row 2471a is not selected. Hereinafter, five pixel rows are sequentially selected (FIGS. 107 (f), (g), and (h)). When the lower side of the display screen 21 is reached, the number of selected dummy pixel rows 2471b increases every 1H.
[0561]
By driving in this way, even when the number of pixel rows to be selected at the same time increases, when selecting the upper side or the lower side of the display screen 21, the pixel rows including the dummy pixel row 2471 can be set to a constant value. For this reason, the current value output from the source driver 14 can be fixed to the simultaneously selected pixel row times of the image data. Therefore, the configuration of the source driver 14 is facilitated, and each pixel has a target predetermined current (voltage). Is written.
[0562]
As described above, in the driving method in which five pixel rows are simultaneously selected, 5-1 = 4 dummy pixel rows may be formed on one side of the screen. That is, it is only necessary to form or arrange dummy pixel rows that are simultaneously selected (number of pixel rows −1) or more.
[0563]
In the above embodiments, two pixel rows are simultaneously selected and five pixel rows are simultaneously selected. However, the present invention is not limited to this. The above pixel rows may be selected simultaneously. Further, although it has been described that adjacent pixel rows are simultaneously selected, the present invention is not limited to this. For example, it may be selected every other pixel row or randomly.
[0564]
In the above embodiment, when selecting a plurality of pixel rows, the dummy pixel row 2471 is selected at the first or last part of the scanning of the display screen 21, and the current Iw flowing through the source driver 14 is set to a constant value. However, the present invention forms or arranges dummy pixel rows, and is not limited to setting the current flowing through the source driver 14 to a constant value.
[0565]
FIG. 108 shows a driving method in which the dummy pixel row 2471a is turned on during a period when the writing pixel row 871a is not selected. The writing pixel row 871a is one pixel row, but the present invention is not limited to this, and it goes without saying that it may be a plurality of pixel rows as shown in FIG. As a case where such driving is performed, a case where the gate driver 12 is directly formed on the array substrate 49 (a gate driver built-in configuration) is exemplified.
[0566]
In the gate driver built-in configuration, it is difficult to form a complicated circuit from the viewpoint of yield or formation area. Therefore, although the gate driver 12 is formed with a circuit configuration simplified as much as possible, there are cases where the operation is restricted.
[0567]
For example, even if data (ST) is input to the shift register 22 of the gate driver 12, the ON signal Vgl is not output to the gate signal line 17a unless it is after 2 to 3 clocks (the clock is 1H). . However, after the ON data is output to the gate signal line 17a (1), the ON data position is sequentially shifted in synchronization with the 1H clock.
[0568]
As described above, if the gate signal line 17a (1) is not selected after 2 to 3 clocks, no pixel row is selected for 2 to 3 clocks. During this period, the output of the source driver 14 is preferably in the 0 state (no current input / output). However, since the output stage of the source driver 14 is composed of a constant current circuit, it is difficult to make the flowing current completely zero. When a current flows through the source signal line 18 (the source driver 14 absorbs the charge of the source signal line 18), the potential of the source signal line 18 is lowered. When the potential of the source signal line 18 decreases, the potential of the capacitor 19 of each pixel 16 may also decrease. When the potential of the capacitor 19 is lowered, the potential of the gate terminal of the TFT 11a is lowered, so that the TFT 11a is more likely to flow current. This state appears prominently when the screen is in a black display state. This is because black floating occurs when a current flows through the TFT 11a of each pixel.
[0569]
For this problem, when none of the gate signal lines 17 on the display screen 21 is selected (state), the dummy pixel row 2471 is selected and driven so that a current flows through the source signal line. That is, the switching TFT 11 in the dummy pixel row 2471 is turned on, and the impedance of the driving TFT 11a is lowered. Therefore, the current flowing into the source driver 14 is configured to be supplied from the TFT 11a in the dummy pixel row 2471.
[0570]
It is also important that the output stage circuit of the source driver 14 is in a state where the current is off as much as possible when no pixel row on the display screen 21 is selected.
[0571]
In FIG. 108 (a1), it is assumed that a start signal is applied to the shift register 22 built in the gate driver 12. FIG. 108 (a2) is after 1H compared to FIG. 108 (a1). Similarly, FIG. 108 (a3) is further 1H later, and FIG. 108 (a4) is further 1H later. That is, in FIGS. 108 (a1) and (a2), no gate signal line on the display screen 21 is selected during the first 2H period, and the pixel row (1) is selected for the first time in FIG. 108 (a3) after 3H. Thereafter, FIG. 108 (a4) shows a state where the pixel row (2) is selected after being shifted by one pixel row.
[0572]
Thus, in FIG. 108 (a1) and (a2), no pixel row is selected. As a countermeasure, the dummy pixel row 2471a is selected, and the current from the TFT 11a is supplied to the dummy pixel row 2471a so that the potential of the source signal line 18 is not changed.
[0573]
As described above, by supplying a current to the dummy pixel row 2471a, there is no black float and a good image display can be realized. In addition, changes such as white balance on the screen do not occur.
[0574]
In FIG. 108A, the dummy pixel row 2471a closer to the source driver 14 is selected. However, the present invention is not limited to this. For example, as shown in FIG. 108B, a dummy pixel row 2471b far from the source driver 14 may be selected. Further, both the dummy pixel rows 2417a and 2471b may be selected.
[0575]
Further, the driving method in FIG. 108B is the same as that in FIG. In FIG. 108 (b1), a start signal is applied to the shift register 22 built in the gate driver 12, and FIG. 108 (b2) is 1H later than FIG. 108 (b1). Similarly, FIG. 108 (b3) is further 1H later, and FIG. 108 (b4) is further 1H later.
[0576]
Similarly to FIG. 108 (a), FIG. 108 (b) does not select any gate signal line on the display screen 21 in the first 2H period, and the pixel row (1) for the first time in FIG. 108 (b3) after 3H. In FIG. 108 (b4), one pixel row is shifted and pixel row (2) is selected. As shown in FIG. 108B, the potential of the source signal line 18 is more easily stabilized when the dummy pixel row 2471b farther from the source driver 14 is selected. This state is shown in FIG.
[0577]
In the embodiment shown in FIG. 108, only one pixel row is selected. However, the present invention is not limited to this. For example, the present invention can be applied to a driving method for selecting a plurality of pixel rows as shown in FIG. In the driving method for selecting a plurality of pixel rows, if the purpose is to solve the black floating or image quality change problem that occurs when no pixel rows on the display screen 21 are selected, FIG. Thus, it is not necessary to form a plurality of dummy pixel rows 2471. One dummy pixel row 2471 may be provided as illustrated in FIG. This is because the potential of the source signal line 18 and the like can be stabilized with this one dummy pixel row.
[0578]
The dummy pixel rows 2471a and 2471b may change the selected dummy pixel row 2471 depending on the scanning direction of the display screen 21 (for example, FIGS. 1 and 104).
[0579]
In FIG. 108, the dummy pixel row 2471 is selected in a state in which no pixel row on the display screen 21 is selected during a period of one frame (or one field). However, there are cases where no pixel row is selected in one horizontal scanning period in the actual driving state.
[0580]
FIG. 110 is an operation waveform diagram for explaining this state. In the display device of the present invention, pixel rows are selected with a clock of 1H (one horizontal scanning period), and the selected pixel rows are sequentially shifted. However, even in the 1H period, the pixel row is selected in the predetermined period.
[0581]
Basically, the off voltage Vgh is applied to the gate signal line 17b of the selected pixel row for the entire period of 1H. In FIG. 110, when the pixel row number is 1, the off voltage Vgh is applied to the gate signal line 17b of the pixel row (1). Further, when the pixel row number is 2, the off voltage Vgh is applied to the gate signal line 17b of the pixel row (2).
[0582]
On the other hand, the ON voltage Vgl is applied to the gate signal line 17a in a period shorter than 1H. Therefore, when the pixel row number is 1, the pixel row (1) in the period a and the period b is not selected. The reason why the non-selection period is generated as described above is that a punch-through voltage is easily generated when the timing at which the gate signal line 17b changes coincides with the timing at which the gate signal line 17a changes. This is because when the punch-through voltage is generated, a desired voltage (current) is not held in the capacitor 19, and the light emission luminance of the EL element 15 varies.
[0583]
It is preferable to ensure at least the period a shown in FIG. The period b may be 0 in some cases. This may be determined in consideration of the timing at which the EL element 15 is turned on / off. Basically, at least 1/64 of 1H and 1/8 of 1H have elapsed since the timing when the gate signal line 17b changed from the on voltage Vgl to the off voltage Vgh (that is, the non-selected state). Further, it is preferable that the gate signal line 17a is selected after 1/32 time of 1H or more and 1/8 time of 1H or less. Alternatively, at least 0.5 μsec to 20 μsec has elapsed from the timing at which the gate signal line 17 b has changed from the on voltage Vgl to the off voltage Vgh (that is, the non-selected state), and further, 1 μsec to 10 μsec has elapsed. Therefore, it is preferable to select the gate signal line 17a. Further, it is more preferable that the precharge (discharge) voltage described with reference to FIG. 163 or the like is applied during the period a or b.
[0584]
During the period when the gate signal line 17a is selected, the switching signal CSW shown in FIG. 110 is at the off voltage Vgh. The output stage of the source driver 14 is controlled to be turned off by the on voltage Vgl of the switching signal CSW. Further, the dummy pixel row 2471 described with reference to FIG. 108 is controlled by the ON voltage Vgl of the switching signal CSW. By configuring or operating as described above, it is possible to realize a good image display without black floating. Further, it is possible to prevent a change in the white balance of the screen from occurring.
[0585]
In FIG. 109, the dummy pixel row 2471 is illustrated as forming the EL element 15 and the TFT 11d, but basically the dummy pixel row 2471 supplies a current to be supplied to the source signal line 18 (depending on the pixel configuration). Therefore, the EL element 15 is not necessary. On the contrary, if the EL element 15 or the like is formed, the EL element 15 is lit and causes a problem.
[0586]
In the present invention, the EL element 15 and the like are not formed in the dummy pixel row 2471 as shown in FIG. The penetration voltage generating capacitor 19b may or may not be added. However, when the penetration voltage generating capacitor 19b is formed in the pixel of the display screen 21, it is preferably formed in the dummy pixel row 2471. This is to make the current flowing through the TFT 11a of the dummy pixel row 2471 equal to the current flowing through the TFT 11a of the pixel 16 of the display screen 21.
[0587]
FIG. 111 shows the case of the pixel configuration of FIG. In the pixel configuration of the current mirror in FIG. 19, the driving TFT 11 b and the EL element 15 are deleted in the dummy pixel row 2471 as illustrated in FIG. 112. In the case of the pixel configuration of the voltage program as shown in FIGS. 85 and 87, it is constituted by a switching TFT 11b and a capacitor 19a as shown in FIG. This is because the current is not supplied from the pixel driving TFT to the source signal line 18 in the voltage programming method.
[0588]
Since the dummy pixel row 2471 illustrated in FIGS. 111 and 112 does not need to emit light, no EL film is formed on the pixel electrode 48 of the dummy pixel row 2471 as illustrated in FIG. As shown in FIG. 114, an insulating film 2561 is formed on the pixel electrode 48 to be in an insulating state. Alternatively, as shown in FIG. 115, the pixel electrode 48 of the dummy pixel row 2471 and the cathode reflection film 46 are electrically short-circuited. With this configuration, the potential of the pixel electrode 48 is stabilized.
[0589]
As in FIG. 89, when one image display area 311 moves downward from the top of the screen as shown in FIG. 94, it is visually recognized that the image display area 311 moves when the frame rate is low. . In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.
[0590]
For this problem, the image display area 311 may be divided into a plurality of parts as shown in FIG. In FIG. 116B, the non-display area 312 is divided into three. If the area obtained by adding these three areas has an area of S (N-1) / N, it is equivalent to the brightness of FIG.
[0591]
FIG. 117 shows voltage waveforms applied to the gate signal line 17. The difference between FIG. 93 and FIG. 117 is basically the operation of the gate signal line 17b. The gate signal lines 17b are turned on / off (Vgl and Vgh) corresponding to the number of divided screens. The other points are almost the same as those in FIG.
[0592]
As shown in FIG. 116 (b), the scanning direction of the non-display area 312 is not limited to the top to bottom direction, but may be scanned from the bottom to the top direction of the screen. Further, the scanning direction from the top to the bottom and the scanning direction from the bottom to the top may be alternately or randomly scanned. Needless to say, the number of divisions may be changed for each frame or at a predetermined position on the display screen 21.
[0593]
As described above, dividing the image display area 311 into a plurality reduces screen flicker, and flicker does not occur, and a good image display can be realized. Note that the division may be made finer, and flicker is reduced as the division is performed. In particular, since the responsiveness of the EL element 15 is fast, even if it is turned on / off in a time shorter than 5 μsec, the display luminance does not decrease.
[0594]
In the driving method of the present invention, since the on / off of the EL element 15 can be controlled by the on / off of the signal applied to the gate signal line 17b, the clock frequency can be controlled at a low frequency on the order of KHz. Further, when realizing black screen insertion (non-display area 312 insertion), an image memory or the like is not required. Therefore, the drive circuit or method of the present invention can be realized at low cost.
[0595]
FIG. 118 shows a case where two pixel rows are selected simultaneously. According to the examination result, in the display panel formed by the low-temperature polysilicon technology, the method of selecting two pixel rows at the same time has practical display uniformity. This is presumed to be because the characteristics of the conversion TFTs 11a of adjacent pixels are very consistent. Further, when the laser annealing was performed, a good result was obtained by irradiating the striped laser in parallel with the source signal line 18.
[0596]
In FIG. 118, when the writing pixel row is the (1) pixel row, (1) and (2) are selected for the gate signal line 17a (see FIG. 119). At this time, the driving TFT 11b and the capturing TFT 11c in the pixel rows (1) and (2) are in the on state. Further, since the gate signal line 17b is in an opposite phase to the gate signal line 17a, at least the switching TFTs 11d in the pixel rows (1) and (2) are in an off state, and the EL elements 15 in the corresponding pixel rows No current is flowing. That is, the non-display area 312 is formed. In FIG. 118, the image display area 311 is divided into five parts in order to reduce the occurrence of flicker.
[0597]
Ideally, each of the conversion TFTs 11a of two pixels (rows) passes a current of Id × 5 (when N = 10) to the source signal line 18, and the capacitor 19 of each pixel 16 has a current five times larger. Will be programmed.
[0598]
Since two pixel rows (K = 2) are selected at the same time, the two conversion TFTs 11a operate. That is, a current of 10/2 = 5 times per pixel flows to the conversion TFT 11a, and a current obtained by adding the program currents of the two conversion TFTs 11a flows to the source signal line 18.
[0599]
For example, a current to be originally written is Id in the write pixel row 871a, and a current of Id × 10 is supplied to the source signal line 18. There is no problem in the writing pixel row 871b because normal image data is written later. Since the writing pixel row 871b is displayed in the same manner as the writing pixel row 871a during the 1H period, at least the writing pixel row 871a and the writing pixel row 871b selected for increasing the current are set as the non-display area 312. .
[0600]
After the next 1H, the gate signal line 17a (1) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (1). At the same time, the gate signal line 17 a (3) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the conversion TFT 11 a of the selected pixel row (3) toward the source driver 14. By operating in this way, regular image data is held in the pixel row (1).
[0601]
After the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (2). At the same time, the gate signal line 17 a (4) is selected (Vgl voltage), and a program current flows from the conversion TFT 11 a of the selected pixel row (4) to the source signal line 18 toward the source driver 14. By operating in this way, regular image data is held in the pixel row (2). One screen is rewritten by performing the above operation and scanning while shifting one pixel row at a time.
[0602]
Similar to FIG. 62, in the driving method of FIG. 120, since each pixel is programmed with a current (voltage) five times that of the pixel, the light emission luminance of the EL element 15 of each pixel is ideally five times. . Therefore, the brightness of the image display area 311 is five times higher than the predetermined value. In order to obtain a predetermined luminance, as shown in FIG. 45, the non-display area 312 may be set to include a writing pixel row 871 and a range of 1/5 of the display screen 21. This has been described with reference to FIG.
[0603]
In the driving method of selecting a plurality of pixel rows at the same time, it becomes difficult to absorb the characteristic variation of the conversion TFT 11a as the number of pixel rows to be selected simultaneously increases. However, when the number of selected lines decreases, the current programmed to one pixel increases, and a large current flows through the EL element 15. When the current flowing through the EL element 15 is large, the EL element 15 tends to deteriorate.
[0604]
FIG. 121 solves this problem. In the basic concept of FIG. 121, as described with reference to FIG. 46 at 1 / 2H (1/2 of the horizontal scanning period), a plurality of pixel rows are simultaneously selected, and then 1 / 2H (1/2 of the horizontal scanning period). ) Is a combination of methods for selecting one pixel row as described in FIG. By combining in this way, it is possible to absorb the variation in characteristics of the conversion TFT 11a, and to improve the in-plane uniformity at a higher speed.
[0605]
In FIG. 121, for ease of explanation, it is assumed that five pixel rows are simultaneously selected in the first period and one pixel row is selected in the second period.
[0606]
First, in the first period, five pixel rows are selected simultaneously as shown in FIG. 121 (a1). This operation has been described with reference to FIG. The current passed through the source signal line is 25 times the predetermined value. Therefore, a current that is five times greater is programmed in the conversion TFT 11a of each pixel 16. Since the current is 25 times, the parasitic capacitance 404 is charged and discharged in a very short time. Therefore, the potential of the source signal line becomes the target potential in a short time, and the terminal voltage of the capacitor 19 of each pixel 16 is programmed to flow five times as much current. The application time of this 25 times current is set to 1 / 2H (1/2 of one horizontal scanning period).
[0607]
As a matter of course, since the same image data is written in the five pixel rows of the writing pixel row 871, the TFT 11 is turned off so as not to be displayed. Therefore, the display state is as shown in FIG. 121 (a2).
[0608]
In the next 1 / 2H period, one pixel row is selected and current (voltage) programming is performed. This state is illustrated in FIG. 121 (b1). The write pixel row 871a is programmed with a current (voltage) so as to pass five times as much current as before. 121 (a1) and 121 (b1), the current flowing through each pixel is the same because the change in the terminal voltage of the programmed capacitor 19 is reduced, and the target current is made faster. This is so that it can flow.
[0609]
That is, in FIG. 121 (a1), a current is passed through a plurality of pixels, and is brought close to a value at which a rough current flows. In this first stage, since programming is performed by a plurality of conversion TFTs 11a, an error due to TFT variation occurs with respect to the target value. In the next second stage, data is written and held. Only a pixel row is selected, and a complete program is executed from a rough target value to a predetermined target value.
[0610]
The non-display area 312 is scanned from the top to the bottom of the screen, and the writing pixel row 871a is scanned from the top to the bottom of the screen, as in the embodiments of FIGS. 45, 46, and 84. Since there is, explanation is omitted.
[0611]
FIG. 122 shows drive waveforms for realizing the drive method of FIG. As can be seen from FIG. 121, 1H (one horizontal scanning period) is composed of two phases and is switched by the ISEL signal. The ISEL signal is illustrated in FIG.
[0612]
First, the ISEL signal will be described. In FIG. 123, the current output circuit 1222 includes two parts 1222a and 1222b. Each current output circuit 1222 includes a DA circuit 1226 for DA-converting 8-bit gradation data, an operational amplifier 1224, and the like. Since the circuit operation of the current output circuit 1222 has been described above, a description thereof will be omitted. In the embodiment of FIG. 121, the current output circuit 1222a is configured to output 25 times the current. On the other hand, the current output circuit 1222b is configured to output five times the current. The outputs of the current output circuits 1222a and 1222b are applied to the source signal line 18 by the switch circuit 1223 being controlled by the ISEL signal.
[0613]
When the ISEL signal is at the L level, the current output circuit 1222a that outputs a 25-fold current is selected, and the source driver 14 absorbs the current from the source signal line 18. When it is at the H level, the current output circuit 1222b that outputs a 5-fold current is selected, and the source driver 14 absorbs the current from the source signal line 18. In this way, since it is only necessary to change the value of the resistor 1228, it is easy to change the magnitude of the current, such as 25 times or 5 times. Further, the resistor 1228 can be easily changed by using a volume, or by connecting and selecting a plurality of resistors and analog switches.
[0614]
As shown in FIG. 122, when the pixel row to be written is the (1) pixel row (see the column of pixel row number 1 in FIG. 122), the gate signal line 17a is (1), (2), (3). , (4), (5) are selected. That is, the driving TFT 11b and the capturing TFT 11c in the pixel rows (1), (2), (3), (4), and (5) are in the on state. Further, since ISEL is at the L level, the current output circuit 1222 a that outputs a 25 times larger current is selected and connected to the source signal line 18. Further, the off voltage Vgh is applied to the gate signal line 17b. Therefore, the switching TFTs 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312.
[0615]
Ideally, the conversion TFTs 11 a of 5 pixels each pass a current of Id × 2 to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with 5 times the current. Here, in order to facilitate understanding, description will be made on the assumption that the characteristics (Vt, S value) of the conversion TFTs 11a are the same.
[0616]
Since five pixel rows (K = 5) are selected at the same time, the five conversion TFTs 11a operate. That is, a current of 25/5 = 5 times flows to the conversion TFT 11a per pixel. A current obtained by adding the program currents of the five conversion TFTs 11a flows through the source signal line 18. For example, a current to be originally written is Id in the write pixel row 871a, and a current of Id × 25 is passed through the source signal line 18. A write pixel row 871b for writing image data after the write pixel row (1) is a pixel row used auxiliary to increase the amount of current to the source signal line 18. However, there is no problem in the writing pixel row 871b because normal image data is written later.
[0617]
Therefore, the writing pixel row 871b has the same display as the writing pixel row 871a during the 1H period. Therefore, the writing pixel row 871a and the writing pixel row 871b selected for increasing the current are set as at least the non-display area 312.
[0618]
In the next 1 / 2H (1/2 of the horizontal scanning period), only the writing pixel row 871a, that is, (1) only the pixel row is selected. As apparent from FIG. 122, the ON voltage Vgl is applied only to the gate signal line 17a (1), and the OFF voltage Vgh is applied to the gate signal lines 17a (2), (3), (4), and (5). Applied. Therefore, the conversion TFT 11a in the pixel row (1) is in an operating state (a state in which a current is supplied to the source signal line 18), but in the pixel rows (2), (3), (4), and (5). The driving TFT 11b and the capturing TFT 11c are in an off state, that is, a non-selected state. In addition, since ISEL is at the H level, the current output circuit 1222b that outputs a 5-fold current is selected, and the current output circuit 1222b and the source signal line 18 are connected. Further, the state of the gate signal line 17b is not changed from the previous state of 1 / 2H, and the off voltage Vgh is applied. Therefore, the switching TFTs 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312.
[0619]
From the above, each of the conversion TFTs 11a in the pixel row (1) passes a current of Id × 5 to the source signal line 18, and the capacitor 19 in each pixel row (1) is programmed with a current that is five times as large. .
[0620]
In the next horizontal scanning period, one pixel row and a writing pixel row are shifted. That is, this time is when the writing pixel row is (2). In the first 1 / 2H period, as shown in FIG. 122, when the writing pixel row is the (2) pixel row, the gate signal line 17a is (2), (3), (4), (5), (6) is selected. That is, the driving TFT 11b and the capturing TFT 11c in the pixel rows (2), (3), (4), (5), and (6) are in the on state. Further, since ISEL is at the L level, the current output circuit 1222 a that outputs a 25 times larger current is selected and connected to the source signal line 18. The off voltage Vgh is applied to the gate signal lines 17b (2), (3), (4), (5), and (6). Therefore, the switching TFTs 11d in the pixel rows (2), (3), (4), (5), and (6) are in an off state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312. On the other hand, since the Vgl voltage is applied to the gate signal line 17b (1) of the pixel row (1), the switching TFT 11d is in the on state, and the EL element 15 of the pixel row (1) is lit.
[0621]
Since five pixel rows (K = 5) are selected at the same time, the five conversion TFTs 11a operate. That is, a current of 25/5 = 5 times flows to the conversion TFT 11a per pixel. A current obtained by adding the program currents of the five conversion TFTs 11a flows through the source signal line 18.
[0622]
In the next 1 / 2H (1/2 of the horizontal scanning period), only the writing pixel row 871a is selected. That is, (2) only the pixel row is selected. As apparent from FIG. 122, the ON voltage Vgl is applied only to the gate signal line 17a (2), and the OFF voltage Vgh is applied to the gate signal lines 17a (3), (4), (5), and (6). Applied. Accordingly, the conversion TFTs 11a in the pixel rows (1) and (2) are in an operating state (the pixel row (1) supplies a current to the EL element 15, and the pixel row (2) supplies a current to the source signal line 18. The driving TFT 11b and the capturing TFT 11c in the pixel rows (3), (4), (5), and (6) are in an off state, that is, a non-selection state. In addition, since ISEL is at the H level, the current output circuit 1222b that outputs a 5-fold current is selected, and the current output circuit 1222b and the source signal line 18 are connected. Further, the state of the gate signal line 17b is not changed from the previous state of 1 / 2H, and the off voltage Vgh is applied. Therefore, the switching TFTs 11d in the pixel rows (2), (3), (4), (5), and (6) are in an off state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312.
[0623]
From the above, the conversion TFTs 11 a in the pixel row (2) flow Id × 5 current to the source signal line 18. Then, the capacitor 19 in each pixel row (2) is programmed with 5 times the current. One screen can be displayed by sequentially performing the above operations.
[0624]
In the driving method described with reference to FIG. 121, a G pixel row (G is 2 or more) is selected in the first period, and programming is performed such that N times the current flows in each pixel row. In the second period after the first period, a B pixel row (B is smaller than G and 1 or more) is selected, and the pixel is programmed to flow N times as much current.
[0625]
However, there are other strategies. In the first period, G pixel rows (G is 2 or more) are selected and programmed so that the total current of each pixel row is N times the current. In the second period after the first period, a B pixel row (B is smaller than G and is 1 or more) is selected, and the total current of the selected pixel rows (however, when the selected pixel row is 1, In this method, the current of one pixel row is programmed to be N times. For example, in FIG. 121 (a1), when five pixel rows are simultaneously selected and a current twice as large as flowing through the conversion TFT 11a of each pixel, a current of 5 × 2 times = 10 times flows through the source signal line 18. In the next second period, one pixel row is selected in FIG. 121 (b1), and a 10-fold current is passed through the conversion TFT 11a of this one pixel.
[0626]
With this method, a plurality of current output circuits 1222 are not necessary as shown in FIG. 123, and the source driver 14 can be configured with one current output circuit 1222 for each source signal line. In other words, in this method, the output current of the source driver 14 through which the current of the source signal line 18 flows is a constant value (of course, this constant value varies depending on the image data. In this case, the number of selected pixels is increased during the 1H period. Regardless, it means constant.) Therefore, the configuration of the source driver 14 becomes easy.
[0627]
In FIG. 121, the period for simultaneously selecting a plurality of pixel rows is set to 1 / 2H, and the period for selecting one pixel row is set to 1 / 2H. However, the present invention is not limited to this. For example, the period for selecting a plurality of pixel rows at the same time may be set to 1 / 4H, and the period for selecting one pixel row may be set to 3 / 4H. In addition, although a period in which a period for selecting a plurality of pixel rows at the same time and a period for selecting one pixel row are set to 1H, the present invention is not limited to this. For example, it may be a 2H period or a 1.5H period.
[0628]
In FIG. 121, the period in which five pixel rows are simultaneously selected may be 1 / 2H, and two pixel rows may be simultaneously selected in the next second period. Even in this case, it is possible to realize an image display that is practically satisfactory.
[0629]
In FIG. 121, the first period for selecting five pixel rows at the same time is ½H, and the second period for selecting one pixel row is ½H. However, the present invention is not limited to this. is not. For example, the first stage may select three pixel rows at the same time, the second period may select three pixel rows among the five pixel rows, and finally select one pixel row. . That is, the image data may be written in the pixel row at a plurality of stages.
[0630]
In FIG. 123, each source signal line 18 is provided with two current output circuits 1222. This is the first embodiment of FIG. 121, in order to output 25 times the current in the first period. This is because a five times larger current is output in the second period. In order to realize this with one current output circuit 1222, the circuit configuration of FIG. The DA circuit 1226 performs digital-analog conversion with the reference voltage (Iref) as a maximum value. For example, if the Iref voltage is 5V, a value obtained by dividing 5V into 256 is analog output as the minimum value. That is, the maximum value of the analog output is an analog value of 5V-1 bits, the minimum value is 0V, and the minimum resolution is 5V / 256 (when the input is an 8-bit specification). If the Iref voltage is 2.5V, a value obtained by dividing 2.5V into 256 is analog output as a minimum value. That is, the maximum value of the analog output is an analog value of 2.5V-1 bit, the minimum value is 0V, and the minimum resolution is 2.5V / 256 (when the input is an 8-bit specification).
[0631]
That is, the output current value can be changed by one current output circuit 1222 by dynamically switching the Iref voltage. FIG. 120 is an implementation circuit thereof.
[0632]
In FIG. 120, a resistor RI for dividing the Vi voltage into four is provided. This divided voltage is input to the switch circuit 1223, and one voltage is selected to become the Iref voltage. This Iref voltage is input to the operational amplifier 1224. Therefore, by switching the Iref voltage during the first half of the period and the Iref voltage during the second half of the period by the current output circuit 1222 connected to all the source signal lines 18, the output current magnification can be increased. Can be changed. Of course, as illustrated in FIG. 124, the Iref voltage may be generated by selecting a plurality of operational amplifiers 1224.
[0633]
Also in the case of FIG. 123, the image display area 311 may be one as shown in FIG. In addition, as illustrated in FIG. 126, the image display area 311 may be divided.
[0634]
As shown in FIG. 127, when the writing pixel row is the (1) pixel row, (1), (2), (3), (4), and (5) are selected for the gate signal line 17a. Yes. That is, the driving TFT 11b and the capturing TFT 11c in the pixel rows (1), (2), (3), (4), and (5) are in the on state. Further, since ISEL is at the L level, the current output circuit 1222 a that outputs a 25 times larger current is selected and connected to the source signal line 18. The off voltage Vgh is applied to the gate signal lines 17b (1), (2), (3), (4), and (5). Therefore, the switching TFTs 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312.
[0635]
Since five pixel rows (K = 5) are selected at the same time, the five conversion TFTs 11a operate. That is, a current of 25/5 = 5 times flows to the conversion TFT 11a per pixel. A current obtained by adding the program currents of the five conversion TFTs 11a flows through the source signal line 18. For example, a current to be originally written is Id in the write pixel row 871a, and a current of Id × 25 is passed through the source signal line 18. The write pixel row 871b for writing image data after the write pixel row (1) is a pixel row used as an auxiliary to increase the amount of current to the source signal line 18, but the write pixel row 871b is a regular image later. There is no problem because the data is written.
[0636]
Therefore, the writing pixel row 871b has the same display as the writing pixel row 871a during the 1H period. Therefore, the writing pixel row 871a and the writing pixel row 871b selected for increasing the current are set as at least the non-display area 312.
[0637]
In the next 1 / 2H (1/2 of the horizontal scanning period), only the writing pixel row 871a is selected. That is, (1) only the pixel row is selected. The on voltage Vgl is applied only to the gate signal line 17a (1), and the off voltage Vgh is applied to the gate signal lines 17a (2), (3), (4), and (5). Therefore, the conversion TFT 11a in the pixel row (1) is in an operating state (a state in which a current is supplied to the source signal line 18), but in the pixel rows (2), (3), (4), and (5). The driving TFT 11b and the capturing TFT 11c are in an off state, that is, a non-selected state. In addition, since ISEL is at the H level, the current output circuit 1222b that outputs a 5-fold current is selected, and the current output circuit 1222b and the source signal line 18 are connected. Further, the state of the gate signal line 17b is not changed from the previous state of 1 / 2H, and the off voltage Vgh is applied. Therefore, the switching TFTs 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312.
[0638]
From the above, each of the conversion TFTs 11a in the pixel row (1) passes a current of Id × 5 to the source signal line 18, and the capacitor 19 in each pixel row (1) is programmed with a current that is five times as large. .
[0639]
In the next horizontal scanning period, one pixel row and a writing pixel row are shifted. That is, this time is when the writing pixel row is (2). In the first 1 / 2H period, (2), (3), (4), (5), and (6) are selected for the gate signal line 17a. That is, the driving TFT 11b and the capturing TFT 11c in the pixel rows (2), (3), (4), (5), and (6) are in the on state. Further, since ISEL is at the L level, the current output circuit 1222 a that outputs a 25 times larger current is selected and connected to the source signal line 18. Also,
The off voltage Vgh is applied to the gate signal lines 17b (2), (3), (4), (5), and (6). Therefore, the switching TFTs 11d in the pixel rows (2), (3), (4), (5), and (6) are in an off state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312. On the other hand, since the Vgl voltage is applied to the gate signal line 17b (1) of the pixel row (1), the switching TFT 11d is in the on state, and the EL element 15 of the pixel row (1) is lit.
[0640]
Since five pixel rows (K = 5) are selected at the same time, the five conversion TFTs 11a operate. That is, a current of 25/5 = 5 times flows to the conversion TFT 11a per pixel, and a current obtained by adding the program currents of the five conversion TFTs 11a flows to the source signal line 18.
[0641]
In the next 1 / 2H (1/2 of the horizontal scanning period), only the writing pixel row 871a is selected. That is, (2) only the pixel row is selected. The on voltage Vgl is applied only to the gate signal line 17a (2), and the off voltage Vgh is applied to the gate signal lines 17a (3), (4), (5), and (6). Accordingly, the conversion TFTs 11a in the pixel rows (1) and (2) are in an operating state (the pixel row (1) supplies a current to the EL element 15, and the pixel row (2) supplies a current to the source signal line 18. The driving TFT 11b and the capturing TFT 11c in the pixel rows (3), (4), (5), and (6) are in an off state, that is, a non-selection state. Further, since ISEL is at the H level, the current output circuit 1222b that outputs a five times current is selected, and the current output circuit 1222b and the source signal line 18 are connected. Further, the state of the gate signal line 17b is not changed from the previous state of 1 / 2H, and the off voltage Vgh is applied. Therefore, the switching TFTs 11d in the pixel rows (2), (3), (4), (5), and (6) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312.
[0642]
From the above, each of the conversion TFTs 11a in the pixel row (2) passes a current of Id × 5 to the source signal line 18, and the capacitor 19 in each pixel row (2) is programmed with a current that is five times larger. . One screen can be displayed by sequentially performing the above operations.
[0643]
As is apparent from the above description, the above operation is the same as that in FIG. The difference is the operation of the gate signal line 17b, and the gate signal line 17b operates on and off (Vgl and Vgh) by the number corresponding to the number of divided screens.
[0644]
Note that as shown in FIG. 126, the scanning direction of the non-display area 312 is not limited to the top to bottom direction. You may scan from the bottom of the screen upward. Further, the scanning direction from the top to the bottom and the scanning direction from the bottom to the top may be alternately or randomly scanned. Needless to say, the number of divisions may be changed for each frame or at a predetermined position on the display screen 21.
[0645]
As described above, screen flickering is reduced by dividing the image display area 311 into a plurality of parts. Therefore, no flicker occurs and a good image display can be realized. Note that the division may be finer, and flicker is reduced as the division is performed. In particular, since the responsiveness of the EL element 15 is fast, even if it is turned on / off in a time shorter than 5 μsec, the display luminance does not decrease.
[0646]
The embodiment of FIG. 127 also selects G pixel rows (G is 2 or more) in the first period, and is programmed to pass N times the current in each pixel row, and the second after the first period. In the period, a B pixel row (B is smaller than G and 1 or more) is selected, and the pixel is programmed to flow N times as much current. However, there are other measures as in FIG. In other words, G pixel rows (G is 2 or more) are selected in the first period, and the total current of each pixel row is programmed to be N times the current. In the second period after the first period, a B pixel row (B is smaller than G and is 1 or more) is selected, and the total current of the selected pixel rows (however, when the selected pixel row is 1, In this method, the current of one pixel row is programmed to be N times.
[0647]
The above embodiment is a method for displaying an image by sequential scanning. That is, in terms of television signals, non-interlaced driving (progressive driving) is used. The present invention is also effective for interlaced driving. FIG. 128 is an explanatory diagram of interlaced driving.
[0648]
Note that interlaced driving is usually 1 frame in 2 fields. FIG. 128 is also described as one frame (one screen) with two fields. However, this is the case of NTSC television signals, and it is not always necessary to observe the principle of 2 fields = 1 frame when displaying images on a mobile phone or the like.
[0649]
For example, four fields may be used as one frame. The first field writes 4Y-3 (Y is an integer greater than or equal to 0) pixel row, and the second field writes 4Y-2 (Y is an integer greater than or equal to 0) pixel row. In the third field, 4Y-1 (Y is an integer of 0 or more) pixel row is written, and in the fourth field, 4Y (Y is an integer of 0 or more) pixel row is written. In other words, interlaced driving is a method of configuring one frame (one screen) with a plurality of fields.
[0650]
FIG. 128A shows the first field, in which even-numbered pixel rows are written. FIG. 128B shows the second field, in which odd-numbered pixel rows are written. FIG. 129 shows drive waveforms for realizing the drive method of FIG. The odd field and the even field are for convenience. In FIG. 128, first, description will be made assuming that an image is written from an odd pixel row.
[0651]
In FIG. 128, the gate signal line 17 a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the conversion TFT 11 a of the selected pixel row toward the source driver 14. Here, for ease of explanation, first, it is assumed that the writing pixel row 871a is the pixel row (1) -th.
[0652]
Further, the program current flowing through the source signal line 18 is N times a predetermined value (in order to facilitate explanation, the explanation will be made assuming that N = 10 as in the previous embodiments. However, the program current is not limited to N = 10. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless white raster display or the like is used.
[0653]
In FIG. 129, when the writing pixel row is the (1) pixel row, the Vgl voltage is applied to the gate signal line 17a (1), and the driving TFT 11b and the capturing TFT 11c are turned on. The Vgh voltage is applied to the gate signal line 17b (1). Accordingly, the switching TFT 11d in the pixel row (1) is in an off state, and no current flows through the EL element 15 in the corresponding pixel row, so that the non-display area 312 is formed.
[0654]
In the next 1H, the writing pixel row is the (3) pixel row. A Vgl voltage is applied to the gate signal line 17a (3), and the driving TFT 11b and the capturing TFT 11c are turned on. A Vgh voltage is applied to the gate signal line 17b (3). Therefore, the switching TFT 11d in the pixel row (3) is in an off state, and no current flows through the EL element 15 in the corresponding pixel row, so that the non-display region 312 is formed. Further, the Vgl voltage is applied to the gate signal line 17b (1), and the switching TFT 11d is in the on state. Accordingly, the switching TFT 11d in the pixel row (1) is also in the on state, and the EL element 15 in the corresponding pixel row emits light.
[0655]
In the next 1H, the writing pixel row is the (5) pixel row. A Vgl voltage is applied to the gate signal line 17a (5), and the driving TFT 11b and the capturing TFT 11c are in an on state. In addition, the Vgh voltage is applied to the gate signal line 17b (5), the switching TFT 11d in the pixel row (5) is turned off, and no current flows through the EL element 15 in the corresponding pixel row. It becomes a display area 312. Further, the Vgl voltage is applied to the gate signal line 17b (3), and the switching TFT 11d is in the ON state. Therefore, the switching TFT 11d in the pixel row (3) is also in the on state, and the EL element 15 in the corresponding pixel row emits light.
[0656]
As described above, in the first field, odd-numbered pixel rows are sequentially selected and image data is written.
[0657]
In the second field, (2) image data is sequentially written from the pixel row. A Vgl voltage is applied to the gate signal line 17a (2), and the driving TFT 11b and the capturing TFT 11c are turned on. In addition, the Vgh voltage is applied to the gate signal line 17b (2), the switching TFT 11d in the pixel row (2) is turned off, and no current flows through the EL element 15 in the corresponding pixel row. It becomes a display area 312.
[0658]
In the next 1H, the writing pixel row is the (4) pixel row. A Vgl voltage is applied to the gate signal line 17a (4), and the driving TFT 11b and the capturing TFT 11c are turned on. In addition, the Vgh voltage is applied to the gate signal line 17b (4), the switching TFT 11d in the pixel row (4) is turned off, and no current flows through the EL element 15 in the corresponding pixel row, so that It becomes a display area 312. Further, the Vgl voltage is applied to the gate signal line 17b (3), and the switching TFT 11d is in the ON state. Therefore, the switching TFT 11d in the pixel row (3) is also in the on state, and the EL element 15 in the corresponding pixel row emits light.
[0659]
In the next 1H, the writing pixel row is the (6) pixel row. A Vgl voltage is applied to the gate signal line 17a (6), and the driving TFT 11b and the capturing TFT 11c are turned on. Further, the Vgh voltage is applied to the gate signal line 17b (6), the switching TFT 11d in the pixel row (6) is turned off, and no current flows through the EL element 15 in the corresponding pixel row. It becomes a display area 312. Further, the Vgl voltage is applied to the gate signal line 17b (4), and the switching TFT 11d is in the ON state. Therefore, the switching TFT 11d in the pixel row (4) is also in the on state, and the EL element 15 in the corresponding pixel row emits light.
[0660]
As described above, in the second field, even-numbered pixel rows are sequentially selected and image data is written. One image display is completed in the first field and the second field. In the second field, when even-numbered pixel rows are written, all the odd-numbered pixel rows are set as the non-display area 312. In the first field, when writing odd-numbered pixel rows, all even-numbered pixel rows are set as non-display areas 312.
[0661]
However, in the driving method of FIG. 128, when a current 10 times (N = 10) is passed through the source signal line 18 and current programming is performed in the conversion TFT 11a, odd pixel rows or even pixel rows are displayed alternately. Even if implemented, the display luminance is 10/2 = 5 times the predetermined luminance. Therefore, in order to increase the display luminance by 1, it is necessary to drive at N = 2. However, when driving with N = 2, the current value written to the source signal line 18 is small and the parasitic capacitance 404 cannot be charged / discharged sufficiently, so that insufficient writing occurs in the capacitor 19 and the resolution is lowered.
[0662]
In order to solve this, as shown in FIG. 130, not only the odd-numbered pixel row or even-numbered pixel row but also a part of the display screen 21 may be set as the non-display area 312a. In FIG. 130, scanning is performed in the order of FIG. 130 (a) → FIG. 130 (b) → FIG. 130 (c) → FIG. 130 (a). As can be seen from FIG. 130B, a display area is formed in a predetermined range above the writing pixel row 871a (when scanning from the top to the bottom of the screen). However, since the display area is an odd-numbered pixel row or an even-numbered pixel row, the display area is provided for each pixel row. The non-display area 312a is a continuous non-display area.
[0663]
However, if the display area is partially fixed on the display screen and scanned as in the driving method of FIG. 130, flicker is likely to occur. However, it should be noted that when the frame rate is 80 Hz or higher, flicker does not occur even in the display state of FIG. 130 (when one image display area 311 is used). That is, if the frame rate is 80 Hz or higher, it is not necessary to divide the image display area 311.
[0664]
When the frame rate is low, it may be divided as shown in FIG. Since this has been described earlier, FIG. 131 will not require an explanation. However, in FIG. 131, in order to facilitate drawing, as a divided area, the non-display area 312b and the image display area 311 are paired. However, the present invention is not limited to this, and a plurality of non-display areas are displayed in the divided area. There is no problem even if the area 312b and the plurality of image display areas 311 exist.
[0665]
A wide variety of configurations are possible for the drive system. In FIG. 132, when the writing pixel row is the (1) pixel row, (1) and (G) are selected for the gate signal line 17a. That is, the driving TFT 11b and the capturing TFT 11c in the pixel rows (1) and (G) are on. A Vgh voltage is applied to the gate signal line 17b. Accordingly, at least the switching TFTs 11d in the pixel rows (1) and (G) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows, so that the non-display area 312 is formed.
[0666]
Since two pixel rows (K = 2) are selected at the same time, the two conversion TFTs 11a operate. That is, a current of 10/2 = 5 times per pixel flows through the conversion TFT 11a. A current obtained by adding the program currents of the two conversion TFTs 11 a flows through the source signal line 18.
[0667]
After the next 1H, the gate signal line 17a (G) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (G). At the same time, the gate signal line 17a (2) is selected (Vgl voltage), and a program current flows from the conversion TFT 11a of the selected pixel row (2) to the source signal line 18 toward the source driver 14. By operating in this way, regular image data is held in the pixel row (G).
[0668]
After the next 1H, the gate signal line 17a (1) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (1). At the same time, the gate signal line 17 a (3) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the conversion TFT 11 a of the selected pixel row (3) toward the source driver 14. By operating in this way, regular image data is held in the pixel row (1). One screen is rewritten by performing the above operation and scanning while shifting one pixel row at a time.
[0669]
If flicker is likely to occur, the non-display area 312 or the image display area 311 may be divided into a plurality of parts as shown in FIG. Since this has been explained earlier, FIG. 133 will not require explanation.
[0670]
134 and 135 show pseudo interlace driving. In the pseudo-interlace drive, in the first F (first field), two pixels (a plurality of pixels) of an odd pixel row and an even pixel row are selected simultaneously, and image data is written without overlapping the selected pixel rows. The second 2F is a method in which two pixels (a plurality of pixels) of an even pixel row and an odd pixel row are selected at the same time except for the first pixel row, and image data is written without overlapping the selected pixel rows.
[0671]
135 (a1), (a2), and (a3) are the first fields, and FIGS. 135 (b1), (b2), and (b3) are the second fields. In the first field, video data is written in pairs of pixel rows 871 in the order of FIG. 135 (a1) → FIG. 135 (a2) → FIG. 135 (a3) →. Therefore, the two pixel rows display the same image, and this display state is maintained for a period of one field. In the first field, the image data of the odd pixel row is displayed in the corresponding odd pixel row and the next even pixel row. That is, the image data of the first row is displayed in the first pixel row and the second pixel row, the image data of the third row is displayed in the third pixel row and the fourth pixel row, and the image of the fifth row is displayed. The data is displayed on the fifth pixel row and the sixth pixel row, and the image data on the seventh row is displayed on the seventh pixel row and the eighth pixel row.
[0672]
In the second field, image data is written in pairs of pixel rows 871 in the order of FIG. 135 (b1) → FIG. 135 (b2) → FIG. 135 (b3) →. Therefore, the two pixel rows display the same image, and this display state is maintained for a period of one field. In the second field, the image data of the even pixel row is displayed in the corresponding even pixel row and the next odd pixel row. That is, the image data of the second row is displayed in the second pixel row and the third pixel row, the image data of the fourth row is displayed in the fourth pixel row and the fifth pixel row, and the image of the sixth row is displayed. The data is displayed in the sixth pixel row and the seventh pixel row, and the image data in the eighth row is displayed in the eighth pixel row and the ninth pixel row.
[0673]
Note that the state of the first field is maintained in the first pixel row in FIG. 135 (a1). In addition, although odd image data is written in the first field and even image data is written in the second field, the present invention is not limited to this and may be reversed.
[0674]
When the image display is performed as described above, it is assumed that the display image of the two fields is added and added by the human eye as an afterimage, and when the first frame (two fields) is completed, the first pixel row is the first pixel row. It is a display image of a field. The second pixel row is obtained by adding the image data of the first pixel row in the first field and the image data of the second pixel row in the second field. The third pixel row is obtained by adding the image data of the third pixel row in the first field and the image data of the second pixel row in the second field. The fourth pixel row is obtained by adding the image data of the third pixel row in the first field and the image data of the fourth pixel row in the second field. The fifth pixel row is obtained by adding the image data of the fifth pixel row in the first field and the image data of the fourth pixel row in the second field.
[0675]
As described above, since each pixel row is obtained by superimposing the images of the two fields, the contour of the display image becomes smooth. In particular, slight moving image blur occurs in moving image display, but a good resolution can be obtained (recognized as such) in almost still images.
[0676]
FIG. 136 shows drive waveforms for realizing the display method of FIG. The upper position in the drawing is the driving waveform of the first field (1F), and the lower position in the drawing is the driving waveform of the second field (2F).
[0677]
In the first field (1F), first, the gate signal lines 17a (1) and (2) of the first pixel row and the second pixel row are selected. Since a drive current of 10 times (N = 10) flows through the source signal line 18, the conversion TFTs 11a in the pixel rows (1) and (2) are programmed with a current of 5 times. At this time, the off voltage Vgh is applied to the gate signal lines 17b (1) and (2) of the first pixel row and the second pixel row, and the switching TFT 11d is in the off state. Therefore, the EL elements 15 in the first pixel row and the second pixel row are not lit.
[0678]
After 2H (the image data is written for each even-numbered pixel row or odd-numbered pixel row, which is 2H), the gate signal lines 17a (3) and (4) of the third pixel row and the fourth pixel row are selected, and the source signal line A drive current 10 times (N = 10) flows through 18. Therefore, each of the conversion TFTs 11a in the pixel rows (3) and (4) is programmed with a five times larger current. At this time, the off voltage Vgh is applied to the gate signal lines 17b (3) and (4) of the third pixel row and the fourth pixel row, and the switching TFT 11d is in the off state. Therefore, the EL elements 15 in the third pixel row and the fourth pixel row are not lit.
[0679]
On the other hand, since the on voltage Vgl is applied to the gate signal lines 17b (1) and (2), the switching TFTs 11d in the first pixel row and the second pixel row are turned on, and the EL element 15 is lit.
[0680]
Further, after 2H, the gate signal lines 17a (5) and (6) of the fifth and sixth pixel rows are selected. Since a drive current of 10 times (N = 10) flows through the source signal line 18, the conversion TFTs 11a in the pixel rows (5) and (6) are programmed with a current of 5 times. At this time, the off voltage Vgh is applied to the gate signal lines 17b (5) and (6) of the fifth pixel row and the sixth pixel row, and the switching TFT 11d is in the off state. Accordingly, the EL elements 15 in the fifth pixel row and the sixth pixel row are not lit.
[0681]
On the other hand, since the ON voltage Vgl is applied to the gate signal lines 17b (1), (2), (3), and (4), the first pixel row, the second pixel row, the third pixel row, and the fourth pixel row. The switching TFT 11d in the pixel row is turned on, and the EL element 15 is lit. The above operation is performed up to the last odd pixel row on the screen, and one screen is displayed.
[0682]
In the second field (2F), the first pixel row is not selected and the state of the first field is maintained. Next, the gate signal lines 17a (2) and (3) of the second pixel row and the third pixel row are selected. A drive current of 10 times (N = 10) flows through the source signal line 18. Therefore, each of the conversion TFTs 11a in the pixel rows (2) and (3) is programmed with a current of 5 times. At this time, the off voltage Vgh is applied to the gate signal lines 17b (2) and (3) of the second pixel row and the third pixel row, and the switching TFT 11d is in the off state. Therefore, the EL elements 15 in the second pixel row and the third pixel row are not lit.
[0683]
After 2H, the gate signal lines 17a (4) and (5) of the fourth pixel row and the fifth pixel row are selected, and a drive current 10 times (N = 10) flows through the source signal line 18. Therefore, each of the conversion TFTs 11a in the pixel rows (4) and (5) is programmed with a current that is five times greater. At this time, the off voltage Vgh is applied to the gate signal lines 17b (4) and (5) of the fourth pixel row and the fifth pixel row, and the switching TFT 11d is in the off state. Therefore, the EL elements 15 in the fourth pixel row and the fifth pixel row are not lit.
[0684]
On the other hand, since the ON voltage Vgl is applied to the gate signal lines 17b (2) and (3), the switching TFTs 11d in the first pixel row, the second pixel row, and the third pixel row are turned on, and the EL element 15 Lights up.
[0685]
Further, after 2H, the gate signal lines 17 a (6) and (7) of the sixth pixel row and the seventh pixel row are selected, and a drive current of 10 times (N = 10) flows through the source signal line 18. Therefore, each of the conversion TFTs 11a in the pixel rows (6) and (7) is programmed with a current of 5 times. At this time, the off voltage Vgh is applied to the gate signal lines 17b (6) and (7) of the sixth pixel row and the seventh pixel row, and the switching TFT 11d is in the off state. Accordingly, the EL elements 15 in the sixth pixel row and the seventh pixel row are not lit.
[0686]
On the other hand, since the ON voltage Vgl is applied to the gate signal lines 17b (1), (2), (3), (4), and (5), the first pixel row, the second pixel row, and the third pixel The switching TFTs 11d in the row, the fourth pixel row, and the fifth pixel row are turned on, and the EL elements 15 are lit. The above operation is performed up to the last even pixel row of the screen, and one screen is displayed.
[0687]
In the above embodiment, one screen is displayed in two fields. FIG. 137 displays one screen with two or more fields. FIG. 137 (a) is the first field, FIG. 137 (b) is the second field, and FIG. 137 (c) is the third field.
[0688]
In the first field, the 4Y-3 (Y is an integer of 1 or more) pixel row and the 4Y-2 pixel row are the writing pixel rows 871. The image data is written every two pixel rows. In the second field, the 4Y-1 pixel row and the 4Y pixel row are the writing pixel row 871. Similarly, the image data is written by two pixel rows in the previous field. In the third field, the 4Y-2 pixel row and the 4Y-1 pixel row are write pixel rows 871. The image data is written every two pixel rows. By writing in 3F as described above, each pixel data is complemented with image data of a plurality of fields.
[0689]
Although FIG. 137 is an example of one screen with three fields, image display may be realized using more fields. For example, in the case of four fields, in the first field, 4Y-3 (Y is an integer of 1 or more) pixel row and 4Y-2 pixel row are the writing pixel rows 871. The image data is written every two pixel rows. In the second field, the 4Y-1 pixel row and the 4Y pixel row are the writing pixel row 871. In the third field, the 4Y-2 pixel row and the 4Y-1 pixel row are write pixel rows 871. Similarly to the previous case, the image data is written by two pixel rows. In the fourth field, the 4Y-3 pixel row and the 4Y pixel row are the writing pixel row 871. Similarly, the image data is written by two pixel rows in the previous field. As described above, by writing in four fields, each pixel data is complemented with image data of a plurality of fields.
[0690]
Although the above embodiment has been described mainly by exemplifying the pixel configuration of FIG. 6, the driving method of the present invention is also effective for other current program pixel configurations such as FIGS. 19 and 79.
[0691]
FIG. 138 is an explanatory diagram of a driving method of the pixel configuration of FIG. Here, for the sake of easy explanation, the current that flows from the source driver 14 to the source signal line 18 (or the current that the source driver 14 sinks from the source signal line 18 and the current that the driving TFT 11a flows to the source signal line 18 are also described. ) Will be described as 10 times the predetermined value (N = 10). In the following description, it is assumed that the current magnification of the driving TFT 11a and TFT 11b is 1: 1 (current magnification 1).
[0692]
Therefore, if the simultaneously selected pixel rows are five pixel rows (K = 5), the five driving TFTs 11a operate. Since the current magnification = 1, the same current as the TFT 11a flows through the driving TFT 11b. That is, 10/5 = 2 times of current flows through the driving TFT 11a per pixel. Since the current programmed in the driving TFT 11a of the pixel 16 is twice the predetermined value, the current flowing in the EL element is also twice. Therefore, the deterioration of the EL element 15 is reduced as compared with the case where 10 times the current flows as shown in FIG. On the other hand, since the current flowing through the source signal line 18 is 10 times, the parasitic capacitance 404 can be charged and discharged in the same manner as in FIG. This also applies to FIG.
[0693]
If the current magnification is 2, the current that the driving TFT 11b passes through the EL element 15 is 1 time. Therefore, a predetermined current can be passed through the EL element 15 so that a predetermined luminance can be obtained. That is, in the pixel configurations of FIGS. 19 and 79, the current magnification (current ratio between the TFT 11a and the TFT 11b) and the current (program current) that flows through the source signal line 18 are designed (adjusted), so that the versatility can be improved. A high display panel drive design is possible.
[0694]
If the simultaneously selected pixel rows are five pixel rows (K = 5), the program current of the five driving TFTs 11a is added. For example, if a current to be originally written is Id and N = 10 in the write pixel row 871a, a current of Id × 10 is supplied to the source signal line 18. A write pixel row 871b adjacent to the write pixel row 871a (871b is a pixel row used auxiliary to increase the amount of current to the source signal line 18. Therefore, a pixel (row) for writing an image is 871a, A write pixel (row) 871b is used as an auxiliary to write to 871a).
[0695]
In FIG. 138, K rows (K = 5) are simultaneously written with the image data of the writing pixel row 871a. Therefore, the range of K rows (871a, 871b) is the same display. Thus, when the same display is used, the resolution is naturally reduced. In order to cope with this, the portion of the writing pixel row 871b is set as a non-display area 312 as shown in FIG. Therefore, resolution reduction does not occur.
[0696]
The write pixel row 871a shown in FIG. 138 (a) is in a display state, but since this pixel is being programmed, it changes depending on the current write state to the pixel. Therefore, the non-display area 312 may be used.
[0697]
After the next 1H, the same operation is performed with the pixel row shifted by one pixel row as the write pixel row 871a. The non-display area 312 is also shifted by one pixel (row). As described above, the writing pixel row 871b in which current data different from the original display data is written is not displayed, and a complete image display can be realized by shifting the above operation one row at a time. Further, due to the effect of the writing pixel row 871b used as an auxiliary, charging / discharging of the parasitic capacitance 404 can be realized within a sufficiently 1H period.
[0698]
FIG. 139 is an explanatory diagram of drive waveforms for realizing the drive method of FIG. 138. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level). In the lower part of FIG. 139, the number of the selected pixel row is described. Also, (1), (2), (3)... (11) in the figure indicate the selected pixel row number. The number of pixel rows is 480 in the VGA panel and 768 in the XGA panel.
[0699]
In FIG. 139, the gate signal line 17a (1) and the gate signal line 17b (1) are selected (Vgl voltage), and the program current is applied to the source signal line 18 from the driving TFT 11a of the selected pixel row toward the source driver 14. Flows. The program current flowing through the source signal line 18 is N times a predetermined value (for ease of explanation, N = 10 will be described. Of course, since the predetermined value is a data current for displaying an image, white raster display is performed. It is not a fixed value unless it is). Further, description will be made assuming that five pixel rows are simultaneously selected (K = 5). Therefore, ideally, the capacitor 19 of one pixel is programmed so that twice the current flows through the driving TFT 11a.
[0700]
Basically, since the gate signal lines 17a and 17b have the same phase, they can be shared. However, strictly speaking, when selecting or deselecting a pixel row, it is preferable to control so that the switching TFT 11d is first turned off and then the take-in TFT 11c is turned off. It is better to keep it separate from the gate signal line 17b.
[0701]
When the writing pixel row is the (1) pixel row, as shown in FIG. 139, the on voltage Vgl is applied to the gate signal lines 17a and 17b. Accordingly, the pixel rows (1), (2), (3), (4), and (5) are selected. That is, the capture TFT 11c and the switching TFT 11d in the pixel rows (1), (2), (3), (4), and (5) are in the on state. Further, the gate signal line 17b has an opposite phase to the gate signal line 17b. Therefore, the switching TFTs 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312.
[0702]
Ideally, the driving TFTs 11a of five pixels each pass Id × 2 current to the source signal line 18, and the capacitor 19 of each pixel 16 is programmed with twice as much current. Here, for easy understanding, description will be made assuming that the characteristics (Vt, S value) of the driving TFTs 11a are the same.
[0703]
Since the simultaneously selected pixel rows are five pixel rows (K = 5), the five driving TFTs 11a operate. That is, 10/5 = 2 times of current flows through the driving TFT 11a per pixel. A current obtained by adding the program currents of the five driving TFTs 11 a flows through the source signal line 18. For example, a current to be originally written is Id in the write pixel row 871a, and a current of Id × 10 is supplied to the source signal line 18.
[0704]
The four write pixel rows 871b for writing image data after the write pixel row (1) are pixel rows that are used supplementarily in order to increase the amount of current to the source signal line 18. However, there is no problem in the writing pixel row 871b because normal image data is written later. Therefore, the writing pixel row 871b has the same display as the writing pixel row 871a during the 1H period. Therefore, at least the non-display area 312 is the writing pixel row 871b selected for increasing the current.
[0705]
After the next 1H (position of pixel row number 6), the gate signal lines 17a (1) and 17b (1) are not selected, and data to be written to the pixels is determined. At the same time, the gate signal line 17a (6) is selected (position of pixel number 2), and a program current flows from the driving TFT 11a of the selected pixel row (6) to the source driver 14 toward the source signal line 18. . By operating in this way, regular image data is held in the pixel row (1).
[0706]
After the next 1H, the gate signal lines 17a (2) and 17b (2) are not selected. Further, the gate signal line 17a (7) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the driving TFT 11a of the selected pixel row (7) toward the source driver. By operating in this way, regular image data is held in the pixel row (2). One screen is rewritten by performing the above operation and scanning while shifting one pixel row at a time.
[0707]
As in FIG. 84, in the driving method of FIG. 93, since each pixel is programmed with twice the current (voltage), the light emission luminance of the EL element 15 of each pixel is ideally doubled. . Therefore, the brightness of the display screen is twice the predetermined value.
[0708]
In order to obtain a predetermined luminance, as shown in FIG. 45, a non-display area 312 may be included that includes a writing pixel row 871 and a half of the display screen 21. This has been described with reference to FIG. Needless to say, the driving method of FIG. 121 can also be applied to FIGS. 138, 79, 81, 86, 87, and the like. Since the explanation has been made first, it will be omitted.
[0709]
As the area of the black display area (non-display area) 312 occupying the display screen 21 is increased, the moving image display performance is improved. Therefore, as shown in FIG. 94, the image display area 311 may be reduced and the area of the non-display area 312 may be increased.
[0710]
In the embodiment of the present invention, the program current (voltage) can be adjusted by changing the current (voltage) flowing through the source signal line 18. That is, the current flowing through the source signal line 18 can be adjusted only by adjusting the reference current (voltage) of the source driver 14. Whether to turn on two pixel rows at the same time, turn on five pixel rows at the same time, or select only one pixel row depends on whether the ST * terminal applied to the shift register 22 of the gate driver 12 shown in FIG. Can be set with data. Therefore, the specification of the source driver 14 does not depend on the number of pixels to be selected. Further, since the brightness of the screen can also be adjusted by turning on / off the gate signal line 17c, the output current from the source driver 14 is not changed by adjusting the brightness of the display screen 21. Therefore, the gamma characteristic of the EL element 15 may be determined for one current. Therefore, the configuration of the source driver 14 is extremely easy and highly versatile. The above matters can be applied to other embodiments of the present invention.
[0711]
As in FIG. 89, when one image display area 311 moves downward from the top of the screen as shown in FIG. 94, it is visually recognized that the image display area 311 moves when the frame rate is low. . In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down. For this problem, the image display area 311 may be divided into a plurality of parts as shown in FIG.
[0712]
As shown in FIG. 116 (b), the scanning direction of the non-display area 312 is not limited to the top to bottom direction, but may be scanned from the bottom to the top direction of the screen. Further, the scanning direction from the top to the bottom and the scanning direction from the bottom to the top may be alternately or randomly scanned. Needless to say, the number of divisions may be changed for each frame or at a predetermined position on the display screen 21.
[0713]
As described above, dividing the image display area 311 into a plurality reduces screen flicker, and flicker does not occur, and a good image display can be realized. Note that the division may be made finer, and flicker is reduced as the division is performed. In particular, since the responsiveness of the EL element 15 is fast, even if it is turned on / off in a time shorter than 5 μsec, the display luminance does not decrease.
[0714]
45 and 46 have been described by exemplifying the current-programmed pixel configuration as shown in FIGS. 6, 79, and 19. However, the present invention is not limited to this. For example, the pixel configuration of the voltage programming method shown in FIGS. 81, 86, and 87 is also effective. By applying a voltage to a plurality of pixel rows at the same time, the pixels can be precharged, so that a high-definition display panel of SXGA or higher can be supported. In addition, the electric drive circuit and the signal processing circuit are simplified, and good black display can be realized.
[0715]
As an application example of the voltage program, the pixel configuration in FIG. 81 will be exemplified and described. 140 and 141 show the drive waveforms. In FIG. 140 and FIG. 141, the description will be made assuming that the five-pixel row is set as the non-display area 312. For example, two pixel rows may be selected simultaneously, or ten pixel rows may be used. One pixel row may be set as the non-display area 312. The same applies to FIGS. 85, 86, 87 and the like.
[0716]
In addition, the driving method described in FIGS. 118, 121, 125, 126, 128, and 137 is applied to the pixel configuration of the voltage program illustrated in FIGS. 81, 85, 86, and 87. Can be applied. Needless to say, a driving method in which the non-display area 312 is formed by driving the EL element 15 so that N times as much current flows can be applied. However, the description will be complicated in FIGS. 140 and 141, and will not be described.
[0717]
As shown in FIG. 141, when the writing pixel row is the (1) pixel row (position of the pixel row number 5), the gate signal line 17a has (1), (2), (3), (4). , (5) is selected. That is, the driving TFTs 11b in the pixel rows (1), (2), (3), (4), and (5) are in the on state, and the off voltage Vgh is applied to the gate signal line 17b. Therefore, the switching TFTs 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. It becomes a non-display area 312. Therefore, the voltage is precharged in the pixel row (1) for a period of 5H.
[0718]
The pre-charged pixel row is displayed in the same manner as the other four pixel rows during the 5H period. Therefore, at least the non-display area 312 is a pixel row in which writing is performed. In particular, in the video signal, the video data is similar in adjacent pixels, so that it is easy to write regular image data if preliminary charging is performed.
[0719]
Therefore, the present invention is a method of writing image data in a plurality of pixel rows and setting the non-display area 312 until regular image data is written. However, even if one pixel row is selected, the display is unstable when the image data of this pixel row is written, and therefore it is also a concept of the present invention to make it non-displayed. Further, the current flowing through the EL element 15 is made larger than a predetermined value, and the non-display area 312 is formed to obtain a predetermined luminance. It is also an effect of the present invention that a good moving image is realized by this display method.
[0720]
In the next 1H, (2) the image data of the pixel row is determined. As is apparent from FIG. 141, an off voltage (Vgl: because the TFT 11b is an N channel) is applied to the gate signal line 17a (1) and the gate signal line 17b (1) (pixel row number 6). An ON voltage (Vgh: because the TFT 11b is an N channel) is applied to the gate signal line 17a (6) and the gate signal line 17b (6). Therefore, the image data to the conversion TFT 11a in the pixel row (2) is retained.
[0721]
As described above, one pixel row and writing pixel row are shifted in synchronization with the horizontal scanning period, and one screen can be displayed by sequentially performing the above operations.
[0722]
FIG. 140 shows a method in which the timing of the gate signal line 17b is shifted by 1H in the pixel configuration of FIG. As is clear from FIG. 140, the pixel to be determined is set in the display state.
[0723]
For example, image data is written in the pixel row (1) for a period of 5H (period of pixel row numbers 1 to 5). That is, the gate signal line 17a of the pixel row (1) is in a selected state (the on-voltage Vgh is applied because the TFT 11b is an N channel). At 5H, an on-voltage (Vgl: because the TFT 11d is a P channel) is applied to the gate signal line 17b (1), and thus a current flows through the EL element 15. Therefore, the EL element 15 is in a lighting state. This is different from FIG. Although the non-display area 312 is shown in FIG. 141, the other points are the same as those in FIG.
[0724]
In the embodiment of the present invention in which the image data is written by turning on the plurality of pixel rows at the same time, the pixel rows on the uppermost side and / or the lowermost side of the display screen 21 are turned on at the same time. There is no. To solve this problem, a dummy pixel row may be formed or arranged on the uppermost side, the lowermost side, or both of the display screen 21.
[0725]
For example, in the driving method for simultaneously selecting five pixel rows described with reference to FIG. 92, four pixel rows are formed on the lower side of the screen. Of course, when performing upside down driving, four dummy pixel rows are also provided on the upper side of the screen. Since the EL element 15 is not formed in this dummy pixel row, no light is emitted. Of course, even if the EL element 15 is formed, light emission is not performed or light is not shielded from being displayed. In addition, in FIG. 6, other than the switching TFT 11d of one pixel may be formed. Note that one or more dummy pixel rows are formed.
[0726]
Although the adjacent pixel rows are simultaneously turned on, the present invention is not limited to this. For example, the timing for turning on a plurality of pixel rows may be different. Even if the first row is separated as the second pixel row of the third row, the effect is exhibited. In an extreme case, when selecting two pixel rows, one pixel row is fixed (for example, the pixel row at the bottom of the screen or a dummy pixel row) and turned on, and the other pixel rows are scanned and sequentially turned on. You may let them.
[0727]
6, 19, 62, 72, 74, and 73 are common to the current programming method, but there is a problem that black display is difficult in the current programming method (of course, FIG. 45, FIG. However, the present invention can be significantly improved by implementing the present invention such as 46. However, it is also effective to combine with the following embodiments, of course, without combining with the embodiments of FIGS. May be implemented). For example, even if the white peak current flowing through the EL element 15 is 2 μA, the first gradation in the 64 gradation display is 2 μA / 64≈30 nA. It is difficult to charge and discharge the parasitic capacitance 404 such as the source signal line 18 in the 1H period with this minute current. Although the pixels 16 are formed or arranged in a matrix, only one pixel is shown in the drawing for easy explanation.
[0728]
In order to cope with this problem, in the present invention, a voltage source 401 for writing a black level voltage (current) to the source signal line 18 is formed or arranged. Specifically, the voltage source 401 is configured so that a DCDC converter generates a predetermined voltage and this voltage can be applied by the power source switching means 403 constituted by an analog switch or the like.
[0729]
A specific example of a signal waveform applied to the source signal line 18 is shown in FIG. In the first t2 period of the 1H period in which current programming is performed, a voltage Vb for turning off or substantially displaying black is applied to the source signal line 18 of the driving TFT 11b (the conversion TFT 11a in FIG. 6 and the like). This voltage is generated by the voltage source 401 and applied to the source signal line 18 by the power source switching means 403. Since the acquisition TFT 11c and the switching TFT 11d are on during the program period, the voltage Vb applied to the source signal line 18 becomes the terminal voltage of the capacitor 19, that is, the gate terminal voltage of the driving TFT 11b. Therefore, the first pixel in the 1H period is displayed in black (non-lighting state).
[0730]
Originally, when the displayed image is black, the terminal voltage of the capacitor 19 is maintained as it is. When the actually displayed image is white display, the white display voltage Vw (which should be expressed as Iw in the case of current programming) is applied after the Vb voltage is applied, and this voltage (current) is applied to the capacitor. 19 and the 1H period ends. Here, for ease of explanation, it is assumed that the white display voltage Vw (current Iw) is applied since the actually displayed image is white display. However, as a matter of course, in the case of a natural image, the voltage held in the capacitor 19 is a voltage (current) between Vb and Vw.
[0731]
As shown in FIG. 142, a good black display can be realized by applying a signal to the source signal line 18 and driving the gate signal lines 17a and 17b, and an image display such as FIG. 49 can be implemented.
[0732]
Even in the pixel configuration of FIG. 6, a good black display can be realized by applying the signal waveform of FIG. In the first t2 period of the 1H period in which the current program is performed, the voltage Vb for turning off or substantially displaying black is applied to the source signal line 18 of the conversion TFT 11a. This voltage is generated by the voltage source 401 and applied to the source signal line 18 by the power source switching means 403.
[0733]
Since the driving TFT 11b and the capturing TFT 11c are on during the program period, the voltage Vb applied to the source signal line 18 becomes the terminal voltage of the capacitor 19, that is, the gate terminal voltage of the conversion TFT 11a. Therefore, the first pixel in the 1H period is displayed in black (non-lighting state).
[0734]
As described above, when the displayed image is black, the terminal voltage of the capacitor 19 is held as it is. When the actually displayed image is white display, the white display voltage Vw (which should be expressed as Iw in the case of current programming) is applied after the Vb voltage is applied, and this voltage (current) is applied to the capacitor. 19 and the 1H period ends.
[0735]
The voltage source 401 (precharge circuit) illustrated in FIG. 62 and the like may be directly formed on the array substrate 49 by a low temperature polysilicon technique or the like. Since the EL element 15 has different element configurations and materials for R, G, and B, the voltage (current) that generates light is often different (rising voltage (current)). In order to cope with this characteristic, it is preferable that the precharge voltage can be set individually for R, G, and B, and that at least one of the three primary colors can be changed.
[0736]
The precharge time t2 for applying the Vb voltage needs to be 1 μsec or longer. The precharge time t2 for applying the Vb voltage is preferably 1% to 10% of 1H, more preferably 2% to 8%.
[0737]
Further, it is preferable that the voltage to be precharged can be changed depending on the contents (brightness, definition, etc.) of the display screen 21. For example, when the user presses the adjustment switch or turns the adjustment volume, this change is detected and the value of the precharge voltage (current) is changed. You may comprise so that it may change automatically with the content and data of the image to display. For example, the intensity of external light from the outside is detected by a photosensor, and the precharge (discharge) voltage (current) is adjusted based on the detected value. In addition, the precharge (discharge) voltage (current) is adjusted according to the type of image (computer image, daytime screen, starry sky, etc.). The adjustment is determined in consideration of the average brightness, maximum brightness, minimum brightness, moving image, still image, and brightness distribution of the image.
[0738]
In FIG. 62 and the like, the precharge circuit and the like have been simply described. Further details will be described with reference to FIG. Since discharge and precharge are simply the application directions of potential, the following description will be made using precharge as the same meaning of discharge and precharge.
[0739]
FIG. 143 shows a circuit configuration in which current driving and voltage driving are combined. The switch circuit 1223 is connected to the source signal line 18 having a display area and is constituted by an analog switch. A voltage is applied to the a terminal of the switch circuit 1223 (precharge voltage), and a program current for programming the pixel is applied to the b terminal.
[0740]
The current output circuit 1222 receives 8-bit (256 gradations) IDATA, and this IDATA is DA-converted by the DA circuit 1226 to become an analog voltage. This analog voltage is applied to the base terminal of the output transistor (or FET) 1227 and converted into a current output by the action of the operational amplifier 1224b and the resistor 1228. The voltage-current conversion circuit using the output transistor 1227 and the operational amplifier 1224 is a general one and is well known to those skilled in the art, so further explanation will not be required.
[0741]
On the other hand, the voltage output circuit 1221 includes a buffer circuit including an adjustment volume (VR) 1225 and an operational amplifier 1224a. The adjustment volume 1225 is common to all source signal lines. By adjusting the adjustment volume 1225, the precharge voltage Vb is determined.
[0741]
When the first precharge voltage Vb in one horizontal scanning period (1H) is applied, the switch circuits 1223 connected to all the source signal lines are connected to the terminal a. Therefore, all the source signal lines 18 are set to the precharge voltage Vb. Thereafter, the switch circuit 1223 is switched to the terminal b, and current data (256 gradations) corresponding to the image is applied to the source signal line 18. This current data is written into each pixel 16, and a current flows through the EL element 15 of each pixel to emit light.
[0743]
In FIG. 143, the precharge voltage Vb has a fixed value, but FIG. 144 is a circuit configuration diagram in which the precharge voltage can be set to 256 values (8 bits). In FIG. 144, the 8-bit VDATA is input to the voltage output circuit 1221 and is converted into an analog voltage by the DA circuit 1226a. The converted analog voltage is input to one terminal of the operational amplifier 1224c and can be adjusted to a predetermined voltage with respect to the reference voltage of the adjustment volume (VR) 1225.
[0744]
The output of the operational amplifier 1224c is applied to the a terminal of the switch circuit 1223a via the operational amplifier 1224a of the buffer. On the other hand, a current output is applied to the b terminal of the switch circuit 1223a.
[0745]
VDATA is a voltage corresponding to IDATA. A precharge voltage Vb corresponding to VDATA is applied during the first 1 to 10 μsec (preferably a period of 1/100 to 1/5 of 1H) of one horizontal scanning period (1H). At this time, the switch circuit 1223 connected to all the source signal lines is connected to the terminal a. Therefore, each source signal line 18 is set to a precharge voltage Vb corresponding to VDATA. The difference from FIG. 143 is that a precharge voltage Vb can be set for each source signal line. That is, each source signal line 18 is provided with a DA circuit that DA-converts IDATA and a DA circuit that DA-converts VDATA. However, each source signal line 18 is not limited to being provided with a DA circuit that DA-converts IDATA and a DA circuit that DA-converts VDATA. This is because, for example, even one DA circuit can be realized if the output is sampled and held by each source signal line.
[0746]
A voltage obtained by converting VDATA is applied in the first period of 1H, and this voltage value is substantially equal to the source signal line potential by a current value corresponding to IDATA to be applied thereafter. Therefore, by applying the voltage of VDATA, the potential of the source signal line becomes almost the target value, and is slightly corrected to the target value by IDATA. With the above configuration, there is no shortage of current writing to the source signal line 18.
[0747]
In FIG. 144 (a), the switch circuit 1223a switches between the a terminal and the b terminal. However, the present invention is not limited to this. For example, as shown in FIG. 144B, the output of the voltage output circuit 1221 may be applied to the terminal a, and the output of the current output circuit 1222 may be continuously connected to the source signal line 18.
[0748]
By making the DA circuit 1226 capable of changing the output in accordance with the reference voltage, the flexibility of the circuit configuration is further improved. For example, when the reference voltage is 2.54 V, the output can be changed in correspondence with the reference voltage means that the output can be changed at intervals of 0.01 V (when an 8-bit, 256-gradation DA circuit is employed). ). When the reference voltage is 5.08V, the output can be changed at intervals of 0.02V. That is, by changing the reference voltage, the output of the DA circuit can be instantaneously changed in proportion to the reference voltage. FIG. 145 is a circuit block diagram when such a DA circuit is employed.
[0749]
In FIG. 145, the Vref voltage is applied to the DA circuit 1226a. The Vref voltage is output from a circuit including an RV * resistor that divides the Vv voltage into four and a switch circuit 1223b. Therefore, the Vref voltage is switched in four stages by the CVS signal, and the output of the DA circuit 1226a can be instantaneously switched in four stages.
[0750]
On the other hand, the Iref voltage is applied to the DA circuit 1226b. The Iref voltage is output from a circuit including an RV * resistor that divides the Vi voltage into four and a switch circuit 1223c. Therefore, the Iref voltage is switched in four stages by the CIS signal, and the output of the DA circuit 1226b can be instantaneously switched in four stages.
[0751]
With the configuration as shown in FIG. 145, the current (voltage) output to the source signal line 18 can be changed in four stages in the period of 1H. For example, a high voltage (current) is first applied for a moment, and the target value is reached at a high speed by this application, and then changed to a steady-state voltage (current). The voltage (current) written to the pixel can be changed at high speed.
[0752]
However, in the configuration of FIG. 145, the circuit scale is considerably large. In general, the configuration shown in FIG. 146 is sufficient. The configuration of FIG. 145 is configured such that the voltage output circuit 1221 can output two voltage values. The two voltages are voltages that make the image display black. The other is a voltage that makes the image display white. Specifically, if the Vdd voltage in FIG. 6 is 6V, the black voltage is 3V to 4V and the white voltage is 1V to 2V. The white voltage and the black voltage are adjusted by an adjustment volume (VR) 1225, and this voltage is applied to the switch circuit 1223b via the operational amplifiers 1224a and 1224c of the buffer. Note that the output of the switch circuit 1223b is switched by the VSL voltage.
[0753]
A precharge voltage Vb (white voltage or black voltage) is applied at the beginning of one horizontal scanning period (1H). Since each source signal line is connected to the terminal c of the switch circuit 1223a, each source signal line 18 is first precharged to a white voltage or a black voltage. Thereafter, the switch circuit 1223 is switched to the terminal b, and current data (256 gradations) corresponding to the image is applied to the source signal line 18. This current data is written into each pixel 16, and a current flows through the EL element 15 of each pixel to emit light.
[0754]
In the above embodiment, each source signal line 18 is set to be precharged to a white voltage or a black voltage. However, the present invention is not limited to this. It is more practical to precharge when the display data (VDATA, IDATA) is greater than or equal to a predetermined value or less than a predetermined value.
[0755]
FIG. 147 illustrates the case of 64-gradation display for ease of explanation. In FIG. 147 (a), the range from 57th to 63rd gradation (KW) is precharged with white voltage. That is, a white voltage is output from the voltage output circuit 1221 in FIG. Further, a range (KB) from the 0th gradation to the 7th gradation is precharged with a black voltage. That is, a black voltage is output from the voltage output circuit 1221 in FIG. The output of the voltage output circuit 1221 is in a high impedance state from the 8th gradation to the 56th gradation (the switch circuit 1223a does not select the terminal a).
[0756]
As described above, the white voltage is applied to the gradation to be displayed in white, and the black voltage is applied to the gradation to be displayed in black. In addition, gradation display can be realized at high speed and satisfactorily by not precharging the halftone portion (KM).
[0757]
In the case of the current programming method, in black display, since the programming current (current written to the pixel) is as small as 5 nA or more and 20 nA or less, insufficient writing occurs. Therefore, the original black display can be realized by precharging the black voltage. However, insufficient writing may occur even in a dark gray display. In this case, it is effective to perform the second black precharge in addition to the white and black precharge.
[0758]
FIG. 147 (b) shows this embodiment. By precharging the black voltage in the range of KB1, original black display can be realized. Then, by precharging the second black (gray) in the range of KB2, sufficient gradation display can be realized for a gray portion close to black.
[0759]
More specifically, in the pixel configuration of FIG. 6, if the Vdd voltage is 6V, the black voltage for precharging in the range of KB1 is 3V to 3.5V, and the gray precharging of KB2 is performed. The black voltage to be performed is 3.5V to 4.0V. The white voltage in the range of KW is 1V to 2V. In the range of KM, precharge by voltage is not performed.
[0760]
FIG. 147 (b) illustrates the case of 64-gradation display for ease of explanation. In FIG. 147 (b), the range from 57th to 63rd gradation (KW) is precharged with white voltage. The range from the 0th gradation to the 7th gradation (KB1) is precharged with a black voltage. A range (KB2) from the 8th gradation to the 15th gradation is precharged with the second black voltage. From the 16th gradation to the 56th gradation, the output of the voltage output circuit 1221 is in a high impedance state (the switch circuit 1223a does not select the terminal a).
[0761]
As described above, a more appropriate gradation display can be realized by separating the black range into a plurality of ranges and precharging them with different voltages. In FIG. 147 (b), the black range is two, but is not limited to this, and may be three or more. In addition, precharging may be performed collectively for all source signal lines. These circuit configurations are easy because it is only necessary to arrange three or more buffer operational amplifiers 1224 in FIG. 146 and select three or more switch circuits 1223b.
[0762]
In FIG. 147, the current flowing through the EL element 15 at gradation 0 (black display) is not 0A. The EL element 15 does not emit light unless a predetermined current or more is passed. This range of current that does not emit light is called dark current. The dark current has a pixel size of 10,000 square μm and is about 10 nA to 50 nA. Within this dark current range, the pixels display black and current flows even at gradation 0. The source driver 14 needs to be driven with a current to which a dark current is added.
[0763]
Hereinafter, the circuit configuration illustrated in FIGS. 143 to 146 is referred to as an output stage circuit 1271. As shown in FIG. 148, the output stage circuit 1271 is generally arranged (formed) on each source signal line 18. In FIG. 148 and the like, the output stage circuit 1271 is illustrated as being formed in the source driver 14 formed of a silicon chip, but is not limited to this, and is formed directly on the glass substrate 241 simultaneously with the pixel TFT 11 and the like. May be. In other words, high temperature polysilicon technology, low temperature polysilicon technology, CGS (Continuous Grain Silicon) technology developed by Sharp Corporation, and seed crystals developed by Fujitsu Ltd. are formed on a substrate and grown. Alternatively, the output stage circuit 1271 may be formed by a technique in which a semiconductor circuit formed on a quartz substrate developed by Seiko Epson Corporation is formed on a glass substrate by transfer. Needless to say, the output stage circuit 1271 can be directly formed when the glass substrate 241 is a metal substrate or a semiconductor substrate.
[0764]
In the source driver 14, a protruding electrode (not shown) made of gold (Au) having a height of several to 100 μm is formed on the signal terminal electrode portion of the source driver by using a plating technique or a nail head bonding technique. Has been. The protruding electrode and each signal line are electrically connected through a conductive bonding layer (not shown). Adhesives for conductive bonding layers are mainly epoxy-based, phenol-based, etc., and silver (Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO)2) Or other flakes, or UV curable resin. The conductive bonding layer is formed on the protruding electrode by a technique such as transfer.
[0765]
Although the source driver 14 (or the gate driver 12) is illustrated or described as being stacked on the substrate, the present invention is not limited to this. Alternatively, the source driver 14 (or the gate driver 12) may not be mounted on the substrate, and may be connected to the signal line using a polyimide film or the like on which a driver IC is mounted using film carrier technology.
[0766]
Although FIG. 148 shows that the output stage circuit 1271 is arranged only at one end of the display screen 21, it is not limited to this. For example, as shown in FIG. 149, source drivers 14a and 14b may be arranged. In FIG. 149, two gate drivers 12 are also formed. That is, the display screen is composed of 21a and 21b, and with this configuration, separate images can be displayed on the display screens 21a and 21b.
[0767]
In the configuration of FIG. 149, since the display screen 21 is divided into two, the video signal output from the output stage circuit 1271 may have a half operating frequency as compared with the case where there is one display screen 21. Further, the parasitic capacitance generated in the source signal line 18 and the like is also halved. Therefore, the burden on the output stage circuit 1271 is 1/2 × 1/2 = 1/4. Therefore, even if the current output from the output stage circuit 1271 is very small, the parasitic capacitance of the source signal line 17 can be charged and discharged sufficiently, and writing shortage does not occur.
[0768]
In the configuration of FIG. 149, the display screen 21 is divided into two at the center of the screen 21a and the screen 21b. FIG. 150 addresses this issue. The source driver 14 a drives odd pixel rows on the display screen 21, and the source driver 14 b drives even pixel rows on the display screen 21. Therefore, the boundary of the display screen 21 does not occur.
[0769]
Further, in order to improve the shortage of the write current to the pixel, as shown in FIG. 151, the output stage circuit 1271 corresponding to each source signal line 18 in the source drivers 14a and 14b may be set to two outputs. That is, the output stage circuit 1271a includes two output stages (output stage A and output stage B), the output stage A is connected to the odd-numbered pixel rows of the display screen 21a, and the output stage B is the even-numbered pixels of the display screen 21a. Connected to the line. The output stage circuit 1271b also includes two output stages (output stage A and output stage B), the output stage A is connected to the odd-numbered pixel row of the display screen 21b, and the output stage B is the even-numbered pixel of the display screen 21b. Connected to the line. With this configuration, a sufficient current can be supplied to the source signal line even with a very small current, and a good image display can be realized.
[0770]
In FIG. 151, the output stage circuit 1271 is connected to one source signal line 18 for each pixel. However, the present invention is not limited to this, and the pixel has a differential configuration, and each pixel has two source signal lines ( One source signal line may be driven with a bias current, and the other source signal line may be driven with a bias current + signal current.
[0771]
FIG. 152 is a more specific module configuration diagram. In FIG. 152, reference numeral 14b denotes a source driver, and reference numeral 14c denotes a chip (one-chip driver IC) in which a gate driver and a source driver are integrated. A one-chip driver IC 14 c drives the gate signal line of the display screen 21. The one-chip driver IC 14c drives the source signal line 18a of the display screen 21a. The source driver 14b drives the source signal line 18b and drives the display area screen 21b.
[0772]
Note that FIG. 152 is an example, and the source driver 14b may also have a gate driver function, and may be configured to drive the gate signal line 17b of the display screen 21b. The power supply IC 102 and the control IC 101 are illustrated as being stacked on the printed circuit board 103, but the present invention is not limited to this. The power supply IC 102 and the control IC 101 are formed directly on the display panel 82 using the polysilicon technique described above. Also good. This can also be applied to FIGS. 227 and 228. Other configurations are the same as those shown in FIGS. 227, 228, 26, 151, etc., and the description thereof will be omitted.
[0773]
The control IC 101 drives both the one-chip driver IC 14c and the source driver 14b. Signals (power supply wiring, data wiring, etc.) supplied from the control IC 101 to the one-chip driver IC 14c are supplied via the flexible substrate 104c. However, since the source driver 14b is quite far away, first, the source driver 14b is connected to the back surface of the display panel 82 by the flexible substrate 104a.
[0774]
FIG. 153 is a view of the display panel 82 observed from the back side. Signal wiring (including power supply wiring) 1321 is formed on the back surface of the display panel 82. The signal wiring 1321 is formed using a metal material such as copper, aluminum (Al), silver, silver-palladium, palladium, gold, or Al-Mo. The signal wiring 1321 transmits a signal from end to end of the display panel 82. A flexible substrate 104b is connected to one end of the display panel 82, and a signal or the like is supplied from the flexible substrate 104b to the source driver 14b. Note that FIG. 154 is a view as seen from A of FIG.
[0775]
62, 142, and 143 to 147 have been described by exemplifying the current programming type pixel configuration as shown in FIGS. 6 and 19, but the present invention is not limited to this. For example, the pixel configuration of the voltage program method such as FIG. 85, FIG. 86, FIG. 87, FIG. In that case, the signal applied to the b terminal of the switch circuit 1223 in FIG. 143 needs to be a voltage. This change is easy and would be easily handled by a person skilled in the art. In the voltage driving, there is no shortage of charging due to the parasitic capacitance of the source signal line 18, but the driving circuit and the signal processing circuit are simplified and good by adopting a method of simultaneously applying voltages to a plurality of pixel rows. This is because black display can be realized. In addition, it is possible to realize hidden display of the image, and the effect of absorbing variation of the TFT 11 is also exhibited.
[0776]
Therefore, it goes without saying that the items described with reference to FIGS. 143 to 147 can be applied to all display panels, display devices, information display devices, and the like of the present invention.
[0777]
As described above, the present invention can be applied to various pixel configurations. FIG. 157 shows an embodiment in which the P channel of the TFT 11 in FIG. Also in FIG. 157, the switching TFT 11d can be turned on / off by controlling the gate signal line 17, and it is needless to say that the image display of FIG. Also, the drive waveforms in FIGS. 48 and 55 are the same or similar, and thus description thereof is omitted. In FIG. 6, it is also effective to use only the driving TFT 11b and the capturing TFT 11c as N-channel TFTs. This is because the penetration voltage to the capacitor 19 is reduced and the holding characteristics of the capacitor are also improved.
[0778]
Note that FIG. 157 is configured to include only the current source 402. That is, the voltage source 401 that performs precharging is not provided. However, when the parasitic capacitance 404 is relatively small or the 1H period is sufficiently long, black display can be sufficiently achieved without the voltage source 401. In addition, as described with reference to FIG. 49 and the like, in the case where the complete non-display area 312 is implemented, the voltage source 401 is almost unnecessary. If necessary, it may be configured as shown in FIG.
[0779]
FIG. 159 shows an embodiment in which the P channel of the TFT 11 in FIG. Also in FIG. 159, the TFT 11e and the like can be turned on and off by controlling the gate signal line 17, so that the image display of FIG. Also, the drive waveforms in FIGS. 48 and 55 are the same or similar, and thus description thereof is omitted.
[0780]
As described above, a satisfactory black display can be realized by applying the Vb voltage (Ib current) with the voltage source 401.
[0781]
When N = 10 or more and a high current pulse is applied to the EL element 15, the EL terminal voltage also increases. The EL element 15 has different rise voltages and gamma curves for R, G, and B. In particular, since the gamma curve of B is gentle, the terminal voltage of the EL element 15 tends to increase. When the terminal voltage is adjusted to the EL element 15 of a color (R, G, B color) having a high rising voltage and a gentle gamma curve, the power consumption increases.
[0782]
One method for solving this is a system in which the cathode shown in FIG. 33 is separated by R, G, and B. Note that R, G, and B need not have different cathode potentials. In particular, only one color cathode whose gamma curve is separated from the other colors may be separated. As another method, a configuration for separating the Vdd power supply voltage as shown in FIG. 160 is also effective. That is, the R color Vdd power supply is VddR, the G color Vdd power supply is VddG, and the B color Vdd power supply is VddB. By separating in this way, each of RGB can be adjusted by a separate power source, and even if the terminal voltages of the RGB EL elements 15 are different, the increase in power consumption is small.
[0783]
Note that R, G, and B do not need to have different Vdd potentials. In particular, only Vdd of only one color whose gamma curve is separated from other colors may be separated. Further, as illustrated in FIG. 161, the configuration of FIG. 33 may be combined. That is, R, G, and B, which are separated by R, G, and B, have different cathode potentials (R pixel is VsR, G pixel is VsG, and B pixel is VsB). In particular, only the cathode potential of only one color whose gamma curve is separated from the other colors may be separated. Further, the Vdd power supply voltage is separated. In this configuration, the R-color Vdd power supply is set to VddR, the G-color Vdd power supply is set to VddG, and the B-color Vdd power supply is set to VddB. Also in this case, it is not necessary to set different Vdd potentials for R, G, and B. In particular, only Vdd of only one color whose gamma curve is separated from other colors may be separated.
[0784]
In FIG. 160 and FIG. 161, the pixel 16 has the structure shown in FIG. 6, but the present invention is not limited to this, and FIGS. 19, 20, 159, 162, 157, 158, 81, and FIG. Needless to say, the configuration may be 85, 86, 72 to 76, 83, 67, 79, 80, 82, or the like.
[0785]
The problem of the present invention is that the current applied to the EL element 15 is instantaneous, but is N times larger than the conventional one. If the current is large, the life of the EL element may be reduced. In order to solve this problem, it is effective to apply a reverse bias voltage Vm to the EL element 15.
[0786]
Hereinafter, a method for applying the reverse bias voltage Vm will be described. In order to apply the reverse bias voltage Vm, it is necessary to individually control the gate terminals of the driving TFT 11b and the capturing TFT 11c in the configuration of FIG. That is, it is necessary to individually turn on and off the driving TFT 11b and the capturing TFT 11c. This control method will be described with reference to FIG.
[0787]
First, as shown in FIG. 163 (a), the take-in TFT 11c is turned on and the switching TFT 11d is turned on (see also FIG. 6). Then, the reverse bias voltage Vm is applied to the a terminal of the EL element 15. The reverse bias voltage Vm is a voltage not lower than the cathode voltage Vs and not lower than 5V and not higher than 15V.
[0788]
When the EL element 15 is lit, a voltage higher than 5V and less than 15V is applied to the terminal a with respect to the cathode voltage Vs. That is, the reverse bias voltage Vm is ideally applied with a voltage having the same absolute value and the opposite polarity to the voltage applied when the EL element 15 is lit. Actually, since it is difficult to apply a voltage having the same absolute value and the opposite polarity, a voltage two to three times the opposite polarity is applied. As described above, the EL element 15 hardly deteriorates by applying the reverse bias voltage Vm.
[0789]
Next, as shown in FIG. 163 (b), the switching TFT 11d is turned off and the driving TFT 11b is turned on. Then, the black display voltage Vb is written into the capacitor 19. This operation is illustrated in FIG. Next, as shown in FIG. 163 (c), the on / off state of the TFT 11 is the same as that in FIG. 163 (b), and the image display voltage (current) from the current source 402 is written into the capacitor 19. This operation is also described with reference to FIG. Finally, as shown in FIG. 163 (d), the driving TFT 11b and the take-in TFT 11c are turned off, the switching TFT 11d is turned on, and a current is supplied to the EL element 15 to light it.
[0790]
The above operation is shown in FIG. The reverse bias voltage Vm is applied to the source signal line 18 at the time t1 of the 1H period, the black display voltage Vb is applied during the next t2 period, and the image data Vw (Iw) is applied during the t3 period. Other operations will be described with reference to FIG. 163 and will be omitted because they are described with reference to FIGS. 49 and 48 such as a driving method.
[0791]
In the configurations of FIGS. 165, 155, 156, and 163, a reverse current flows through the EL element 15 when the current of the source signal line 18 is taken into the pixel 16. Therefore, when the EL element 15 is an organic electroluminescent element, it is possible to delay the electrochemical deterioration due to the oxidation-reduction reaction of organic molecules, as in the case where a reverse voltage is applied.
[0792]
FIG. 166 shows an energy diagram of a three-layer organic light-emitting device composed of an anode / hole transport layer / light-emitting layer / electron transport layer / cathode. The behavior of positive and negative carriers at the time of light emission is shown in FIG. Electrons are injected from the cathode (cathode) into the electron transport layer, and holes are also injected from the anode (anode) into the hole transport layer. The injected electrons and holes move to the counter electrode by the applied electric field. At this time, carriers are trapped in the organic layer or carriers are accumulated due to a difference in energy level at the light emitting layer interface.
[0793]
When space charge is accumulated in the organic layer, the molecule is oxidized or reduced, and the generated radical anion molecule or radical cation molecule is unstable. It is known to cause an increase in voltage. In order to prevent this, the device structure is changed as an example, and a reverse voltage is applied.
[0794]
In FIG. 166 (b), a reverse current is applied, so that injected electrons and holes are extracted to the cathode and the anode, respectively. Thereby, it becomes possible to extend the lifetime by eliminating the formation of space charge in the organic layer and suppressing the electrochemical degradation of the molecules.
[0795]
In FIG. 166, the three-layer type element is described. However, in the multilayer type element of four layers or more and the element of two layers or less, the electrochemistry of the organic film is caused by electrons and holes injected from the electrodes. It is the same that mechanical degradation occurs. Therefore, the lifetime can be extended by this embodiment regardless of the number of layers. Even in an element in which a plurality of materials are mixed in one layer, the electrochemical deterioration of molecules occurs in the same manner, which is effective.
[0796]
As described above, the feature of the present invention is that even if the pixel has a function of preventing deterioration of organic molecules and a function of flowing a bias current for preventing waveform rounding caused by stray capacitance parasitic on the source signal line, The display is possible without increasing the number of necessary transistors. That is, it is not necessary to increase the number of transistors for flowing a reverse current, which leads to an advantage that the aperture ratio of each pixel of the display device does not need to be reduced.
[0797]
FIG. 167 explains the application effect of the reverse bias voltage Vm. FIG. 167 shows the light emission luminance of the EL element 15 and the terminal voltage of the EL element when driven with a predetermined current. In FIG. 167, a dotted line b indicates the terminal voltage of the EL element 15 when the reverse bias voltage Vm is applied to the EL element 15. An alternate long and short dash line c indicates a terminal voltage of the EL element 15 when the reverse bias voltage Vm is not applied to the EL element 15. The solid line a indicates the emission luminance ratio (ratio when the initial luminance is 1) of the EL element 15 when the reverse bias voltage Vm is applied to the EL element 15 (solid line a).
[0798]
In FIG. 167, specifically, the EL element emits R light and is current-driven at a current density of 100 A / square meter. Sample B is continuously applying a current of 100 A / square meter for a time t. Although the terminal voltage increased at the lighting time of 1500 hours, the luminance dropped rapidly, and after about 2500 hours, only about 15% of the luminance was obtained with respect to the initial luminance.
[0799]
Sample A was pulse-driven at 30 Hz, applied a current density of 200 A / square meter at half time t2, and applied a reverse bias voltage of -14 V at half time t1 (that is, average per unit time). The emission brightness is the same for samples A and B). In sample A, the terminal voltage of the EL element 15 hardly changed as indicated by the dotted line b, and the lighting time when the luminance was 50% was 4000 hours.
[0800]
Thus, even if the reverse bias voltage Vm is applied, the terminal voltage of the EL element 15 does not increase, and the reduction rate of the light emission luminance is small. Therefore, long-life driving of the EL element 15 can be realized.
[0801]
FIG. 168 shows changes in the reverse bias voltage Vm and the terminal voltage of the EL element 15. This terminal voltage is when a rated current is applied to the EL element 15. FIG. 168 shows the case where the current flowing through the EL element 15 is a current density of 100 A / square meter, but the tendency of FIG. 168 is almost the same as the case where the current density is 50 to 100 A / square meter. Therefore, it is estimated that it can be applied in a wide range of current densities.
[0802]
The vertical axis represents the ratio of the terminal voltage after 2500 hours to the terminal voltage of the initial EL element 15. For example, the terminal voltage when a current density of 100 A / square meter is applied at an elapsed time of 0 hours is 8 V, and the terminal voltage when a current density of 100 A / square meter is applied is 10 V at an elapsed time of 2500 hours. Then, the terminal voltage ratio is 10/8 = 1.25.
[0803]
The horizontal axis represents the ratio of the rated terminal voltage V0 to the product of the reverse bias voltage Vm and the time t1 when the reverse bias voltage is applied in one cycle. For example, if the time when the reverse bias voltage Vm is applied is ½ at 60 Hz, t1 = 0.5. In addition, if the terminal voltage (rated terminal voltage) when the current density of 100 A / square meter is applied at an elapsed time of 0 hour is 8 V and the reverse bias voltage Vm is 8 V, | reverse bias voltage × t 1 | / (Rated terminal voltage × t2) = | −8V × 0.5 | / (8V × 0.5) = 1.0.
[0804]
According to FIG. 168, when | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.0 or more, the terminal voltage ratio does not change (it does not change from the initial rated terminal voltage), and the reverse bias voltage Vm The effect of application is well demonstrated. However, since the terminal voltage ratio tends to increase when | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 or more, the reverse bias voltage is 1.0 or more, preferably 1.75 or less. The magnitude of the bias voltage Vm and the application time ratio t1 (or t2, or the ratio between t1 and t2) may be determined.
[0805]
However, when bias driving is performed, it is necessary to alternately apply the reverse bias voltage Vm and the rated current. As shown in FIG. 167, if the average luminance per unit time of samples A and B is to be made equal, when applying reverse bias voltage Vm, it is necessary to flow a higher current instantaneously than when not applying. is there. Therefore, the terminal voltage of the EL element 15 when applying the reverse bias voltage Vm (sample A in FIG. 167) must also be increased.
[0806]
However, in FIG. 168, the rated terminal voltage V0 is a terminal voltage that satisfies the average luminance (that is, a terminal voltage that lights the EL element 15) even in a driving method in which a reverse bias voltage is applied (in the specific example of this specification). Therefore, it is a terminal voltage when a current having a current density of 200 A / square meter is applied (however, since it is ½ duty, the average luminance in one cycle is the luminance at a current density of 200 A / square meter).
[0807]
In addition, although the above matter assumes the case where the EL element 15 is white raster display (when the maximum current is applied to the EL element of the entire screen), when displaying an image of the EL display device, It is a natural image and performs gradation display. Therefore, the white peak current of the EL element 15 (current flowing at maximum white display. In the specific example of the present specification, the average current density of 100 A / square meter) does not always flow.
[0808]
In general, when video display is performed, the current (current flowing) applied to each EL element 15 is white peak current (current flowing at the rated terminal voltage. According to a specific example of the present specification, a current density of 100 A / In the embodiment shown in FIG. 168, when displaying an image, the value on the horizontal axis needs to be multiplied by 0.2. Therefore, the magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or the ratio between t1 and t2) so that | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 0.2 or more. ) Should be determined. Preferably, the magnitude of the reverse bias voltage Vm and the application time ratio t1 are such that | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 × 0.2 = 0.35 or less. It is good to decide.
[0809]
That is, since the value of 1.0 on the horizontal axis (| reverse bias voltage × t1 | / (rated terminal voltage × t2)) in FIG. 168 needs to be 0.2, an image is displayed on the display panel (this (Normally, the white raster will not be displayed at all times.) When the reverse bias voltage × t1 | / (rated terminal voltage × t2) is larger than 0.2, The reverse bias voltage Vm is applied for a predetermined time t1. Further, even if the value of | reverse bias voltage × t1 | / (rated terminal voltage × t2) increases, the terminal voltage ratio does not increase so much as illustrated in FIG. Therefore, considering that white raster display is performed, the upper limit value may be set so that the value of | reverse bias voltage × t1 | / (rated terminal voltage × t2) satisfies 1.75 or less.
[0810]
(Embodiment 11)
Hereinafter, the reverse bias system of the present invention will be described with reference to the drawings. The present invention is basically applied with the reverse bias voltage Vm (current) during a period in which no current flows through the EL element 15, but is not limited thereto. For example, the reverse bias voltage Vm may be forcibly applied while a current is flowing through the EL element 15. In this case, as a result, no current flows through the EL element 15, and the non-lighting state (black display state) will occur. The present invention will be described mainly with respect to the application of the reverse bias voltage Vm in the pixel configuration of the current program, but is not limited to this. For example, if the TFT 11e is turned off in FIG. 87 and the reverse bias voltage Vm is applied to the anode of the EL element 15 in the same manner as in FIG. 169, the reverse bias voltage Vm described below can be obtained even in the pixel configuration of the voltage programming method. Application can be easily realized. Therefore, the effects described in FIG. 168 and the like can be exhibited.
[0811]
FIG. 169 is an explanatory diagram of the driving method of the reverse bias voltage application method of the present invention. In FIG. 169, a switching TFT 11g for applying a reverse bias voltage Vm is arranged or formed in the pixel configuration of FIG. The gate terminal of the switching TFT 11g is connected to the control gate signal line 17d. The reverse bias voltage Vm is applied to the anode of the EL element 15 by turning on the switching TFT 11g.
[0812]
First, as shown in FIG. 170 (a1), when the ON voltage Vgl is applied to the gate signal line 17a, the driving TFT 11b and the capturing TFT 11c are turned ON. Then, as shown in FIG. 170 (a2), the program current Iw flows from the source driver 14 to the capturing TFT 11c and the like, and the capacitor 19 is current-programmed. Although not limited to N times, here, for ease of explanation, it is assumed that a current of N times is programmed and a current Id is allowed to flow through the EL element 15 for a period of 1 F / N.
[0813]
Next, as shown in FIG. 170 (b1), the off voltage Vgh is applied to the gate signal line 17b, and the driving TFT 11b and the capturing TFT 11c are turned off. When the on-voltage Vgl is applied to the gate signal line 17b at the same time (but not simultaneously), the switching TFT 11d is turned on. Then, as shown in FIG. 170 (c2), the power source Vdd flows the current programmed current Id through the conversion TFT 11a to the EL element 15, and the EL element 15 emits light as shown in FIG. 170 (c1). To do. If the program conversion efficiency is 100%, the light emission luminance is about N times as high.
[0814]
The light emission period is 1 F / N. During the remaining 1F (1-1 / N) period, the switching TFT 11d is in an off state, and the EL element 15 is not lit (black display). Since no current flows through the EL element 15 at the time of non-lighting, complete black display can be realized. Further, since the white peak current is large during light emission, the light emission luminance is also high. Therefore, with the driving method of the present invention, a very high contrast display can be realized.
[0815]
When black current is to be realized when a current of 1 times is passed through the EL element 15 (conventional driving method) during the entire period of 1F, the black display current needs to be programmed in the capacitor 19. However, in the current driving method, since the current value at the time of black display is small, there is a problem that black floating occurs due to a large influence of parasitic capacitance and insufficient resolution. In addition, it is also affected by the penetration voltage from the gate signal line 17. Due to these problems, the EL element 15 is slightly turned on even in the black display portion, and the contrast becomes very poor.
[0816]
In the driving method of the present invention, since a current does not flow completely through the EL element 15 during the period of 1F (1-1 / N), a complete black display can be realized. In other words, black float does not occur. Therefore, high-contrast display can be realized without performing the precharge for black display described in FIG.
[0817]
Needless to say, the method illustrated in FIG. 169 may be added to the method illustrated in FIG. 163. The realization of high contrast display is also effective in the voltage program pixel configuration shown in FIG. That is, by performing 1F / N pulse driving, no current flows through the EL element 15 during the period of 1F (1-1 / N), and high contrast display can be realized. Of course, it is possible to realize a good moving image display by intermittently displaying the image.
[0818]
Further, depending on the pixel configuration, when the punch-through voltage acts in the direction of increasing the current flowing through the EL element 15, the white peak current increases and the contrast of the image display increases, so that a good image display can be realized. It becomes like this.
[0819]
As shown in FIG. 170 (d1), an on-voltage is applied to the gate signal line 17d to turn on the switching TFT 11g. At this time, the switching TFT 11d is turned off. By turning on the switching TFT 11g, the anode of the EL element 15 (depending on the pixel configuration, the reverse bias voltage Vm may be applied to the cathode of the EL element 15. The reverse bias voltage Vm is a positive voltage. The reverse bias voltage Vm (reverse bias current Im flows) can be expressed as the EL element 15. Since the EL element 15 can be regarded as a capacitor in terms of circuit, a current flows in an alternating manner by applying the reverse bias voltage Vm. Also, the accumulated charge is discharged). The application time t1 is configured to satisfy the state of FIG. 168 (FIG. 170 (d2)).
[0820]
The period in which the reverse bias voltage Vm is applied is preferably a period in which the current Id does not flow through the EL element 15. This is not impossible, but if the current Id is flowing, the reverse bias voltage Vm is short-circuited.
[0821]
In FIG. 170 (d1), the period for applying the reverse bias voltage Vm is one of 1F. However, the period is not limited to this, and is not limited to this. The reverse bias voltage Vm may be applied to the EL element 15 in three or more times).
[0822]
This control can be easily performed because the on / off voltage may be applied to the gate signal line 17d at an arbitrary timing during the period in which the off voltage is applied to the gate signal line 17b. Then, the sum of these ON times may be set to the time t1 described in FIG.
[0823]
In addition, the period 1F (1-1 / N) in which no current flows through the EL element 15 may be divided into a plurality of periods. By dividing into a plurality, the occurrence of flicker is suppressed. When the period 1F (1-1 / N) is divided into a plurality of periods, the reverse bias voltage Vm may be applied during that period. However, it is not necessary to apply the reverse bias voltage Vm to all of the divided periods 1F (1-1 / N).
[0824]
As shown in FIG. 167, a driving method in which no reverse bias voltage is applied and no current flows through the EL element 15 is corrected (or supplemented) based on the contents described in FIG. The time t1 described in FIG. 168 is the time when the reverse bias voltage Vm is applied. The time t2 is a time during which a current is applied to the EL element 15.
[0825]
Note that the reverse bias voltage Vm does not have to be a fixed value (Vm = −8 V) in terms of DC. That is, the reverse bias voltage Vm may be a sawtooth waveform signal or a pulse-like waveform signal. Moreover, the signal waveform of a sine wave may be sufficient. In this case, the reverse bias voltage is an integrated waveform or an effective value. Further, although the application time t1 is unclear, the integration time of the reverse bias voltage Vm, the effective value is a rectangular waveform, and the time when the rectangular waveform is applied may be t1.
[0826]
For example, it is assumed that the reverse bias voltage waveform is the voltage waveform (triangular wave) illustrated in FIG. 171 (a), the maximum amplitude value is 16V, and the application time is t1 = 100 μsec. In this case, as shown in FIG. 171 (b), this is equivalent to a voltage waveform having a maximum amplitude value of 8V and an application time of t1 = 100 μsec. Further, as illustrated in FIG. 171 (c), the processing may be performed on the assumption that the maximum amplitude value is 16V and the application time is equivalent to a voltage waveform of t1 = 50 μsec. The above matters also apply to the positive voltage applied to the EL element 15.
[0827]
The same applies to the current Id flowing through the EL element 15. That is, the current (voltage) that flows through the EL element 15 may be a sine waveform instead of a direct current. In this case, too, if converted to a direct current effective value and converted to the rectangular wave application period t2. Good.
[0828]
The period during which the reverse bias voltage Vm is applied may be any period other than the period during which the ON voltage is applied to the gate signal line 17a (normally, 1H period: program period), as shown in FIG. 172 (a).
[0829]
Further, since it is sufficient to apply the reverse bias voltage Vm during the period when the current Id is not applied to the EL element 15, as shown in FIG. 172 (b), the period during which the ON voltage is applied to the gate signal line 17a (program The reverse bias voltage Vm may be applied in a period including the period (FIG. 172 (b) shows a period in which the current Id is applied to the EL element 15 (an ON voltage is applied to the gate signal line 17b). The reverse bias voltage Vm is applied in addition to the period of time).
[0830]
Note that the items relating to the application time, application method, application timing, etc. of the reverse bias voltage Vm described in FIGS.
[0831]
As described above, in the present invention, the non-lighting period (non-display area) 312 is provided in the 1F period. By providing this non-lighting period, the moving image display performance is improved, and the EL element 15 is provided in the non-lighting period. A reverse bias voltage Vm can be applied. Therefore, the EL element 15 does not deteriorate and the terminal voltage does not increase, so that the power supply voltage Vdd can be set low.
[0832]
Although FIG. 172 is configured to apply the reverse bias voltage Vm immediately before the EL element 15, as another configuration, as shown in FIG. 173, the reverse bias voltage Vm is reversed to the EL element 15 via the switching TFT 11d. A configuration in which the bias voltage Vm (current −Im) is applied is also exemplified.
[0833]
By applying an on voltage to the gate signal line 17d, the switching TFT 11g is turned on, and the reverse bias voltage Vm is applied. At the same time, the reverse bias voltage Vm can be applied to the EL element 15 by turning on the switching TFT 11d. With the configuration of FIG. 173, the application of the reverse bias voltage Vm can be controlled by both the switching TFTs 11g and 11d, so that the control becomes easy and the flexibility is improved.
[0834]
A turn-on voltage is applied to the gate signal line 17 when the corresponding pixel is selected. The off voltage is applied during the non-selection period. Accordingly, the off-voltage can be used as the reverse bias voltage because the off-voltage is applied to the gate signal line in most of the 1F period.
[0835]
The off voltage is normally a potential lower than the cathode voltage in order to completely turn off the TFT (of course, the opposite is true when the TFT is a P-channel). In particular, when the TFT is amorphous silicon, the off-voltage is usually set to be quite low.
[0836]
In the configuration of FIG. 174, the driving TFT 11b and the capturing TFT 11c connected to the gate signal line 17a are N-channel TFTs. Therefore, the driving TFT 11b and the take-in TFT 11c are turned on at the on voltage Vgh and turned off at the off voltage Vgl. During most of the period of 1F, the off voltage Vgl is applied to the gate signal line 17b. The off voltage Vgl is set as a reverse bias voltage Vm (Vgl = Vm).
[0837]
The switching TFT 11g is also controlled by the voltage applied to the gate signal line 17d, as in the previous embodiment. Note that, since the voltage applied to the gate signal line 17d controls on / off of the switching TFT 11g, the voltage to be applied is not limited to Vgh and Vgl, and other arbitrary voltages are used. Can be used.
[0838]
When the switching TFT 11g is turned on, the off voltage Vgl applied to the gate signal line 17a is applied to the EL element 15. Therefore, the reverse bias voltage Vm can be applied to the EL element 15. In the configuration of FIG. 174, a signal line for supplying the reverse bias voltage Vm is not required as shown in FIG. 173, so that the pixel aperture ratio can be improved. In FIG. 174, the voltage applied to the gate signal line 17b may be applied to the EL element 15 (the switching TFT 11d needs to be configured as an N channel, etc.).
[0839]
FIG. 174 shows a configuration in which the voltage of the gate signal line 17 is a reverse bias voltage. FIG. 175 shows a configuration in which the voltage applied to the source signal line 18 is a reverse bias voltage of the EL element 15. When the reverse bias voltage Vm is applied to the source signal line 18 at the timing when the switching TFT 11 g is turned on, the reverse bias voltage Vm can be applied to the EL element 15 through the source signal line 18. The timing and the like have been described with reference to FIG.
[0840]
When the time for applying the reverse bias voltage Vm is longer than the period in which the current is applied to the EL element 15, the voltage charged in the EL element 15 is discharged as shown in FIG. It is also effective to short-circuit between the anode terminal and the cathode terminal of the EL element 15. By short-circuiting in this way, holes accumulated in the hole transport layer of the EL element 15 are extracted, and electrons accumulated in the electron transport layer are also extracted, so that deterioration of the EL element can be suppressed. . Needless to say, the matters relating to the application time, application method, application timing, etc. of the reverse bias voltage Vm described with reference to FIGS. 172, 170, etc. also apply to the embodiment of FIG.
[0841]
In FIG. 176, each TFT is configured by the P channel, but in FIG. 177, the configuration of FIG. 176 is changed to the N channel. In FIG. 177, when the switching TFT 11g is turned on, the anode terminal and the cathode terminal of the EL element 15 are short-circuited, and the Vdd voltage is applied to both terminals. During this period, holes accumulated in the hole transport layer of the EL element 15 are extracted, and electrons accumulated in the electron transport layer are also extracted, so that deterioration of the EL element can be suppressed. As in FIG. 176, it goes without saying that the matters relating to the application time, application method, application timing, etc. of the reverse bias voltage Vm described in FIG. 172, FIG.
[0841]
Further, the reverse bias voltage Vm can be applied to the EL element 15 by changing the control direction in which the current flows. FIG. 178 is a configuration diagram thereof. Reference numeral 402 in FIG. 178 denotes a constant current source.
[0843]
In FIG. 178, when the switching TFT 11g is on, a current in the same direction as the constant current source 402 flows through the switching TFT 11g, and a forward voltage is applied to the EL element 15. On the other hand, when the switching TFT 11g is off, the EL element 15 and the constant current source 402 form a loop, so the direction of the current flowing through the EL element 15 is reversed. That is, by arranging or forming the constant current source 402, the reverse bias voltage Vm can be easily applied to the EL element 15 under the control of the switching TFT 11g. The timing of the gate signal line 17 at this time is shown in FIG. The on-voltage is applied to the gate signal line 17d during a period other than the period when the gate signal line 17a is selected. In this way, holes accumulated in the hole transport layer of the EL element 15 are extracted, and electrons accumulated in the electron transport layer are also extracted, thereby suppressing deterioration due to oxidation of the hole transport material and reduction of the electron transport material. become able to.
[0844]
In FIG. 180, the switching TFT 11g is an N channel, the switching TFT 11g is turned off when the switching TFT 11d is turned on, and the switching TFT 11g is turned on when the switching TFT 11d is turned off. . When the switching TFT 11d is on, the EL element 15 is lit, and when the switching TFT 11g is on, the reverse bias voltage Vm is applied to the EL element 15.
[0845]
It is effective to set the reverse bias voltage Vm to a voltage lower than the cathode voltage Vk. However, if a reverse bias voltage Vm is separately generated, a generation circuit is required. To solve this problem, a flying capacitor is formed in FIG. The flying capacitor 1001 may be disposed (formed) for each pixel, or one circuit may be disposed (formed) on the panel.
[0846]
The flying capacitor 1001 is operated by controlling the gate signal lines 17e and 17f. The gate signal line 17e and the gate signal line 17f are operated in opposite phases.
[0847]
First, an on voltage is applied to the gate signal line 17e, the TFTs 11i and 11j are turned on, and a Vdd voltage is applied to the capacitor 19b. At this time, a turn-off voltage is applied to the gate signal line 17f, and after charging the capacitor 19b, the TFTs 11h and 11k are turned off.
[0848]
Next, an off voltage is applied to the gate signal line 17e to turn off the TFTs 11i and 11j, and an on voltage is applied to the gate signal line 17f to turn on the TFTs 11h and 11k. Then, the Vdd voltage charged in the capacitor 19 b has an opposite phase, and the −Vdd voltage is applied to the EL element 15.
[0849]
With the configuration described above, an antiphase Vm voltage (Vm = −Vdd) can be generated. Therefore, the supply wiring for the Vm voltage is not necessary.
[0850]
The above embodiment has been described mainly by exemplifying the pixel configuration of the current programming method described with reference to FIG. 6, but the present invention is not limited to this, and as shown in FIG. Needless to say, the bias voltage Vm can be applied. The operation is omitted because the configuration described in FIG. 169 can be applied as it is. Further, as shown in FIG. 183, it is needless to say that a reverse bias voltage can be applied even in a pixel configuration of voltage programming. The same applies to FIG. 87 and the like. Therefore, a configuration or a system in which a reverse bias voltage is applied to the EL element 15 at the time of non-lighting can be applied even with a voltage programmed pixel configuration.
[0851]
In the above embodiments, the present invention has been described on the assumption that the reverse bias voltage Vm is applied to the EL element 15 when not lit. This is not limited to displaying the display screen 21 and applying the reverse bias voltage Vm to the EL element 15 when the EL element 15 is not lit. In the active matrix EL display panel, a configuration in which the reverse bias voltage Vm is constantly applied when not lit is also within the scope of the present invention.
[0852]
For example, the reverse bias voltage Vm may be applied to the EL elements 15 of the entire display screen 21 for a predetermined period after the use of the EL display panel is completed. Alternatively, the reverse bias voltage Vm may be applied by sequentially scanning the EL elements 15 of the entire display screen 21 for a predetermined period after the use of the EL display panel is finished. Further, when the EL display panel is used (for example, when the power is turned on), the reverse bias voltage Vm may be applied by sequentially scanning the EL elements 15 of the entire display screen 21 for a predetermined time. . Further, when the EL display panel is not used, the reverse bias voltage Vm may be applied every predetermined time interval (for example, every 10 hours, for example, 10 seconds). Conversely, when the EL display panel is used, the reverse bias voltage Vm may be applied at predetermined time intervals (for example, 10 seconds every hour).
[0853]
In FIG. 159, there are five TFTs 11 constituting the pixel. However, in FIG. 6A, there are four. Therefore, the configuration of FIG. 6A has an advantage that the aperture ratio can be increased and the rate of occurrence of pixel defects is small because the number of TFTs 11 constituting the pixel 16 is smaller by one.
[0854]
FIG. 162 also shows a pixel configuration of a current programming method. A current program can be performed by applying an ON voltage to the gate signal line 17a. Further, a programmed current can be supplied to the EL element 15 by applying an off voltage to the gate signal line 17b and applying an on voltage to the gate signal line 17b.
[0855]
In the configuration of FIG. 162 as well, by applying an on voltage or an off voltage to the gate signal line 17c, the current flowing through the EL element 15 can be controlled, and the driving method or display state illustrated in FIG. 49 and the like can be realized.
[0856]
Although the TFT 11e is added in FIG. 162, it goes without saying that the image display of FIG. 49 and the like can also be realized by deleting the TFT 11e, operating the gate signal line 17b, and controlling the on / off state of the switching TFT 11d. Yes.
[0857]
FIG. 184 also shows a current programming pixel configuration. A current program can be performed by applying an ON voltage to the gate signal line 17a. Further, a programmed current can be supplied to the EL element 15 by applying an off voltage to the gate signal line 17b and applying an on voltage to the gate signal line 17b.
[0858]
In the configuration of FIG. 184 as well, the on / off state of the switching TFT 11d can be realized by applying an on voltage or an off voltage to the gate signal line 17c, so that the current flowing through the EL element 15 can be controlled. Therefore, the driving method or display state illustrated in FIG. 49 and the like can be realized.
[0859]
FIG. 81 shows an example of the pixel configuration of the voltage program. In the present invention, a predetermined light emission luminance can be obtained by controlling the application time of the current flowing in the EL element 15 in a predetermined time of one field or one frame (1F, of course, 2F or more can be considered as one segment). How to get. That is, this is a method of obtaining a predetermined luminance by making the current passed through the EL element higher than a predetermined luminance and shortening the ON time for the luminance higher than the predetermined luminance.
[0860]
FIG. 87 also shows a pixel configuration by a voltage program. In FIG. 87, 19a is a threshold detection capacitor (capacitor), and 19b is an input signal voltage holding capacitor (capacitor).
[0861]
In step 1 (section 1), since all the TFTs 11a to 11e are turned on and the driving transistors are once turned on, a current value shift occurs due to variations in threshold values.
[0862]
In step 2 (section 2), the current value of the driving TFT 11a becomes 0 by turning off the TFT 11c and TFT 11e while keeping the TFT 11b and TFT 11d on, so that the threshold value of the driving TFT 11a becomes the threshold value. It is detected by the detection capacitor 19a.
[0863]
In step 3 (section 3), the TFT 11b and TFT 11d are turned off and the TFT 11c and TFT 11e are turned on to hold the input signal voltage of the data signal line in the input signal voltage holding capacitor 19b and at the same time the driving A signal voltage obtained by adding a threshold to the input signal voltage is applied to the gate of the TFT 11a for driving the EL element 15 to emit light. Since the driving TFT 11a operates in the saturation region, a current proportional to the square of the voltage value obtained by subtracting the threshold value from the gate voltage flows, but the threshold value is already applied to the gate voltage by the threshold detection capacitor 19a. As a result, the threshold value is canceled as a result. Therefore, even if the threshold value of the driving TFT 11a varies, a constant current value always flows to the EL element 15 as shown in the simulation result.
[0864]
In step 4 (section 4), when the pixel 16 enters the non-selection period, the TFT 11b and the TFT 11d are turned off, the TFT 11e is kept on, and the TFT 11c is turned off, and is held in the input signal voltage holding capacitor 19b. Since the input signal voltage and the threshold voltage held by the threshold detection capacitor 19a are applied to the gate of the driving TFT 11a, a current flows through the EL element 15 and the light continues to be emitted.
[0865]
As described above, in order to detect the threshold value of the driving transistor more accurately, the period of the first step is set to 2 μsec or more and 10 μsec or less, and the period of the second step is set to 2 μsec or more and 10 μsec or less. is necessary. This is to ensure sufficient writing or operation time. However, if it is too long, the original voltage programming time is shortened and stability is lost.
[0866]
Therefore, the voltage programming method of FIG. 81 is also effective for implementing the driving method or display device of the present invention. In FIG. 81, the switching TFT 11d can be turned on and off by controlling the gate signal line 17b. Therefore, the current flowing through the EL element 15 can be made intermittent. Also in FIG. 87, the TFT 11e can be controlled to be turned on / off by controlling the gate signal line 17c. Therefore, the display states shown in FIGS. 49 and 53 can be realized.
[0867]
In addition, the current flowing through the EL element 15 is multiplied by N and the on / off state of the TFT 11e is controlled to light up for a period of 1 / N (not limited to N times or 1 / N). It is clear that can be realized. In other words, the present invention is not limited to the pixel configuration of the current program of FIG. 6, and the driving method of the present invention can be realized even with the pixel configuration of the voltage program such as FIG. Therefore, the matters described in this specification can be applied to the pixel configuration or device described or illustrated in this specification.
[0868]
Similarly, FIG. 85 and FIG. 86 also show the pixel configuration of the voltage program. 85 and 86, the TFT 11e can be turned on and off by controlling the gate signal line 17b. Therefore, the current flowing through the EL element 15 can be made intermittent. Therefore, the display states shown in FIGS. 49 and 53 can be realized. Therefore, an animation effect can be easily realized. Various image displays can be realized. Other items or operations are the same as or similar to those in FIG. Needless to say, the above items can also be applied to the reverse bias voltage Vm application method described in FIG. 163, FIG.
[0869]
For example, the reverse bias voltage Vm may have a different voltage value for each of the R, G, and B pixels. In that case, the number of gate signal lines of the TFT for controlling the reverse bias voltage Vm increases. This is because the R, G, and B EL elements 15 have different terminal voltages and applied currents. For example, -15V is applied to the EL element of the R pixel, and -12V is applied to the EL elements of the G and B pixels.
[0870]
The application time of the reverse bias voltage (current) applied to the R, G, and B EL elements 15 may be varied. This is because the terminal voltage and the applied current are different for each RGB pixel. For example, the reverse bias voltage Vm is applied to the EL element of the R pixel for 1/2 time of 1F, and the reverse bias voltage Vm is applied to the EL element of the G and B pixels for 1/3 time of 1F. This is the method.
[0871]
Further, the application time or applied voltage of the reverse bias voltage (current) may be varied for each portion of the display screen 21. For example, when the Gaussian distribution method for brightening the central portion of the display screen is adopted, the EL element in the central portion has a larger current value to flow than the peripheral portion.
[0872]
As a problem of the method of applying N times the pulse voltage, there is a problem that the current flowing through the EL element 15 increases and the EL element 15 is likely to deteriorate. Further, when N = 10 or more, there is a problem that the terminal voltage of the EL element 15 required when a current flows becomes high and power efficiency is deteriorated. However, this problem occurs when the current flowing through the EL element is large as in white display. A solution to this problem will be described with reference to FIG. 185 (a), taking the pixel configuration of FIG. 6 as an example.
[0873]
As shown in FIG. 185 (a), when the current Idd to the EL element 15 flows, the Vdd voltage (power supply voltage) is the source-drain voltage Vsd of the driving TFT 11a and the terminal voltage Vd of the EL element 15. Divided pressure. At this time, if the Idd current is large, the Vd voltage also increases.
[0874]
When the Vdd voltage is sufficiently high, a current Idd equal to the current Iw programmed in the driving TFT 11a flows through the EL element 15. Therefore, as shown by the solid line in FIG. 186, the currents Iw and Idd are equal or substantially linear (proportional relationship). The linear relationship means that a penetration occurs in the capacitor 19 due to a signal applied to the gate signal line 17 and the like, and Idd = Iw is not established.
[0875]
In the present invention, the Vdd voltage is used at such a low voltage that Idd and Iw cannot maintain a linear (proportional) relationship. That is, the necessary relationship is Vsd + Vd> Vdd. Furthermore, it is preferable that Vd> Vdd.
[0876]
For example, as an example, assume that N = 10 and the Iw current necessary for maximum white display is 2 μA. In this state, if the Idd current is 2 μA, Vd = 14V in the G color EL element, and the Vdd voltage at this time is set to 14V or less. Alternatively, at this time, if Vsd = 7V, Vd + Vsd = 14V + 7V = 21V <Vdd = 21V.
[0877]
When driven in this state, the relationship between the currents Idd and Iw is as shown by the dotted line in FIG. 186, and in the maximum white display, the relationship between Iw and Idd is not a linear relationship (nonlinear relationship, range A in FIG. 186). ). However, the linear relationship (range B in FIG. 154) is maintained in black display or gray display (region where display luminance is relatively low).
[0878]
In the region A, the current flowing through the EL element 15 is limited, and a large current that deteriorates the EL element 15 does not flow. Further, when the Iw current is increased in the area A, the change rate is small but the Idd current increases, so that gradation display can be realized. However, since it is non-linear in the area A, gamma conversion is necessary. For example, if the image display is 64 gradation display, the input image data 64 gradation data is converted into a table, converted into 128 gradations or 256 gradations, and applied to the source driver 14.
[0879]
In the region A, the Vsd voltage of the driving TFT 11a and the Vd voltage of the EL element 15 are divided, and the terminal voltage Va of the EL element 15 is determined. At this time, as a matter to be noted, the EL element 15 is formed uniformly by vapor deposition (or formed by application by an ink jet technique or the like), so that it is formed uniformly. Therefore, the EL terminal voltage Va becomes a uniform value within the surface of the display screen 21. Therefore, the characteristics of the driving TFT 11a vary and are corrected by the terminal voltage Va of the EL element 15. As a result, by reducing the Vdd voltage as in the present invention, variations in characteristics of the driving TFT 11a can be absorbed, and low power consumption can be realized by reducing the Vdd voltage. Even when N is large, a high voltage is not applied to the EL element 15.
[0880]
The EL element 15 can be formed not only by a vapor deposition technique and an ink jet technique, but also by a stamp technique in which an inked stamp is applied to paper and printed.
[0881]
First, a portion to be a stamp is formed. A groove pattern having the same shape as the light emitting region of the organic EL element is formed on the Si substrate by a semiconductor process, and a material for doping the organic EL material is filled in the groove to obtain a stamp. On the other hand, an organic EL material to be an electrode or a light emitting layer is formed on the glass substrate on which the organic EL element is formed.
[0882]
Next, the stamp and the glass substrate to which the material for the organic EL element is attached are exactly overlapped. While maintaining this state, heat treatment is performed at + 100 ° C. to + 200 ° C. for about 10 minutes. By doing so, the doping material embedded in the stamp groove evaporates and diffuses into the light emitting layer of the organic EL element. After that, a stamp in which a doping material corresponding to the color is embedded is sequentially applied to the organic EL element, and RGB is separately applied. By using this stamp technology, an EL element 15 having a rectangular pattern of 10 μm or a pattern having a line width of 10 μm can be easily formed.
[0883]
In addition, a current is applied to the EL element 15 at 1 / N of the period of 1F, the applied current is higher than a predetermined luminance, and a luminance higher than the predetermined is obtained by shortening the ON time to obtain the predetermined luminance. It was supposed to be. However, the present invention is a method of setting the average brightness within a certain period to a predetermined value. Therefore, it is not limited to 1F (1 field or 1 frame). For example, the display state of FIG. 53 (c1) continues for 2F, the display state of FIG. 53 (c2) continues for 3F, or the states of FIG. 53 (c1) and FIG. 53 (c2) are alternately repeated. Also good. Finally, it may be driven so as to obtain a desired average luminance at 5F.
[0884]
Therefore, the technical idea of the present invention is to generate an ON state and an OFF state of the EL element 15 within a certain period, and alternately repeat the ON state and the OFF state. It is a method to obtain. Control is realized by controlling the on / off voltage of the gate signal line 17.
[0885]
Although a current N times the predetermined current is supplied to the source signal line 18 and a current N times the predetermined current is supplied to the EL element 15 for 1 / N period, this cannot be realized in practice. This is because the signal pulse applied to the gate signal line 17 actually penetrates the capacitor 19 and a desired voltage value (current value) cannot be set in the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set for the capacitor 19. For example, even if it is driven to set a current value 10 times, only about 5 times the current is set in the capacitor 19. Even if N = 10, the current that actually flows through the EL element 15 is the same as in the case of N = 5. Therefore, the present invention is a method of setting a current value of N times and driving so that a current proportional to or corresponding to N times flows to the EL element 15 (however, the driving method described in FIG. 186 is also implemented). Limited is difficult). Alternatively, it is a driving method in which a current larger than a desired value is applied to the EL element 15 in a pulse shape.
[0886]
Further, a current (voltage) program is performed on the driving TFT 11a (in the case of FIG. 6) with a current that is higher than a desired value (a current that is higher than the desired luminance when current is continuously passed through the EL element 15). The light emission luminance of the desired EL element is obtained by intermittently flowing the current flowing through the EL element 15.
[0887]
Further, if FIG. 6 is shown as an example (which is also effective in the voltage program pixel configuration shown in FIGS. 142, 85, 86, 183, 87, etc.), the driving TFT 11a and a signal for programming the driving TFT ( A first switching TFT 11c for setting (configuration, arrangement, connection), and a second switching for setting (configuration, arrangement, connection) through which the current from the driving TFT 11a flows to the EL element 15. In the pixel configuration including the TFT for driving 11d, the driving TFT is in a first state in which the first switching TFT 11c is turned on (path is set) and the second switching TFT 11d is turned off (path is cut). A first state in which current (voltage) is programmed into the first switching TFT 11c, the first switching TFT 11c is turned off (the path is disconnected), and the second switching A second state in which the TFT 11d for switching is turned on (a path is set), and a third state in which the first switching TFT 11c is turned off (a path is disconnected) and the second switching TFT 11d is turned off (a path is disconnected) And implement.
[0888]
In the active matrix display panel, the current path flowing from the driving TFT 11a to the EL element 15 is cut or reduced for a predetermined period of one frame (one field) period (the current waveform flowing to the EL element 15 is rectangular or DC). There is also a sine waveform, etc. Further, the DC amplitude value may be changed) to reduce the light emission luminance of the EL element 15 of at least one frame (one field).
[0889]
In addition, the driving TFT 11a is programmed so that the EL element 15 emits light with a luminance higher than a desired value, and the programmed signal (current) is supplied to the EL element 15 so as to have at least one frame (one field) period. The operation is performed so as not to flow to the EL element 15 during a predetermined period.
[0890]
Alternatively, the current flowing through the EL element 15 is limited so that the luminance is equal to or lower than the luminance corresponding to the current programmed in the driving TFT 11a.
[0891]
Further, the operation for performing the programming so that the EL element 15 emits light with a luminance higher than the desired value and the average luminance (desired luminance) of one frame (one field) are the desired luminance or at least the desired luminance (programmed luminance) (Current)) The operation is performed so that the program current does not flow to the EL element 15 so as to be as follows. Further, the present invention is not limited to completely turning on and off the current flowing through the EL element 15.
[0892]
For example, when the switching TFT 11d is turned on in a high resistance state in FIG. 6 (that is, a current smaller than a predetermined value flows through the EL element 15), the EL element 15 is turned off or low luminance light emission is performed. it can. When the EL element 15 emits light with low luminance, the non-display area 312 of the display screen 21 needs to be understood by replacing it with dark (gray or luminance close to black display) instead of complete black display. That is, the non-display area 312 may be a display with lower luminance than the normal display. Low luminance display includes a display state in which an image can be recognized.
[0893]
In the above embodiment, it is effective to combine the application of a reverse bias voltage during the non-lighting time of the EL element 15 (see FIGS. 170, 168, etc.). It goes without saying that the present invention is also effective for the voltage program pixel configuration shown in FIG.
[0894]
In FIG. 49 and the like, the non-display area 312 does not need to be completely in a non-lighted state. There is no problem in practical use even if weak light emission or light image display is present. That is, it should be interpreted that the display luminance is lower than that of the image display area 311. In addition, the non-display area 312 includes a case where only one or two colors of the R, G, and B image displays are in a non-display state.
[0895]
In each pixel configuration (for example, FIG. 81, FIG. 158, FIG. 184 (a)), even when the gate terminal of the switching TFT 11d can be directly applied to the on / off voltage, Intermittent operation is possible. Further, even if the on / off voltage can be directly applied to the gate terminal of the TFT 11e in FIG. 159, the conversion TFT 11a in FIG. 19, and the driving TFT 11b in FIG. 20, the current flowing through the EL element 15 is intermittently operated. Can be made. In other words, the display state shown in FIG. 49 can be implemented by controlling the gate terminal of the TFT that applies current to the EL element 15.
[0896]
As described above, according to the present invention, the EL element 15 is intermittently displayed by turning on and off the current applied to the EL element 15. In order to perform intermittent display, it is necessary to turn on and off the switching TFT 11d in the example of FIG. Therefore, a gate signal line for turning on / off the switching TFT 11d is required. That is, in order to display the EL element 15 intermittently, a first switching element that forms a path for programming a current flowing through the EL element 15 in the capacitor, and an on / off control for the first switching element. A first gate signal line is required. Further, a second switching element that forms a current path flowing through the EL element 15 and a second gate signal line for turning on and off the second switching element are required. That is, two gate signal lines are required per pixel.
[0897]
However, when two or more gate signal lines are required per pixel, the three-side free pixel configuration described with reference to FIG. This is because even if the gate driver 12 is formed by low-temperature polysilicon technology or the like, the number of shift registers increases and the circuit configuration becomes complicated. In particular, when an attempt is made to realize a three-side free configuration with amorphous silicon technology, the problem becomes even greater. This is because the gate driver 12 (or the source driver 14) cannot be formed directly on the display panel 82 with amorphous silicon technology.
[0898]
Therefore, in order to configure a display panel using the amorphous silicon technology, it is necessary to arrange the source driver 14 and the gate driver 12 on one side of the display screen 21. Then, all of the gate signal line 17a and the gate signal line 17b need to be wired separately on the left and right sides of the display screen. If the number of gate signal lines 17 is small, there is a possibility that it can still be dealt with. However, since the number of vertical pixels is 220 dots even in QCIF, the number of gate signal lines 17 is 220 × 2 = 440. In addition, even when the gate driver 12 is built in the low-temperature polysilicon technology, if the number of the gate signal lines 17 is large, the frame cannot be narrowed. Therefore, the product power is lost.
[0899]
The present invention described below solves the above problems. In short, a plurality of gate signal lines 17b for turning on and off the EL element 15 are made common. The current flowing through the EL element 15 is turned on and off for each common block.
[0900]
45 and 116, it is not necessary to control on / off of the EL elements 15 for each pixel row. This is because the non-display area 312 can be formed and the image display area 311 can also be formed even if each block is turned on / off. A method of performing on / off control in a block as described above is called block driving. However, since there is an embodiment in which blocks are formed by adjacent pixel rows, it is broader than the concept of normal blocks. However, in the pixel configuration of FIG. 6, the pixel row for which current programming is performed needs to be in a non-lighted state. Therefore, a block including a pixel row selected for current programming needs to be a non-display area 312. However, even in the case of FIG. 6, it is not necessary to set the non-display area 312 even in the pixel row for which current programming is performed when the sag is allowed in some images. In the pixel configuration of the current mirror in FIG. 19, it is not necessary to set the non-display area 312 even in the pixel row for which current programming is performed.
[0901]
The present invention will be mainly described by exemplifying the pixel configuration of the current program illustrated in FIG. 6, but is not limited to this. Other current program configurations described in FIG. 19 and the like (pixels of the current mirror) (Configuration). Further, the technical concept of turning on / off in a block can be applied even to the pixel configuration of the voltage program shown in FIGS. Further, since the present invention is a method of intermittently flowing the current flowing through the EL element 15, it can be combined with the method of applying the reverse bias voltage described with reference to FIG. As described above, the present invention can be implemented in combination with other embodiments.
[0902]
FIG. 187 shows an example of block driving. First, for ease of explanation, it is assumed that the gate driver 12 is formed directly on the array substrate 49 or that the silicon chip gate driver 12 is mounted on the array substrate 49. Further, the source driver 14 and the source signal line 18 are omitted because the drawing becomes complicated.
[0903]
In FIG. 187, the gate signal line 17a is connected to the gate driver 12. On the other hand, the gate signal line 17b of each pixel is connected to the lighting control line 1791. In FIG. 187, four gate signal lines 17b are connected to one lighting control line 1791. The blocking with the four gate signal lines 17b is not limited to this, and may be more than that. Generally, the display screen 21 is preferably divided into at least 5 or more, and further 10 or more. Furthermore, it is preferable to divide into 20 or more. This is because if the number of divisions is small, flicker is easily visible, and if the number of divisions is too large, the number of lighting control lines 1791 increases, and the layout of the lighting control lines 1791 becomes difficult.
[0904]
Therefore, in the case of a QCIF display panel, since the number of vertical scanning lines is 220, it is necessary to block at least 220/5 = 44 or more, preferably 220/10 = 11 or more. However, when two blocks are formed on the odd and even lines, the occurrence of flicker is relatively small even at a low frame rate, and thus two blocks may be sufficient.
[0905]
In the embodiment of FIG. 187, the turn-on voltage Vgl or the turn-off voltage Vgh is sequentially applied to the lighting control lines 1791a, 1791b, 1791c, and 1791d to turn on and off the current flowing through the EL element 15 for each block.
[0906]
In the embodiment of FIG. 187, the gate signal line 17b and the lighting control line 1791 do not cross each other. Therefore, a short defect between the gate signal line 17b and the lighting control line 1791 does not occur. Further, since the gate signal line 17b and the lighting control line 1791 are not capacitively coupled, the capacitance addition when the gate signal line 17b side is viewed from the lighting control line 1791 is extremely small. Therefore, it is easy to drive the lighting control line 1791.
[0907]
FIG. 188 illustrates the connection state of FIG. 187 in more detail. A gate signal line 17 a is connected to the gate driver 12. By applying an on voltage Vgl to the gate signal line 17a, a pixel row is selected, the TFTs 11b and 11c of each selected pixel are turned on, and the current (voltage) applied to the source signal line 18 is supplied to each pixel. Program the capacitor 19. On the other hand, the gate signal line 17b is connected to the gate terminal of the TFT 11d of each pixel. Therefore, when the on voltage Vgl is applied to the lighting control line 1791, a current path is formed between the driving TFT 11a and the EL element 15, and conversely, when the off voltage Vgh is applied, the anode terminal of the EL element 15 is connected. Open.
[0908]
It is preferable that the control timing of the on / off voltage applied to the lighting control line 1791 and the timing of the pixel row selection voltage Vgl output from the gate driver 12 to the gate signal line 17a are synchronized with one horizontal scanning clock (1H). . However, it is not limited to this. A signal applied to the lighting control line 1791 simply turns on and off the current to the EL element 15. Further, it is not necessary to be synchronized with the image data output from the source driver 14. This is because the signal applied to the lighting control line 1791 controls the current programmed in the capacitor 19 of each pixel 16. Therefore, it is not necessarily required to be synchronized with the pixel row selection signal. Even in the case of synchronization, the clock is not limited to the 1H signal, and may be 1 / 2H or 1 / 4H.
[0909]
FIG. 189 shows a case where the pixel configuration is that of the current mirror shown in FIG. However, as described in the previous embodiment, in order to control the current flowing through the EL element 15, the TFT 11e is formed, and the gate signal line 17b for controlling the TFT 11e is added.
[0910]
In FIG. 189, the gate signal line for controlling (turning on and off) the capture TFT 11c and the switching TFT 11d is the same (gate signal line 17a), but the present invention is not limited to this. It is good. In this case, the first gate signal line 17 that controls the take-in TFT 11c and the second gate signal line 17 that controls the switching TFT 11d are connected to the gate driver 12.
[0911]
In FIG. 189, a gate signal line 17a is connected to the gate driver 12. A pixel row is selected by applying an ON voltage to the gate signal line 17a. Note that the same applies to FIG. 188 and the like, but the selected pixel row is not limited to one pixel row. For example, in FIG. 94, FIG. 118, and FIG. 121, a plurality of pixel rows are selected. As described above, the present invention is not limited to the number of selected pixel rows.
[0912]
In FIG. 189, when the on-voltage Vgl is applied to the gate signal line 17a, the driving TFT 11b and the switching TFT 11d of each selected pixel are turned on, and the current (voltage) applied to the source signal line 18 is changed to each. The pixel capacitor 19 is programmed. That is, the source driver 14 outputs (absorbs) a current (voltage) written to the pixel 16. On the other hand, the gate signal line 17b is connected to the gate terminal of the TFT 11e of each pixel. Therefore, when the on voltage Vgl is applied to the lighting control line 1791, a current path is formed between the driving TFT 11b and the EL element 15, and conversely, when the off voltage Vgh is applied, the anode terminal of the EL element 15 is connected. Open.
[0913]
FIG. 190 shows a pixel configuration of a voltage program. However, as described in the previous embodiment, the switching TFT 11d is formed in order to control the current flowing in the EL element 15 (so that it can be intermittently operated), and the gate signal for controlling the switching TFT 11d. A line 17b is added. The gate signal line 17b is connected to a lighting control line 1791 for each of a plurality of pixel rows.
[0914]
In FIG. 190, a gate signal line 17a is connected to the gate driver 12. By applying an on voltage to the gate signal line 17a, the driving TFT 11b is turned on, and a predetermined pixel row is selected.
[0915]
In FIG. 190, when the on voltage Vgl is applied to the gate signal line 17a, the driving TFT 11b of each selected pixel is turned on, and the current (voltage) applied to the source signal line 18 is supplied to the capacitor 19 of each pixel. To program. That is, the source driver 14 outputs (absorbs) a current (voltage) written to the pixel 16. On the other hand, the gate signal line 17b is connected to the gate terminal of the switching TFT 11d of each pixel. Therefore, when the on voltage Vgl is applied to the lighting control line 1791, a current path is formed between the driving TFT 11a and the EL element 15, and conversely, when the off voltage Vgh is applied, the anode terminal of the EL element 15 is connected. Open.
[0916]
FIG. 191 shows another voltage program pixel configuration, in which an intermittent operation of the current flowing through the EL element 15 is performed using the switching TFT 11d. A gate signal line 17d for controlling the switching TFT 11d is connected to a lighting control line 1791 for each of a plurality of pixel rows.
[0917]
In the pixel configuration of FIG. 191, two gate signal lines 17a and 17c are required to measure the offset voltage and hold the voltage written in one frame period in the capacitor 19. For this reason, the two gate signal lines 17 a and 17 c are connected to the gate driver 12. This configuration is illustrated in FIG. The gate driver 12 applies on / off voltages to the gate signal line 17a and the gate signal line 17c, thereby turning on and off the capturing TFT 11c and the driving TFT 11b, and programs the voltage output from the source driver 14 into the pixel. On the other hand, the gate signal line 17d is connected to the gate terminal of the switching TFT 11d of each pixel. Therefore, when the on voltage Vgl is applied to the lighting control line 1791, a current path is formed between the driving TFT 11a and the EL element 15, and conversely, when the off voltage Vgh is applied, the anode terminal of the EL element 15 is connected. Open.
[0918]
As described above, the present invention can be applied regardless of whether the pixel configuration is a current program system or a voltage program system. Although the above embodiment has been described by exemplifying an active matrix display panel, the present invention is not limited to this and can be applied to a simple matrix display panel. This is because lighting or non-lighting of the EL element 15 for each block can be realized even with a simple matrix display panel.
[0919]
FIG. 193 shows another embodiment. In the following embodiment, the difference from the above-described embodiment will be mainly described. Accordingly, in the embodiments after FIG. 193, any of the pixel configurations described in FIGS. 189 to 191 can be applied.
[0920]
FIG. 193 shows a configuration in which the gate signal line 17b is shared by two pixel rows and the lighting control line 1791 is shared every four blocks. The gate signal lines 17b of the first and second pixel rows and the gate signal lines 17b of the ninth and tenth pixel rows are shared by the lighting control line 1791a. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791a, at least the first, second, ninth and tenth pixel rows are lit.
[0921]
In addition, the gate signal line 17b of the third and fourth pixel rows and the gate signal line 17b of the eleventh and twelfth pixel rows are shared by the lighting control line 1791b. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791b, at least the third, fourth, eleventh and twelfth pixel rows are lit.
[0922]
Similarly, the gate signal lines 17b of the fifth and sixth pixel rows and the gate signal lines 17b of the thirteenth and fourteenth pixel rows are shared by the lighting control line 1791c. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791c, at least the fifth, sixth, thirteenth and fourteenth pixel rows are lit. The gate signal lines 17b of the seventh and eighth pixel rows and the gate signal lines 17b of the fifteenth and sixteenth pixel rows are shared by the lighting control line 1791d. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791d, at least the seventh, eighth, fifteenth and sixteenth pixel rows are lit.
[0923]
As shown in FIG. 193, when the gate signal line 17b is connected to the lighting control line 1791, small lighting blocks are displayed in a dispersed manner. Therefore, the occurrence of flicker is reduced even at a low rate.
[0924]
FIG. 194 shows a configuration in which the gate signal line 17b is connected to the lighting control line 1791 in common with four pixels. The gate signal lines 17b of the first, fifth, ninth, and thirteenth pixel rows are shared by the lighting control line 1791a. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791a, at least the first, fifth, ninth and thirteenth pixel rows are lit.
[0925]
Further, the gate signal lines 17b of the second, sixth, tenth, and fourteenth pixel rows are shared by the lighting control line 1791b. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791b, at least the second, sixth, tenth and fourteenth pixel rows are lit.
[0926]
Similarly, the gate signal lines 17b of the third, seventh, eleventh, and fifteenth pixel rows are shared by the lighting control line 1791c. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791c, at least the third, seventh, eleventh and fifteenth pixel rows are lit. In addition, the gate signal lines 17b of the fourth, eighth, twelfth, and sixteenth pixel rows are shared by the lighting control line 1791d. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791d, at least the fourth, eighth, twelfth and sixteenth pixel rows are lit.
[0927]
As shown in FIG. 194, when the gate signal line 17b is connected to the lighting control line 1791, pixel rows that are lit up are distributed more than in FIG. Therefore, the occurrence of flicker is reduced even at a low rate.
[0928]
FIG. 195 shows a configuration in which the gate signal line 17b in the odd pixel row is connected to the lighting control line 1791a, and the gate signal line 17b in the even pixel row is connected to the lighting control line 1791b.
[0929]
In FIG. 195, since the EL element 15 can be controlled to be turned on every pixel row, the occurrence of flicker is reduced even at a low rate. Further, the number of lighting control lines 1791 is reduced to two.
[0930]
FIG. 196 shows a configuration in which the gate signal line 17b is connected to the lighting control line 1791a or the lighting control line 1791b every four pixel rows. In FIG. 196, it is easy to synchronize with the timing of current (voltage) programming to the pixel.
[0931]
The above embodiment performs on / off control for each pixel row by the voltage applied to the lighting control line 1791, and the present invention aims to cause the EL element 15 to operate intermittently. Therefore, the present invention is not limited to the presence or absence of the lighting control line 1791.
[0932]
For example, in FIG. 197, the lighting control driver circuit 1891 is formed (arranged) on one side of the display screen. That is, the gate driver 12 is formed (placed) on one side of the display screen, and the lighting control driver circuit 1891 is placed (formed) on the opposite side of the side. The lighting control driver circuit 1891 may be formed directly on the array substrate 49 using low-temperature polysilicon or high-temperature polysilicon technology, or may be formed of a silicon chip and loaded on the array substrate 49 using COG technology or the like. Also good. However, as shown in FIG. 197, the circuit configuration becomes extremely simple by sharing (blocking) the plurality of gate signal lines 17b. Therefore, even if it is formed directly on the array substrate 49 or constituted by a silicon chip and stacked on the array substrate 49, it occupies almost no area. Therefore, a narrow frame of the display panel can be realized. The lighting control driver circuit 1891 may be arranged on the same side as the source driver 14 to realize a three-side free configuration.
[0933]
In the embodiment up to FIG. 197, the gate driver 12 is formed directly on the array substrate 49 using low-temperature polysilicon or high-temperature polysilicon technology, or is formed of a silicon chip, and the array substrate 49 is formed using COG technology or the like. Although described as loading, the present invention is not limited to this. For example, as shown in FIG. 198, the gate signal line 17a may be wired from the side where the source driver 14 is arranged. That is, both the lighting control line 1791 and the gate signal line 17a are formed at the end of the display screen 21. Other configurations are the same as those in FIG.
[0934]
Further, as shown in FIG. 199, the source driver 14 and the gate driver 12 are respectively arranged (formed) on two sides of the display screen, and the gate driver 12 and the source driver 14 are connected to each other at the center of the display screen 21. You may comprise. With this configuration, the routing of the gate signal line 17a is reduced (halved), and a narrow frame can be realized.
[0935]
FIG. 200 is an explanatory diagram in which the source driver 14 and the gate driver 12 are arranged on a panel. In FIG. 200, the source driver 14 is made of a silicon chip and disposed on one side of the array substrate 49. The gate driver 12 is directly formed on the array substrate 49 using low temperature polysilicon, CGS technology, or high temperature polysilicon technology. The on / off voltage to the lighting control line 1791 is output from the source driver 14.
[0936]
FIG. 201 shows an embodiment in which the lighting control driver circuit 1891 is formed directly on the array substrate 49 using low-temperature polysilicon, CGS technology, or high-temperature polysilicon technology. Of course, the lighting control driver circuit 1891 may be made of a silicon chip and mounted on the array substrate 49 using COG technology or the like.
[0937]
FIG. 202 shows an example in which an on / off signal to the lighting control line 1791 is output from the control IC 101 or the like. In this way, by configuring the on / off data of the lighting control line 1791 to be output from the control IC 101 such as a microcomputer, the specification of the source driver 14 is simplified, and even if the driving method is changed, the source driver 14 changes become unnecessary.
[0938]
FIG. 203 shows a configuration using a gate driver 12a and a source driver 14a for driving the display screen 21a, and a gate driver 12b and a source driver 14b for driving the display screen 21b. Other configurations are the same as those in the previous embodiment, and thus the description thereof is omitted.
[0939]
In FIG. 204, an ON / OFF signal to the lighting control line 1791 is output from the control IC 101 or the like, and the gate driver 12 and the source driver 14 are directly formed on the array substrate 49 using low temperature polysilicon, CGS technology, or high temperature polysilicon technology. This is an example. Of course, the source driver 14, the lighting control driver circuit 1891, and the like may be manufactured using a silicon chip and stacked on the array substrate 49 using COG technology or the like.
[0940]
FIG. 205 shows a configuration in which an on / off signal to the lighting control line 1791 is output from the control IC 101 and the like, and a control signal to the gate signal line 17a and image data to the source signal line 18 are realized by the source driver 14a. The source driver 14a may be formed directly on the array substrate 49 using low temperature polysilicon, CGS technology, or high temperature polysilicon technology. Alternatively, the source driver 14a or the like may be manufactured using a silicon chip and loaded on the array substrate 49 using COG technology or the like.
[0941]
A method of applying the reverse bias voltage Vm has been described with reference to FIGS. The reverse bias voltage Vm is basically applied when no current is applied to the EL element 15. On the other hand, the block driving method described in FIG. 188 and the like forms the non-display area 312 and the image display area 311 for each block. Based on these, the reverse bias voltage Vm can be applied to the EL element 15 in the non-display area 312 by block driving. That is, a reverse bias voltage (current) is applied to each block. However, the reverse bias voltage Vm is not limited to being applied to all blocks in the non-display area 312. For example, an arbitrary block may be divided into a plurality of blocks, and the reverse bias voltage Vm may be applied to each divided block. Of course, the non-display area 312 may be controlled for each block, and the application control of the reverse bias voltage Vm may be performed for each pixel row.
[0942]
As described above, the configuration in which the reverse bias voltage Vm is applied to each block simplifies the pixel configuration described with reference to FIG. 173 and the like, and facilitates control. In particular, since the reverse bias voltage Vm is applied to the non-display area 312, the logic is simple.
[0943]
FIG. 206 shows an embodiment of the present invention in which block driving and reverse bias voltage driving are combined, and is the same as the pixel configuration in FIG. 173. This pixel configuration is combined with the block drive described in FIG. Needless to say, the block drive can be applied to any of the configurations described with reference to FIGS.
[0944]
In FIG. 206, by applying the off voltage Vgh to the lighting control line 1791, the corresponding block becomes the non-display area 312. At the same time (not limited at the same time, any period may be used as long as the off voltage Vgh is applied to the corresponding lighting control line 1791), and the on voltage Vgl is applied to the reverse bias control line 2111. Then, the reverse bias voltage Vm is applied to the EL element 15 of the corresponding block. That is, in terms of logic, a reverse phase signal of the lighting control line 1791 may be used as the reverse bias control line 2111.
[0945]
Similarly, FIG. 207 is a configuration in which a reverse bias driving method is added to the configuration of FIG. 189. 208 is a configuration obtained by adding a reverse bias drive method to the configuration of FIG. 190, and FIG. 209 is a configuration obtained by adding a reverse bias drive method to the configuration of FIG. Since the operation is easy, no explanation will be required.
[0946]
As described above, it is not necessary to completely synchronize the application of the reverse bias voltage Vm and the block driving. Further, it is not necessary to completely match the scanning periods.
[0947]
Hereinafter, the description of the block driving of the present invention will be continued. FIG. 210 is an explanatory diagram of the block driving method of the present invention. In the following explanatory diagrams, the pixel configuration will be described as the pixel configuration shown in FIG. 6 for ease of explanation. However, the present invention is not limited to this, and it goes without saying that other pixel configurations such as FIG. 19, FIG. 86, and FIG. 87 may be used.
[0948]
In the pixel configuration of FIG. 6, the switching TFT 11d in the pixel row for which current programming is being performed needs to be turned off. That is, driving is performed so that the EL element 15 cannot be seen from the source signal line 18 in the selected pixel row (the EL element 15 is not connected to the source signal line 18). This is to prevent a program current from the source signal line 18 from flowing into the EL element 15. This is because when the program current flows in the EL element 15, the regular current cannot be programmed in the capacitor 19.
[0949]
Therefore, when block driving is performed, the block including the selected pixel row needs to be a non-display area 312. That is, when a pixel row in the corresponding block is selected, this block is constantly set as a non-display area 312. Conversely, the other blocks may be either the image display area 311 or the non-display area 312. In order to suppress flicker, the blocks other than the selected pixel row are turned on / off.
[0950]
In FIG. 210A, one write pixel row 871a of the block 1981b is selected. Therefore, the block 1981b is controlled to a non-lighting state. If the block 1981 is composed of 6 pixel rows, the selected block 1981 is controlled to be in a non-lighting display for a period of 6H.
[0951]
FIG. 210 (b) shows a display state after 1H from FIG. 210 (a). The selected writing pixel row 871a is shifted by one pixel row. In FIG. 210A, the blocks of the non-display area 312 are 1981b, 1981d, 1981f, 1981h, and 1981j. In FIG. 210 (b), the blocks of the non-display area 312 are 1981a, 1981b, 1981e, 1981g, and 1981i. That is, in FIGS. 210A and 210B, the blocks other than the block 1981b including the selected writing pixel row 871a are reversed (the non-display area 312 and the image display area 311 are reversed).
[0952]
The selected pixel row is not limited to one pixel row, and a plurality of selected pixel rows may be used. For example, as described in FIG. 45, FIG. 46, FIG. 121, etc., the method of selecting a plurality of pixel rows can be combined with the block driving of FIG. 210 or the reverse bias voltage driving of FIG.
[0953]
In FIG. 210, the switching TFT 11d in the selected pixel row is turned off and the EL element 15 is not turned on. However, in the case of the current mirror configuration as shown in FIG. 19, the source signal line 18 and the EL element 15 are Not connected. Therefore, the selected pixel row may be displayed. However, since the selected pixel row is being programmed and an image in that period is found, it is preferable to control the selected pixel row to a non-lighting state.
[0954]
In FIG. 210, the inversion of the non-display area 312 and the image display area 311 is performed in the 1H cycle. However, the inversion is not limited to this and may be 2H or more. Further, lighting control may be performed relatively randomly. As a matter of course, the reverse bias voltage Vm may be applied to the non-lighted block.
[0955]
Note that the control of the non-display area 312 and the image display area 311 does not have to be performed simultaneously for the RGB pixels, and the lighting control may be different for R, G, and B. This includes the case of FSC (frame sequential control).
[0956]
In FIG. 210, the on / off control is performed for each block, but the present invention is not limited to this. For example, as shown in FIG. 211, control is performed with two blocks (for example, in FIG. 211 (a), blocks 1981b and 1981c are non-display areas 312. Blocks 1981d and 1981e are image display areas 311). May be performed. Alternatively, lighting control may be performed after 1H as shown in FIG. 211 (b). In FIGS. 211 (a) and 211 (b), lighting control is performed by shifting one block at a time. In FIG. 210, FIG. 211, etc., the number of blocks 1981 is very small for easy illustration. The above matters are the same in other embodiments.
[0957]
FIG. 212 shows a method of forming a brightness distribution on the display screen 21 by lighting control of the block. For ease of explanation, it is assumed that FIG. 212 (a) is in the 1H state, and FIG. 212 (b) is after 1H after FIG. 212 (a). Of course, FIGS. 212 (a) and 212 (b) may be in a state where they are separated from each other by a predetermined period.
[0958]
To configure the brightness distribution, a Gaussian distribution is exemplified. In other words, it is a technique for making the display screen brighter and reducing the power consumption by making the central part of the display screen brighter and the peripheral part darker. In the present invention, in the horizontal direction of the screen, the data itself is changed by modulation of the video signal to form a brightness distribution. For example, a line memory of one pixel row is mounted, and coefficients necessary for calculation are held in this memory. For example, if the edge of the screen is 50% compared to the center, a coefficient corresponding to 50% is held. Hereinafter, the coefficients are held in the line memory so that the central portion is 100% and the Gaussian distribution is satisfied. The applied image data is calculated as a coefficient of the line memory, and the calculated result is applied to each source signal line.
[0959]
If pixels are configured so that the non-display area 312 can be turned on and off in the vertical direction of the screen, the data itself is changed by the modulation of the video signal in the left and right direction of the screen, and thus it is necessary to form a brightness distribution. Disappear. For example, a signal line may be formed so that the switching TFT 11d of one pixel column can be controlled on and off. That is, the switching TFT 11d can be controlled in a matrix on the display screen.
[0960]
The Gaussian distribution is an example. That is, a luminance distribution state that brightens the vicinity of the center of the display screen 21 is generated. Therefore, the brightness distribution is not limited to the Gaussian distribution, and may be a sine curve-shaped brightness distribution or a conical brightness distribution. In addition, since the present invention controls the switching TFT 11d and the like to generate the brightness distribution, the present invention is not limited to brightening the central portion of the display screen 21. For example, the center part of the display screen may be in the darkest state, or the upper part of the display screen may be in the brightest state. These brightness distribution states can also be easily realized by controlling the switching TFT 11d and the like. This is because it can be realized simply by adjusting (changing) the control timing and on-time of the gate signal line 17b.
[0961]
Also, the brightness distribution state can be freely or automatically changed by the user in accordance with the type of image. For example, during partial display, the partial display position can be displayed particularly brightly. In addition, it is possible to easily change the color of an arbitrary display portion or to display only a necessary portion outdoors so that it can be seen brightly.
[0962]
Further, the brightness is not limited to the generation of the three primary colors of R, G, and B that are simultaneously changed to the same position (white moves). For example, the maximum luminance position of only R can be moved. As described above, the color pattern on the display screen 21 can be generated by changing the maximum luminance (minimum luminance) position of each color.
[0964]
Formation of brightness distribution in the vertical direction of the display screen 21 is realized by on / off control of the block 1981. That is, the number of off times of the block 1981 in the center of the display screen is reduced, and the number of off times above or below the display screen is increased. The larger the number of off times, the darker the display screen, and the lower the number of times, the brighter the screen. By controlling this on / off, a Gaussian distribution can be formed in the vertical direction of the display screen. Accordingly, the brightness in the horizontal direction of the display screen is adjusted (controlled) by calculating video data (or the amplitude value may be modulated by analog modulation). The brightness of the display screen is adjusted (controlled) by on / off control.
[0964]
In FIG. 212 and the like, the brightness distribution is formed by the on / off control of the block 1981. However, the present invention is not limited to this. It goes without saying that the brightness distribution can be formed not only by the block 1981 but also by performing on / off control for each pixel row. It can also be realized by performing on / off control for each of a plurality of pixel rows. That is, the on / off control in the block 1981 is merely on / off control as a collection of a plurality of pixel rows. Therefore, FIG. 212 and the like are one embodiment in which the technical scope of the present invention is limited.
[0965]
The non-display area 312 in FIG. 212 (a) is blocks 1981b, 1981d, 1981h, and 1981j. The non-display area 312 in FIG. 212 (b) is blocks 1981a, 1981c, 1981i, and 1981k. Therefore, the blocks 1981e, 1981f, and 1981g in the center are lit in both FIGS. 212 (a) and 212 (b). Therefore, the central part becomes bright.
[0966]
On the other hand, in FIG. 212 (a), blocks 1981a, 1981c, 1981i, and 1981k are image display areas 311, but in FIG. 212 (b), conversely they are non-display areas 312. Therefore, the upper and lower portions of the display image are darkened.
[0967]
From the above, by performing on / off control for each block 1981, a brightness distribution can be formed in the display image. In FIG. 212, the blocks 1981e, 1981f, and 1981g in the central portion are lit in both FIGS. 212 (a) and (b), but can be freely set by performing control such as turning off the light at the next 1H. In addition, the brightness can be controlled and the occurrence of flicker can be suppressed.
[0968]
In FIG. 212, all the widths of the blocks 1981 are the same. However, visually, the central portion of the display screen 21 may be made finer and the peripheral portion may be made rougher, for example, as shown in FIG. This is because the human visual resolution is high in the center of the screen.
[0969]
In FIG. 213, on / off control alternately performs FIGS. 213 (a) and (b). The blocks 1981f to 1981n in the central portion of the display screen 21 perform on / off control in fine block units (one unit), the central portion performs on / off control in two block units, and the top and bottom of the display screen has three block units. ON / OFF control is performed with. Note that the off control of the writing pixel row 871a is performed by the method described with reference to FIG.
[0970]
FIG. 213 performs on / off control at the center of the display screen by changing the width of the lighting block 1981, and realizes a visually matched display. FIG. 214 shows the number of times of turning on / off in a plurality of unit cycles. By controlling the above, a Gaussian distribution on the display screen is realized. 214 shows six periods (FIG. 214 (a) → (b) → (c) → (d) → (e) → (f) → (a) → (b) → (c) → (d) → (e ) → (f) → (a)), the brightness distribution of the display screen is formed. Of course, it is not limited to 6 cycles, and may be 2 cycles or 8 cycles or more. The period unit may be synchronized with 1H, 1F, or another clock. Also in FIG. 214, the Gaussian distribution in the left-right direction of the display screen is performed by a video signal or the like. This has been described with reference to FIG. Moreover, the above matter is applied also to other this invention.
[0971]
As can be seen in FIG. 214, an image display area 311 is generated at the center of the display screen in FIGS. 214 (b) and 214 (e), and an image is displayed near the center of the display screen in FIGS. 214 (c) and 214 (f). A lot of areas are generated. By controlling in this way, the central part of the display screen becomes brighter. Therefore, a good Gaussian distribution can be generated.
[0972]
FIG. 215 does not generate a Gaussian distribution, but suppresses the generation of flicker by changing the position of the lighting block 1981 in a plurality of periods. In FIG. 215 (a), the non-display area 312 is generated every two blocks, and in FIG. 215 (b) of the next block, the non-display area 312 is generated every three blocks. Further, in FIG. 215 (c) of the next block, the non-display area 312 is generated every four blocks. As described above, the occurrence of flicker can be suppressed by changing the position of the non-display area 312 or the image display area 311 in a plurality of cycles. In addition, a Gaussian distribution can be generated by combining the methods described in FIGS. 213 and 214.
[0973]
In the above embodiment, the lighting position is changed in units of block 1981 as shown in FIG. However, the present invention is not limited to this. For example, as shown in FIG. 217, the lighting position may be changed by 1/2 block. That is, although the above embodiment mainly explained on-off control in units of blocks, the present invention is not limited to this. This is because the generation of Gaussian distribution and the suppression of flicker can be realized without using the block 1981 unit. As described before, non-lighting control may be performed in units of one pixel row. Of course, non-lighting control or lighting control may be performed in units of a plurality of pixel rows.
[0974]
Further, the present invention is not limited to pixel rows, and on / off processing may be performed on pixel columns, and on / off processing may be performed on both pixel rows and pixel columns. Further, the pixel rows to be turned on / off are not limited to sequential processing, and random processing may be performed. By randomly turning on / off pixel rows (pixel columns), it is possible to make the display screen 21 difficult to see and to generate flicker. Further, the specific pixel row (pixel column) can be always set as the non-display area 312. In addition, the screen can be flushed by displaying on or off the entire screen or a part of the screen at a low frame rate (the non-display area 312 and the image display area 311 are alternately repeated). These can be applied as image scramble processing or special effect processing.
[0975]
However, it goes without saying that the display state described above is controlled in units of block 1981, so that the circuit configuration becomes easy, and the panel configuration and pixel configuration become easy.
[0976]
As shown in FIG. 218, an image is displayed by scanning the image display area 311 from the top to the bottom of the display screen 21 ((a) → (b) → (c) → (d) → (e) → (A) → (b) → (c) →). At this time, brightness distribution (Gaussian distribution, etc.) can be realized in the vertical direction of the display screen by controlling the scanning clock.
[0977]
In FIG. 218, when the image display area 311 is scanned in the display state (c), the scanning speed of the image display area 311 is decreased. When the image display area 311 is scanned in the portions (a) and (e), the scanning speed of the image display area 311 is increased. When the image display area 311 is scanned in the portions (b) and (d), the scanning speed of the image display area 311 is set to an intermediate speed between (a) and (c). The scanning speed can be realized by controlling CLK * applied to the shift register 22 of the gate driver 12 described with reference to FIG. Further, it can be realized by controlling the lighting control line 1791 described in FIG.
[0978]
As described above, by controlling the image display area 311, the central portion of the display screen 21 has the highest luminance, and the upper and lower portions of the screen become darkest. Accordingly, a Gaussian distribution or the like can be formed in the vertical direction of the display screen 21. Of course, a Gaussian distribution or the like may be formed in the horizontal direction of the screen by controlling in the pixel column direction. It can also be realized by arithmetic processing of a video signal.
[0979]
In FIG. 218, a luminance distribution such as a Gaussian distribution is formed on the display screen by changing the scanning speed of the image display area 311 according to the screen position. However, this technical idea is limited to an EL display device. is not. For example, it is obvious that the present invention can also be applied to an LED display device. Further, the present invention is not limited to a self-luminous display panel (display device). For example, it can be applied to a liquid crystal display device.
[0980]
The liquid crystal display device is realized by improving the backlight. As the backlight, a backlight in which a plurality of stripe-shaped light emitting regions are arranged along the pixel row direction is used. For example, a device in which at least 10 striped white EL elements are formed along the pixel row direction is used. The striped light emitting elements may be lit in order from the top. That is, when the stripe-shaped EL element is lit, if the lighting time of the stripe-shaped EL element 15 corresponding to the center portion of the display screen 21 is lengthened, the light emission state of the backlight can be changed to the state shown in FIG.
[0981]
Therefore, the liquid crystal display device itself cannot make the lighting display state as shown in FIG. 218, but the image display described in FIG. 218 can be realized by setting the lighting region of the backlight to the scanning state. Needless to say, the above items can also be applied to FIGS. 221, 222, 223, and 210.
[0982]
FIG. 219 shows a driving waveform of the gate signal line 17a. For ease of explanation, the cycle of MCLK is 1H (one horizontal scanning period). However, it is not limited to this. Flexible control can be realized by using a clock faster than 1H.
[0983]
A portion indicated by 'a' in FIG. 219 corresponds to the display state in FIG. 218 (a). Similarly, the part indicated by 'b' in FIG. 219 corresponds to the display state of FIG. 218 (b), and the part indicated by 'c' in FIG. 219 corresponds to the display state of FIG. 218 (c). 219 in FIG. 219 corresponds to the display state of FIG. 218 (d), and the portion indicated by ‘e’ in FIG. 219 corresponds to the display state in FIG. 218 (e).
[0984]
The pixel configuration will be described by exemplifying the configuration in FIG. Therefore, when the ON voltage Vgl is applied to the gate signal line 17a, the corresponding pixel row is selected. However, the embodiment of the present invention is not limited to the pixel configuration of FIG. 6, but can be applied to a current mirror configuration such as FIG. 19 and a voltage program pixel configuration such as FIG. 86 and FIG.
[0985]
As shown in FIG. 219, the pixel rows are shifted by the 1H-wide clock in the portions 'a' and 'e'. The pixel rows are shifted by a 2H-wide clock in the portions 'b' and 'd'. Further, in the portion “c”, the pixel row is shifted by a 3H-wide clock. Accordingly, the shift operation of the pixel row is slow in the portion “c” three times compared to the portion “a”. That is, the “c” portion is three times brighter than the “a” portion. Therefore, the center part of the display screen can be brightest and the upper and lower parts can be darkest.
[0986]
In FIG. 219, the data transfer of the shift register 22 is 3 clocks in the center of the display screen. Further, the data transfer of the shift register 22 is set to one clock at the upper and lower portions of the display screen. Further, the data transfer of the shift register 22 is set to 2 clocks in the upper and lower parts and the center part of the display screen. However, as shown in FIG. 219, when the clock is switched in three stages, the boundary of switching is displayed with a clear difference in brightness. Therefore, it is preferable to reduce the difference between the data transfer clocks and diversify the number of changing clocks so that the boundary is not visible. That is, FIG. 219 is a diagram for explanation.
[0987]
For example, the data transfer of the shift register 22 is 5 clocks in the center portion of the display screen, the data transfer of the shift register 22 is 3 clocks in the upper and lower portions of the display screen, and the shift registers in the upper and lower portions and the center portion of the display screen. The data transfer of 22 is assumed to be 4 clocks.
[0988]
In addition, if the display screen is divided into nine or more areas, and the first area, the second area, the third area,... The ninth area from the top of the display screen, the fifth area in the center is shifted. The data transfer of the register 22 is set to 15 clocks, and the data transfer of the shift register 22 is set to 11 clocks in the first area and the ninth area. In the second area and the eighth area, the data transfer of the shift register 22 is 12 clocks. In the third area and the seventh area, the data transfer of the shift register 22 is 13 clocks. In the fourth area and the sixth area, the data transfer of the shift register 22 is 14 clocks. As described above, if the display screen is divided and optimally turned on and off, the brightness boundary is not noticeable.
[0989]
The method shown in FIG. 220 is also effective for making the brightness boundary of the display screen invisible. In FIG. 220, the signal waveform of the gate signal line 17 a in the central region of the display screen 21 is illustrated.
[0990]
As can be seen from FIG. 220, the shift start timing of 3 clocks with respect to the display position is changed in each field (frame) (F). In FIG. 220, for easy explanation, the start position is shifted by 1 clock from 1F to 4F. Actually, it is not shifted by one clock for each F, but a process of shifting by one clock in one F but not shifting in another F is performed. In addition, the number of shifts of 3 clocks is changed for each F.
[0991]
For example, in the first floor, the start position of 3 clocks in the center of the display screen starts from the pixel row (90) (90th pixel row), and the range in which the shift register is transferred in 3 clocks is 20 pixel rows. And In the second floor, the start position of 3 clocks in the center of the display screen starts from the pixel row (92), and the range in which the shift register is transferred in 3 clocks is 16 pixel rows. In the third floor, the start position of 3 clocks in the center of the display screen starts from the pixel row (94), and the range in which the shift register is transferred in 3 clocks is 12 pixel rows. Further, for the 4th F, the start position of 3 clocks in the center of the display screen starts from the pixel row (96), and the range in which the shift register is transferred in 3 clocks is 8 pixel rows. By performing the processing as described above, it is possible to make the central portion brightest and make the boundary changing from the display luminance at the top of the display screen to the display luminance at the central portion inconspicuous.
[0992]
The shift start position is processed in a loop. For example, in FIG. 220, 1F → 2F → 3F → 4F → 1F → 2F... In FIG. 220, the pixel row is shifted in the center portion of the display screen in a cycle of 3 clocks. However, the present invention is not limited to this. As described with reference to FIG. 219, the number of clocks so that the luminance distribution changes smoothly. Needless to say, the display area is adjusted.
[0993]
Needless to say, by combining FIG. 219 and FIG. 220, the brightness distribution processing of the screen display is not conspicuous and a good display can be realized.
[0994]
The driving method described with reference to FIGS. 219 and 220 consciously forms a luminance distribution on the display screen 21, but this technical concept can also be applied to other image displays.
[0995]
FIG. 221 shows the display screen 21 with two luminance portions formed (displayed). In FIG. 221, the image display area 311a is displayed brighter than the image display area 311b. In FIG. 221 (a), the image display area 311a of the memo 1 is made brighter than the other image display areas 311b. Displaying the image display area 311a brighter than the image display area 311b can be easily configured by the method described in FIG. Further, since the number of times of selecting the display area of each part may be controlled, other methods can be easily realized.
[0996]
In FIG. 221, the area selected by the user is displayed brightly (or darkly), thereby improving the usability of the display device. Of course, it is also preferable to change the color of the selected image display area 311. The display method of FIG. 221 is preferably applied to a menu selection screen or the like. This is because the screen display can be switched by a user operation, and the operability is improved. Further, it may be configured such that the screen display state of FIG. In addition, since the outside light is strong and the display image cannot be seen outdoors, the control may be performed so that only particularly necessary portions are lit strongly (image display region 311a). For example, when the brightness of external light is detected and the intensity of the detected external light is a certain value or more, the user presses the power switch to display the display screen 21.
[0997]
Further, as shown in FIG. 222 (a), image display areas 311a that are strongly lit may be provided at a plurality of locations on the display screen 21 or blinked. In FIG. 222 (a), blinking means that the image display area 311a is turned on / off in a 0.5 second cycle, or low luminance and high luminance are alternately displayed.
[0998]
Further, as shown in FIG. 222B, image display may be performed by combining a high-luminance image display area 311a, a low-luminance image display area 311b, and a non-display area 312.
[0999]
FIG. 223 shows the scroll effect of the display screen 21. 190A, the high-brightness image display area 311a is used up to the center of the display screen 21, and the high-brightness image display area 311a is shown in FIG. 190B up to the vicinity of the lower end of the display screen 21.
[1000]
Needless to say, the entire display screen 21 can be simultaneously displayed with low luminance. The present invention adjusts (controls) the luminance of the display screen 21 by controlling the lighting control line 1791 or the gate signal line 17b to turn on and off the current flowing through the EL element 15. Therefore, since the image data output from the source driver 14 does not change, the contrast and gamma curve of the display image are also characterized by being kept constant regardless of the brightness of the display image. Therefore, even if the entire display screen 21 is displayed with low luminance at the same time, the gradation characteristics are maintained as it is (for example, when displaying 64 gradations, even if the luminance of the display screen is ½, 64 gradations are maintained).
[1001]
As shown in FIG. 223, first, the entire display screen 21 is set as a low-brightness image display area 311b (low-brightness display), and in order to exert the effect of rewriting the display screen, from above the display screen 21, A high luminance image display area 311a is set downward (high luminance display is performed). Therefore, the one display screen 21 is rewritten by performing the high luminance display in the direction of the arrow in FIG. Then, if the high luminance display is continued for a certain time, the entire display screen 21 is changed to the low luminance display from the viewpoint of reducing power consumption.
[1002]
Note that the organic EL display panel requires a large amount of power for white raster display. When this white raster display power supply circuit is provided, the power supply circuit becomes very large. On the other hand, in normal character display, only 1/5 to 1/3 of the power of white raster display is redundantly consumed. Therefore, it is not preferable from the viewpoint of economy or system size to hold the output current of the power supply so that white raster display can be supported.
[1003]
In order to cope with this problem, in the present invention, when displaying an image (for example, white raster display) that consumes more than a certain value, the brightness of the image is reduced and displayed. . For example, when a current of 100 mA flows in a white raster, the image data is processed so that a current of 50 mA is halved. That is, the sum of the input image data is obtained, and when the sum exceeds a certain value, the image data is subjected to arithmetic processing to reduce the value of the image data so that it can be displayed with the power supply power held.
[1004]
Of course, the present invention is not limited to reducing the value of the image data. By performing the non-lighting control described with reference to FIGS. 187, 218, 222, etc., the brightness of the entire display screen 21 can be reduced. . Of course, it goes without saying that the brightness of only the image display unit can be reduced, and the icon portions such as the antenna display and the clock display can be controlled so as to maintain the conventional brightness (as is).
[1005]
In the above embodiment, the image display area 311 or the non-display area 312 is scanned in the vertical direction of the display screen to display an image or to form (display) a different luminance display area. However, the present invention is not limited to this. For example, in FIG. 221, the brightness distribution can be formed by controlling the number of times each part of the display screen 21 is selected. That is, in FIG. 221, when the frame rate for displaying the display screen 21 is 60 Hz, if the image display area 311b is selected 25 times and the image display area 311a is selected 50 times, the image display area 311a is displayed as an image. The display area can be displayed with twice the luminance of the display area 311b. Similarly, in FIG. 223 (b), when the frame rate for displaying the display screen 21 is 60 Hz, the image display area 311b is selected 25 times, the image display area 311a is selected 50 times, and the non-display area 312 is completely selected. If control is performed so that the image display area 311a does not, the image display area 311a can be displayed with twice the luminance of the image display area 311b, and the non-display area 312 can be displayed in black.
[1006]
Needless to say, the items described above can be applied to the block driving described with reference to FIG. 205 or the like, or the reverse bias voltage driving described with reference to FIG. 206. In block driving, the number of pixel rows constituting each block is preferably set to the number representing one character string. For example, if one character is composed of 16 × 16 dots, 16 pixel rows are set as one block. If one character is composed of 24 × 24 dots, 24 pixel rows are made one block. As described above, by matching the number of vertical dots constituting the character with the number of blocks, the image display area 311 and the non-display area 312 can be controlled for each line displaying the character.
[1007]
(Embodiment 12)
As in the display method of FIG. 63, a display method for switching between odd-numbered pixel rows and even-numbered pixel rows (or every plurality of pixel rows) for each predetermined field (frame) can be applied to a stereoscopic image display apparatus or method. Hereinafter, the stereoscopic display device of the present invention will be described with reference to FIGS. 224 and 225.
[1008]
First, in the display method of the present invention, the image display area 311 and the non-display area 312 are basically configured in pixel row units (pixel row direction). Therefore, when displaying as in FIG. 63, it is necessary to convert the vertical and horizontal directions, but this conversion is easy. This is because the rows and columns of the image data stored in the memory may be switched. If the vertical and horizontal directions are converted, the display state of FIG. 224 (a1) is obtained. In other words, the scanning direction of the display panel is the arrow direction indicated by A, but the image is on the screen and the image below the screen as shown in FIG. 224 (a1). Therefore, it appears to the user of the display panel as if scanning from the top to the bottom of the screen.
[1009]
The display screen 21 of the display panel displays the image of the right eye from the left on the odd pixel columns (rows) and the image of the left eye on the even pixel columns (rows). The image display is synchronized with observation glasses 852 that are synchronized with the display panel. The observation glasses 852 include two liquid crystal panels that function as shutters 851.
[1010]
In the first field (first frame), as shown in FIG. 224 (a1), the odd-numbered pixel columns from the left (actually odd-numbered pixel rows) become the image display area 311 and the even-numbered pixel columns from the left (actually) The even-numbered pixel row) is the non-display area 312. In synchronization with the display state of FIG. 224 (a1), the left eye shutter 851L of the observation glasses 852 is closed, and the right eye shutter 851R of the observation glasses 852 is opened. Therefore, the observer sees the image of FIG. 224 (a1) with only the right eye.
[1011]
In the second field (second frame) next to the first field (first frame), as shown in FIG. 224 (a2), even-numbered pixel columns (actually even-numbered pixel rows) from the left are image display areas 311. Thus, an odd-numbered pixel column from the left (actually an odd-numbered pixel row) becomes the non-display area 312. In synchronization with the display state of FIG. 224 (a2), the right eye shutter 851R of the observation glasses 852 is closed, and the left eye shutter 851L of the observation glasses 852 is opened. Therefore, the observer sees the image in FIG. 224 (a2) with only the left eye.
[1012]
By repeating the above operations alternately, stereoscopic image display can be realized by making the eyeglass-type shutter 851 used by the observer and the image display state appear alternately and synchronously.
[1013]
In order to realize stereoscopic image display without using the shutter 851, a prism 861 may be disposed on the light emission side of the display panel as illustrated in FIG. The A part of the prism 861 is arranged so as to correspond to the image display area 311 at a certain display timing, and the B part of the prism 861 is arranged so as to correspond to the non-display area 312 at the above display timing. In this manner, by arranging the prism 861, it is possible to make an image of an odd-numbered pixel row enter the right eye of the viewer and an image of an even-numbered pixel row enter the left eye of the viewer. Note that an optical coupling material 862 such as ethylene glycol is disposed between the prism 861 and the display panel and optically coupled.
[1014]
In FIG. 224, the switching means 852 is glasses, but is not limited to this. Any light source can be used as long as it can control light incident on the right eye and light incident on the left eye of the observer. For example, a goggle type is exemplified. Further, an example in which the switching unit 852 and the display panel are integrated (head mounted display) is exemplified. The shutter 851 is not limited to the liquid crystal display panel, and may be a mechanical one such as a camera shutter or a rotary filter. In addition, examples incorporating a polygon mirror, a shutter using PLZT, a shutter using electroluminescence, and the like are also exemplified.
[1015]
As described above, stereoscopic display can be realized by using the display method of FIG. 63 on the display image of one display panel. Note that the apparatus or method of FIGS. 224 and 225 displays different images for each of a plurality of pixel rows (columns) or for each of odd-numbered pixel rows (columns) and even-numbered pixel rows (columns). It is not limited only to stereoscopic display. For example, it may be used for the purpose of simply displaying two images superimposed. Needless to say, it is particularly effective to implement the driving method of the present invention using the EL display device of the present invention.
[1016]
In addition, although the element which drives each pixel was TFT11, it is not limited to this. For example, the pixel 16 can be configured by a combination of a thin film diode (TFD), and the current flowing through the EL element 15 can be intermittently operated by operating one terminal voltage level of the diode. In this configuration, the cathode electrode is processed (formed) into a horizontal stripe shape as necessary. The same applies to switching elements such as varistors and thyristors.
[1017]
For example, if the driving TFT in the conversion TFT 11a of FIG. 6 is taken as an example, an N-channel or P-channel bipolar transistor may be used as shown in FIG. 226 (a). Further, as shown in FIG. 226 (b), an N-channel or P-channel MOS transistor may be used. Further, a phototransistor or a photodiode may be used as shown in FIG. 226 (c), and a thyristor element or the like may be used as shown in FIG. 226 (d). This means that the present invention can also be applied to switching elements constituting other pixels.
[1018]
The TFT element can be used for either the P channel or the N channel. Further, the position of the EL element 15 is not limited to the position as shown in FIG. For example, FIG. 185 (a) shows the connection state between the conversion TFT 11a and the EL element 15 shown in FIG. As a modification, the configuration of FIG. 185 (b) is also exemplified. Further, the configuration of FIGS. 185 (c) and (d) in which the driving TFT is an N channel is also illustrated. These matters apply not only to the conversion TFT 11a but also to switching elements (for example, TFTs 11b, 11c, and 11d in FIG. 6) constituting other pixels. The same applies to the elements constituting the gate driver 12 and the source driver 14.
[1019]
The switching element such as TFT is preferably formed of a low-temperature polycrystalline Si-TFT, but may be an amorphous silicon TFT. In particular, when the current flowing through the EL element 15 is 1 μA or less, it is sufficient in terms of characteristics to be formed by amorphous silicon technology. In addition, a gate driver circuit, a source driver circuit, and the like may be formed using elements using amorphous silicon technology.
[1020]
Further, the configuration of the gate driver 12 shown in FIGS. 21, 66, 67, and 69 is not limited to this (in FIG. 21, etc., the ST signal is sequentially shifted in synchronization with the clock (serial processing). For example, it may be a parallel input that determines the on / off state of each gate signal line at once (the on / off logic of all the gate signal lines is equal to the number of controllers or gate signal lines 17 at a time. Output configuration, etc.).
[1021]
FIG. 227 is a configuration diagram of the organic EL module. A control IC 101 and a power supply IC 102 are mounted on the printed circuit board 103. The printed circuit board 103 and the array substrate 49 are electrically connected by a flexible substrate 104. The power supply voltage, current, control signal, and video data are supplied to the source driver 14 and the gate driver 12 of the array substrate 49 through the flexible substrate 104.
[1022]
At this time, the problem is the control signal of the gate driver 12. It is necessary to apply a control signal having an amplitude of at least 5V to the gate driver 12. However, since the power supply voltage of the control IC 101 is 2.5V or 3.3V, the control signal cannot be directly applied from the control IC 101 to the gate driver 12.
[1023]
In response to this problem, the present invention applies a control signal for the gate driver 12 from the power supply IC 102 driven at a high voltage. Since the power supply IC 102 also generates the operating voltage of the gate driver 12, it is a matter of course that a control signal having an optimum amplitude can be generated for the gate driver 12.
[1024]
In FIG. 228, the control signal of the gate driver 12 is generated by the control IC 101, the level is once shifted by the source driver 14, and then applied to the gate driver 12. Since the drive voltage of the source driver 14 is 5 to 8 V, the 3.3 V amplitude control signal output from the control IC 101 can be converted to 5 V amplitude that the gate driver 12 can receive.
[1025]
229 and 164 are explanatory views of the display module device of the present invention. FIG. 229 shows a configuration in which a built-in display memory 151 is provided in the source driver 14. The built-in display memory has a capacity of 8 color display (1 bit for each color), 256 color display (RG is 3 bits, B is 2 bits), and 4096 color display (RGB is 4 bits each). When the 8-color, 256-color, or 4096-color display is performed and a still image is displayed, the driver controller disposed in the source driver 14 reads the image data in the built-in display memory 151, so that ultra-low power consumption can be realized. . Of course, the built-in display memory 151 may be a multi-color display memory having 260,000 colors or more. Also, the image data in the built-in display memory 151 may be used for moving images.
[1026]
The image data in the built-in display memory 151 may be stored after the error diffusion process or the dither process. By performing error diffusion processing, dither processing, etc., 260,000 color display data can be converted into 4096 colors, and the capacity of the built-in display memory 151 can be reduced. Error diffusion processing and the like can be performed by the error diffusion controller 141. Further, after the dither process, an error diffusion process may be further performed. The above items also apply to the inverse error diffusion process.
[1027]
In FIG. 229 and the like, 14 is described as a source driver, but it is not only a driver, but also a power supply IC 102, a buffer circuit 154 (including circuits such as a shift register), a data conversion circuit, a latch circuit, a command decoder, and a shift circuit. The address conversion circuit and various functions or circuits for processing the input from the built-in display memory 151 and outputting the voltage or current to the source signal line are configured. These matters are the same in other embodiments of the present invention.
[1028]
Needless to say, the configuration described in FIG. 229 and the like can also be applied to the three-side free configuration described in FIGS. 23 to 27, FIG. 29, FIG. 32, FIG.
[1029]
FIG. 230 shows a configuration example in which a protective cover for protecting the EL element 15 from humidity is used as the sealing lid 41, and may also be used as a protective cover for a mobile phone or the like. The protective cover is a transparent plate arranged to protect the front surface of the display panel. Alternatively, in the reflective liquid crystal display panel, the front light is a protective cover. A circularly polarizing plate 74 is attached to the sealing lid 41. The circularly polarizing plate 74 may be formed by applying a resin to a thin film or the sealing lid 41 and stretching the resin.
[1030]
An EL element array substrate 49 is attached to a housing 193 such as a mobile phone (an EL display panel is attached). The gate driver 12 (or the source driver 14) is disposed in the sealing lid 41. The gate driver 12 (or the source driver 14) is also protected by the sealing lid 41. Formed as above
By (configuring), the protective cover can be omitted, and the overall thickness of the display panel module can be reduced.
[1031]
Further, as described with reference to FIG. 2, the organic EL panel needs to form the reflective film 46 as a cathode electrode (or an anode electrode). This electrode is made of aluminum or the like. Therefore, the reflectivity is as good as 85% or more.
[1032]
FIG. 231 shows a mobile phone configured such that the reflective film 46 can be used as a mirror. In a normal use state, it is used as shown in FIG. 232 (or see FIG. 233). When the display panel 2046 is used as a mirror, the display panel 2046 is turned over around a right or left fulcrum (not shown), and the back mirror 2045 is used.
[1033]
However, the above embodiment uses the reflective film formed on the back surface of the EL display panel as a mirror. Therefore, the object used as a mirror is not limited to a mobile phone, but may be a television, a monitor, or a PDA. In addition, a mirror is formed on the back surface of the display panel. Therefore, the present invention is not limited to the cathode, and a configuration in which a mirror is separately formed on the back surface of the display panel may be used. For example, since a reflective liquid crystal display panel does not use a back surface, aluminum or silver may be deposited on the back surface to form a mirror. In this case, to prevent corrosion of aluminum or silver,2It is preferable to form an inorganic thin film. Moreover, you may protect also with UV resin etc.
[1034]
In FIG. 231, reference numeral 2041 denotes a speaker that allows the received voice to be heard, and 2044 denotes a microphone for inputting the user's voice. Further, as described with reference to FIG. 55, it is preferable to arrange the display mode changeover switch 465. Furthermore, it is preferable to form (arrange) a switch for realizing the function of switching the screen brightness described with reference to FIG.
[1035]
The frame rate is related to the power consumption of the panel module. That is, if the frame rate is increased, the power consumption increases almost in proportion. For mobile phones and the like, it is necessary to reduce power consumption from the standpoint of extending the standby time. On the other hand, in order to increase the display color (increase the number of gradations), the drive frequency of the source driver 14 and the like must be increased. However, it is difficult to increase power consumption due to power consumption problems.
[1036]
In general, in an information display device such as a mobile phone, lower power consumption is given priority over the number of display colors. The power consumption increases because the operating frequency of the circuit that increases the number of display colors increases or the change in the voltage (current) waveform applied to the EL element increases. Therefore, the number of display colors cannot be increased too much. In response to this problem, the present invention displays an image by performing error diffusion processing or dither processing on the image data.
[1037]
Although not shown in the cellular phone of the present invention described with reference to FIG. 232, a CCD camera is provided on the back side of the housing. Images and data captured by the CCD camera can be immediately displayed on the display screen 21 of the display panel. The CCD camera image data can be switched by key input from 24 bits (16.7 million colors), 18 bits (260,000 colors), 16 bits (650,000 colors), 12 bits (4096 colors), and 8 bits (256 colors). be able to.
[1038]
When the display data is 12 bits or more, error diffusion processing is performed for display. That is, when the image data from the CCD camera is greater than or equal to the capacity of the built-in display memory 151, error diffusion processing or the like is performed, and image processing is performed so that the number of display colors is less than or equal to the capacity of the built-in display memory 151.
[1039]
Now, the source driver 14 will be described assuming that it has a built-in display memory 151 of 4096 colors (4 bits for each of RGB) and one screen. When the image data sent from the outside of the module is 4096 colors, it is directly stored in the built-in display memory 151 of the source driver 14, the image data is read from the built-in display memory 151, and the image is displayed on the display screen 21.
[1040]
If the image data is 260,000 colors (G: 6 bits, R, B: 5 bits each, a total of 16 bits), it is temporarily stored in the arithmetic memory 152 of the error diffusion controller 141 as shown in FIGS. At the same time, the arithmetic circuit 153 performs error diffusion or dither processing. By this error diffusion processing or the like, the 16-bit image data is converted into 12 bits that is the number of bits of the built-in display memory 151 and transferred to the source driver 14. The source driver 14 outputs RGB 4-bit (4096 colors) image data and displays the image on the display screen 21.
[1041]
In the configuration of FIG. 164, the error diffusion processing or dither processing method may be changed for each field or frame by using the vertical synchronization signal VD (by changing the processing method using the vertical synchronization signal VD). For example, in the dither processing, the Bayer type is used in the first frame, and the halftone type is used in the next second frame. In this way, by changing and switching the dither processing for each frame, an effect of making the dot unevenness associated with the error diffusion processing less noticeable is exhibited.
[1042]
Further, processing coefficients such as error diffusion processing may be changed between the first frame and the second frame. Various processes such as error diffusion processing in the first frame, dither processing in the second frame, and error diffusion processing in the third frame may be combined. Further, a processing method may be selected in which a random number generation circuit is provided and processing is performed for each frame with a random value.
[1043]
If information such as the frame rate is described in the transmitted format, the frame rate can be automatically changed by decoding or detecting the described data. It is preferable to describe whether the transmitted image is a moving image or a still image, and in particular, in the case of a moving image, it is preferable to describe the number of frames per second of the moving image. Further, it is preferable to describe the model number of the mobile phone in the transmission packet. In this specification, although it is described as a transmission packet, it does not have to be a packet. If information (number of display colors, frame rate, etc.) described in FIG. Either is acceptable.
[1044]
FIG. 235 shows a transmission format sent to the cellular phone of the present invention. Transmission includes both data to be received and data to be transmitted. That is, the cellular phone may transmit the voice from the receiver or the image taken by the CCD camera attached to the cellular phone to another cellular phone or the like. Therefore, matters related to the transmission format described in FIG. 234 and the like apply to both transmission and reception.
[1045]
In the mobile phone of the present invention, data is digitized and transmitted in a packet format. As described in FIG. 235, the frame includes a flag part (F), an address part (A), a control part (C), an information part (I), and a frame check sequence (FCS). As shown in FIG. 236, the control unit (C) has three formats: information transfer (I frame), monitoring (S frame), and unnumbered system (U frame).
[1046]
First, the information transfer format is a control field format used when transferring information (data), and the information transfer format is the only format having a data field except for a part of the non-numbered format. A frame in this format is called an information frame (I frame).
[1047]
The monitoring format is a format used for performing a data link monitoring control function, that is, information frame reception confirmation, information frame retransmission request, and the like. A frame in this format is called a monitoring frame (S frame).
[1048]
The unnumbered format is a control field format used to perform other data ring control functions. A frame in this format is called an unnumbered frame (U frame).
[1049]
The terminal and the network manage information frames to be transmitted and received using a transmission sequence number N (S) and a reception sequence number N (R). Both N (S) and N (R) are composed of 3 bits, and 8 are used as a circulation number from 0 to 7, and the next to 7 has a modulus structure of 0. Therefore, the modulus in this case is 8, and the number of frames that can be continuously transmitted without receiving a response frame is 7.
[1050]
In the data area, 8-bit data indicating the color number data and 8-bit data indicating the frame rate are described. Examples of these are shown in FIGS. 234 (a) and (b). In addition, it is preferable to describe the distinction between still images and moving images in the number of display colors. In addition, it is desirable to describe the model name of the mobile phone, the content of image data to be transmitted / received (natural image such as a person, menu screen), etc. in the packet of FIG. When the model receiving the data decodes the data and recognizes it as its own (corresponding model number) data, the display color, the frame rate, etc. are automatically changed according to the described contents. Moreover, you may comprise so that the described content may be displayed on the display screen 21 of a display apparatus. The user may manually change to an optimal display state by looking at the description content (display color, recommended frame rate) on the display screen 21 and operating keys.
[1051]
As an example, in FIG. 234 (b), the numerical value 3 is described with an example of a frame rate of 80 Hz, but is not limited thereto, and indicates a certain range such as 40 to 60 Hz. Also good. In addition, the mobile phone model may be described in the data area. This is because the performance varies depending on the model and the frame rate needs to be changed. It is also preferable to describe information such as whether the image is a comic or advertisement (CM). Further, information such as a viewing fee and a packet length may be described in the packet. This is because the user can determine whether to receive the information after confirming the viewing fee. In addition, it is preferable that data indicating whether or not the image data has been subjected to error diffusion processing is also described.
[1052]
Information such as the image processing method (types such as error diffusion processing and dither processing, types of weighting functions and their data, gamma coefficients, etc.) and model number may be described in the transmitted format. In addition, if information such as whether the image data is data taken by a CCD, JPEG data, resolution, MPEG data, or BITMAP data is described, the data is decoded or detected based on this, It becomes possible to change automatically received mobile phones to the optimum state.
[1053]
Of course, it is preferable to describe whether the transmitted image is a moving image or a still image, and in particular, in the case of a moving image, it is preferable to describe the number of frames per second of the moving image. It is also preferable to describe information such as the number of playback frames recommended per second at the receiving terminal.
[1054]
The above matters are the same even when the transmission packet is transmission. Further, although described in this specification as a transmission packet, it need not be a packet. That is, any data may be used as long as the information described in FIG. 201 is described in the data to be transmitted or transmitted.
[1055]
It is preferable to add a function to the error diffusion processing controller 141 to perform inverse error diffusion processing on the data sent after being subjected to error processing, return to the original data, and then perform error diffusion processing again. The presence / absence of error diffusion processing is placed in the packet data of FIG. Also, data necessary for inverse error diffusion processing such as error diffusion (including dithering) processing method and format is also stored.
[1056]
The reverse error diffusion process is performed because the correction of the gamma curve can be realized in the process of the error diffusion process. There are cases where the gamma curve of the EL display device or the like that has received the data and the transmitted gamma curve are not adapted, or the transmitted data is image data that has already undergone processing such as error diffusion. In order to cope with this situation, reverse error diffusion processing is performed and converted to original data so as not to be affected by gamma curve correction. Thereafter, error diffusion processing is performed by the received EL display device, etc., and error diffusion processing is performed so as to obtain an optimal gamma curve for the reception display panel and to achieve an optimal error diffusion processing.
[1057]
If it is desired to switch the frame rate depending on the display color, a user button may be arranged on a device such as a cellular phone so that the display color can be switched using the button.
[1058]
FIG. 232 is a plan view of a mobile phone as an example of an information terminal device. An antenna 191, a numeric keypad 192, and the like are attached to the housing 193. Reference numeral 194 denotes a display color switching key or a power on / off / frame rate switching key.
[1059]
FIG. 237 shows an internal circuit block of a mobile phone or the like. The circuit mainly includes blocks such as an up-converter 205 and a down-converter 204, a demultiplexer 201, and an LO buffer 203.
[1060]
If the key 194 is pressed once, the display color is set to the 8-color mode, and if the same key 194 is pressed, the display color is set to the 256 color mode, and if the same key 194 is pressed further, the display color is set to the 4096 color mode. But you can. The key is a toggle switch that changes the display color mode each time it is pressed. In addition, you may provide the change key with respect to a display color separately. In this case, there are three (or more) keys 194.
[1061]
The key 194 may be a push switch, a mechanical switch such as a slide switch, or may be switched by voice recognition or the like. For example, voice input of 4096 colors to the receiver, for example, “high quality display”, “256 color mode” or “low display color mode” is input to the receiver and displayed on the display screen 21 of the display panel. Configure the color to change. This can be easily realized by adopting the current speech recognition technology.
[1062]
The display color may be switched by an electrically switched switch or a touch panel that is selected by touching a menu displayed on the display screen 21 of the display panel. Further, it may be configured to be switched by the number of times the switch is pressed, or to be switched by rotation or direction like a click ball.
[1063]
Although 194 is a display color switching key, it may be a key for switching a frame rate. Moreover, it is good also as a key etc. which switch a moving image and a still image. A plurality of requirements such as a moving image, a still image, and a frame rate may be switched at the same time. Alternatively, the frame rate may be changed gradually (continuously) as long as the pressure is kept pressed. This case can be realized by making the resistor R of the capacitor C and the resistor R constituting the oscillator a variable resistor or an electronic volume. The capacitor can be realized by using a trimmer capacitor. Alternatively, a plurality of capacitors may be formed on the semiconductor chip, one or more capacitors may be selected, and these may be connected in parallel in a circuit.
[1064]
The technical idea of switching the frame rate depending on the display color is not limited to mobile phones, but can be widely applied to devices having display screens such as palmtop computers, laptop computers, desktop computers, and portable watches. it can. Further, the present invention is not limited to a liquid crystal display device, and can be applied to a liquid crystal display panel, an organic EL display panel, a TFT panel, a PLZT panel, and a CRT.
[1065]
In FIG. 231, reference numeral 2043 denotes a function switch (FSW). The FSW 2043 is disposed at a position where the FSW 2043 can be pressed with the little finger or the ring finger. The FSWs 2043a and 2043b are arranged on the left and right. This is because it is configured to be able to be pressed with the little finger and ring finger of the right hand and to be pressed with the little finger and ring finger of the left hand. Note that the FSW may be disposed on the back surface of the housing 193.
[1066]
Whether to enable the right-hand FSW 2043 or the left-hand FSW 2043 can be switched by a command setting. That is, when the user sets the right side to be enabled on the menu screen, the right hand FSW 2043 is enabled and the left hand FSW 2043 is disabled. Conversely, when the user sets the left side to be enabled on the menu screen, the left hand FSW 2043 is enabled and the right hand FSW 2043 is disabled.
[1067]
As shown in FIG. 238 (a), when the FSW 2043 is not pressed, the numeric keypad 192 becomes a numeric input key. As shown in FIG. 238 (b), when the FSW 2043a is pressed, the hiragana input mode is set. At this time, the uppermost character of “A, K, Sa, Ta, Na…” is designated. In this state, first, “A” is selected. Next, when the FSW 2043b is also pressed, an input state of five characters including the previously pressed character string is entered. When a specific key is pressed in this state, a character is input. Therefore, Japanese input can be easily realized by combining the FSW 2043 and the numeric keypad 192. Also, as shown in FIG. 238 (d), when only the FSW 2043b is pressed, the English character input mode is set.
[1068]
As described above, by arranging the FSW 2043 in addition to the numeric keypad 192, a wide variety of characters can be easily input.
[1069]
(Embodiment 13)
Further, an embodiment in which the EL display panel, the EL display device, or the driving method of the present invention is employed will be described with reference to the drawings.
[1070]
FIG. 239 is a cross-sectional view of the viewfinder in the embodiment of the present invention. However, it is schematically drawn for easy explanation. In addition, there are places that are partially enlarged or reduced or omitted. For example, the eyepiece cover is omitted in FIG. The above also applies to other drawings.
[1071]
The back surface of the body 451 is dark or black. This is because stray light emitted from the display panel 82 is diffusely reflected on the inner surface of the body 451 to prevent a decrease in display contrast. A λ / 4 plate 50 (phase plate or the like), a polarizing plate 54, or the like is disposed on the light emission side of the display panel. This is also illustrated in FIG.
[1072]
A magnifying lens 453 is attached to the eyepiece ring 452. The observer changes the insertion position of the eyepiece ring 452 in the body 451 and adjusts it so that the display image on the display panel is in focus. Further, if the positive lens 454 is disposed on the light exit side of the display panel as necessary, the principal ray incident on the magnifying lens 453 can be converged. Therefore, the lens diameter of the magnifying lens 453 can be reduced, and the viewfinder can be downsized.
[1073]
FIG. 240 is a perspective view of the video camera. The video camera includes a photographing lens 461 and a video camera body 462, and the photographing lens 461 and the viewfinder 466 are back to back. Further, an eyepiece cover 464 is attached to the viewfinder 466 (see also FIG. 239). An observer (user) observes an image on the display panel from the eyepiece cover 464 portion.
[1074]
On the other hand, the EL display panel of the present invention is also used as the display screen 21. The display screen 21 can freely adjust the angle at a fulcrum 468. When the display screen 21 is not used, it is stored in the storage unit 463.
[1075]
In FIG. 240, reference numeral 465 denotes a display mode switch. When the display mode changeover switch 465 is pressed, the circuit of FIG. 55 operates and the items described in FIG. 55 are performed.
[1076]
The EL display device of this embodiment can be applied not only to a video camera but also to an electronic camera as shown in FIG. The display panel 82 is used as a monitor attached to the digital camera body 472. In addition to the shutter 471, a display mode changeover switch 465 is attached to the digital camera main body 472.
[1077]
This display mode changeover switch 465 is preferably attached to a mobile phone or the like. In addition, it is preferable to add a function of switching the display brightness of the display mode switch described above to a mobile phone or the like. Hereinafter, a method for digitally changing the display luminance will be described.
[1078]
As described with reference to FIG. 91 and the like, as one of the driving methods of the present invention, there is a method in which an N-fold current is supplied to the EL element 15 to light it for a period of 1 / M of 1F. The brightness can be changed digitally by switching only the 1 / M value to be lit. For example, assuming that N = 4, a current that is four times the current flows through the EL element 15. If the lighting period is set to 1 / M and M = 1, 2, 3, and 4 are switched, the brightness can be switched from 1 to 4 times. In addition, you may comprise so that it can change with M = 1, 1.5, 2, 3, 4, 5, 6, etc.
[1079]
The above switching operation is used for a configuration in which the display screen 21 is displayed very bright when the power of the mobile phone is turned on, and the display brightness is lowered to save power after a predetermined time has elapsed. It can also be used as a function for setting the brightness desired by the user. For example, outdoors, the surroundings are bright and the screen is completely invisible, so the screen is very bright. However, if the display is continued with high luminance, the EL element 15 deteriorates rapidly. For this reason, when it is very bright, it is configured to return to normal luminance in a short time. Furthermore, when displaying with high brightness, the display brightness can be increased by the user pressing a button.
[1080]
Therefore, it is preferable to adopt a configuration in which the user can switch with a button, can be automatically changed in a setting mode, or can be switched automatically by detecting the brightness of external light. Further, it is preferable that the display brightness is set to 50%, 60%, and 80% and can be set by the user.
[1081]
The display screen is preferably a Gaussian distribution display. The Gaussian distribution display is a method in which the brightness at the center is bright and the periphery is relatively dark. Visually, if the central part is bright, it is felt bright even if the peripheral part is dark. According to the subjective evaluation, if the peripheral part keeps 70% of brightness compared to the central part, it is visually inferior. There is almost no problem even if it is further reduced to 50% luminance. In the self-luminous display panel of the present invention, the above-described N-fold pulse driving (a method in which an N-fold current is supplied to the EL element 15 and the light is lit for 1 / M of 1F) is used from the top to the bottom of the screen. A Gaussian distribution is generated in the direction.
[1082]
Specifically, the value of M is increased at the top and bottom of the screen, and the value of M is decreased at the center. This can be realized by modulating the operation speed of the shift register of the gate driver 12 or the like. The left and right brightness modulation of the screen is generated by multiplying the table data and the video data. With the above operation, when the peripheral luminance (angle of view 0.9) is 50%, the power consumption can be reduced by about 20% compared to the case of 100% luminance. Further, when the peripheral luminance (angle of view 0.9) is 70%, the power consumption can be reduced by about 15% compared to the case of 100% luminance.
[1083]
It is preferable to provide a changeover switch or the like so that the Gaussian distribution display can be turned on and off. This is because, for example, when the Gaussian display is performed outdoors, the periphery of the screen cannot be seen at all. Therefore, it is preferable to adopt a configuration in which the user can switch with a button, can be automatically changed in a setting mode, or can be switched automatically by detecting the brightness of external light. Further, it is preferable that the peripheral brightness is set to 50%, 60%, 80% and so on by the user.
[1084]
In the liquid crystal display panel, since a fixed Gaussian distribution is generated by the backlight, the Gaussian distribution cannot be turned on / off. The fact that the Gaussian distribution can be turned on / off is an effect peculiar to a self-luminous display device.
[1085]
Further, when the frame rate is predetermined, flicker may occur due to interference with the lighting state of an indoor fluorescent lamp or the like. In other words, when the fluorescent lamp is lit at an alternating current of 60 Hz, if the EL element 15 is operating at a frame rate of 60 Hz, there may be a case where a slight interference occurs and the screen feels blinking slowly. is there. To avoid this, change the frame rate. The present invention adds a frame rate changing function. In addition, the N or M value can be changed in N-fold pulse driving (a method in which an N-fold current is supplied to the EL element 15 and lighted only for a period of 1 / M of 1F).
[1086]
The above items are not limited to mobile phones, but can be used for televisions, monitors, and the like. Further, it is preferable to display an icon on the display screen so that the user can immediately recognize the display state. The above matters are the same for the following items.
[1087]
It is also preferable to have an “automatic screen adjustment” function that automatically adjusts the clock phase and screen position (horizontal / vertical) and an “auto gain control function” that automatically adjusts the black level and contrast. If the black level contrast is adjusted to an appropriate value, the optimum gradation display can be realized for each of the RGB colors. Furthermore, it is preferable to install a function for suppressing bleeding that occurs when the VGA mode or the like is reduced or enlarged. In addition, it is preferable to install a “power save mode” in which the backlight is automatically turned off when not used for a certain period of time.
[1088]
In addition, using N-times pulse driving (a method in which N-times current flows through the EL element 15 and lights it for a period of 1 / M of 1F), the value of M is considerably increased, and the image is displayed to a level that can be recognized slightly. The luminance may be reduced. The above matters are the same in other embodiments of the present invention.
[1089]
The above is a case where the display area of the display panel 82 is relatively small, but the display screen 21 is easily bent when the display area is larger than 30 inches. As a countermeasure, in the present invention, as shown in FIG. 242, an outer frame 481 is attached to the display panel 82, and a fixing member 482 is attached so that the outer frame 481 can be suspended. As shown in FIG. 243, the fixing member 482 is attached to the wall 491 or the like using a fixing member 482 such as a screw.
[1090]
However, as the screen size of the display panel 82 increases, the weight increases. Therefore, a leg attachment portion 484 is disposed below the display panel 82 so that the weight of the display panel 82 can be held by the plurality of legs 483.
[1091]
As shown in FIG. 242, the leg 483 can move left and right as shown in A, and the leg 483 can be contracted as shown in B. Therefore, the display device can be easily installed even in a narrow place.
[1092]
Note that a plastic film-metal plate composite material (hereinafter referred to as a composite material) is used for the legs 483 or the casing (also in the present invention). The composite material is obtained by strongly bonding a metal and a plastic film via a special surface treatment layer (adhesive layer). The metal plate is preferably 0.2 mm or more and 0.8 mm or less, and the plastic film bonded to the metal plate via a special surface treatment layer is preferably 15 μm or more and 100 μm or less. A special adhesion method provides strong adhesion between the plastic and the metal plate. By using this composite material, the plastic layer can be colored, dyed, and printed, and the secondary processing steps (manual application of the film and plating) on the pressed parts can be eliminated. In addition, it is suitable for deep drawing and DI molding, which was impossible in the past.
[1093]
In the television of FIG. 242, the surface of the screen is covered with a protective film (which may be a protective plate) 493. This is for the purpose of preventing an object from hitting the display screen 21 of the display panel 82 and damaging it. An AIR coat is formed on the surface of the protective film 493, and the surface is embossed to prevent external conditions (external light) from appearing on the liquid crystal display screen 21.
[1094]
By dispersing beads or the like between the protective film 493 and the display panel 82, a certain space is arranged. Further, a minute convex portion is formed on the back surface of the protective film 493, and a space is held between the display panel 82 and the protective film 493 by the convex portion. Thus, holding the space prevents the impact from the protective film 493 from being transmitted to the display panel 82.
[1095]
It is also effective to place or inject an optical binder such as a liquid such as alcohol or ethylene glycol or a solid resin such as an epoxy resin between the protective film 493 and the display panel 82. This is because interface reflection can be prevented and the optical binder functions as a buffer material.
[1096]
Examples of the protective film 493 include a polycarbonate film (plate), a polypropylene film (plate), an acrylic film (plate), a polyester film (plate), a PVA film (plate), and the like. In addition, an engineering resin film (ABS or the like) can also be used. Moreover, what consists of inorganic materials, such as tempered glass, may be used. The same effect can be obtained by coating the surface of the display panel 82 with a thickness of 0.5 mm or more and 2.0 mm or less with an epoxy resin, a phenol resin, or an acrylic resin instead of disposing the protective film 493. It is also effective to emboss the surface of these resins.
[1097]
It is also effective to coat the surface of the protective film 493 or the coating material with fluorine. This is because the dirt on the surface can be easily wiped off with a detergent or the like. Further, the protective film may be formed thick and may also be used as a front light.
[1098]
The screen is not limited to 4: 3, and may be a wide display. The resolution is preferably 1280 × 768 dots or higher. By adopting the wide type, it is possible to enjoy full-screen titles and programs such as DVD movies and TV broadcasts in a wide display. The brightness of the display panel 82 is 300 cd / m.2(Candela / square meter) and even 500 cd / m2(Candela / square meter) is preferable. In addition, the brightness (200 cd / m) suitable for Internet and normal personal computer work.2) Is installed so that it can be displayed.
[1099]
In this way, the user can obtain an optimal screen brightness depending on the display contents or the usage method. Furthermore, only the window displaying the video is 500 cd / m.2And other parts are 200cd / m2It is also possible to set to You can flexibly handle the usage of displaying TV programs in the corner of the display and checking emails. The speaker has a tower shape and is designed to spread the sound not only in the front direction but also in the entire space.
[1100]
The usability of TV program playback and recording functions has also improved. For example, recording reservation from i-mode can be easily performed. Conventionally, it has been necessary to make a reservation after confirming the time and channel in a TV program guide such as a newspaper, but the electronic program guide can be checked and reserved in i-mode. If this is the case, you don't need to know the broadcast time. In addition, the recorded program can be shortened. While judging the importance based on the presence or absence of telops and audio of news programs, etc., it is possible to skip the part judged unnecessary and to watch the outline of the program in a short time (about 1 to 10 minutes for a 30-minute program).
[1101]
In addition, a hard disk with a disk capacity of 40 GB or more is loaded so that television recording can be performed. In addition to the main unit, it is composed of an expansion box that combines a power supply and video input / output terminals. In addition to a personal computer and a TV, two systems of video equipment can be connected to an expansion box used to connect AV equipment such as video. Video input is provided with S terminal input in addition to D1 terminal for BS digital tuner, and can be selected according to the connected equipment. In addition, AV terminals are arranged on the front surface for convenient connection with a game machine or the like.
[1102]
Further, by arranging the display screen to be 30 ° or more forward bent and 120 ° or more bent backward and to be rotated 90 ° / 180 ° / 270 °, the display screen can be freely installed according to the operating environment. For example, the browser screen can be displayed vertically by rotating 90 degrees. Moreover, a screen can be displayed toward the person sitting face-to-face by bending back 145 degrees.
[1103]
Needless to say, the above-described matters relating to the protective film 493, the casing, the configuration, the characteristics, the functions, and the like are also applied to other display devices or information display devices of the present invention.
[1104]
In FIG. 72 and the like, one terminal of the capacitor 19 is connected to the Vdd power supply. However, the present invention is not limited to this. For example, as shown in FIG. 165, one terminal may be connected to the gate signal line 17a in the previous stage (the previous pixel row). The gate signal line 17a in the previous stage is selected 1H before, and potential fluctuation occurs, but thereafter, the potential is fixed until it is selected in the next 1F (until the next selection). That is, the gate signal line 17a1 in the previous stage is fixed to the off potential Vgh and can be used as one electrode of the capacitor 19. In this way, a configuration in which the previous gate signal line is used as the capacitor electrode is referred to as a previous configuration.
[1105]
In FIG. 165, the gate signal line 17a is used as an electrode. However, the present invention is not limited to this, and another gate signal line may be used. In addition, the technical idea of the previous configuration is a method of using a fixed potential of an unselected pixel. Therefore, in some cases, the gate potential of the subsequent stage can be used (for example, the gate signal line 17b, the reverse bias voltage Vm, etc.). Needless to say, the above matters can be applied to other pixel configurations.
[1106]
The same matters can be applied to the pixel configuration of the voltage program of FIG. As the previous stage configuration, the configuration of FIG. 155 is exemplified, and one potential of the capacitor 19 is set to the potential of the gate signal line 17a1. 87 is the same as that shown in FIG. As described above, by adopting the former configuration, the number of power supply wirings formed in the pixel can be reduced, and a high aperture ratio can be realized.
[1107]
The TFT 11d in FIG. 72, the TFT 11e in FIG. 73, the TFT 11d in FIG. 74, the TFT 11b in FIG. 75, the TFT 11d in FIG. 76, the TFT 11d in FIG. 77, the TFT 11e in FIG. By controlling the on / off state of the TFT 11d in FIG. 82, the TFT 11d in FIG. 83, the TFT 11e in FIG. 85, the TFT 11e in FIG. 86, etc., FIGS. 49, 53, 59, 61, 63 to 65, 68, Needless to say, the driving method, the display method, or the apparatus described with reference to FIGS.
[1108]
Further, the driving TFT 11b, the taking-in TFT 11c, and the like shown in FIG. 6 are preferably formed of an N channel. This is because the penetration voltage to the capacitor 19 is reduced. Further, since the off-leakage of the capacitor 19 is also reduced, it can be applied to a low frame rate of 10 Hz or less.
[1109]
On the other hand, it is also effective to use a driving TFT 11b and a capturing TFT 11c shown in FIG. When the driving TFT 11b is turned off in the P channel, the off voltage Vgh is obtained. Therefore, the terminal voltage of the capacitor 19 is slightly shifted to the Vdd side, the gate terminal voltage of the conversion TFT 11a is increased, and black display is performed. In addition, since the current value for the first gradation display can be increased (a constant base current can be passed by the gradation 1), writing current shortage can be reduced by the current programming method.
[1110]
In addition, a configuration in which a capacitor is positively formed between the gate signal line 17a and the gate terminal of the conversion TFT 11a to increase the penetration voltage is also effective (see FIG. 244). The capacity of this capacitor is preferably 1/50 or more and 1/10 or less of the capacity of the capacitor 19, and more preferably 1/40 or more and 1/15 or less. Alternatively, the source-gate (SG) or gate-drain (GD) capacitance of the driving TFT 11b is preferably 1 to 10 times, more preferably 2 to 6 times the SG (or GD) capacitance. The capacitor may be formed or disposed between one terminal of the capacitor 19 (gate terminal of the conversion TFT 11a) and the source terminal of the switching TFT 11d (see FIG. 245). Also in this case, the capacity and the like are the same as the values described above.
[1111]
The capacitance of the penetration voltage generating capacitor 19b (capacitance is Cb (pF)) is equal to the capacitance of the charge holding capacitor 19a (capacitance is Ca (pF)) and the white peak current of the TFT 11a (image display). The gate terminal voltage Vb at the time when the current at the black display is applied to the gate terminal voltage Vw at the maximum brightness of the white display (basically the current is 0. That is, when the black display is performed at the image display). Is related. These relationships are
Ca / (200Cb) ≦ | Vw−Vb | ≦ Ca / (8Cb)
Moreover,
Ca / (100 Cb) ≦ | Vw−Vb | ≦ Ca / (10 Cb)
It is preferable to satisfy the following condition. | Vw−Vb | is the absolute value of the difference between the terminal voltage at the time of white display and the terminal voltage at the time of black display of the driving TFT (that is, the changing voltage width).
[1112]
The driving TFT 11b is a P channel, and the P channel is at least a double gate or more, preferably a triple gate or more. More preferably, the number of gates is 4 or more. And it is preferable to form or arrange in parallel a capacitor of 1 to 10 times the source-gate (SG) or gate-drain (GD) capacitance (capacitance when the TFT is on) of the driving TFT 11b. .
[1113]
The above items are effective not only in the pixel configuration of FIG. 6 but also in other pixel configurations. For example, in the pixel configuration of the current mirror shown in FIGS. 19 and 20, a capacitor for causing penetration is arranged or formed between the gate signal line 17a or 17b and the gate terminal of the conversion TFT 11a (see FIGS. 246 and 247). The N channel of the take-in TFT 11c is set to a double gate or more. Alternatively, the take-in TFT 11c and the switching TFT 11d are P-channel, and the triple gate or more. In the voltage program configuration of FIG. 86, a penetration voltage generating capacitor 19c is formed or arranged between the gate signal line 17c and the gate terminal of the driving TFT 11a (see FIG. 248). The take-in TFT 11c is not less than a triple gate.
[1114]
Further, the penetration voltage generating capacitor 19c may be disposed between the drain terminal (capacitor 19b side) of the TFT 11c and the gate signal line 17a or 17c. Further, the penetration voltage generating capacitor 19c may be disposed between the gate terminal of the TFT 11a and the gate signal line 17a.
[1115]
Further, the capacitance of the charge holding capacitor (capacitor 19 in FIGS. 6 and 19) is Ca, and the source-gate capacitance of the switching TFT (11b in FIG. 6, 11c or 11d in FIG. 19) is Cc (for penetration) If the capacitor is a value obtained by adding the capacitance of the capacitor, the high voltage signal applied to the gate signal line is Vgh, and the low voltage signal applied to the gate signal line is Vgl. By configuring so as to satisfy the above, good black display can be realized.
[1116]
0.05V ≦ (Vgh−Vgl) × (Cc / Ca) ≦ 0.8V
More preferably, it is preferable to satisfy the following conditions.
[1117]
0.1V ≦ (Vgh−Vgl) × (Cc / Ca) ≦ 0.5V
The above items are also effective for the pixel configurations of FIGS. 142 and 87. For example, in the pixel configuration of the voltage program of FIG. 142, a penetration voltage generating capacitor 19b is formed or arranged between the gate terminal of the TFT 11a and the gate signal line 17a.
[1118]
The capacitor 19b for generating a penetration voltage is formed by a TFT source wiring and a gate wiring. However, since this is a configuration in which the source width of the TFT 11 is widened and overlapped with the gate signal line 17, there may be a configuration that cannot be clearly separated from the TFT in practice. Further, a method of forming the capacitor 19b for punch-through voltage by forming the driving TFT 11b and the taking-in TFT 11c (in the case of the configuration of FIG. 6) larger than necessary is also within the scope of the present invention. The driving TFT 11b and the capturing TFT 11c are often formed with a channel width W / channel length L = 6/6 μm. The penetration voltage capacitor 19b can also be configured by increasing the channel width W. For example, a configuration in which the ratio of W: L is 2: 1 to 20: 1, preferably 3: 1 to 10: 1 is exemplified.
[1119]
Further, the penetration voltage capacitor 19b is preferably changed in size (capacitance) by R, G, and B modulated by the pixel (see FIG. 249). Since the drive currents of the R, G, and B EL elements 15 are different and the cutoff voltage of the EL element 15 is different, the voltage (current) programmed to the gate terminal of the conversion TFT 11a of the EL element 15 is also different. It is. For example, when the capacitor 19bR for the R pixel is set to 0.02 pF, the capacitors 19bG and 19bB for other colors (G and B pixels) are set to 0.025 pF. Further, when the capacitor 19bR for the R pixel is set to 0.02 pF, the capacitor 19bG for the G pixel is set to 0.03 pF, the capacitor 19bB for the B pixel is set to 0.025 pF, and the like. Thus, the drive current of the offset can be adjusted for each RGB by changing the capacitance of the capacitor 19b for each of R, G, and B pixels. Therefore, the black display level of each RGB can be set to an optimum value.
[1120]
As described above, the capacitance of the punch-through voltage generating capacitor 19b is changed. However, the punch-through voltage in the configuration of FIG. 249 and the like is a relative value of the capacitances of the charge holding capacitor 19a and the punch-through voltage generating capacitor 19b. It is. Therefore, the punch-through voltage generating capacitor 19b is not limited to being changed between R, G, and B pixels. That is, the capacitance of the charge holding capacitor 19a may be changed. For example, when the capacitor 19aR for the R pixel is set to 1.0 pF, the capacitor 19aG for the G pixel is set to 1.2 pF, and the capacitor 19aB for the B pixel is set to 0.9 pF. At this time, the capacitance of the penetration voltage generating capacitor 19b is set to a common value for R, G, and B. Therefore, in the present invention, the capacitance ratio between the charge holding capacitor 19a and the punch-through voltage generating capacitor 19b is different from at least one of the R, G, and B pixels. Note that the capacitances of both the charge holding capacitor 19a and the penetration voltage generating capacitor 19b may be changed in the R, G, and B pixels.
[1121]
Further, the capacitance of the penetration voltage capacitor 19b may be changed on the left and right of the display screen 21 (see FIG. 250). The pixel 16 a is in a position close to the gate driver 12. That is, the pixel 16a is arranged on the signal supply side, and the rise of the gate signal is fast (because the slew rate is high; see the gate waveform 2341a), so that the punch-through voltage increases. Since the pixel 16b is disposed (formed) at the end of the gate signal line 17, the signal waveform is dull (because the gate signal line 17 has a capacity; see the gate waveform 2341b). Therefore, the rise of the gate signal is slow (slew rate is slow), and the punch-through voltage is reduced. Therefore, the penetration voltage generating capacitor 19b of the pixel 16a close to the connection side with the gate driver 12 is reduced, and the capacitor 19b on the end side of the gate signal line 17 is increased. For example, the capacitance of the capacitor is changed by about 10% on the left and right sides of the screen.
[1122]
As described in FIG. 249, the punch-through voltage generated is determined by the capacitance ratio of the charge holding capacitor 19a and the punch-through voltage generating capacitor 19b. Therefore, in FIG. 250, the size of the penetration voltage generating capacitor 19b is changed between the left and right sides of the screen, but the present invention is not limited to this. The penetration voltage generating capacitor 19b may be constant on the left and right sides of the screen, and the capacitance of the charge holding capacitor 19a may be changed on the left and right sides of the screen. It goes without saying that the capacitances of both the punch-through voltage generating capacitor 19b and the charge holding capacitor 19a may be changed on the left and right sides of the screen.
[1123]
In FIG. 250, the capacitance of the charge holding capacitor 19a or the punch-through voltage generating 19b is changed on the left and right of the display screen 21, but the gate driver 12 and the like are arranged on the left and right of the display screen 21 (for example, , The capacitances of the left and right capacitors 19a and 19b of the display screen 21 may be equal. However, if the signal waveform at the center of the screen is dull compared to the signal waveforms on the left and right of the screen, the penetration voltage generating capacitor 19b is made constant on the left and right of the screen, and the charge holding capacitor 19a is penetrated. The capacitance of the voltage generating capacitor 19b is the same on the left and right sides of the display screen 21, and at least one of the capacitance of the charge holding capacitor 19a and the penetration voltage generating capacitor 19b is set at the end and the center of the display screen 21. Change.
[1124]
In FIG. 250, the punch-through voltage and the like may be different even at the same position from the formation position of the gate driver 12 as in the pixel 16a and the pixel 16c. For example, the power supply position or voltage drop of the gate driver 12 and the signal supply position relationship from the source driver 14 are considered. Therefore, the pixel 16c in FIG. 250 differs from the pixel 16a in at least one of the capacitance of the penetration voltage generating capacitor 19b and the capacitance of the charge holding capacitor 19a. The same applies to the pixel 16d.
[1125]
As described above, according to the present invention, at least one of the capacitance of the penetration voltage generating capacitor 19b and the capacitance of the charge holding capacitor 19a is changed in the display screen 21 according to other conditions.
[1126]
As shown in FIGS. 211 and 212, the configuration for forming (arranging) the capacitor 19b of the present invention is as follows. That is, the switching TFT is turned on and then turned off. At this time, it acts on the capacitor 19a and the like, and by changing the gate terminal of the conversion TFT 11 (TFT 11a in FIG. 6) of the EL element 15, it functions to prevent the current of the TFT 11 from flowing. 211, 212, and the like are for the P channel, but the present invention can also be applied to the N channel as shown in FIG. In the case of the N channel, the TFT is turned on at the Vgh voltage, and the TFT is turned off at the Vgl voltage. Therefore, in the case of the N channel, when the TFT 11b (11c) is turned on (a pixel row is selected) to off (the next pixel row is selected), the conversion TFT 11a acts in a direction in which no current flows. What is necessary is just to comprise. Therefore, the present invention is configured to operate the EL element 15 in a direction in which no current flows when the TFT to be selected is turned off.
[1127]
If it demonstrates using FIG. 252, it will still become easy to understand. First, a current Iw as image data is sucked into the source driver 14 from the source signal line 18. Here, for ease of explanation, it is assumed that the program current Iw operates in the direction in which the source driver 14 sucks and is programmed in each pixel 16. Hereinafter, the operation will be described with reference to FIGS. 252 and 253. The description will be made on the pixel row (1).
[1128]
As shown in FIG. 252 (a), an ON voltage Vgl is applied to the gate signal line 17a (1), and a pixel is selected. At this time, the off voltage Vgh is applied to the gate signal line 17b (1). Accordingly, the switching TFTs 11b and 11c are turned on, and the TFT 11d is in an off state.
[1129]
A program current Iw flows through the source signal line 18 and is supplied by the TFT 11a (current Idd = Iw). When the program current Idd flows, the potential of the source signal line 18 becomes a predetermined voltage, and the gate terminal voltage Vg of the TFT 11a is current-programmed. Here, the current programmed current is an Iw current, and the gate terminal voltage Vg is set so that the program current Iw flows in the TFT 11a. In other words, it can be said that the potential of the source signal line is programmed in the pixel. That is, it can be said that the voltage is programmed as the operation state of the pixel.
[1130]
After 1H (one horizontal scanning period), the off voltage Vgh is applied to the gate signal line 17a (1), the TFT 11b and the TFT 11c are turned off, and the voltage necessary for flowing the program current Iw to the capacitor 19a is held. Further, the on voltage Vgl is applied to the gate signal line 17b (1), and the TFT 11d is turned on. Therefore, an Ie (= Iw) current flows through the EL element 15, and the EL element 15 is turned on with the programmed current Ie (see FIG. 252 (b)).
[1131]
The above is the operation of the current programming method described before. However, the present invention differs from the above operation. This is because the current Ie flowing through the EL element 15 is made smaller than the program current Iw. The reason for this can be seen from the change in Vg (gate terminal voltage of the TFT 11a) in FIG.
[1132]
In order to facilitate understanding, the operation of the TFT P-channel will be described. A larger ON current flows through the P-channel TFT as the gate terminal voltage Vg is on the negative side, and the P-channel TFT is completely turned off at 0V. The on-current varies depending on the W / L, mobility, and S value of the TFT. When the W / L of the TFT is 6/12, the channel current Idd is very small up to about −3V. A current of 1 to 5 μA flows at −4V to −4.5V.
[1133]
FIG. 253 shows the time when the current for programming the TFT 11a of the pixel (1) to display substantially black is programmed. First, it is assumed that the gate terminal voltage Vg of the pixel (1) is a Vw voltage (white display or the like). When the pixel (1) is selected, the gate signal line 17a (1) changes from the off voltage Vgh to the on voltage Vgl, so that the potential of the gate signal line 17a penetrates through the capacitor 19b. Due to this penetration, the gate terminal voltage Vg becomes V0.
[1134]
Next, the TFT 11a passes a current equal to the program current Iw absorbed by the source driver 14. However, in the case of black display, the value of current flowing through the TFT 11a is small. As an example, it is 30 nA or less. With such a current, the parasitic capacitance of the source signal line 18 cannot be sufficiently charged / discharged within the 1H period, so the potential of the source signal line 18 cannot be set to a predetermined voltage within the 1H period. That is, the gate terminal voltage Vg is also low, and cannot be set to the originally required Vb voltage, but becomes the Vc voltage.
[1135]
Since the Vc voltage is lower than the Vb voltage, the TFT 11a passes a larger current than the black display to the EL element 15, so that the EL element 15 emits light brighter than a desired value. Therefore, in the EL display panel, black floating occurs and high contrast display cannot be realized.
[1136]
However, the operation of the present invention is different from the above operation. This is because the penetration signal is generated again by the capacitor 19b because the gate signal line 17a (1) changes from the ON voltage Vgl to the OFF voltage Vgh. Due to this punch-through voltage, the Vg voltage shifts from the Vc voltage to the originally required Vb voltage. Accordingly, the TFT 11a is programmed not to pass any current, or is programmed to pass a desired black current. That is, the EL element 15 is programmed so that only a minute current flows. Therefore, the EL display panel of the present invention does not float black and can realize high contrast display. This Vb voltage is held for one field (one frame), that is, until the next pixel is selected and rewritten.
[1137]
As described above, the present invention achieves a good black display by making good use of the punch-through voltage. When the corresponding pixel row is selected and an ON voltage is applied to the gate signal line 17a, the V0 voltage penetrates as shown in FIG. 253, and the Vg voltage is further shifted in the direction of white display. However, the penetrating voltage is charged in a short time by the voltage from the source signal line 18. In particular, since the gate terminal voltage Vg of the TFT 11a is in a decreasing direction, the TFT 11a is in a direction in which more current flows and is charged in a short time. Therefore, there is no problem with penetrating the voltage V0.
[1138]
As the gate terminal voltage Vg of the TFT 11a approaches the target value Vb voltage, the TFT 11a does not flow current. Therefore, the target Vb voltage is not easily reached. In particular, the effect becomes more prominent as the programmed current approaches the black display current. In FIG. 253, the Vb voltage is used instead of the Vb voltage even at the end of the selection period of 1H.
[1139]
After the 1H period, when the corresponding pixel row is not selected and the off voltage Vgh is applied to the gate signal line 17a, the off voltage Vgh is applied to the gate signal line 17a as shown in FIG. Voltage is generated. Due to this punch-through voltage, the gate terminal voltage Vg of the TFT 11a reaches the target Vb voltage.
[1140]
As described above, according to the present invention, the voltage fluctuation of the gate signal line 17a is supplied to the TFT 11a via the capacitor 19b, and the current flowing through the EL element 15 is controlled. This control is particularly effective for realizing black display.
[1141]
In the above description, the driving TFT 11a is controlled by the penetration voltage of the gate signal line 17a of the selected pixel row. However, the present invention is not limited to this. For example, as shown in FIG. 254, a penetration through gate signal lines 17a in adjacent pixel rows may be used.
[1142]
As described with reference to FIG. 93, FIG. 255 shows the voltage waveform of the gate signal line 17 to be applied in the method of simultaneously selecting a plurality of pixel rows and shifting the selected pixel row by one pixel row.
[1143]
In FIG. 254, one terminal of the capacitor 19b is connected to the gate signal line 17a of the next pixel row as described in FIGS. Further, as shown in FIG. 187, the gate signal line 17b is shared by a plurality of pixel rows (short-circuited by the lighting control line 1791). Further, as described with reference to FIGS. 152 and 205, a three-side free configuration in which the gate driver 12 is arranged on one side of the display screen 21 is employed.
[1144]
In order to reduce the influence of kink variations in the TFT 11a of FIG. 6 and the TFT 11b of FIG. 19, it is preferable to fix the potential of the substrate on which the TFT 11 is formed. For example, a TFT may be formed on a metal substrate such as a silicon substrate. Even when a TFT is formed on a glass substrate, a thin potential stabilizing layer is formed on the substrate with a metal or the like, and the TFT 11 or the like is formed thereon. Further, one terminal of an element such as a TFT may be grounded to the potential stabilizing layer. As described above, kink variation can be greatly reduced by fixing the potential of the substrate. In particular, in the case of a configuration in which light is extracted, it is not necessary to make the substrate transparent, and thus the above configuration can be easily adopted.
[1145]
As can be understood from FIG. 255, the gate signal line 17a of the adjacent pixel row becomes the off voltage Vgh with a delay of 1H from the gate signal line 17a of the pixel row of interest. Therefore, the punch-through voltage is applied with a delay of 1H. Other operations are the same as those described with reference to FIGS. 252 and 253, and thus description thereof is omitted.
[1146]
252 and 253 show the case where the driving TFT 11a is a P channel. When the driving TFT 11a is an N channel, the driving waveform shown in FIG. 256 is obtained. In the case of the N channel, the switching TFT 11b and the like are turned on by applying the Vgh voltage and turned off by applying the Vgl voltage. Therefore, as can be seen from the Vg waveform in FIG. 256, the punch-through voltage is generated when the voltage applied to the gate signal line 17a changes from Vgl to Vgh and from Vgh to Vgl. When the next pixel row is selected or not selected, the Vg voltage is lower. Therefore, if the driving TFT 11a is formed with an N channel, a good black display can be realized as described with reference to FIGS.
[1147]
Since FIG. 215 is changed to the P channel and N channel of the TFT of FIG. 6, the operation is the same as that of FIG. Since the change between the P channel and the N channel is the same in FIG. 8 and the like, the concept of the punch-through voltage capacitor 19b of the present invention can be applied to other pixel configurations as they are.
[1148]
Further, the driving TFT 11 (TFT 11a in FIG. 6, TFT 11b in FIG. 19, etc.) is often controlled by the penetration voltage in the N channel rather than in the P channel. The reason for this will be described below.
[1149]
FIG. 257 (a) shows the current output when the drain voltage (D) is sufficiently lower than the source voltage (S) (saturation region). The horizontal axis represents the gate (G) voltage with respect to the source (S) voltage. When the gate voltage is set to the negative side, a current flows between the source (S) and the drain (D). The vertical axis represents the current Ii between the source (S) and the drain (D).
[1150]
In general, a current flows in a TFT formed by low-temperature polysilicon technology when the voltage is lower than V0. The V0 voltage is 3-4V. In general, a P-channel TFT has a current of 1 to 10 μA (for example, W / L = 6/9 μm) from 1 to 1.5 V from a voltage V0 at which current starts to flow. This voltage width is assumed to be Vc (V).
Therefore, in the case of the P channel, when black is displayed, a current starts to flow at the gate (G) voltage V0, and a current of 1 to 10 μA flows at the gate (G) voltage V0 + Vc. When the main part of FIG. 6 is extracted and written in an equivalent circuit diagram, it is as shown in FIG. 257 (c). The capacitance of the charge holding capacitor 19a is Ca, the capacitance of the penetration voltage generating capacitor 19b is Cb, and the channel capacitance of the TFT 11b is Ct. A capacity obtained by adding Cb and Ct is Cc. The gate voltage of the TFT 11a is Vg.
[1151]
The voltage applied to the gate signal line 17a is divided into Ca and Cc capacitors and applied to the gate terminal of the TFT 11a. For example, if Ca: Cc = 3: 2 and the voltage of the gate signal line changes by 10 V, this voltage is divided by 3: 2 and applied to the gate terminal as the Vg voltage. That is, if Vdd = 0V, Vg = -4V when the potential of the gate signal line 17a changes from 0V to -10V.
[1152]
The same applies when a predetermined voltage is applied in advance to the gate voltage Vg. A change in voltage applied to the gate signal line 17a is divided and applied to Ca and Cc capacitors. However, the punch-through voltage is due to a change in the potential of the gate signal line 17. Ca and Cc are fixed values. Therefore, the change in potential is constant because it is determined by the off voltage Vgh and the on voltage Vgl. For example, the punch-through voltage is a constant value such as 0.1 V regardless of the image display state.
[1153]
The gate voltage Vg varies depending on the image. For example, in black display, the gate voltage Vg is -3V, and in white display is -4V (see the solid line a in FIG. 257 (a)). However, since the punch-through voltage is a fixed value such as 0.1 V, for example, the punch-through voltage 0.1 V for black display Vg = 3 V and the punch-through voltage 0.1 V for white display Vg = 4 V are contributions. Is different. That is, the ratio of the punch-through voltage for black display is larger than the ratio of the punch-through voltage for white display. Therefore, the influence of the penetration voltage is large in black display and small in white display.
[1154]
This operation contributes to better display on the EL display panel. That is, if the punch-through voltage is large in black display, the program current flowing through the source signal line 18 is large due to black display. Therefore, it is better that the writing shortage is solved and the influence of the punch-through voltage due to white display is small.
[1155]
When the driving TFT 11 is a P channel, the V0 voltage for black display is -3 V or less, and the absolute value is relatively large. At least a voltage V0 that generates a current (approximately 2 to 50 nA) that flows in gradation 1 (first gradation) for black display and a current Ii (μA) that flows in the maximum gradation for white display are generated. The relationship with the voltage V0 + Vc preferably satisfies the following equation.
[1156]
1/2 ≦ | (Vc + V0) / V0 | ≦ 3
More preferably,
1 ≦ | (Vc + V0) / V0 | ≦ 2
It is preferable to satisfy. This is because the influence of the punch-through voltage becomes noticeable in black display, a good black display can be realized, and the influence of the punch-through voltage in white display can be reduced.
[1157]
In FIG. 257 (a), the conventional voltage width Vc may be relatively larger than V0. That is, the S value is decreased. Or reduce mobility.
[1158]
In the case of the P channel in FIG. 257 (a), it is preferable to shift the V0 voltage to the 0 potential side as indicated by the dotted line b. This shift can be realized by changing the doping amount of the semiconductor layer of the P-channel TFT. The above matters are the same for the N channel in FIG. 257 (b).
[1159]
In manufacturing the array, the doping of the TFTs constituting the gate driver 12 and the like is made the same as the conventional one, and the doping amount of the TFT 11a of the pixel may be changed. This can be formed by using a mask during doping. Further, the TFTs constituting the gate driver 12 and the like are constituted by only the N channel, and the TFT 11a of the pixel is set as the P channel. On the contrary, when the TFT 11a of the pixel is an N channel, the TFT constituting the gate driver 12 is a P channel. The above items can be applied to the following items.
[1160]
FIG. 257 (b) shows the current output when the voltage is sufficiently high (saturation region) with respect to the source voltage (S) and drain voltage (D) of the N-channel TFT. The horizontal axis represents the gate (G) voltage with respect to the source (S) voltage. When the gate voltage is set to the positive side, a current flows between the source (S) and the drain (D). The vertical axis represents the current Ii between the source (S) and the drain (D).
[1161]
In general, an N-channel TFT formed by low-temperature polysilicon technology causes a current to flow when the voltage is V0 voltage or higher. The V0 voltage is 1-2V. In general, an N-channel TFT has a current of 1 to 10 μA (for example, W / L = 6/9 μm) from 1 to 1.5 V from a voltage V0 at which current starts to flow. This voltage width is assumed to be Vc (V).
[1162]
Therefore, in the case of the N channel, when black is displayed, a current starts to flow at the gate (G) voltage V0, and a current of 1 to 10 μA flows at the gate (G) voltage V0 + Vc.
[1163]
The gate voltage Vg varies depending on the image. For example, in black display, the gate voltage Vg is 1.5 V from the ground voltage, and in white display is 2.5 V (see FIG. 257 (b)). However, since the punch-through voltage is a fixed value such as 0.1 V, for example, the punch-through voltage 0.1 V for Vg = 1.5 V for black display and the punch-through voltage 0.1 V for Vg = 2.5 V for white display The contribution is different. That is, the ratio of the punch-through voltage for black display is larger than the ratio of the punch-through voltage for white display. Therefore, the influence of the penetration voltage is large in black display and small in white display. That is, the V0 voltage is lower in the N channel than in the P channel. Therefore, in the driving TFT 11a, the penetration voltage is larger in the N channel than in the P channel, that is, in black display, and the program current supplied to the source signal line 18 is large in black display. Therefore, the shortage of writing is solved.
[1164]
The above matters can be applied to the pixel configuration of the voltage program shown in FIGS. That is, it is possible to prevent current from flowing through the EL element 15 unless the program voltage exceeds a certain level. Therefore, in black display or the like, when the signal fluctuates due to noise, the noise level can be removed (the EL element 15 does not light up to a certain level due to the effect of the punch-through voltage). In addition, the white peak luminance is easily obtained, and the image quality is improved.
[1165]
In the above embodiment, the penetration voltage is set (set to a desired value) by the capacitance of the capacitor 19b. However, the value of the penetration voltage also changes depending on the amplitude value of the gate signal line 17. Therefore, the punch-through voltage can be adjusted by adjusting the amplitude value of the gate signal line 17a (in the case of FIG. 6). For example, if the Vgh voltage of the gate signal line = 10V and the Vgl voltage = 0V, the amplitude value is 10V. In this state, if the punch-through voltage is 0.1 V and the Vgh voltage is 12 V, the amplitude value is 12 V. Therefore, the punch-through voltage is ideally 0.12V. That is, the penetration voltage can be freely changed by the amplitude of the gate signal line 17 and the base current can be adjusted.
[1166]
This control is easy because the power supply circuit that generates the gate voltage may be set to the value of the Vgh voltage or the Vgl voltage by a command. By adjusting this voltage, it is possible to finely adjust the punch-through voltage.
[1167]
When the slew rate of the signal applied to the gate signal line 17a (on / off signal of the TFT 11) (change in voltage with respect to the rise and fall times) is high, the punch-through voltage tends to increase. Conversely, if the slew rate is low, the punch-through voltage decreases. That is, the penetration voltage is larger when the slew rate is 40 V / μsec than when the slew rate is 20 V / μsec. The slew rate of the gate signal varies depending on the driving capability of the output buffer (inverter circuit, operational amplifier, etc.) of the gate driver 12. By controlling the output current of the output buffer, the slew rate can be adjusted and the punch-through voltage can also be adjusted. Controlling the output current of the output buffer can be realized by adjusting the supply voltage of the output buffer, blunting the waveform applied to the gate terminal, and the like. Moreover, it is easy to adjust the supply voltage in terms of the circuit configuration. Dulling the waveform applied to the gate terminal can be realized by reducing the size of the previous buffer (decreasing the capacity). The punch-through voltage can also be changed by using an on / off signal applied to the gate signal line 17a as a sine curve or sawtooth signal. The above matters are also applied to the control of the voltage control signal line and the common signal line described below.
[1168]
In FIG. 211 and the like, the penetration voltage generating capacitor 19b has one electrode serving as the gate signal line 17 (although it is connected to the gate signal line 17), but is not limited thereto. For example, a voltage control signal line for controlling the capacitor 19b is separately formed for generating a penetration voltage. One of the two electrodes of the capacitor 19b may be connected to the gate terminal of the conversion TFT 11a, and the other may be connected to the voltage control signal line formed separately. In this configuration, a pulse signal (not limited to a rectangular wave, may be a sine curve or a sawtooth signal) may be applied to the voltage control signal line in synchronization with the selection state of the gate signal line 17a. Further, the penetration voltage can be easily adjusted by adjusting the pulse amplitude value.
[1169]
This configuration is shown in FIG. By a pulse voltage applied to the voltage control signal line 17c, a punch-through voltage is applied to the gate terminal of the TFT 11a through the capacitor 19b.
[1170]
The operation of the voltage control signal line 17c is the same as that of the gate signal line 17. As illustrated in FIG. 259, the voltage control signal line 17 c is configured as an output terminal of the gate driver 12. Further, as described in FIG. 187, the gate signal line 17b is connected to the lighting control line 1791.
[1171]
If the signal for generating the punch-through voltage is not supplied from the gate signal line 17a but supplied from the voltage control signal line 17c as shown in FIG. 260, the control of the punch-through voltage becomes easy. FIG. 260 is an explanatory diagram of signal waveforms for driving the display panel of FIG. For ease of explanation, it is assumed that the selected pixel row is the pixel row number (1).
[1172]
When the pixel row (1) is selected, the gate signal line 17a (1) changes from the Vgh voltage to the Vgl voltage, so that the potential of the gate signal line 17a penetrates through the capacitor 19b. By this penetration, the Vg voltage becomes V0.
[1173]
Next, the TFT 11 a passes a current equal to the current Iw absorbed by the source driver 14. However, in the case of black display, the value of current flowing through the TFT 11a is small. As an example, it is 30 nA or less. Such a current cannot sufficiently charge and discharge the parasitic capacitance of the source signal line 18 within the 1H period. Therefore, the potential of the source signal line 18 cannot be set to a predetermined voltage within the 1H period. That is, the Vg voltage is also low, and cannot be set to the originally required voltage Vb, but becomes the Vc voltage.
[1174]
Next, since the gate signal line 17a (1) changes from the on voltage Vgl to the off voltage Vgh, a penetration voltage is generated again by the capacitor 19b. Due to this punch-through voltage, the Vg voltage shifts from the Vc voltage to the Va voltage.
[1175]
Further, the voltage control signal line 17c (1) shifts from a low voltage to a high voltage with a time delay of t1. Therefore, a punch-through voltage is further generated, and the gate terminal voltage Vg of the TFT 11a is shifted to the target voltage Vb. By adjusting the shifting voltage, the punch-through voltage can be freely controlled. That is, in the configurations of FIGS. 252 and 253, the change in voltage (the amount of penetration voltage) is restricted by the amplitude of the gate signal line 17a. However, as shown in FIG. 259, by providing the voltage control signal line 17c separately, it becomes easy to change the penetration voltage amount. Further, it is easy to control the slew rate of the applied signal. In addition, since the potential level of the signal applied to the voltage control signal line 17c is not restricted, the circuit configuration is facilitated.
[1176]
Accordingly, the TFT 11a is programmed not to pass any current, or is programmed to pass a desired black current. That is, the EL element 15 is programmed so that only a minute current flows. Therefore, the EL display panel of the present invention does not float black and can realize high contrast display. This Vb voltage is held for one field (one frame), that is, until the next pixel is selected and rewritten.
[1177]
As described above, in the present invention, the voltage fluctuation of the voltage control signal line 17c is supplied to the TFT 11a via the capacitor 11b. Therefore, the current flowing through the EL element 15 is controlled. This control is particularly effective for realizing black display.
[1178]
The difference between FIG. 260 and FIG. 261 is that the operation timing t1 of the voltage control signal line 17c is set to 1H. Other points are the same. With the configuration as shown in FIG. 261, the operation clocks of the gate signal line 17a and the voltage control signal line 17c can be made the same, so that the circuit configuration becomes easy.
[1179]
FIG. 259 shows the pixel configuration of the current program shown in FIG. However, the present invention is not limited to the current programming method, and can be applied to a pixel configuration for voltage programming. FIG. 262 applies the technical idea of the present invention to the pixel configuration of the voltage program described in FIG.
[1180]
In FIG. 262, one terminal of the capacitor 19b is connected to the drain terminal of the TFT 11b, and the other terminal is connected to the voltage control signal line 17c. Note that the switching TFT 11b is formed of an N-channel TFT.
[1181]
FIG. 263 is an explanatory diagram of drive waveforms in the pixel configuration of FIG. When the pixel row (1) is selected, the gate signal line 17a (1) changes from the Vgl voltage to the Vgh voltage, so that the potential of the gate signal line 17a penetrates through the capacitor 19b. Due to this penetration, the Vg voltage changes from Vw held to V0.
[1182]
Next, the TFT 11 a passes a current equal to the current Iw absorbed by the source driver 14. However, with a small black display current, the parasitic capacitance of the source signal line 18 cannot be sufficiently charged / discharged within the 1H period. Therefore, the potential of the source signal line 18 cannot be set to a predetermined voltage within the 1H period. That is, the Vg voltage is also low, and cannot be set to the originally required voltage Vb, but becomes the Vc voltage.
[1183]
Next, since the gate signal line 17a (1) changes from the on voltage Vgh to the off voltage Vgl, a penetration voltage is generated again by the capacitor 19b. Due to this punch-through voltage, the Vg voltage further decreases from the Vc voltage and shifts to the Va voltage.
[1184]
Further, the voltage control signal line 17c (1) shifts from a low voltage to a high voltage with a time delay of t1. Therefore, a punch-through voltage is generated, and the gate terminal voltage Vg of the TFT 11a is shifted to the target voltage Vb. Therefore, the target voltage Vb can be applied to the gate terminal of the TFT 11a.
[1185]
The difference between FIG. 263 and FIG. 264 is that the operation timing t1 of the voltage control signal line 17c is set to 1H. Other points are the same. With the configuration as shown in FIG. 264, the operation clocks of the gate signal line 17a and the voltage control signal line 17c can be made the same, which facilitates the circuit configuration.
[1186]
Various other configurations are exemplified as the configuration using the voltage control signal line 17c. For example, FIG. 265 shows a configuration in which a capacitor 19b is disposed (formed) between the drain terminal of the switching TFT 11c and the voltage control signal line 17c. The configuration in FIG. 265 is not a configuration in which a penetration voltage is directly applied to the gate terminal of the TFT 11a. However, the signal waveform applied to the voltage control signal line 17c is applied to the drain terminal of the TFT 11c via the capacitor 19b. Then, the voltage applied to the drain terminal is reflected (influence, action, control) on the gate terminal of the TFT 11a via the TFT 11b and the like.
[1187]
That is, the pixel configuration in FIG. 265 does not directly control the driving TFT 11a that supplies current to the EL element 15. However, the current flowing through the driving TFT 11a can be controlled. In the present invention, the programmed current is controlled to be lower than that (in some cases, it may be increased. For example, the white peak current is controlled to flow more). is there. Therefore, the configuration of FIG. 265 is also within the scope of the technical idea of the present invention.
[1188]
FIG. 266 shows a method in which the voltage control signal line 17c and the punch-through voltage generating capacitor 19b are formed in the pixel configuration of the current mirror of FIG. This configuration will not require any particular explanation. Therefore, the description is omitted.
[1189]
In FIG. 267, the punch-through voltage generating 11a is not formed. The voltage control signal line 17 c is connected to one terminal of the holding capacitor 19. It has been described so far that the voltage applied to the penetration voltage generating capacitor 19b is used to control the potential of the gate terminal of the TFT 11a to adjust the current flowing through the TFT 11a.
[1190]
In FIG. 267, the voltage at the gate terminal of the TFT 11a is controlled by directly controlling the charge holding capacitor 19, and the current flowing through the TFT 11a is controlled. The operation can be applied as it is or by analogy with the operation described in FIG. In the pixel configuration of FIG. 267, the punch-through voltage generating capacitor 19b is unnecessary. Therefore, the pixel configuration becomes easy.
[1191]
FIG. 268 is an explanatory diagram of drive waveforms in the pixel configuration of FIG. 267. When the gate signal line 17a (1) is selected, the TFTs 11c and 11d are turned on. Next, the TFT 11 a passes a current equal to the current Iw absorbed by the source driver 14. However, with a small black display current, the parasitic capacitance of the source signal line 18 cannot be sufficiently charged / discharged within the 1H period. Therefore, the potential of the source signal line 18 cannot be set to a predetermined voltage within the 1H period. That is, the Vg voltage is also low, and cannot be set to the originally required voltage Vb, but becomes the Vc voltage.
[1192]
Next, the gate signal line 17a (1) changes from the on voltage Vgl to the off voltage Vgh. At the same time, the voltage control signal line 17c (1) shifts from a low voltage to a high voltage. Therefore, a punch-through voltage is generated, and the gate terminal voltage Vg of the TFT 11a is shifted to the target voltage Vb. Therefore, the target voltage Vb can be applied to the gate terminal of the TFT 11a.
[1193]
In FIG. 268, “the gate signal line 17a (1) changes from the on voltage Vgl to the off voltage Vgh. At the same time, the voltage control signal line 17c (1) shifts from a low voltage to a high voltage”. However, the present invention is not limited to this, and the signal waveform may be changed with a period of t1 as shown in FIG. 263 or 264.
[1194]
Needless to say, the pixel configuration in FIG. 267 can also be applied to the pixel configuration in FIG. 6. The voltage control signal line 17c is connected to one terminal of the charge retaining capacitor 19 (see FIG. 269). Then, the gate terminal voltage of the TFT 11a is changed by a signal applied to the voltage control signal line 17c, and the current flowing through the TFT 11a is controlled (adjusted).
[1195]
Further, a signal line insulated from the electrode may be formed under the electrode of the capacitor 19a. This signal line is called a common signal line. If such a configuration is realized, the second capacitor can be formed by the common signal line, the insulating film, and the capacitor electrode. This capacitor can be regarded as the capacitor 19b in FIG. Therefore, by applying a pulse signal to the common signal line in the same manner as before, the same operation and effect as before can be exhibited. Although the calling method is called a common signal line, the function and configuration are not different from the voltage control signal line 17c described above. Therefore, the matters and contents described in the voltage control signal line 17c can be applied to the common signal line as they are.
[1196]
In the above embodiment, one terminal of the punch-through voltage generating capacitor 19b is connected to the gate terminal of the TFT 11a. However, the present invention is not limited to this configuration. For example, as shown in FIG. 270, one terminal of the penetration voltage generating capacitor 19b may be connected to the midpoint of the charge holding capacitors 19a and 19c. By configuring as shown in FIG. 270, the ratio of the influence of the punch-through voltage to the gate terminal of the TFT 11a is reduced.
[1197]
The configuration shown in FIG. 271 is also effective. In FIG. 271, when a pixel is selected, the voltage from the source driver 14 is applied to the drain terminal Vk of the TFT 11b. This voltage (that is, the program current) is divided by the capacitor 19a and the capacitor 19c to become the gate terminal voltage Vg of the driving TFT 11a. Therefore, the gate terminal voltage Vg is lower than the programmed voltage Vk. Therefore, the current flowing through the TFT 11a (current flowing through the EL element 15) is smaller than the programmed current. Therefore, the program current can be increased and the current flowing through the EL element 15 can be reduced. Accordingly, there is no shortage of writing even in black display.
[1198]
In FIG. 271, the capacitance of the charge holding capacitor 19a is Ca, the capacitance of the voltage shifting capacitor 19c is Cc, the high voltage signal applied to the gate signal line is Vgh, and the low voltage applied to the gate signal line. When the signal is Vgl, a satisfactory black display can be realized by configuring so as to satisfy the following conditions.
[1199]
0.5 ≦ | Vgh−Vgl | × (Ca / Cc) ≦ 10
More preferably, it is preferable to satisfy the following conditions.
[1200]
1 ≦ | Vgh−Vgl | × (Ca / Cc) ≦ 5
Also, with reference to Vc in FIG. 257,
0.05 ≦ | Vc | × (Ca / Cc) ≦ 1
More preferably, it is preferable to satisfy the following conditions.
[1201]
1 ≦ | Vc | × (Ca / Cc) ≦ 5
The above items are also effective for the pixel configurations of FIGS. 142 and 87. For example, in the pixel configuration of the voltage program of FIG. 142, a penetration voltage generating capacitor 19b is formed or arranged between the gate terminal of the TFT 11a and the gate signal line 17a.
[1202]
The above matters also apply to the embodiment of FIG. Needless to say, the present invention can also be applied to the pixel configuration described in FIG. 19 and the like (see FIG. 273). Also, the present invention can be applied to the pixel configuration of the voltage program shown in FIGS. The voltage that penetrates the TFT can be compensated. Further, it is possible to operate at the best operating point by shifting the potential.
[1203]
FIG. 271 shows a configuration in which a capacitor 19b for punch-through voltage generation is added. However, in the configuration of FIG. 271, in general, the P-channel TFT 11b needs to have a relatively large channel width W in order to reduce the on-resistance. Therefore, the source-gate capacitance is relatively large. Therefore, the parasitic capacitance generated in the TFT 11b can be substituted without adding the capacitor 19b.
[1204]
As shown in FIG. 271, when both the punch-through voltage generating capacitor 19b and the voltage shifting capacitor 19c are manufactured, the operating point Vg may vary. To solve this problem, it is effective to reduce the punch-through voltage as much as possible by using switching TFTs (TFTs 11b and 11c in FIG. 6; TFTs 11c and 11d in FIG. 19) for selecting pixel rows as N-channels. This embodiment is shown in FIG. In FIG. 272, by setting the switching TFT 11b to the N channel, the punch-through voltage can be reduced to 1/2 to 1/5 as compared with the P channel. Therefore, a punch-through voltage is unlikely to occur and a Vk voltage shift is unlikely to occur. Therefore, variations in the gate terminal voltage Vg of the TFT 11a hardly occur. In FIG. 272, a TFT 11g (switching means) for applying a reverse bias voltage Vm is added.
[1205]
The above is the case of the pixel configuration of FIG. 6, but the configuration of FIG. 19 is also the same (see FIG. 274). When the pixel is selected, the TFT 11d is turned on, and the voltage (current) from the source signal line 18 is written to one terminal of the capacitor 19a connected to the drain terminal of the TFT 11d. That is, the voltage from the source driver 14 is applied to the drain terminal Vk of the TFT 11b. This voltage (that is, the program current) is divided by the capacitor 19a and the capacitor 19c and becomes the gate terminal voltage Vg of the driving TFT 11b. Therefore, the gate terminal voltage Vg is smaller than the programmed voltage Vk, and therefore the current flowing through the TFT 11b (current flowing through the EL element 15) is smaller than the programmed current. Therefore, the program current can be increased and the current flowing through the EL element 15 can be reduced. Accordingly, there is no shortage of writing even in black display.
[1206]
As is obvious, a reverse bias TFT 11g may be added to each pixel 16 as shown in FIG. Needless to say, a capacitor 19b for generating a penetration voltage may be added. Of course, it goes without saying that a TFT 11d for controlling on / off of the current flowing through the EL element 15 may be added. As described above, the present invention can combine the configurations, examples, and technical ideas described in this specification.
[1207]
Note that the common signal line and the voltage control signal line are formed in parallel with the pixel row. That is, the signal line is formed (arranged) for each pixel row. However, it is not necessarily limited to forming for every pixel row. For example, when selecting pixels by two or more pixel rows, the signal lines may be formed (or arranged) for each of a plurality of pixel rows.
[1208]
In FIG. 211 and the like, 19b is a two-terminal capacitor, but is not limited to this. For example, a TFT may be used and a capacitor may be formed using a source-gate capacitance of the TFT. That is, the element that generates the punch-through voltage is not limited to the capacitor, and any element can be used as long as it can be insulated from the gate terminal of the conversion TFT 11a of the EL element 15 and the potential of this terminal can be changed. Of course, it goes without saying that the capacitor can also be configured with the junction capacitance of the diode.
[1209]
Further, although the capacitor 19b is formed in each pixel, it is not necessarily limited to this. For example, one capacitor 19b may be formed by adjacent pixels.
[1210]
Further, a switching element such as a TFT may be disposed (formed) at one end of the capacitor 19b, and the switching element may be controlled to be turned on / off so that the capacitor 19b can be separated from the pixel 16. That is, by separating the capacitor 19b from the pixel 16, the base current can be changed (present or not). Although the capacitor 19b is separated by the switching element, a TFT (switching element) or the like that shorts the electrodes of the capacitor 19b is formed (arranged), and the switching element is turned on, so that the capacitance of the capacitor 19b is reduced to zero. Control may be performed.
[1211]
The target of potential change is not limited to the conversion TFT 11a. Any element that sets the current amount of the EL element 15 may be used. That is, the conversion TFT 11a can be configured by MIM, TFD (thin film diode) or the like. What is necessary is just to comprise so that the electric current which flows into EL element 15 (or flowing) can be controlled by controlling these. In this configuration, the cathode electrode is processed (formed) into a horizontal stripe shape as necessary.
[1212]
In addition, in FIG. 166, FIG. 169, FIG. 172 to FIG. 183, etc., the reverse bias drive method for preventing the deterioration of the EL element 15 by applying the reverse bias voltage Vm has been described. Needless to say, this reverse bias driving method is combined with the method of controlling the current flowing through the EL element 15 by the punch-through voltage described in FIGS. 275, 276, 277, etc. (referred to as the punch-through driving method). Needless to say.
[1213]
FIG. 276 shows a configuration in which a penetration voltage generating capacitor 19b and a TFT 11d for applying a reverse bias voltage Vm are added to the pixel configuration of the voltage program of FIG.
[1214]
Although the reverse bias voltage Vm is applied by the TFT 11d, the present invention is not limited to this and may be replaced by a capacitor. That is, as in the punch-through voltage generating capacitor 19b, a voltage applied to one end of the capacitor may be applied to the EL element 15 by punch-out by applying a pulse voltage to one end of the capacitor.
[1215]
FIG. 277 shows a configuration in which a reverse bias TFT 11g is added to the pixel configuration (current programming method) of the current mirror described in FIG. FIG. 278 shows a pixel configuration in which a reverse bias TFT 11g is added to the voltage programming type pixel configuration described in FIG. FIG. 279 shows a pixel configuration in which a reverse bias TFT 11g is added to the pixel configuration (current programming method) in FIG.
[1216]
In the above embodiment, the punch-through voltage generating capacitor 19b has been described as a two-terminal capacitor. However, the present invention is not limited to this. For example, in FIG. 280, the capacitor 19b is configured (formed, manufactured) with the channel capacity of the transistor 2271. A source-drain capacitance may be used.
[1217]
Similarly, the charge holding capacitor 19a is not limited to a two-terminal capacitor. As described with reference to FIG. 280, a channel capacity of a transistor may be used. Further, a capacitor may be formed by a diode (the transistor 2271 (capacitor 19b) in FIG. 280 can be regarded as a diode). Any other element that can hold a charge may be used. It goes without saying that the above matters can be applied to other embodiments of the present invention.
[1218]
Further, the present invention described in this specification can be combined with each other such as a block driving method, an N-fold pulse driving method, and a multiple pixel row selection method as well as a combination of a punch-through driving method and a reverse bias driving. The above items are the same for the following items.
[1219]
Note that a deviation occurs with respect to the target current due to the punch-through voltage. However, in the method of programming the current to flow approximately N times as large as the EL element 15 and intermittently displaying the display image as in the present invention, the deviation from the target value is also approximately 1 / N. Further, since the TFT 11a is operated in a region closer to the saturation state as compared with a current of one time (normal driving, conventional driving), the deviation is reduced. Therefore, a better image display can be realized as compared with the prior art.
[1220]
The technical idea of the present invention is to control the current flowing through the EL element 15. Therefore, it is not essential that the punch-out voltage generation timing is synchronized with the scanning timing of the gate signal line 17a. Asynchronous control may be possible. The punch-through voltage may be applied by being dispersed multiple times.
[1221]
As shown in FIGS. 111 to 114, the current output circuit 1222 including the DA circuit 1226 outputs current to the source signal line 18. However, as shown in FIGS. 211, 212, and 215, a punch-through voltage is generated. In the case of the driving method, it is necessary to output by adding a constant base current. For example, when a current of 30 nA is programmed in the pixel 16 at a certain gradation, a current obtained by adding a base current due to a punch-through voltage is applied to the source signal line 18. If the base current is 40 nA, a current of 30 nA + 40 nA is applied to the source signal line 18 (absorbed from the source signal line 18 toward the current output circuit 1222). Therefore, it is necessary to configure the circuit so that the base current is applied. For example, a configuration in which a current mirror circuit for base current is added is exemplified.
[1222]
In FIGS. 111 to 114, the current output circuit 1222 including the DA circuit 1226 outputs current to the source signal line 18. However, the present invention is not limited to this. For example, one first current mirror circuit for generating a reference current is formed in the source driver 14 (see FIG. 281).
[1223]
FIG. 281 shows the main part of the current output circuit 1222 corresponding to each source signal line 18. In FIG. 281, description will be made assuming that the applied image data is 6 bits (RGB is 64 gradations). 6 bits correspond to image data D (0 to 5), MSB (most significant bit) is D5, and LSB (least significant bit) is D0.
[1224]
As can be seen from FIG. 281, the switching transistor 2752a is turned on by the image data D0, and one child transistor 2754a is turned on. Similarly, the switching transistor 2752b is turned on by the image data D1, and the two child transistors 2754b are turned on. Further, the switching transistor 2752c is turned on by the image data D2, and the four child transistors 2754c are turned on. Further, the switching transistor 2752d is turned on by the image data D3, and the eight child transistors 2754d are turned on. Further, the switching transistor 2752e is turned on from the image data D4, and the 16 child transistors 2754e are turned on. Further, the switching transistor 2752f is turned on by the image data D5, and the 32 child transistors 2754f are turned on. Therefore, the current Iw expressing 64 gradations flows from the source signal line 18 in accordance with the input image data D. That is, an ON voltage is applied to the gate signal line 17a, and an Idd (= Iw) current flows from the TFT 11a (in the case of FIG. 6) in the selected pixel row.
[1225]
In FIG. 281, one parent transistor 2753 is formed (arranged) in the source driver 14. The current flowing through the parent transistor 2753 flows through the child transistor 2754. That is, if there are 176 source signal lines 18 (in the case of QCIF), 176 × 63 child transistors 2753 are connected to the parent transistor 2753.
[1226]
However, in this case, since the number connected to one parent transistor 2753 is too large, an intermediate transistor may be arranged. For example, if the parent transistor is the first transistor, a second transistor and a third transistor are formed, and 63 child transistors 2754 are connected to the third transistor to form a current mirror relationship. Therefore, when QCIF is exemplified (the number of source signal lines is 176), one second transistor (parent transistor) and 16 second transistors having a current mirror relationship are formed (arranged). Eleventh third transistors having a current mirror relationship with these transistors are formed (arranged). That is, the number of the first to third transistors in the current mirror relationship is 1 × 16 × 11 = 176. The first to third transistors are densely arranged in the source driver 14. This is to eliminate the influence of the Vt variation of each transistor. In particular, the first transistor and the second transistor need to be arranged very close to each other.
[1227]
With the above relationship, the amount of output current of the entire IC chip can be adjusted by adjusting the current flowing through the first current mirror circuit (parent transistor 2753). The current flowing through the parent transistor 2753 is configured to be adjustable with an electronic volume. Further, as shown in FIG. 281, an external volume (bias resistor) 2751 is arranged in the source driver 14, and the resistance value of this resistor is changed, whereby the current flowing through the parent transistor (first transistor) 2753 is changed. You may comprise so that it may change. In any case, by adjusting the current flowing through the parent transistor 2753, the minimum increment of the program current Iw can be easily changed simultaneously with all the source signal lines 18.
[1228]
In FIG. 45, FIG. 46, FIG. 116, etc., a plurality of pixel rows are selected simultaneously. This case can be dealt with by changing the current flowing through the parent transistor 2753. That is, as compared with the case where one pixel row is selected, it is sufficient to pass a current twice as large as the selected pixel row to the parent transistor 2753. In addition, as described with reference to FIG. 121, it is possible to easily cope with a driving method in which a current flowing through the source signal line 18 (absorbed from the source signal line 18) is changed in a period of 1H. This is because the current flowing through the parent transistor 2753 may be varied.
[1229]
By adjusting the current of the parent transistor 2753, the brightness and gamma characteristics of the display panel can be adjusted. Note that the reference current flowing through the parent transistor 2753 is configured to be independently adjustable for each of the R, G, and B pixels. This is because RGB has different gamma curves and applied currents. This configuration is shown in FIG. As shown in FIG. 282, the current flowing through the parent transistors 2753 (2753R, 2753G, 2753B) of the respective colors can be changed by an electronic volume or a bias resistor. Of course, the current flowing through the parent transistor 2753 is corrected so as to match the gamma characteristic and temperature characteristic of the EL element 15.
[1230]
Alternatively, the current output may be changed by forming one (or a plurality of) child transistors 2754 for each of the data D0 to D5 and changing the current magnification of the current mirror circuit with the parent transistor 2753. . For example, the child transistor 2754 corresponding to D0 has a current magnification of 1 with the parent transistor 2753, and the child transistor 2754 corresponding to D1 has a current magnification of 2 with the parent transistor 2753. Similarly, the child transistor 2754 corresponding to D2 has a current magnification of 4 times that of the parent transistor 2753, and the child transistor 2754 corresponding to D3 has a current magnification of 8 times that of the parent transistor 2753. Further, the child transistor 2754 corresponding to D4 has a current magnification of 16 times that of the parent transistor 2753, and the child transistor 2754 corresponding to D5 has a current magnification of 32 times that of the parent transistor 2753.
[1231]
As described above, the output current circuit 1222 adopts a two-stage or three-stage (first transistor, second transistor, and third transistor) current mirror circuit configuration, so that each source signal line 18 is connected to each source signal line 18. The programmed current variation can be eliminated.
When the punch-through voltage capacitor 19b is formed as shown in FIGS. 211 and 215, it is necessary to add and output a constant base current. Further, even when the punch-through voltage capacitor 19b is not disposed (formed), a punch-through voltage is generated by the source-gate terminal capacitance of the TFT 11b. For example, as in the previous case, when a current of 30 nA is programmed in the pixel 16 at a certain gradation, a current obtained by adding a base current due to a punch-through voltage is applied to the source signal line 18. If the base current is 40 nA, a current of 30 nA + 40 nA is applied to the source signal line 18 (absorbed from the source signal line 18 toward the current output circuit 1222). Therefore, it is necessary to configure the circuit so that the base current is applied. For example, a configuration in which a current mirror circuit for base current is added separately is exemplified.
[1232]
In FIG. 283, the transistors 2752bb and 2754bb for applying the base current are arranged (formed) in the source driver 14. The application of the base current is switched by a logic signal applied to the terminal Dbb. In other words, whether or not to apply the base current can be logically controlled.
[1233]
Since the RGB EL elements 15 have different gamma curves and applied currents, it is preferable to configure the base current so that it can be independently adjusted for each RGB, and to be capable of on / off control. This is because, when the base current is applied (the current may be absorbed from the source signal line 18), black floating may occur depending on the image. Therefore, the base current can be optimally adjusted by turning on and off. Further, it is preferable that the ON / OFF of the base current can be set independently for each RGB.
[1234]
As described above, temperature compensation is performed for the reference current flowing through the parent transistor 2753 and the base current flowing through the transistor 2754bb. A panel (more precisely, the temperature of the EL element 15) is detected, and the values of the reference current and the base current are changed according to the detected temperature. In general, the EL element 15 is configured to increase the current applied to the EL element 15 when the temperature rises, because the luminous efficiency decreases as the temperature rises. Further, it is preferable that the temperature compensation of the reference current and the base current can be set independently for each RGB.
[1235]
In the above embodiment, the penetration voltage generating capacitor 19b is formed in the pixel 16, or a larger amount of black display bias current is made to flow using the channel capacitance of the TFT 11b or the like. The matter can also be realized by shifting the potential of the source signal line 18. FIG. 284 shows an example.
[1236]
For example, the voltage applied to the switch circuit 1223 is the voltage output circuit 1221 in FIG. That is, according to the image data, the switch circuit 1223 is turned on to shift the potential of the source signal line 18 toward the Vdd voltage. Accordingly, the potential Vg of the gate terminal of the TFT 11a becomes high, and the TFT 11a does not flow current. The timing for closing the switch circuit 1223 is immediately before the selected pixel row is not selected. That is, immediately before the off voltage is applied to the gate signal line 17a. Therefore, after the current is programmed in the capacitor 19a of the pixel 16 and the switch circuit 1223 is operated, the potential shift caused by the source signal line 18 is superimposed on the capacitor 19a, and then the off voltage is applied to the gate signal line 17a. Is not selected.
[1237]
Note that “according to the image data” means that control is performed to close the switch circuit 1223 in the lower eight gradations close to black display out of the 64 gradations. This is because in black display, since the current flowing through the source signal line 18 is small, insufficient writing tends to occur. That is, the selective precharge described previously.
[1238]
The current output circuit 1222 in FIG. 284 is not limited to FIGS. 143, 144, 281, 282, and 283. Hereinafter, another current output circuit 1222 of the present invention will be described.
[1239]
FIG. 285 is a configuration diagram of a display panel using another current output circuit 1222. In FIG. 285 and the like, the current output circuit 1222 may be formed on the array substrate 49 simultaneously with the pixels 16. That is, the current output circuit 1222 may be formed by low-temperature polysilicon technology. That is, it goes without saying that the pixel TFT may be formed in the same process as that of the pixel TFT, and may be formed in the source driver 14 of the silicon chip and mounted on the array substrate 49 using COG technology or the like. Further, it may be formed by high-temperature polysilicon technology or may be formed by an organic material (organic TFT).
[1240]
The current output circuit 1222 of FIG. 285 has a configuration in which the EL element 15 of FIG. 157 is deleted, and the deleted EL element portion and the source signal line 18 are connected. That is, the source signal line 18 in FIG. 157 becomes the current program line 3002. The output of the current sampling circuit 3001 is connected to the current program line 3002. The current flowing through the current program line 3002 is the current flowing through the source signal line 18. Therefore, the current from the current sampling circuit 3001 flows through the current program line 3002 and is programmed into the capacitor 19. Then, the programmed current is applied to the source signal line 18 in synchronization with the 1H clock. Therefore, since it is necessary to apply current to the source signal line 18 simultaneously in synchronization with the 1H clock, the output stage of the current output circuit 1222 has a switch that is turned on / off in synchronization with the 1H clock.
[1241]
The current output circuit 1222 may have the configuration of the pixel 16 of the current mirror in FIG. The current output circuit 1222 in FIG. 285 has a configuration in which the EL element 15 in FIG. 159 is deleted and the portion of the deleted EL element is connected to the source signal line 18. That is, the source signal line 18 in FIG. 159 becomes the current program line 3002.
[1242]
In the configuration of the current mirror in FIG. 159, the current sampled and written in the current output circuit 1222 and the current value sucked from the source signal line 18 can be made different by setting (configuring) the current magnification. . Therefore, the write current from the current sampling circuit 3001 can be increased, and insufficient writing of the current sampling circuit 3001 can be solved. Conversely, the write current to the source signal line 18 can be increased.
[1243]
In FIGS. 285 and 286, the current output circuit 1222 has been described as a modification of FIGS. 157 and 159, but the present invention is not limited to this. For example, a differential configuration in which a difference between currents flowing through two signal lines (one current is a bias current and the other current is a bias current + signal (write) current) is written in the current output circuit 1222 may be employed. In the differential configuration, current writing shortage from the current sampling circuit 3001 to the current output circuit 1222 does not occur. However, two current program lines 3002 are required.
[1244]
In FIGS. 157 and 159, as described in FIGS. 271, 277, and 275, a bias current can be generated by adding a punch-through voltage generating capacitor 19b to the pixel 16 configuration. Accordingly, the current flowing through the source signal line 18 can be increased in a black display state or the like.
[1245]
In the configuration of FIG. 285, an output from a DA circuit (not shown) that converts digital image data into an analog current is current-sampled by a current sampling circuit 3001, and each current output is arranged (formed) on the source signal line 18. It is held in the circuit 1222 (stored in the capacitor 19). The held current is applied to the source signal line 18 in synchronization with the 1H clock (current is absorbed from the source signal line 18), and is sequentially written into the pixels 16 of the respective display screens 21. By adopting the above configuration, the operational amplifier described with reference to FIG. 144 or the like becomes unnecessary, and the current mirror circuit described with reference to FIG. Further, since the configuration of the current output circuit 1222 is easy, the current output circuit 1222 can also be formed by a low temperature polysilicon technique or the like.
[1246]
However, there are challenges. This is because the operating frequency of the current sampling circuit 3001 is high and insufficient writing into the current output circuit 1222 occurs. To solve this, as shown in FIG. 286, two current output circuits (1222a, 1222b) and two current sampling circuits 3001 (3001a, 3001b) may be arranged (formed).
[1247]
By using two layers in this way, in the first H, current is applied from the current output circuit 1222a to the source signal line 18, and during that period, the current sampling circuit 3001b is operated to hold the write current in the current output circuit 1222b. Let In the next second H, a current is applied from the current output circuit 1222b to the source signal line 18, and during that period, the current sampling circuit 3001a can be operated to hold the write current in the current output circuit 1222a. That is, the operation speed of the current sampling circuit 3001 can be halved. The display screen may be divided into two screens 21a and 21b as shown in FIG. 286 (the source signal line 18 is cut at the center of the screen).
[1248]
Note that whether the current output circuit 1222 described in FIG. 285, FIG. 286, etc. sucks or discharges the program current Iw depends on the pixel 16 configuration. That is, the configuration of the current output circuit 1222 is set (formed) in accordance with the configuration of the pixel 16.
[1249]
In FIG. 286, as described in FIG. 187, the gate signal line 17b is shared by a plurality of signal lines. That is, the block driving method is implemented. As described above, the present invention can be combined with other structures described in this specification. Further, in FIG. 287, a plurality of lighting control lines 1791 are formed and a reverse bias voltage is applied. As described above, the present invention can be combined with other structures described in this specification.
[1250]
The EL display device does not require a backlight like a liquid crystal display device. Therefore, the module thickness can be reduced. The liquid crystal display device displays an image by turning on a backlight. Further, the power consumption of the backlight is as large as 200 to 300 mW for a module used for a mobile phone. In comparison, the power consumption used in the EL display panel is as small as 5 to 10 mW. Therefore, since the backlight is turned on when displaying an image, there is no difference in power consumption as a module no matter what image is displayed.
[1251]
In an EL display device, there is a close relationship between an image display state and power consumption. Normal natural images consume less power. However, white raster display consumes 3 to 4 times as much current as a natural image. Further, the current flowing through the module constantly changes depending on the display state of the image.
[1252]
If the power supply circuit is configured to follow the white raster display and the image display state, the circuit configuration becomes very large. In addition, the power capacity increases. The present invention solves these problems and easily realizes brightness control of the display screen 21.
[1253]
FIG. 288 is an explanatory diagram of the display method of the mobile phone of the present invention as an example of the information display device. FIG. 288 (a) shows the display screen 21 of the mobile phone. The display screen 21b is a part that displays the reception state of the antenna, the time, and the like. That is, it is an area for displaying necessary information on a regular basis. Similarly, the display screen 21c is an area for displaying regularly necessary information such as operation icons. The display screen 21a is an area where menus, images, and the like are constantly displayed, and the displayed image changes constantly.
[1254]
In FIG. 288, it is assumed that the block display method described in FIG. 187, FIG. The display screen 21b corresponds to the three blocks 1981b, and the display screen 21c corresponds to the three blocks 1981c. The display screen 21a corresponds to the remaining block 1981a. Therefore, the brightness of the image can be easily adjusted for each block 1981 by controlling the number of blocks 1981 to be selected. Note that the brightness adjustment of the display screens 21a, 21b, 21c and the like is not limited to the block driving described with reference to FIGS. Of course, it goes without saying that the sequential driving described with reference to FIGS. This is because the brightness adjustment on the display screen 21 can be easily realized for each portion by controlling the clock speed and the like even in the sequential driving.
[1255]
Since the display screens 21b and 21c are portions that are constantly displayed, it is necessary to maintain a constant brightness of the display screen. Further, the current consumption is constant. However, the display screen 21a in FIG. 288 (a) preferably controls the brightness of the image according to the type of image. For example, when a television image is displayed on the display screen 21a and the entire screen suddenly changes to white display (white raster), current suddenly flows from the power supply circuit to the module. The module generates heat due to this current, and there is a risk of deterioration or failure. Note that each of the blocks 1981a, 1981b, and 1981c illustrated in FIG. 288 (b) can be individually subjected to on / off processing (lighting / non-lighting processing), and the brightness of the image can be adjusted. This can be easily realized by controlling the lighting control line 1791.
[1256]
  Therefore, what kind of image is displayed on the display screen 21a is monitored,power consumptionWhen the value increases rapidly, it is necessary to reduce the overall luminance of the display screen 21a by performing arithmetic processing on the image data to be displayed. For example, when white raster display is performed, the size of the image data of the white raster is halved and the display brightness is reduced to ½. Note that the luminance of the image is determined by changing the ratio between the non-display area 312 and the image display area 311 as described in FIG. 187 and the like. By doing so, it is possible to realize image brightness adjustment without changing the size of the image data. Of course, it goes without saying that it may be realized by changing the size of the image data.
[1257]
FIG. 289 is a circuit that suppresses changes in power consumption due to image data. The frame (field) memory 2621 is divided into two areas (2621a, 2621b), and each can hold image data of one screen. The frame memory 2621a and the frame memory 2621b are selected alternately. For example, when image data is read from the frame memory 2621a to the data conversion circuit 2623, the image data is written from the microcomputer (not shown) to the frame memory 2621b. Conversely, when image data is read from the frame memory 2621b to the data conversion circuit 2623, the image data is written from the microcomputer (not shown) to the frame memory 2621a. For ease of explanation, it is assumed that the image data DATA (5: 0) is 6 bits (64 gradations) from D5 to D0.
[1258]
Image data DATA (5: 0) is alternately written in frame memories 2621a and 2621b. The MSB DATA5 is counted by the counter circuit 2622. The reason why DATA5 is counted is that the number of image data in which the bit of DATA5 is set, that is, the number of image data that is 1/2 or more of the maximum luminance is counted. Therefore, the larger the count value of the counter circuit 2622, the higher the luminance of the image, indicating that the power consumed by the module is larger.
[1259]
Now, it is assumed that the image data is written in the frame memory 2621a and is counted by the counter circuit 2622. At this time, the image data in the frame memory 2621b is read.
[1260]
When the count value of the counter circuit 2622 is equal to or greater than a predetermined value (this predetermined value is configured to be variable by a microcomputer (not shown)), the counter circuit 2622 controls the data conversion circuit 2623. This control is a process such as halving the value of the image data from the frame memory 2622 (shifting to the right by 1 bit). That is, the counter circuit counts image data of one screen (image data is written in the frame memory 2621a). Then, this image data is read from the frame memory 2621a, and this image data is controlled.
[1261]
It goes without saying that the image feature extraction can be performed more accurately by counting not only D5 but also DATA (5: 4) or DATA (5: 3). By performing feature extraction accurately, the brightness of the display screen 21a can be adjusted more appropriately.
[1262]
When the power consumption is very large such as image data is white raster, the data conversion circuit 2623 performs image data conversion processing for reducing the image data, and then applies the converted data to the source driver 14. Note that if the image is processed frame by frame and the brightness of the display image is adjusted for each frame, the image blinks (the bright screen and the dark screen are repeated, and the image is blinked). This problem can be dealt with by performing data conversion control of the data conversion circuit 2623 while delaying image processing and considering image changes of a plurality of frames.
[1263]
In FIG. 289, the brightness of the display screen 21a is adjusted by converting the image data and applying it to the source driver 14. However, the present invention is not limited to this, and the lighting time of the block 1981a in FIG. It goes without saying that it may be realized by controlling the above. Hereinafter, this implementation will be described.
[1264]
FIG. 290 is an explanatory diagram of this embodiment. The frame (field) memory 2681 is divided into two areas (2681a and 2681b), and each can hold image data of one screen. The frame memory 2681a and the frame memory 2681b are selected alternately. For example, when image data is being read from the frame memory 2681a to the source driver 14, the image data is written from the microcomputer (not shown) to the frame memory 2681b. Conversely, when image data is being read from the frame memory 2681b to the source driver 14, the image data is written from the microcomputer (not shown) to the frame memory 2681a. The above items are the same as those in FIG.
[1265]
The MSB DATA5 of the image data DATA (5: 0) is counted by the adding circuit 2682a. This is to count the number of image data that is 1/2 or more of the maximum luminance, as in the embodiment of FIG. Therefore, the larger the count value of the adding circuit 2682a, the more image data with higher image brightness.
[1266]
An adder circuit (arithmetic processing circuit) 2682b divides the display screen 21 into a plurality of blocks and processes the average luminance distribution in each block. Further, the arithmetic processing circuit 2682c obtains the distribution state of image data having a predetermined luminance or higher and the distribution state of image data having a predetermined luminance or lower by calculation. That is, the addition circuit (arithmetic processing circuit) 2682 analyzes the average luminance distribution of the display screen 21, the distribution state of the image data, and the like.
[1267]
The gate driver control circuit 2683 accumulates the calculation results (processing results) from the calculation processing circuit 2682 over a plurality of frames, and sends ST data applied to the shift register 22 of the gate driver 12 or ON / OFF data of the lighting control line 1791. .
[1268]
For example, if the brightness of the screen is adjusted by the control of the shift register 22, it is as shown in FIG. When darkening an image, the number of ST data applied to the shift register 22 is reduced as shown in FIG. Therefore, the ratio of the image display area 311 occupying the display screen 21 is lowered and darkened. When the display screen 21 is relatively brightened, the width of the image display area 311 in FIG. 291 (b) is increased, or the number of the image display areas 311 is increased. Further, when the display screen 21 is brightened, the width of the image display area 311 in FIG. 291 (c) is further increased, or the number of the image display areas 311 is further increased. It should be noted that the above processing can also be realized by the selection processing in block 1981 in FIG. Therefore, the description is omitted.
[1269]
Further, whether the image data is a moving image or a still image is detected (moving image detection and ID processing are performed), and the number of image display areas 311 in FIG. 291 may be adjusted. That is, in the case of a moving image, the number of image display areas 311 is reduced and moving image blur is eliminated. In the case of a still image, the number of image display areas 311 is increased and the image display areas are distributed over the display screen 21 in order to suppress the occurrence of flicker.
[1270]
In FIG. 289, the number of pieces of image data having a predetermined luminance or higher is counted and the brightness of the display screen 21 is controlled. However, as in FIG. 290, image features are extracted to change the luminance of the display screen 21. May be. This embodiment is shown in FIG. Needless to say, the embodiments of FIGS. 290 and 292 may be combined.
[1271]
FIG. 292 is an explanatory diagram of this embodiment. The frame (field) memory 2621 is divided into two areas (2621a, 2621b), and each can hold image data of one screen. The frame memory 2621a and the frame memory 2621b are selected alternately. For example, when image data is read from the frame memory 2621a to the data conversion circuit 2692, the image data is written from the microcomputer (not shown) to the frame memory 2621b. Conversely, when image data is being read from the frame memory 2621b to the data conversion circuit 2692, the image data is written from the microcomputer (not shown) to the frame memory 2621a. The above items are the same as in FIG. 289 or FIG.
[1272]
The MSB DATA5 of the image data DATA (5: 0) is counted by the adding circuit 2682a. The larger the count value of the adder circuit 2682a, the more image data with higher image brightness. The adder circuit (arithmetic processing circuit) 2682b divides the display screen 21 into a plurality of blocks, and processes the average luminance distribution in each block as before. Further, the arithmetic processing circuit 2682c obtains the distribution state of image data having a predetermined luminance or higher and the distribution state of image data having a predetermined luminance or lower by calculation. That is, the addition circuit (arithmetic processing circuit) 2682 analyzes the average luminance distribution of the display screen 21, the distribution state of the image data, and the like.
[1273]
The data control circuit 2691 accumulates the operation results (processing results) from the operation processing circuit 2682 over a plurality of frames, controls the data conversion circuit 2692, and performs image data conversion processing.
[1274]
For example, if the brightness of the screen is to be adjusted, the size of the image data obtained by bit-shifting the data is converted as in FIG. At the same time, based on the analysis result of the image data, optimal gamma conversion processing is performed as shown in FIG.
[1275]
FIG. 293 is a gamma table. The horizontal axis indicates the gradation number, and the vertical axis indicates the relative value of the display luminance. The dotted line in FIG. 293 is a linear case, and the solid line is a case where gradation collapse occurs in the black display area and the white display area. In addition, the alternate long and short dash line is a case where gradation collapse occurs only in the black gradation part.
[1276]
As described above, the feature extraction of the image is performed by the arithmetic processing circuit 2682, and the gamma curve of the display image is selected based on the result, and the data is converted into a table. Three or more types of gamma tables are provided, and the optimum one is selected. Then, the converted image data is input to the source driver 14.
[1277]
Further, as described with reference to FIG. 291, when darkening an image, the number of ST data applied to the shift register 22 is reduced as shown in FIG. Therefore, the ratio of the image display area 311 occupying the display screen 21 is lowered and darkened. When the display screen 21 is relatively brightened, the width of the image display area 311 in FIG. 291 (b) is increased, or the number of the image display areas 311 is increased. Further, when the display screen 21 is brightened, the width of the image display area 311 in FIG. 291 (c) is further increased, or the number of the image display areas 311 is further increased. In order to make the displayed image look relatively bright with low power consumption, the maximum luminance of the display luminance is decreased, the minimum luminance is increased (that is, the contrast of the image is reduced), and the overall average luminance is also achieved. Should be reduced.
[1278]
Further, whether the image data is a moving image or a still image is detected (moving image detection and ID processing are performed), and the number of image display areas 311 in FIG. 291 may be adjusted. That is, in the case of a moving image, the number of image display areas 311 is reduced and moving image blur is eliminated. In the case of a still image, the number of image display areas 311 is increased and the image display areas are distributed over the display screen 21 in order to suppress the occurrence of flicker.
[1279]
In FIG. 288, the display screen has three areas 21a, 21b, and 21c, and the display brightness of the display screen 21a is changed. However, the display screen 21a is not limited to this, and the display screens 21b and 21c are also changed. Also good.
[1280]
In addition, as illustrated in FIG. 294, display screens 21d and 21e may be provided at the end of the display screen. The display screens 21d and 21e display as a simple frame (that is, a pixel electrode is formed and a dot pattern cannot be displayed). Accordingly, the display screens 21d and 21e are displayed as a simple matrix. That is, when a voltage is applied to the display screens 21d and 21e, the entire screen is turned on.
[1281]
As shown in FIG. 295, when a voltage is applied to the lighting control line 1791a, the EL film on the display screen 21d is turned on. Further, when a voltage is applied to the lighting control line 1791b, the EL film of the display screen 21e is turned on. Other configurations (such as 1891) have been described before and will not be described.
[1282]
As shown in FIG. 296, a smoothing film 71 is formed on the gate driver 12 formed by polysilicon technology. A pixel electrode 48b is formed of the same material as the pixel electrode 48a thereon, and an organic EL layer 47 is formed on the pixel electrode 48b. A cathode electrode (or anode electrode) is formed on the organic EL layer 47. By applying a voltage to the pixel electrode 48b, the display screens 21d and 21e are turned on.
[1283]
In the above embodiment, the EL element 15 is R, G, B, but is not limited thereto. For example, cyan, yellow, magenta, or any two colors may be used. Six colors of R, G, B, cyan, yellow, and magenta, or any four or more colors may be used. Further, it may be a white single color, or white single color light may be converted to RGB by a color filter. Moreover, it is not limited to an organic EL element, An inorganic EL element may be sufficient.
[1284]
In the liquid crystal display panel of the present invention or the display device using the same, it is preferable that a plurality (a plurality of types) of gate drivers 12 and source drivers 14 are integrated. By doing this, it is possible to display images entering from any communication network, such as videos and still images downloaded from mobile phone networks and wireless LANs, and images received from terrestrial television broadcasts, without burdening the MPU. . High-definition images are displayed using a VGA-compatible 6-bit gate driver 12 and source driver 14, and are switched to QVGA if the definition is reduced, and 1-bit gate driver 12 and source driver 14 are used for text data. . It is also preferable to separately form an NTSC display driver (interlace, pseudo-interlace scanning) and a progressive display driver (non-interlace). Needless to say, the gate driver 12 and the source driver 14 having a plurality of functions may be formed of a silicon chip and mounted by COG technology or the like.
[1285]
In FIGS. 45 and 46, the active matrix display panel has been described as an example. However, the present invention is not limited to this. The source driver 14 or the like applies (absorbs) a current N times the predetermined current to the source signal line 18. A plurality of pixel rows are selected simultaneously. The concept that current is supplied to the EL element only during a predetermined period and current is not supplied during the other periods can be applied to a simple matrix display panel.
[1286]
When the gate driver 12 and the source driver 14 are of one type, it is necessary to perform signal conversion processing by the MPU in order to display images with different resolutions. When a large number of gate drivers 12 and source drivers 14 are prepared in addition to the liquid crystal display panel, it is necessary to individually mount ICs, which increases costs and increases the mounting area. In addition to the gate driver 12 and the source driver 14, many circuits such as an image processing circuit may be integrated in the Si film on the display panel 82.
[1287]
In addition, since the EL element has a large characteristic change in the early stage of lighting, burning and the like are likely to occur. For this measure, it is preferable to ship the product as a product after aging with white raster display for 20 hours or more and 150 hours or less after the panel is formed. In this aging, it is preferable to display at a brightness of about 2 to 10 times the predetermined display luminance.
[1288]
In the present invention, the pixel configuration described in FIG. 85, FIG. 87, etc. will be described focusing on the pixel configuration of the voltage program, and the pixel configuration of the current program described in FIG. 6, FIG. Although a signal is supplied from the source driver 14 and written in synchronization with the 1H period, the present invention is not limited to this. For example, it may be combined with time-division driving in which one frame or one field is divided into a plurality of subframes (fields). In addition, an area gradation method in which a pixel is divided into a plurality of pixels may be combined.
[1289]
21, 49, 50 to 53, 55, 60, 63, 66, 67, 69, 169, 172 to 183, etc. Although described, a semiconductor chip made of gallium arsenide, silicon, germanium or the like that realizes these technical ideas is also within the scope of the present invention. A display device, an information display device, or the like can be realized by mounting these semiconductor chips on a display panel.
[1290]
Further, by connecting the terminal for applying the Vbb voltage in FIG. 6B, FIG. 20, FIG. 76, FIG. 79, FIG. 80, FIG. 82, etc. to the gate driver 12b as described in FIG. Image display can be realized.
[1291]
Further, the items related to the power supply voltage Vdd described in FIGS. 185 and 226 and the like are also applied to all pixel configurations, display panels, information display devices, and driving methods in this specification. 2-5, 23-33, 37, 38, 164, 169, 172-183, 225, 227-229, 234, 237, 239- Needless to say, the present invention also applies to all pixel configurations, driver arrangements, display panels, information display devices, and driving methods in this specification with reference to FIG.
[1292]
45, FIG. 46, FIG. 84, FIG. 88 to FIG. 94, FIG. 116 to FIG. 141, the driving method and driving circuit of the present invention, and FIG. 163, FIG. 166, FIG. By combining a method or configuration for applying a reverse bias voltage to the EL element 15, a more characteristic effect is exhibited. Further, it goes without saying that these can be applied to the pixel configurations described in FIGS. 6, 19, 85 to 87, 168, 169 to 183, 244 to 247, and 251. Further, it is not necessary to explain that these configurations can realize FIGS. 48 to 51, 53 to 60, 63 to 65, 68, 70, 71, and 85. Needless to say, the combination with the three-side free configuration of FIGS. 23 to 32 is also effective. 2-5, 23-33, 37, 38, 164, 169, 172-183, 225, 227-229, 234 using these techniques. Needless to say, the present invention can be applied to the display panel, the information display device, or the driving method shown in FIGS. 237 and 239 to 242.
[1293]
In addition, the method or configuration for applying a reverse bias voltage to the EL element 15 described with reference to FIGS. 163, 169, 172 to 183, etc. are also shown in FIGS. 6, 19, 49, 62, 66, 67, 72 to 76, 79 to 83, 85 to 87, 155 to 162, 165, 169, 172 to 184, 244 to 247, 251 and other pixel configurations or arrays Needless to say, it applies to the configuration. Further, it is not necessary to explain that these configurations can realize FIGS. 48 to 51, 53 to 60, 63 to 65, 68, 70, 71, and 85. Needless to say, it is also effective to combine with a three-side free configuration such as FIGS. 23 to 32, 187 to 200, and 206 to 209. In particular, the three-side free configuration is effective when the pixel is manufactured using amorphous silicon technology. In addition, in a panel formed by amorphous silicon technology, it is not possible to control the process of variation in characteristics of TFT elements, and therefore it is preferable to implement current driving according to the present invention.
[1294]
Furthermore, using these techniques, FIGS. 2-5, 23-33, 37, 38, 164, 169, 172-183, 225, 227-229, 234, Needless to say, the present invention can be applied to the display panel, the information display device, or the driving method shown in FIGS. 237 and 239 to 242.
[1295]
The pixel configuration described in FIGS. 168, 169, 170 to 183, or the pixel configuration or array configuration in the driving method is not limited to the EL display panel. For example, it can be applied to a liquid crystal display panel. In that case, the EL element 15 may be replaced with a light modulation layer such as a liquid crystal layer, PLZT, or LED. For example, in the case of liquid crystal, TN (Twisted Nematic), IPS (In-Plane Switching), FLC (Ferroelectric Liquid Crystal), OCB (Optical Compensatory Bend), STN (Super Tender Vend). Electrically Controlled Birefringence (HAN), Hybrid Aligned Nematic (HAN) mode, DSM mode (dynamic scattering mode), and the like. In particular, since DSM can be optically modulated by an applied current, matching with the present invention is good.
[1296]
Further, the switching element is not limited to the TFT. Needless to say, the present invention is applied to all pixel configurations, driver arrangements, display panels, information display devices, and driving methods in this specification.
[1297]
1, 6, 19, 28 to 32, 49, 62, 66, 67, 72 to 76, 79 to 83, 85 to 87, 95, 100 to 100 106, 109 to 115, 155 to 162, 165, 169, 172 to 184, 244 to 256, 258 to 267, 269, 270, 272, 273, The pixel configuration or array configuration shown in FIGS. 275 to 280 is not limited to the EL display panel. For example, it can be applied to a liquid crystal display panel. In that case, the EL element 15 may be replaced with a light modulation layer such as a liquid crystal layer, PLZT, or LED. Further, the switching element is not limited to the TFT as described with reference to FIG.
[1298]
3, 10 to 12, 23, 26, 28 to 32, 164, 232, 234, 235, 239 to 242, 268, 288, 296, etc. The configuration, apparatus, and method are not limited to those using an EL display panel. For example, the present invention can be applied to a display using a PDP display panel, a PLZT display panel, a liquid crystal display panel, or the like.
[1299]
By using the manufacturing method of FIGS. 13 to 16, 20, and 43, FIGS. 1, 6, 10 to 12, 19, 39, 49, 62, 66, 67, and FIG. 72 to 76, 79 to 83, 85 to 87, 95, 100 to 106, 109 to 115, 155 to 162, 165, 169, 172 to 184, Display panels having pixel configurations or array configurations such as those shown in FIGS. 244 to 256, FIGS. 258 to 267, 269, 270, 272, 273, and 275 to 280 can be easily manufactured. Moreover, an information display apparatus can be comprised using these. Needless to say, the configurations or structures of FIGS. 7 to 12 and 17 can be applied to the display panel or display device of the present invention.
[1300]
101 to 106, 109, and 110, or the driving method thereof, the pixel configuration is as shown in FIGS. 1, 6, 10 to 12, 19, 39, 49, 49, and FIG. 62, 66, 67, 72-76, 79-83, 85-87, 95, 100-106, 109-115, 155-162, 165, 169 172 to 184, 244 to 256, 258 to 267, 269, 270, 272, 273, 275 to 280, and the like can be applied. .
[1301]
1, 6, 19, 49, 62, 157 to 159, 162, 184, 81, 160, 161, 66, 85, 86, 72 to 75. 83, 67, 76, 80, 82, 79, 183, 169, 172 to 182, 87, 165, 155, 156, 244 to 247, FIG. 251, 39, 248, 275-280, 252-256, 249, 250, 258-267, 269, 100-106, 109-115, 270, Needless to say, the pixel configuration or array configuration shown in FIGS. 273, 272, and 95 can be applied to the information display devices shown in FIGS. 230, 231, 233, 238, 295, 288, and 294.
[1302]
6, 19, 49, 62, 157, 158, 159, 162, 184, 81, 160, 161, 66, 85, 86, 72 to FIG. 75, 83, 67, 76, 80, 82, 79, 183, 169, 172 to 182, 87, 165, 155, 156, 244 to 247, 251, 248, 275 to 280, 252 to 256, 249, 250, 250, 258 to 267, 269, 100, FIG. 1, 101 to 104, 110, 109 105, 106, 111-115, 270, FIGS. 10-12, 273, 272, and other pixel configurations or array configurations are shown in FIGS. 164, 232, 235, 234, 3 23, 26, 239, 240, 241, FIG. 242, FIGS. 28 to 32, FIGS. 210 to 217, 230, FIG. 231, 233, FIG. 238, FIG. 218 to 223, FIGS. 251, 248, 275 to 280, FIG. 256, 249, 250, 258 to 267, 269, 100, 1, 101 to 104, 110, 109, 105, 106, 111 to 115, 270 Needless to say, these can be employed in FIGS. 273, 272, and 95.
[1303]
In addition, the configuration of the source driver in FIGS. 281 to 283, the configuration of the current output circuit 1222 in FIGS. 284 to 287, and the like are the pixel configurations in FIGS. 6, 19, 49, 62, 157, 158, 159, 162, 184, 81, 160, 161, 66, 85, 86, 72-75, 83, 67, 76, 80, 82, 79 183, 169, 172-182, 87, 165, 155, 156, 244-247, 251, 248, 275-280, 252-256, 249, 250, 258 to 267, 269, 100, 1, 101 to 104, 110, 109, 105, 106, 111 to 115, 270, 10 to 12 Applicable to FIG. 273, FIG. 272, etc. Rukoto goes without saying. Similarly, the present invention is applicable to the driving method or data processing method shown in FIGS. 107, 108, 110, 253, 255, 256, 260, 261, 263, 264, and 289 to 293. Needless to say, you can. The same applies to the driving method and pixel configuration described in FIGS. 101 to 106, 109, 110, and the like. It goes without saying that an information display device or the like can be configured using these.
[1304]
The manufacturing method of FIGS. 13 to 16, FIG. 43, FIG. 44, etc. is not limited to the manufacturing method of the EL display panel. For example, the present invention can be applied to a liquid crystal display panel manufacturing method. Moreover, even if it is in the structure or method of FIGS. 23-32, it is not limited to an EL display panel, and it cannot be overemphasized that it can apply also to an LED display panel, a liquid crystal display panel, etc. 49, 48, 53-59, 63-65, 68, 70, 71, 85, 50, 51, 60, 288, 294, 295, etc. The same applies to the method.
[1305]
As described above, the technical idea described in the embodiments of the present invention can be applied to a video camera, a projector, a stereoscopic television, a projection television, and the like. The present invention can also be applied to a viewfinder, a mobile phone monitor, a PHS, a portable information terminal and its monitor, a digital camera and its monitor. The present invention can also be applied to an electrophotographic system, a head mounted display, a direct view monitor display, a notebook personal computer, a video camera, and an electronic still camera. The present invention can also be applied to an automatic cash drawer monitor, public telephone, videophone, personal computer, wristwatch, and display device thereof. Furthermore, it goes without saying that the present invention can be applied or applied to display monitors for home appliances, pocket game devices and their monitors, backlights for display panels, or lighting devices for home use or business use. The lighting device is preferably configured so that the color temperature can be varied. In this case, the color temperature can be changed by forming RGB pixels in a stripe or dot matrix and adjusting the current flowing through them. It can also be applied to display devices such as advertisements or posters, RGB traffic lights, warning indicator lights, and the like.
[1306]
The organic EL panel is also effective as a light source for the scanner. Using an RGB dot matrix as a light source, the object is irradiated with light to read an image. Of course, it goes without saying that it may be monochromatic. Moreover, it is not limited to an active matrix, A simple matrix may be sufficient. If the color temperature can be adjusted, the image reading accuracy can be improved.
[1307]
The organic EL display device is also effective for the backlight of the liquid crystal display device. The RGB pixels of the EL display device (backlight) are formed in a stripe shape or dot matrix shape, and the color temperature can be changed by adjusting the current passed through them, and the brightness can be easily adjusted. In addition, since it is a surface light source, a Gaussian distribution that brightens the central part of the screen and darkens the peripheral part can be easily configured. It is also effective as a backlight for a field sequential type liquid crystal display panel that alternately scans R, G, and B light. Further, even when the backlight is blinking, it can be used as a backlight of a moving image display liquid crystal display panel by inserting black.
[1308]
【The invention's effect】
The display panel, display device, and the like of the present invention exhibit distinctive effects according to their respective configurations such as high image quality, good moving image display performance, low power consumption, low cost, and high brightness.
[1309]
Note that if the present invention is used, a low power consumption information display device or the like can be configured, so that power is not consumed. Moreover, since it can be reduced in size and weight, resources are not consumed. Further, even a high-definition display panel can be sufficiently handled. Therefore, it is friendly to the global environment and space environment.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a display panel of the present invention.
FIG. 2 is a cross-sectional view of the display device of the present invention.
FIG. 3 is a cross-sectional view of the display panel of the present invention.
FIG. 4 is a cross-sectional view of the display device of the present invention.
FIG. 5 is a cross-sectional view of the display device of the present invention.
FIG. 6 is a circuit configuration diagram of the display panel of the present invention.
FIG. 7 is an explanatory diagram of a display panel according to the present invention.
FIG. 8 is an explanatory diagram of a display panel according to the present invention.
FIG. 9 is an explanatory diagram of a display panel according to the present invention.
FIG. 10 is an explanatory diagram of a display panel of the present invention.
FIG. 11 is an explanatory diagram of a display panel of the present invention.
FIG. 12 is an explanatory diagram of a display panel according to the present invention.
FIG. 13 is an explanatory diagram of a method for manufacturing a display panel according to the present invention.
FIG. 14 is an explanatory diagram of a method for manufacturing a display panel according to the present invention.
FIG. 15 is an explanatory diagram of a display panel manufacturing method according to the present invention.
FIG. 16 is an explanatory diagram of a method for manufacturing a display panel according to the present invention.
FIG. 17 is an explanatory diagram of a display panel of the present invention.
FIG. 18 is an explanatory diagram of a display panel of the present invention.
FIG. 19 is an explanatory diagram of a display panel of the present invention.
FIG. 20 is an explanatory diagram of a display panel of the present invention.
FIG. 21 is a circuit configuration diagram of a display device of the present invention.
FIG. 22 is an explanatory diagram of a display device of the present invention.
FIG. 23 is an explanatory diagram of a display panel of the present invention.
FIG. 24 is an explanatory diagram of a display panel of the present invention.
FIG. 25 is an explanatory diagram of a display panel of the present invention.
FIG. 26 is an explanatory diagram of a display panel of the present invention.
FIG. 27 is an explanatory diagram of a display panel of the present invention.
FIG 28 is an explanatory diagram of a display panel driving method according to the invention.
FIG. 29 is an explanatory diagram of a display panel of the present invention.
FIG. 30 is an explanatory diagram of a display panel of the present invention.
FIG. 31 is an explanatory diagram of a display panel of the present invention.
FIG. 32 is an explanatory diagram of a display panel of the present invention.
FIG. 33 is an explanatory diagram of a display device of the present invention.
34 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 35 is an explanatory diagram of a display panel of the present invention.
36 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 37 is an explanatory diagram of a display device of the present invention.
FIG. 38 is a cross-sectional view of a display device of the present invention.
FIG. 39 is an explanatory diagram of a display panel of the present invention.
FIG. 40 is an explanatory diagram of a display panel of the present invention.
41 is an explanatory diagram of a method for manufacturing a display panel of the present invention. FIG.
42 is an explanatory diagram of a display panel of the present invention. FIG.
43 is an explanatory diagram of a display panel manufacturing method according to the present invention. FIG.
44 is an explanatory diagram of a method for manufacturing a display panel of the present invention. FIG.
FIG. 45 is an explanatory diagram of a display panel driving method according to the present invention.
46 is an explanatory diagram of a display panel driving method according to the present invention. FIG.
47 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 48 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 49 is an explanatory diagram of a display panel driving method according to the present invention.
50 is an explanatory diagram of a display panel driving method according to the present invention. FIG.
FIG. 51 is an explanatory diagram of a display panel driving method according to the present invention.
52 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
FIG. 53 is an explanatory diagram of a display panel driving method according to the present invention.
54 is an explanatory diagram of a display panel driving method according to the present invention. FIG.
FIG. 55 is a circuit block diagram of a display panel of the present invention.
56 is an explanatory diagram of a display panel driving method according to the present invention. FIG.
57 is an explanatory diagram of a display panel driving method according to the present invention. FIG.
FIG. 58 is an explanatory diagram of a display panel driving method according to the present invention.
59 is an explanatory diagram of a display panel driving method according to the present invention. FIG.
60 is an explanatory diagram of a display panel driving method according to the present invention. FIG.
61 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
FIG. 62 is an explanatory diagram of a display panel of the present invention.
FIG. 63 is an explanatory diagram of a display panel driving method according to the present invention;
FIG. 64 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 65 is an explanatory diagram of a display panel driving method according to the present invention.
66 is a circuit block diagram of a display panel of the present invention. FIG.
67 is a circuit block diagram of a display panel of the present invention. FIG.
68 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
FIG. 69 is a circuit block diagram of a display panel of the present invention.
70 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
71 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
72 is an explanatory diagram of a display panel of the present invention. FIG.
73 is an explanatory diagram of a display panel of the present invention. FIG.
74 is an explanatory diagram of a display panel of the present invention. FIG.
75 is an explanatory diagram of a display panel of the present invention. FIG.
76 is an explanatory diagram of a display panel of the present invention. FIG.
77 is an explanatory diagram of a display panel of the present invention. FIG.
78 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 79 is an explanatory diagram of a display panel of the present invention.
80 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 81 is an explanatory diagram of a display panel of the present invention
82 is an explanatory diagram of a display panel of the present invention. FIG.
83 is an explanatory diagram of a display panel of the present invention. FIG.
84 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
FIG. 85 is an explanatory diagram of a display panel of the present invention.
FIG. 86 is an explanatory diagram of a display panel of the present invention.
87 is an explanatory diagram of a display panel of the present invention. FIG.
88 is an explanatory diagram of a display panel driving method according to the present invention. FIG.
FIG. 89 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 90 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 91 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 92 is an explanatory diagram of a display panel driving method according to the present invention.
93 is an explanatory diagram of a display panel driving method of the invention. FIG.
FIG. 94 is an explanatory diagram of a display panel driving method according to the present invention.
95 is an explanatory diagram of a display panel of the present invention. FIG.
96 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 97 is an explanatory diagram of a display panel according to the present invention.
FIG. 98 is an explanatory diagram of a display panel of the present invention.
FIG. 99 is an explanatory diagram of a display panel of the present invention.
FIG. 100 is an explanatory diagram of a display panel of the present invention.
FIG. 101 is an explanatory diagram of a display panel of the present invention.
FIG. 102 is an explanatory diagram of a display panel of the present invention.
FIG. 103 is an explanatory diagram of a display panel of the present invention.
FIG. 104 is an explanatory diagram of a display panel of the present invention.
105 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 106 is an explanatory diagram of a display panel of the present invention.
FIG. 107 is an explanatory diagram of a display panel of the present invention.
108 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 109 is an explanatory diagram of a display panel of the present invention.
110 is an explanatory diagram of a display panel of the present invention. FIG.
111 is an explanatory diagram of a display panel of the present invention. FIG.
112 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 113 is an explanatory diagram of a display panel of the present invention.
FIG. 114 is an explanatory diagram of a display panel of the present invention.
FIG. 115 is an explanatory diagram of a display panel of the present invention.
FIG. 116 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 117 is an explanatory diagram of a display panel driving method according to the present invention;
118 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
119 is an explanatory diagram of a display panel driving method of the invention. FIG.
120 is an explanatory diagram of a drive circuit of a display panel of the present invention. FIG.
FIG. 121 is an explanatory diagram of a display panel driving method according to the present invention;
122 is an explanatory diagram of a display panel driving method according to the present invention. FIG.
FIG. 123 is an explanatory diagram of a display panel drive circuit of the present invention.
124 is an explanatory diagram of a driver circuit of a display panel of the present invention. FIG.
125 is an explanatory diagram of a display panel driving method of the present invention. FIG.
126 is an explanatory diagram of a display panel driving method of the present invention. FIG.
127 is an explanatory diagram of a display panel driving method according to the present invention; FIG.
FIG. 128 is an explanatory diagram of a display panel driving method of the invention.
FIG. 129 is an explanatory diagram of a driving method of a display panel of the present invention.
FIG. 130 is an explanatory diagram of a display panel driving method according to the present invention;
FIG. 131 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 132 is an explanatory diagram of a display panel driving method according to the present invention.
133 is an explanatory diagram of a display panel driving method of the invention. FIG.
FIG. 134 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 135 is an explanatory diagram of a display panel driving method according to the present invention.
136 is an explanatory diagram of a display panel driving method of the invention. FIG.
FIG. 137 is an explanatory diagram of a display panel driving method according to the present invention.
138 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
139 is an explanatory diagram of a display panel driving method according to the present invention; FIG.
FIG. 140 is an explanatory diagram of a display panel driving method according to the present invention;
FIG. 141 is an explanatory diagram of a display panel driving method according to the present invention;
FIG. 142 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 143 is an explanatory diagram of a display panel driving method according to the present invention;
FIG. 144 is an explanatory diagram of a display panel driving method according to the present invention;
FIG. 145 is an explanatory diagram of a display panel driving method according to the present invention.
146 is an explanatory diagram of a display panel driving method according to the present invention; FIG.
147 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
148 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 149 is an explanatory diagram of a display panel of the present invention.
FIG. 150 is an explanatory diagram of a display panel of the present invention.
151 is an explanatory diagram of a display panel of the present invention; FIG.
FIG. 152 is an explanatory diagram of a display panel of the present invention.
FIG. 153 is an explanatory diagram of a display panel of the present invention.
FIG. 154 is an explanatory diagram of a display panel of the present invention.
FIG. 155 is an explanatory diagram of a pixel structure of a display panel of the present invention.
FIG. 156 is an explanatory diagram of a pixel structure of a display panel of the present invention.
FIG. 157 is an explanatory diagram of a display panel of the present invention.
FIG. 158 is an explanatory diagram of a display panel of the present invention.
FIG. 159 is an explanatory diagram of a display panel of the present invention.
FIG. 160 is an explanatory diagram of a display panel of the present invention.
FIG. 161 is an explanatory diagram of a display panel of the present invention.
FIG. 162 is an explanatory diagram of a display panel of the present invention.
FIG. 163 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 164 is an explanatory diagram of a display device of the present invention.
FIG. 165 is an explanatory diagram of a pixel structure of a display panel of the present invention.
FIG. 166 is an explanatory diagram of a display panel of the present invention.
167 is an explanatory diagram of a display panel driving method of the invention. FIG.
168 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
FIG. 169 is an explanatory diagram of a display panel of the present invention.
FIG. 170 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 171 is an explanatory diagram of a display panel of the present invention.
FIG. 172 is an explanatory diagram of a display panel of the present invention.
FIG. 173 is an explanatory diagram of a display panel of the present invention.
FIG. 174 is an explanatory diagram of a display panel of the present invention.
FIG. 175 is an explanatory diagram of a display panel of the present invention.
FIG. 176 is an explanatory diagram of a display panel of the present invention.
FIG. 177 is an explanatory diagram of a display panel of the present invention.
FIG. 178 is an explanatory diagram of a display panel of the present invention.
FIG. 179 is an explanatory diagram of a display panel of the present invention.
FIG. 180 is an explanatory diagram of a display panel of the present invention.
FIG. 181 is an explanatory diagram of a display panel of the present invention.
FIG. 182 is an explanatory diagram of a display panel of the present invention.
FIG. 183 is an explanatory diagram of a display panel of the present invention.
FIG. 184 is an explanatory diagram of a display panel of the present invention.
FIG. 185 is an explanatory diagram of a display panel of the present invention.
FIG. 186 is an explanatory diagram of a display panel of the present invention.
187 is an explanatory diagram of a display panel of the present invention. FIG.
188 is an explanatory diagram of a display panel of the present invention. FIG.
189 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 190 is an explanatory diagram of a display panel of the present invention.
FIG. 191 is an explanatory diagram of a display panel of the present invention.
FIG. 192 is an explanatory diagram of a display panel of the present invention.
FIG. 193 is an explanatory diagram of a display panel of the present invention.
FIG. 194 is an explanatory diagram of a display panel of the present invention.
FIG. 195 is an explanatory diagram of a display panel of the present invention.
FIG. 196 is an explanatory diagram of a display panel of the present invention.
FIG. 197 is an explanatory diagram of a display panel of the present invention.
FIG. 198 is an explanatory diagram of a display panel of the present invention.
199 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 200 is an explanatory diagram of a display panel of the present invention.
FIG. 201 is an explanatory diagram of a display panel of the present invention.
202 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 203 is an explanatory diagram of a display panel of the present invention.
FIG. 204 is an explanatory diagram of a display panel of the present invention.
FIG. 205 is an explanatory diagram of a display panel of the present invention.
FIG. 206 is an explanatory diagram of a display panel of the present invention.
FIG. 207 is an explanatory diagram of a display panel of the present invention.
FIG. 208 is an explanatory diagram of a display panel of the present invention.
FIG. 209 is an explanatory diagram of a display panel of the present invention.
FIG. 210 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 211 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 212 is an explanatory diagram of a display panel driving method according to the present invention.
213 is an explanatory diagram of a display panel driving method according to the present invention; FIG.
214 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
FIG. 215 is an explanatory diagram of a driving method of a display device of the present invention.
216 is an explanatory diagram of a driving method of a display device of the present invention. FIG.
FIG. 217 is an explanatory diagram of a driving method of a display device of the present invention.
218 is an explanatory diagram of a driving method of a display panel of the present invention. FIG.
219 is an explanatory diagram of a display panel driving method according to the present invention; FIG.
FIG. 220 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 221 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 222 is an explanatory diagram of a display panel driving method according to the present invention.
FIG. 223 is an explanatory diagram of a driving method of a display panel of the present invention.
224 is an explanatory diagram of an information display device of the present invention. FIG.
225 is an explanatory diagram of an information display device of the present invention. FIG.
FIG. 226 is an explanatory diagram of a display panel of the present invention.
FIG. 227 is a block diagram of a display device of the present invention.
228 is a block diagram of a display device of the present invention. FIG.
FIG. 229 is an explanatory diagram of a display device of the present invention.
230 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 231 is an explanatory diagram of an information display device of the present invention.
FIG. 232 is a plan view of the information display device of the present invention.
233 is an explanatory diagram of an information display device of the present invention. FIG.
234 is an explanatory diagram of a data transmission method of a display device of the present invention. FIG.
235 is an explanatory diagram of a data transmission method of a display device of the invention. FIG.
236 is an explanatory diagram of a data transmission method of a display device of the present invention; FIG.
237 is an explanatory diagram of an information display device of the present invention. FIG.
238 is an explanatory diagram of an information display device of the present invention. FIG.
239 is a cross-sectional view of the viewfinder of the present invention
240 is a perspective view of the video camera of the present invention. FIG.
FIG. 241 is a perspective view of the electronic camera of the present invention.
FIG. 242 is an explanatory diagram of a television according to the present invention.
FIG. 243 is an explanatory diagram of a television according to the present invention.
FIG. 244 is an explanatory diagram of a display panel of the present invention.
245 is an explanatory diagram of a display panel of the present invention. FIG.
246 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 247 is an explanatory diagram of a display panel of the present invention.
248 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 249 is an explanatory diagram of a display panel of the present invention.
FIG. 250 is an explanatory diagram of a display panel of the present invention.
FIG. 251 is an explanatory diagram of a display panel device of the present invention.
FIG. 252 is an explanatory diagram of a display panel of the present invention.
FIG. 253 is an explanatory diagram of a display panel of the present invention.
FIG. 254 is an explanatory diagram of a display panel of the present invention.
FIG. 255 is an explanatory diagram of a display panel of the present invention.
256 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 257 is an explanatory diagram of a display panel of the present invention.
FIG. 258 is an explanatory diagram of a display panel of the present invention.
FIG. 259 is an explanatory diagram of a display panel of the present invention.
FIG. 260 is an explanatory diagram of a display panel of the present invention.
FIG. 261 is an explanatory diagram of a display panel of the present invention.
FIG. 262 is an explanatory diagram of a display panel of the present invention.
FIG. 263 is an explanatory diagram of a display panel of the present invention.
FIG. 264 is an explanatory diagram of a display panel of the present invention.
FIG. 265 is an explanatory diagram of a display panel of the present invention.
FIG. 266 is an explanatory diagram of a display panel of the present invention.
FIG. 267 is an explanatory diagram of a display panel of the present invention.
268 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 269 is an explanatory diagram of a display panel of the present invention.
270 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 271 is an explanatory diagram of a display panel of the present invention.
FIG. 272 is an explanatory diagram of a display panel of the present invention.
FIG. 273 is an explanatory diagram of a display panel of the present invention.
FIG. 274 is an explanatory diagram of a display panel of the present invention.
FIG. 275 is an explanatory diagram of a display panel of the present invention.
276 is an explanatory diagram of a display panel of the present invention. FIG.
FIG. 277 is an explanatory diagram of a display panel of the present invention.
FIG. 278 is an explanatory diagram of a display panel of the present invention.
FIG. 279 is an explanatory diagram of a display panel of the present invention.
FIG. 280 is an explanatory diagram of a display panel of the present invention.
FIG. 281 is an explanatory diagram of a display panel of the present invention.
FIG. 282 is an explanatory diagram of a display panel of the present invention.
FIG. 283 is an explanatory diagram of a display panel of the present invention.
FIG. 284 is an explanatory diagram of a display panel of the present invention.
FIG. 285 is an explanatory diagram of a display panel of the present invention.
FIG. 286 is an explanatory diagram of a display panel of the present invention.
FIG. 287 is an explanatory diagram of a display panel of the present invention.
FIG. 288 is an explanatory diagram of a display panel of the present invention.
FIG. 289 is an explanatory diagram of a display panel of the present invention.
FIG. 290 is an explanatory diagram of a display panel of the present invention.
FIG. 291 is an explanatory diagram of a display panel of the present invention.
FIG. 292 is an explanatory diagram of a display panel of the present invention.
FIG. 293 is an explanatory diagram of a display panel of the present invention.
FIG. 294 is an explanatory diagram of a display panel of the present invention.
FIG. 295 is an explanatory diagram of a display panel of the present invention.
FIG. 296 is an explanatory diagram of a display panel of the present invention.
FIG. 297 is an explanatory diagram of a driving method of a display panel of the present invention.
FIG. 298 is an explanatory diagram of a pixel structure of a display panel of the present invention.
299 is an explanatory diagram of a pixel structure of a display panel of the present invention.
FIG. 300 is an explanatory diagram of a pixel structure of a display panel of the present invention.
FIG. 301 is an explanatory diagram of a conventional display panel
FIG. 302 is a circuit configuration diagram of a conventional display panel.
[Explanation of symbols]
11 TFT
12 Gate driver
14 Source driver
14c 1 chip driver IC
15 EL element
16 pixels
17 Gate signal line
18 Source signal line
19 Capacitor
20 Current supply line
21 Display screen
22 Shift register
23 Inverter circuit
24 Output gate
41 Sealing lid
43 recess
44 Convex
45 Sealant
46 Reflective film
47 Organic EL layer
48 pixel electrodes
49 Array substrate
50 λ / 4 plate
51 Cathode wiring
52 Contact hole
53 Cathode electrode
54 Polarizing plate
55 Desiccant
61,62 connection terminal
63 Anode wiring
71 Smoothing film
72 Transparent electrode
73 Sealing film
74 circularly polarizing plate
81 Edge protection film
82 Display panel
91 Shading film
92 Low resistance wiring
101 Control IC
102 Power IC
103 Printed circuit board
104 Flexible substrate
105 Data signal
141 Error diffusion controller
151 Built-in display memory
152 arithmetic memory
153 arithmetic circuit
154 Buffer circuit
191 Antenna
192 numeric keypad
193 housing
194 key
201 Deplexa
202 LNA
203 LO buffer
204 Downconverter
205 Upconverter
206 PA pre-driver
207 PA
230 Laser irradiation spot
241 glass substrate
242 Positioning marker
251 Convex
252 Uneven part (embossed part)
311 Image display area
312 Non-display area
351 counter circuit
352 brightness memory
353 CPU
354 frame memory (field memory)
355 switching circuit
391 Write pixel row
392 retention pixel row
401 Voltage source
402 Current source
403 Power supply switching means
404 Parasitic capacitance
451 body
452 eyepiece ring
453 Magnifying lens
454 positive lens
461 Photo lens
462 Video camera body
463 storage
464 eyepiece cover
465 Display mode selector switch
466 viewfinder
467 lid
468 fulcrum
471 Shutter
472 Digital camera body
481 Outer frame
482 Fixing member
483 legs
484 Leg mounting part
491 wall
492 Fixing bracket
493 Protective film (protective plate)
501 Scanning area
601 ENBL terminal
602 OR circuit
851 Shutter
852 Glasses for observation (switching means)
861 Prism
862 Optical coupling material
871 Write pixel row
1001 Flying capacitor
1221 Voltage output circuit
1222 Current output circuit
1223 Switch circuit (analog switch)
1224 operational amplifier (output buffer)
1225 Adjustment volume
1226 DA circuit (digital-analog conversion means)
1227 Output transistor (FET)
1228 resistance
1271 Output stage circuit
1321 Signal wiring
1751 Pixel contact area
1761 Protective film
1771 mask
1772 Contact hole
1781 spacer
1791 Lighting control line
1891 Lighting control driver circuit
1981 block
2041 Speaker
2043 Function switch (FSW)
2044 microphone
2045 mirror
2046 Display panel
2111 Reverse bias control line
2271 transistor
2341 Gate waveform
2471 dummy pixel row
2561 Insulating film
2621,2681 Frame (field) memory
2622 counter circuit
2623 Data conversion circuit
2682 Adder circuit (arithmetic processing circuit)
2683 Gate driver control circuit
2691 Data control circuit
2692 Data conversion circuit
2751 Bias resistor (electronic volume, current changing means)
2752 Switching transistor (selection switch)
2753 Parent transistor
2754 child transistor
2791 Light (trajectory)
2801 Refractive sheet (plate, film)
2802 Refraction part
2861 transparent film
2862 Roller
2863 Concavity and convexity (concave part)
2871 Convex
2881 metal mask
2901 Press plate (pressure contact means, transfer means)
2902 light (UV light, visible light)
3001 Current sampling circuit
3002 Current program line

Claims (8)

  1. In an EL display device having a screen region in which pixels are arranged in a matrix,
    A driving element that is formed in each pixel and supplies a driving current to the EL element;
    A switching element that is formed in each of the pixels and controls on / off of a current flowing through the EL element;
    A gate driver circuit whose output gate is connected to the gate of the switching element through a gate signal line ,
    It is configured to change the brightness of the screen area by controlling on / off of the switching element ,
    The on / off control of the switching element is configured based on a start pulse input to the shift register of the gate driver circuit,
    An EL display device , wherein two or more inverter circuits are formed between the output side of the shift register and the output gate .
  2. A source driver circuit;
    A selection element for generating a path for applying a signal output from the source driver circuit to the driving element;
    2. The EL display device according to claim 1, wherein the switching element and the selection element are controlled by different gate signal lines.
  3. The screen area is divided into a plurality of display screens,
    3. The EL display device according to claim 1, wherein luminance is changed for each of the plurality of display screens by controlling on / off of the switching element. 4.
  4.   The EL display device according to claim 1, wherein the number of frames per second is 10 or more and 100 or less.
  5.   The EL display device according to claim 1, wherein the EL display device is configured to perform a delay process when changing the luminance of the screen.
  6.   The EL display device according to claim 1, wherein the EL display device is configured to count image data and perform screen brightness control in accordance with the count result.
  7.   The EL display device according to any one of claims 1 to 3, wherein a period for cutting off a current to the EL element and then a flow of the current is controlled to be 0.5 msec or more and 100 msec or less. .
  8.   The EL display device according to claim 1, wherein the pixel has a pixel configuration of a current program.
JP2001349887A 2001-11-15 2001-11-15 EL display device and driving method of EL display device Active JP4251801B2 (en)

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AU2003276706A1 (en) 2002-10-31 2004-05-25 Casio Computer Co., Ltd. Display device and method for driving display device
JP5057637B2 (en) * 2002-11-29 2012-10-24 株式会社半導体エネルギー研究所 Semiconductor device
TWI470607B (en) 2002-11-29 2015-01-21 Semiconductor Energy Lab A current driving circuit and a display device using the same
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