JP2009151315A - El display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily attain a reset drive by a front gate control system in an EL display device. <P>SOLUTION: The EL display device with a display screen where pixels 16 are arranged in matrix includes: a gate driver circuit 12; and a source driver circuit 14 for outputting an image signal. Each pixel 16 includes: an EL element 15; a drive transistor 11a for supplying a current to the EL element 15; a first switching transistor 11b for applying a first voltage to the gate terminal of the drive transistor 11a; and a second switching transistor 11c for applying the image signal to the drive transistor 11a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention mainly relates to an EL display panel for displaying an image by self-emission and an information display device such as a mobile phone using these EL display panels. The present invention also relates to a drive circuit for driving an EL display panel or the like.

  Liquid crystal display panels are widely used in portable devices because of their thinness and low power consumption, so they are also used in devices such as word processors, personal computers, and televisions (TVs), video camera viewfinders, and monitors. It is used.

  However, since the liquid crystal display panel is not a self-luminous device, there is a problem that an image cannot be displayed unless a backlight is used. Since a predetermined thickness is required to configure the backlight, there is a problem that the thickness of the display module is increased. In order to perform color display on the liquid crystal display panel, it is necessary to use a color filter. Therefore, there is a problem that the light utilization efficiency is low. There is also a problem that the color reproduction range is narrow.

  In recent years, organic EL (electroluminescence) display panels have been developed. The organic EL display panel is configured by using a low-temperature polysilicon TFT (thin film transistor) array. A panel is formed using a TFT array formed by amorphous silicon technology. However, since the organic EL device emits light by current, there is a problem that display unevenness occurs when there is variation in TFT characteristics.

In order to achieve the above object, the present invention comprises a constant current generating circuit having a reference voltage and a resistor and generating a constant current;
A first current source that receives a constant current from the constant current generation circuit and outputs a first current corresponding to the constant current to a plurality of second current sources;
A second current source that receives a first current output from the first current source and outputs a second current corresponding to the first current to a plurality of third current sources;
A third current source that receives a second current output from the second current source and outputs a third current corresponding to the second current to a plurality of fourth current sources; And
The fourth current source is an EL display panel or the like in which the number corresponding to the input image data is selected.

  The display panel, display device, and the like of the present invention exhibit distinctive effects according to their respective configurations such as high image quality, good moving image display performance, low power consumption, low cost, and high brightness.

In the present specification, each drawing is omitted or / and enlarged or reduced for easy understanding and / or drawing. For example, in the cross-sectional view of the display panel shown in FIG. 11, the sealing film 111 and the like are shown to be sufficiently thick. On the other hand, in FIG. 10, the sealing lid 85 is shown thinly. Also, there are some omitted parts. For example, in the display panel of the present invention, a phase film for preventing reflection of unnecessary light is omitted, but it is desirable to add it timely. The same applies to the following drawings. Moreover, the part which attached | subjected the same number or the symbol etc. has the same or similar form, material, function, or operation | movement.

  Note that the contents described in the drawings and the like can be combined with other embodiments and the like without particular notice. For example, by adding a touch panel or the like to the display panel of FIG. 8, the information display device shown in FIGS. 19 and 59 to 61 can be obtained. In addition, a viewfinder (see FIG. 58) which is attached to a magnifying lens 582 and used for a video camera (see FIG. 59, etc.) can also be configured. Further, the driving method of the present invention described with reference to FIGS. 4, 15, 18, 21, and 23 can be applied to any display device or display panel of the present invention. That is, the driving method described in this specification can be applied to the display panel of the present invention. Further, the present invention mainly describes an active matrix display panel in which a transistor is formed in each pixel. However, the present invention is not limited to this and can be applied to a simple matrix display.

  Thus, even if not specifically exemplified in the specification, matters, contents, and specifications described or explained in the specification and drawings can be combined with each other and described in the claims. This is because it is impossible to describe all combinations in the specification.

  2. Description of the Related Art In recent years, organic EL display panels configured by arranging a plurality of organic electroluminescence (EL) elements in a matrix form have attracted attention as display panels that have low power consumption and high display quality and can be further thinned. Yes. As shown in FIG. 10, the organic EL display panel includes at least one of an electron transport layer, a light emitting layer, a hole transport layer, and the like on a glass plate 71 (array substrate) on which a transparent electrode 105 as a pixel electrode is formed. An organic functional layer (EL layer) 15 and a metal electrode (reflection film) (cathode) 106 are laminated. A positive voltage is applied to the anode (anode), which is the transparent electrode (pixel electrode) 105, and a negative voltage is applied to the cathode (cathode) of the metal electrode (reflection electrode) 106, that is, a direct current is applied between the transparent electrode 105 and the metal electrode 106. As a result, the organic functional layer (EL layer) 15 emits light. By using an organic compound that can be expected to have good light emission characteristics in the organic functional layer, the EL display panel can withstand practical use. Although the present invention will be described by taking an organic EL display panel as an example, the present invention is not limited to this and can be applied to an inorganic EL panel. In addition, the structure, circuit, and the like are applicable to other display panels such as a TN liquid crystal display panel and an STN liquid crystal display panel.

  The cathode electrode, the anode electrode, or the reflective film may be configured by forming an optical interference film made of a dielectric multilayer film on the ITO electrode. The dielectric multilayer film is formed by alternately laminating a low refractive index dielectric film and a high refractive index dielectric film. That is, it is a dielectric mirror. This dielectric multilayer film has a function of improving the color tone of light emitted from the organic EL structure (filter effect). The transparent electrode ITO may be other materials such as IZO. The same applies to the pixel electrode.

A large current flows through wirings for supplying current to the anode or cathode (the cathode wiring 86 and the anode wiring 87 in FIG. 8). For example, when the screen size of the EL display device is 40 inches, a current of about 100 (A) flows. Therefore, the resistance values of these wirings must be made sufficiently low. In response to this problem, in the present invention, first, a wiring such as an anode is formed as a thin film. The thin conductor is formed thick on the thin film wiring by an electrolytic plating technique or an electroless plating technique. Examples of the plating metal include chromium, nickel, gold, copper, aluminum, alloys thereof, amalgam, or a laminated structure. Further, as necessary, the wiring itself or a metal wiring made of copper thin is added to the wiring. In addition, copper paste or the like is screen-printed on the wiring, and the paste is stacked to increase the thickness of the wiring and reduce the wiring resistance. Alternatively, the wiring may be formed by overlapping with a bonding technique to reinforce the wiring. Further, if necessary, a ground pattern may be formed by stacking on the wiring, and a capacitor (capacitance) may be formed between the wiring and the wiring.

  In addition, in order to supply a large current to the anode or cathode wiring, a high-voltage, low-current power wiring is routed from the current supply means to the vicinity of the anode wiring and the like, and the DCDC converter is used to reduce the voltage to a high current. The power is converted and supplied. That is, wiring is performed from the power source to a power consumption target with high voltage and low current wiring, and converted to a large current and low voltage in the vicinity of the power consumption target. Examples of such devices include DCDC converters and transformers.

  The metal electrode 106 is preferably made of a material having a small work function such as lithium, silver, aluminum, magnesium, indium, copper, or an alloy thereof. In particular, for example, an Al—Li alloy is preferably used. The transparent electrode 105 can be made of a conductive material having a high work function such as ITO or gold. In addition, when gold is used as an electrode material, the electrode is in a translucent state. ITO may be other materials such as IZO. The same applies to the other pixel electrodes 105.

  Note that when depositing a thin film on the pixel electrode 105 or the like, the organic EL film 15 may be formed in an argon atmosphere. Further, by forming a carbon film with a thickness of 20 to 50 nm on ITO as the pixel electrode 105, the stability of the interface is improved, and the light emission luminance and the light emission efficiency are also improved. Moreover, it is needless to say that the EL film 15 is not limited to being formed by vapor deposition, and may be formed by inkjet. This inkjet method is particularly effective for polymer organic EL materials. In this case, it is preferable to form a hydrophilic film at a location where the polymer organic EL material is applied.

  Hereinafter, in order to facilitate understanding of the EL display panel structure of the present invention, a method for manufacturing the organic EL display panel of the present invention will be described first.

  In order to improve the heat dissipation of the substrate 85 and the substrate 71, the substrate may be formed of sapphire glass. Further, a thin film or a thick film having good thermal conductivity may be formed. For example, the use of a substrate on which a diamond thin film (such as DLC) is formed is exemplified. Of course, a quartz glass substrate or a soda glass substrate may be used. In addition, a ceramic substrate such as alumina, a metal plate made of copper, or the like, or a metal film or carbon film coated on the insulating film by vapor deposition or coating may be used. When the pixel electrode 105 is of a reflective type, light is emitted from the surface direction of the substrate as the substrate material. Therefore, non-transparent materials such as stainless steel can be used in addition to transparent or translucent materials such as glass, quartz and resin.

  In addition, a micro lens may be formed or disposed outside or inside the substrate 85 and the substrate 71 corresponding to the pixel shape. By configuring the microlens, the directivity of light emitted from the EL film is narrowed, and high luminance can be realized.

  In the embodiment of the present invention, the cathode electrode 106 and the like are formed of a metal film. However, the present invention is not limited to this, and may be formed of a transparent film such as ITO or IZO. Thus, by making both the anode and cathode electrodes of the EL element 15 transparent, a transparent EL display panel can be formed (of course, one of them may be formed of a light-transmitting metal film, or An extremely thin metal film may be used as a cathode electrode, and a transparent conductor material such as ITO may be laminated on the cathode electrode). By increasing the transmittance to about 80% without using a metal film, it is possible to make the other side of the display panel almost transparent while displaying characters and pictures.

  Needless to say, the substrates 85 and 71 may be plastic substrates. Plastic substrates are difficult to break and are lightweight, making them ideal as display panel substrates for mobile phones. The plastic substrate is preferably used as a laminated substrate by attaching an auxiliary substrate to one surface of a base substrate serving as a core material with an adhesive. Of course, these substrates are not limited to plates, and may be films having a thickness of 0.05 mm or more and 0.3 mm or less.

  As the base substrate, an alicyclic polyolefin resin is preferably used. As such alicyclic polyolefin resin, a single plate of 200 μm in thickness of ARTON manufactured by Nippon Synthetic Rubber Co., Ltd. is exemplified. From polyester resin, polyethylene resin or polyethersulfone resin, etc., on which one side of the base substrate is formed with a hard coat layer with heat resistance, solvent resistance or moisture permeability function, and a gas barrier layer with air permeability resistance function An auxiliary substrate (or film or membrane) is placed.

  As described above, when the substrate 71 and the like are formed of plastic, the substrate 71 and the like are formed of a base substrate and an auxiliary substrate. On the other surface of the base substrate, an auxiliary substrate (or film or film) made of a polyethersulfone resin or the like on which a hard coat layer and a gas barrier layer are formed is disposed in the same manner as described above. It is preferable that the angle formed by the optical slow axis of the auxiliary substrate and the optical slow axis of the auxiliary substrate is 90 degrees. Note that the base substrate and the auxiliary substrate are attached to each other with an adhesive or a pressure-sensitive adhesive to form a laminated substrate.

  As the adhesive, it is preferable to use a UV (ultraviolet) curable adhesive made of an acrylic resin. The acrylic resin preferably has a fluorine group. In addition, an epoxy adhesive or pressure-sensitive adhesive may be used. The refractive index of the adhesive or pressure-sensitive adhesive is preferably 1.47 or more and 1.54 or less. Moreover, it is preferable that the difference in refractive index with the refractive index of the substrate is 0.03 or less. In particular, the adhesive is preferably added with a light diffusing material such as titanium oxide as described above to function as a light scattering layer.

  When the auxiliary substrate and the auxiliary substrate are bonded to the base substrate, the angle formed by the optical slow axis of the auxiliary substrate and the optical slow axis of the auxiliary substrate is preferably set to 45 degrees or more and 120 degrees or less. More preferably, it is 80 degrees or more and 100 degrees or less. By setting it within this range, the retardation generated in the auxiliary substrate and the polyethersulfone resin as the auxiliary substrate can be completely canceled in the laminated substrate. Therefore, the plastic substrate for display panel can be handled as an isotropic substrate having no phase difference. Therefore, the structure using a circularly polarizing plate does not cause unevenness of the display panel due to different phase states. Needless to say, the matter regarding the circularly polarizing plate is not limited to a plastic substrate, but is also effective for a glass substrate. This is because a reduction in contrast due to external light reflected on the substrate surface can be effectively suppressed.

  With this configuration, versatility is significantly increased as compared with a film substrate or a film laminated substrate having a phase difference. That is, by combining with the retardation film, linearly polarized light can be converted into elliptically polarized light as designed. If the substrate has a phase difference, an error from the design value occurs due to this phase difference.

  Here, as the hard coat layer, a polyester resin, an epoxy resin, a urethane resin, an acrylic resin, or the like can be used, and a stripe electrode (simple matrix EL display panel) or a pixel electrode (active matrix display panel). ) Also serves as the first undercoat layer of the transparent conductive film.

As the gas barrier layer, inorganic materials such as SiO ₂ and SiO _x , or organic materials such as polyvinyl alcohol and polyimide can be used. As an adhesive, an adhesive, etc., an epoxy adhesive or a polyester adhesive can be used in addition to the acrylic described above. The adhesive layer has a thickness of 100 μm or less. However, it is preferably 10 μm or more in order to smooth the surface irregularities such as the substrate.

  Further, it is preferable to use a substrate having a thickness of 40 μm or more and 400 μm as the auxiliary substrate and the auxiliary substrate constituting the substrates 71 and 85. Further, by setting the thickness of the auxiliary substrate and the auxiliary substrate to 120 μm or less, the unevenness or phase difference at the time of melt extrusion called a polyethersulfone resin die line can be suppressed low. Preferably, the auxiliary substrate has a thickness of 50 μm or more and 80 μm or less.

Next, SiO _x is formed as an auxiliary undercoat layer of the transparent conductive film on the laminated substrate, and a transparent conductive film made of ITO which becomes a pixel electrode is formed by a sputtering technique as necessary. Further, if necessary, an ITO film is formed as static electricity prevention. Thus, the transparent conductive film of the plastic substrate for display panels manufactured can implement | achieve the sheet resistance value 25 ohms / square and the transmittance | permeability 80% as the film | membrane characteristic.

  When the thickness of the base substrate is 50 μm to 100 μm, the display panel plastic substrate is curled by heat treatment in the manufacturing process of the display panel. Also, good results cannot be obtained in connection of circuit components. When the thickness of the base substrate is 200 μm or more and 500 μm or less with a single plate, the substrate is not deformed and has excellent smoothness, good transportability, and stable transparent conductive film characteristics. Also, connection of circuit components can be carried out without any problem. Further, the thickness is particularly preferably 250 μm or more and 450 μm or less. This is thought to be due to moderate flexibility and flatness. ITO may be other materials such as IZO. The same applies to the pixel electrode.

  In addition, when using organic materials, such as the above-mentioned plastic substrate, as a board | substrate etc., it is preferable to form the thin film which consists of inorganic materials as a barrier layer also in the surface which touches a light modulation layer. This barrier layer made of an inorganic material is preferably formed of the same material as the AIR coat. Needless to say, the sealing lid 85 and the substrate 71 can be manufactured by a technique or configuration.

Further, when the barrier film is formed on the pixel electrode or the stripe electrode, it is preferable to use a low dielectric constant material in order to reduce the loss of the voltage applied to the light modulation layer as much as possible. For example, an amorphous carbon film (relative dielectric constant: 2.0 to 2.5) to which fluorine is added is exemplified. Other examples include the LKD series (LKD-T200 series (relative permittivity 2.5 to 2.7), LKD-T400 series (relative permittivity 2.0 to 2.2)) manufactured and sold by JSR. The The LKD series is a spin coating type based on MSQ (methy-silsesquioxane) and has a low dielectric constant of 2.0 to 2.7, which is preferable. In addition, organic materials such as polyimide, urethane, and acrylic, and inorganic materials such as SiN _x and SiO ₂ may be used. Needless to say, these barrier film materials may be used for the auxiliary substrate.

  By using the substrate 85 or 71 formed of plastic, the advantage that it is not broken and can be reduced in weight can be exhibited. Another advantage is that it can be pressed. That is, a substrate having an arbitrary shape can be produced by pressing or cutting. Moreover, it can be processed into an arbitrary shape and thickness by melting or chemical treatment. For example, it is exemplified that it is formed into a circular shape, a spherical shape (curved surface or the like), or a conical shape. Further, by pressing, simultaneously with the manufacture of the substrate, an uneven shape can be formed on one of the substrate surfaces to form a scattering surface or embossing.

It is also easy to form the positioning pins of the sealing lid 85 into the holes (not shown) of the substrate 71 formed by pressing plastic. Further, an electric circuit such as a capacitor or a resistor formed by thick film technology or thin film technology may be formed in the substrate 71. Further, a recess (not shown) is formed in the substrate 71 and the like, and a convex portion is formed in the substrate 85, and the concave portion and the convex portion are formed so as to be fitted, thereby fitting the substrate 71 and the substrate 85. You may comprise so that it can integrate.

  When a glass substrate was used, a bank used for depositing EL on the periphery of the pixel 16 was formed. The banks (ribs) are formed in a convex shape with a thickness of 1.0 μm to 3.5 μm using a resin material. More preferably, it is formed to a height of 1.5 μm or more and 2.5 μm or less. The bank (convex portion) 101 made of this resin can be produced simultaneously with the formation of the substrate 71. The bank 101 material may be SOG material in addition to acrylic resin and polyimide resin. The bank 101 is preferably formed simultaneously with the convex portion of the resin when the substrate 71 is pressed. This is a great effect generated by forming the substrate 71 and the like with resin.

  Since the resin portion is formed at the same time as the substrate in this manner, the manufacturing time can be shortened and the cost can be reduced. Further, when the substrate 71 or the like is manufactured, convex portions are formed in a dot shape in the display region portion. This convex portion is preferably formed between adjacent pixels. This convex portion becomes the bank 101.

  In the above embodiment, the convex portion functioning as a bank is formed. However, the present invention is not limited to this. For example, the pixel portion may be dug down (concave portion) by press working or the like. In addition, the system which forms the planar board | substrate 71 first, and then presses by reheating and forms an unevenness | corrugation is also included.

  Further, a mosaic color filter may be formed by directly coloring the substrates 71 and 85. A dye, pigment, or the like is applied to the substrate using a technique such as ink jet printing and is allowed to penetrate. After permeation, drying may be performed at a high temperature, and the surface may be coated with a resin such as a UV resin, or an inorganic material such as silicon oxide or nitrogen oxide. Further, a color filter is formed by a gravure printing technique, an offset printing technique, a semiconductor pattern forming technique in which a film is applied by a spinner and developed. Similarly, a black matrix (BM) may be directly formed by using a technique, in addition to a color filter, by coloring that is in the relationship of black or dark color or a complementary color of light to be modulated. Further, a recess may be formed on the substrate surface so as to correspond to the pixel, and a color filter, BM, or transistor may be embedded in the recess. It is particularly preferable to coat the surface with an acrylic resin. This configuration also has an advantage that the pixel electrode surface and the like are flattened.

  Alternatively, the pixel electrode 105 or the cathode electrode 106 may be configured directly by making the resin on the substrate surface conductive with a conductive polymer or the like. Further, a configuration in which a hole is formed in the substrate and an electronic component such as a capacitor is inserted into the hole is also exemplified. The advantage that the substrate can be made thin is exhibited.

  Moreover, you may form a pattern freely by cutting the surface of a board | substrate. Alternatively, it may be formed by melting the peripheral portion of the substrate 71 or the like. In the case of an organic EL display panel, the peripheral portion of the substrate may be melted and sealed in order to prevent moisture from entering from the outside.

  As described above, by forming the substrate with a resin, it is easy to make a hole in the substrate. Further, the substrate shape can be freely configured by press working or the like. Further, a hole can be formed in the substrate 71 and the hole can be filled with a conductive resin or the like to electrically connect the front and back of the substrate. The substrate 71 or the like can be used as a multilayer circuit board or a double-sided board.

Further, a conductive pin or the like may be inserted instead of the conductive resin. You may comprise so that the terminal of electronic components, such as a capacitor | condenser, can be inserted in the formed hole. In addition, a circuit wiring, a capacitor, a coil, or a resistor using a thin film may be formed in the substrate. That is, the substrate 71 itself may be a multilayer wiring board. Multi-layering is configured by laminating thin substrates. One or more substrates (films) to be bonded may be colored.

  In addition, dyes and pigments can be added to the substrate material to color the substrate itself and to form a filter. Further, the serial number can be formed simultaneously with the production of the substrate. In addition, by coloring only the portion other than the display area, it is possible to prevent malfunction due to light being applied to the mounted IC chip.

  Also, half of the display area of the substrate can be colored in a different color. This may be achieved by applying resin plate processing techniques (injection processing, compression processing, etc.). In addition, by using the same processing technique, half of the display area can be made to have a different EL layer thickness. In addition, the display portion and the circuit portion can be formed at the same time. It is also easy to change the substrate thickness between the display area and the driver loading area.

  In addition, a microlens can be formed on the substrate 71 or the substrate 85 so as to correspond to a pixel or a display region. Further, the diffraction grating may be formed by processing the substrates 71 and 85. Further, unevenness sufficiently finer than the pixel size can be formed, and the viewing angle can be improved or the viewing angle can be made dependent. It is to be noted that such arbitrary-shaped processing and fine processing technology can be realized by a stamper technology for forming a microlens developed by OMRON Corporation.

  An antireflection film (AIR coat) is formed on the surface where the substrates 71 and 85 are in contact with air. When a polarizing plate or the like is not attached to the substrate 71 or the like, an antireflection film (AIR coat) is directly formed on the substrate 71 or the like. When other constituent materials such as a polarizing plate (polarizing film) are attached, an antireflection film (AIR coat) is formed on the surface of the constituent material.

  Although the above embodiment has been described mainly with respect to the substrate 71 and the like made of plastic, the present invention is not limited to this. For example, even if the substrates 71 and 859 are a glass substrate or a metal substrate, the uneven portions such as the bank 101 can be formed or configured by pressing, cutting, or the like. Further, coloring to the substrate is also possible. Therefore, the items described are not limited to plastic substrates. Moreover, it is not limited to a substrate. For example, a film or a sheet may be used.

  In addition, it is effective to form a thin film made of a fluororesin in order to prevent or suppress the adhesion of dust to the surface of the polarizing plate. Moreover, you may apply | coat or vapor-deposit conductor films, such as a thin film which has a hydrophilic group, a conductive polymer film, and a metal film, for electrostatic prevention.

  Note that the polarizing plate (polarizing film) disposed or formed on the light incident surface or the light emitting surface of the display panel is not limited to linearly polarized light, and may be elliptically polarized light. Alternatively, a plurality of polarizing plates may be bonded together, a polarizing plate and a retardation plate may be combined, or a combination of the polarizing plates may be used.

  As the main material constituting the polarizing film, a TAC film (triacetyl cellulose film) is optimal. This is because the TAC film has excellent optical properties, surface smoothness and processability.

A configuration in which the AIR coat is formed of a dielectric single layer film or a multilayer film is exemplified. Other, 1
. A resin having a low refractive index of 35 to 1.45 may be applied. For example, a fluorine-type acrylic resin etc. are illustrated. Particularly, those having a refractive index of 1.37 or more and 1.42 or less have good characteristics.

  The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide wavelength band of visible light. This is called multi-coat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band. This is called a V coat. Multi-coat and V-coat are used properly according to the use of the display panel. In addition, it is not limited to two or more layers, and may be a single layer.

In the case of multi-coat, the optical film thickness of aluminum oxide (Al ₂ O ₃ ) is nd = λ / 4, zirconium (ZrO ₂ ) is nd1 = λ / 2, and magnesium fluoride (MgF ₂ ) is nd1 = λ / 4. It is formed by stacking. Usually, a thin film is formed with λ as 520 nm or a value in the vicinity thereof.

In the case of V coating, silicon monoxide (SiO) has an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgSO ₂ ) nd1 = λ / 4, or yttrium oxide (Y ₂ O ₃ ) and magnesium fluoride ( MgF ₂ ) is laminated by nd1 = λ / 4. Since SiO has an absorption band on the blue side, it is better to use Y ₂ O ₃ when modulating blue light. Further, Y ₂ O ₃ is more preferable because of its stability. It may also be used SiO ₂ thin film. Of course, a low refractive index resin or the like may be used for the AIR coating. For example, an acrylic resin such as fluorine is exemplified. These are preferably ultraviolet curable types.

  In order to prevent static electricity from being charged to the display panel, a hydrophilic resin is applied to the surface of the light guide plate such as a cover substrate or the display panel, or the substrate material such as the panel is made hydrophilic. It is preferable to use a good material.

  A thin film transistor (transistor) as a plurality of switching elements or current control elements is formed in one pixel. The transistors to be formed may be the same type of transistors, or may be different types of transistors such as P-channel type and N-channel type transistors, but preferably the same polarity for the switching transistor and the driving transistor. Is desirable. Further, the structure of the transistor is not limited to a planar type transistor, and may be a staggered type or an inverted staggered type, or may have an impurity region (source, drain) formed using a self-alignment method. A non-self-aligned method may be used.

  The EL display element 15 of the present invention has an EL structure in which ITO serving as a hole injection electrode (pixel electrode), one or more organic layers, and an electron injection electrode are sequentially stacked on a substrate. A transistor is provided on the substrate.

  In order to manufacture the EL display element of the present invention, first, an array of transistors is formed in a desired shape on a substrate. Then, ITO, which is a transparent electrode, is formed and patterned as a pixel electrode on the planarizing film by sputtering. Thereafter, an organic EL layer, an electron injection electrode, and the like are stacked.

  A normal polycrystalline silicon transistor may be used as the transistor. The transistor is provided at the end of each pixel of the EL structure, and the size thereof is about 10 to 30 μm. The size of the pixel is about 20 μm × 20 μm to 300 μm × 300 μm.

On the substrate 71, a wiring electrode of the transistor is provided. The wiring electrode has a low resistance and has a function of suppressing the resistance value by electrically connecting the hole injection electrode. Generally, the wiring electrode includes Al, Al and transition metals (excluding Ti), Ti or A material containing one or more of titanium nitride (TiN) is used, but the present invention is not limited to this material. The total thickness of the hole injection electrode serving as the foundation of the EL structure and the wiring electrode of the transistor is not particularly limited, but is usually about 100 to 1000 nm.

An insulating layer is provided between the wiring electrode of the transistor 11 and the organic layer of the EL structure. The insulating layer is formed by sputtering or vacuum deposition of an inorganic material such as silicon oxide such as SiO ₂ or silicon nitride, a silicon oxide layer formed by SOG (spin-on-glass), photoresist, polyimide, acrylic Any film may be used as long as it has insulating properties, such as a coating film of a resin-based material such as a resin. Of these, polyimide is preferable. The insulating layer also serves as a corrosion / water resistant film that protects the wiring electrode from moisture and corrosion.

  There may be two or more emission peaks of the EL structure. In the EL display element of the present invention, the green and blue light-emitting portions are obtained, for example, by a combination of a blue-green light-emitting EL structure and a green transmission layer or a blue transmission layer. The red light-emitting portion can be obtained by an EL structure that emits blue-green light and a fluorescence conversion layer that converts blue-green light emitted from the EL structure to a wavelength close to red.

  Next, the EL structure constituting the EL display element 15 of the present invention will be described. The EL structure of the present invention includes an electron injection electrode that is a transparent electrode, one or more organic layers, and a hole injection electrode. Each of the organic layers has at least one hole transport layer and a light emitting layer. For example, the organic layer sequentially includes an electron injection transport layer, a light emitting layer, a hole transport layer, and a hole injection layer. Note that the hole transport layer may be omitted. The organic layer of the EL structure of the present invention can have various configurations, and the electron injection / transport layer is omitted, or is integrated with the light emitting layer, or the hole injection transport layer and the light emitting layer are mixed. May be. The electron injection electrode is made of a metal, a compound or an alloy having a low work function formed by vapor deposition, sputtering, or the like, preferably by vapor deposition.

Since the hole injection electrode has a structure for extracting light emitted from the hole injection electrode side, for example, ITO (tin doped indium oxide), IZO (zinc doped indium oxide), ZnO, SnO ₂ , In ₂ O _3, etc. Among them, ITO and IZO are particularly preferable. The thickness of the hole injection electrode is sufficient if it has a certain thickness or more that can sufficiently perform hole injection, and is usually preferably about 10 to 500 nm. In order to improve the reliability of the device, it is necessary that the driving voltage is low, and preferred examples include ITO of 10 to 30 Ω / □ (film thickness of 50 to 300 nm). When actually used, the film thickness and optical constant of the electrode may be set so that the interference effect due to reflection at the hole injection electrode interface such as ITO sufficiently satisfies the light extraction efficiency and color purity.

  The hole injection electrode can be formed by vapor deposition or the like, but is preferably formed by sputtering. The sputtering gas is not particularly limited, and an inert gas such as Ar, He, Ne, Kr, Xe, or a mixed gas thereof may be used.

  The electron injection electrode is made of a metal, a compound or an alloy having a low work function formed by vapor deposition, sputtering, or the like, preferably by vapor deposition. As a constituent material of the electron injection electrode to be formed, for example, a simple metal element such as K, Li, Na, Mg, La, Ce, Ca, Sr, Ba, Al, Ag, In, Sn, Zn, Zr, or In order to improve the stability, it is preferable to use a two-component or three-component alloy system containing them. Examples of alloy systems include Ag · Mg (Ag: 1 to 20 at%), Al·Li (Li: 0.3 to 14 at%), In · Mg (Mg: 50 to 80 at%), Al · Ca (Ca: 5 to 20 at%) and the like are preferable.

The thickness of the electron injecting electrode thin film may be a certain thickness that allows sufficient electron injection.
The thickness may be 1 nm or more, preferably 1 nm or more. Moreover, although there is no restriction | limiting in particular in the upper limit, Usually, a film thickness should just be about 100-500 nm.

  The hole injection layer has a function of facilitating injection of holes from the hole injection electrode, and the hole transport layer has a function of transporting holes and a function of blocking electrons. Also called transport layer.

  The electron injecting and transporting layer is provided when the electron injecting and transporting function of the compound used for the light emitting layer is not so high, and prevents the function of facilitating the injection of electrons from the electron injecting electrode, the function of transporting electrons and the holes. It has a function. The hole injection layer, hole transport layer, and electron injection transport layer increase and confine holes and electrons injected into the light emitting layer, optimize the recombination region, and improve the light emission efficiency. Note that the electron injecting and transporting layer may be provided separately for the layer having an injection function and the layer having a transport function.

  The thickness of the light-emitting layer, the combined thickness of the hole injection layer and the hole transport layer, and the thickness of the electron injection transport layer are not particularly limited, and are usually about 5 to 100 nm, although they vary depending on the forming method. It is preferable.

  The thickness of the hole injection layer, the hole transport layer, and the thickness of the electron injection / transport layer depends on the design of the recombination / light emitting region, but if it is about the same as the thickness of the light emitting layer or about 1/10 to 10 times Good. The thicknesses of the hole injection layer, the hole transport layer, and the thickness in the case of separating the electron injection layer and the electron transport layer are preferably 1 nm or more for the injection layer and 20 nm or more for the transport layer. In this case, the upper limit of the thickness of the injection layer and the transport layer is usually about 100 nm for the injection layer and about 100 nm for the transport layer. Such a film thickness is the same when two injection transport layers are provided.

  In addition, the recombination region and light emission can be controlled by controlling the film thickness while considering the carrier mobility and carrier density (determined by the ionization potential and electron affinity) of the light-emitting layer, electron injection transport layer, and hole injection transport layer to be combined. The region can be designed freely, and it is possible to design the light emission color, control the light emission luminance / light emission spectrum by the interference effect of both electrodes, and control the spatial distribution of light emission.

The light emitting layer of the EL element 15 of the present invention contains a fluorescent material which is a compound having a light emitting function. Examples of the fluorescent substance include metal complex dyes such as tris (8-quinolinolato) aluminum [Alq ₃ ], phenylanthracene derivatives, tetraarylethene derivatives, and blue-green light emitting materials.

  In addition, it is good to employ | adopt CuPc which added 2% phthalocyanine to the material of a positive hole injection layer. Compared with the case where CuPc is used alone, the heat resistance is remarkably improved.

The luminance after driving at 85 ° C. for 1000 hours is about 45% lower with CuPc alone than the initial luminance (set to 400 cd / m ² ), but only about 35% is reduced with phthalocyanine added. This is presumably because CuPc crystallization was suppressed by the addition of phthalocyanine. If CuPc is kept in an amorphous state, a decrease in luminance can be suppressed. The effect of improving the heat resistance by adding phthalocyanine is greatest at 1% or more and 5% or more. In particular, 1% to 3% is appropriate. In addition, there is an effect of addition up to about 20%, but if the addition amount is further increased, the heat resistance is rather lowered.

The blue light-emitting organic EL element 15 may use “DMPhen (Triphenylamine)” having an emission wavelength of about 400 nm as the material of the light emitting layer. At this time, for the purpose of increasing luminous efficiency, an electron injection layer (Bathocupline) and a hole injection layer (M-MTDATXA)
It is preferable to use the same material as that of the light emitting layer. If only DMPhen with a large band gap of 3.4 eV is used for the light emitting layer, electrons remain in the electron injection layer and holes remain in the hole injection layer, and recombination of electrons and holes is unlikely to occur in the light emitting layer. is there. The problem that a light emitting material having an amine group such as DMPhen is unstable in structure and difficult to extend the life can be solved by transferring energy excited in DMPhen to a dopant and emitting light from the dopant.

  Luminescence efficiency can be improved by using a phosphorescent material as the EL material. The fluorescent material has an external quantum efficiency of about 2-3%. The fluorescent light emitting material has an internal quantum efficiency (efficiency in which the energy by excitation is changed to light) is 25%, whereas the phosphorescent light emitting material reaches nearly 100%, so that the external quantum efficiency is high.

  CBP is preferably used as the host material of the light emitting layer of the organic EL element. Here, red (R), green (G), and blue (B) phosphorescent materials are doped. All doped materials contain Ir. It is preferable to use Btp2Ir (acac) for the R material, (ppy) 2Ir (acac) for the G material, and FIrpic for the B material.

  Various organic compounds can be used for the hole injection layer and the hole transport layer. For the formation of the hole injecting and transporting layer, the light emitting layer, and the electron injecting and transporting layer, it is preferable to use a vacuum deposition method because a homogeneous thin film can be formed.

  Hereinafter, the manufacturing method and structure of the EL display panel of the present invention will be described in more detail. As described before, first, the transistor 11 for driving the pixels is formed on the array substrate 71. One pixel is composed of two or more, preferably four or five transistors. Further, the pixel is current-programmed, and the programmed current is supplied to the EL element 15. Normally, the current programmed value is held in the storage capacitor 19 as a voltage value. The pixel configuration such as the combination of the transistors 11 will be described later. Next, a pixel electrode as a hole injection electrode is formed in the transistor 11. The pixel electrode 105 is patterned by photolithography. Note that a light-shielding film is formed or disposed in the lower layer or the upper layer of the transistor 11 in order to prevent deterioration in image quality due to a photoconductor phenomenon (hereinafter referred to as a photocon) that occurs when light enters the transistor 11.

  In the current program, a program current is applied to the pixel from the source driver circuit 14 (or absorbed by the source driver circuit 14 from the pixel), and a signal value corresponding to this current is held in the pixel. A current corresponding to the held signal value is supplied to the EL element 15 (or supplied from the EL element 15). That is, the current is programmed, and a current corresponding to (corresponding to) the programmed current is caused to flow through the EL element 15.

  On the other hand, the voltage program is to apply a program voltage from the source driver circuit 14 to the pixel and hold the signal value corresponding to this voltage in the pixel. A current corresponding to the held voltage is supplied to the EL element 15. That is, the voltage is programmed, the voltage is converted into a current value in the pixel, and a current corresponding to (corresponding to) the programmed voltage is caused to flow to the EL element 15.

  In order to form a transistor on a plastic substrate, an electronic thin film may be formed using a pentacene molecule composed of carbon and hydrogen by processing the surface on which an organic semiconductor is formed. This thin film has a size 20 to 100 times that of conventional crystal grains and has sufficient semiconductor properties suitable for electronic device manufacturing.

Pentacene tends to adhere to surface impurities when grown on a silicon substrate. This makes the growth irregular and results in crystal grains that are too small to produce a high quality device. In order to grow the crystal grains larger, it is preferable to apply a single layer “molecular buffer” of molecules called cyclohexene on a silicon substrate. This layer is sticky on silicon
To cover the "sites", pentacene grows to very large grains with a clean surface.

  By using these new large crystal grain thin films, a flexible transistor using a large crystal grain pentacene can be manufactured. For mass production of such a flexible transistor, a transistor (transistor) can be manufactured by applying a liquid material at a low temperature.

  Alternatively, a metal thin film to be a gate and an island shape may be formed on a substrate, and an amorphous silicon film may be deposited or applied thereon, and then heated to form a semiconductor film. The semiconductor film is crystallized well in the island-shaped portion. Therefore, mobility becomes good.

As the organic transistor (transistor), it is preferable to adopt a structure called a static induction transistor (SIT). Amorphous pentacene is used. The hole mobility is 1 × 10 cm ² / Vs, which is lower than crystallized pentacene. However, the frequency characteristic can be enhanced by adopting the SIT structure. The film thickness of pentacene is preferably 100 to 300 nm.

  The organic transistor may be a p-type field effect transistor. A transistor can be formed over a plastic substrate. Since it is possible to bend the entire plastic substrate, it is preferable that pentacene capable of forming a flexible transistor display panel be in a polycrystalline state. PMMA is preferably used as the material for the gate insulating film. Naphthacene may be used for the active layer of the organic transistor.

If oxygen plasma or O ₂ asher is used at the time of cleaning, the planarizing film 102 at the periphery of the pixel electrode 105 is simultaneously ashed, and the periphery of the pixel electrode 105 is removed. In order to solve this problem, an edge protective film (basically a bank 101) made of acrylic resin is formed on the periphery of the pixel electrode 105. Examples of the constituent material of the edge protective film 105 include the same materials as organic materials such as an acrylic resin and a polyimide resin that constitute the planarizing film 102, and other inorganic materials such as SiO ₂ and SiN _x . Needless to say, Al ₂ O ₃ , Ta ₂ O _{3 and the} like may be used.

  The edge protection film 101 is formed so as to fill the space between the pixel electrodes 105 after the patterning of the pixel electrodes 105. Of course, the edge protective film 101 is formed to a height of 2 to 4 μm and used as a bank of a metal mask (a spacer that prevents the metal mask from directly contacting the pixel electrode 105) when the organic EL material is separately applied. Needless to say.

Ta ₂ O ₅ having a high dielectric constant of 24 is preferably used for the gate insulating film. Although the gate insulating film is as thick as 129 nm and the channel length is as long as 500 μm, the P-type transistor operates well at a power supply voltage of −5V. An organic material called pentacene is used as the material of the channel layer. The mobility of holes serving as carriers is 0.40 cm ² / Vs or more, and the ratio of drain current when the transistor is on to leakage current when the transistor is off can be 10 ⁴ .

  An EL film (15R (red), 15G (green), 15B (blue)) is formed on the pixel electrode 105. Each EL film 15 is formed with a slight gap or overlapped with the periphery. The overlapped portion hardly emits light. Further, an aluminum film 106 serving as a cathode is formed on the EL film 15.

As the vacuum deposition apparatus, an apparatus obtained by modifying a commercially available high vacuum deposition apparatus (manufactured by Nippon Vacuum Technology Co., Ltd., EBV-6DA type) is used. The main exhaust device is a turbo molecular pump (TC 1500, manufactured by Osaka Vacuum Co., Ltd.) with an exhaust speed of 1500 liters / min, the ultimate vacuum is about 1 × 10 ⁻⁶ Torr or less, and all the vapor deposition is 2-3 × 10 ^-6 Perform within the range of Torr. All vapor deposition may be performed by connecting a DC power source (manufactured by Kikusui Electronics Co., Ltd., PAK10-70A) to a resistance heating vapor deposition boat made of tungsten.

  A carbon film of 20 to 50 nm is formed on the array substrate arranged in the vacuum layer in this way. Next, 4- (N, N-bis (p-methylphenyl) amino) -α-phenylstilbene is formed to a film thickness of about 5 nm at a deposition rate of 0.3 nm / sec as a hole injection layer.

  As the hole transport layer, N, N′-bis (4′-diphenylamino-4-biphenylyl) -N, N′-diphenylbenzidine (manufactured by Hodogaya Chemical Co., Ltd.), 4-N, N-diphenylamino-α -Phenylstilbene was co-deposited at a deposition rate of 0.3 nm / sec and 0.01 nm / s, respectively, to form a film thickness of about 80 nm. Tris (8-quinolinolato) aluminum (manufactured by Dojin Chemical Co., Ltd.) is formed as a light emitting layer (electron transport layer) to a film thickness of about 40 nm at a deposition rate of 0.3 nm / sec.

  Next, as an electron injection electrode, only Li is formed at a low temperature from an AlLi alloy (manufactured by High Purity Chemical Co., Ltd., Al / Li weight ratio 99/1) at a deposition rate of about 0.1 nm / sec to a film thickness of about 1 nm. Subsequently, the temperature of the AlLi alloy is further increased. From the state where Li was exhausted, only Al was formed at a film thickness of about 100 nm at a deposition rate of about 1.5 nm / sec to obtain a stacked electron injection electrode.

  The organic thin film EL element 15 thus prepared leaks the inside of the vapor deposition tank with dry nitrogen, and then seals the sealing lid 85 made of Corning 7059 glass in a dry nitrogen atmosphere (sealing agent) (Anelva Co., Ltd.) A display panel is obtained by pasting with a company name, Super Back Seal 953-7000).

  A desiccant 107 is disposed in the space between the sealing lid 85 and the array substrate 71. This is because the organic EL film 15 is vulnerable to humidity. The desiccant 107 absorbs moisture penetrating the sealant and prevents the organic EL film 15 from deteriorating.

  In order to suppress the permeation of moisture from the sealant 15, it is a good measure to lengthen the path from the outside. For this reason, in the display panel of the present invention, fine irregularities are formed in the periphery of the display area. The concavo-convex portions formed on the peripheral portion of the array substrate 71 are formed at least twice. The distance between the protrusions (protrusion pitch) is preferably 100 μm or more and 500 μm or less, and the height of the protrusions is preferably 30 μm or more and 300 μm or less. This convex portion is formed by a stamper technique. This stamper technology applies the method used by OMRON as a method for forming a microlens, the method used by Matsushita Electric as a method for forming a microlens with a CD pickup lens, and the like.

  On the other hand, a concave or convex portion is also formed in the sealing lid 85. The formation pitch of the recesses or projections is the same as the formation pitch of the projections formed on the substrate 71. Thus, by making the formation pitch of the recesses or protrusions of the substrate 71 and the substrate 85 the same, the recesses fit into the protrusions. For this reason, the positional deviation between the sealing lid 85 and the array substrate 71 does not occur during the manufacture of the display panel. A sealant is disposed between the convex portion and the concave portion. The sealant adheres the sealing lid 85 and the array substrate 71 and prevents moisture from entering from the outside.

  As the sealant, it is preferable to use a UV (ultraviolet) curable type made of an acrylic resin. The acrylic resin preferably has a fluorine group. In addition, an epoxy adhesive or pressure-sensitive adhesive may be used. The refractive index of the adhesive or pressure-sensitive adhesive is preferably 1.47 or more and 1.54 or less. In particular, it is preferable to add a fine powder of titanium oxide, fine powder of silicon oxide or the like to the seal adhesive in a proportion of 65% to 95% by weight. Moreover, it is preferable that the particle diameter of this fine powder shall be an average diameter of 20 micrometers or more and 100 micrometers or less. As the weight ratio of the fine powder increases, the effect of suppressing the entry of humidity from the outside increases. However, if the amount is too large, bubbles or the like are likely to enter, and on the contrary, the space becomes larger and the sealing effect is lowered.

  The weight of the desiccant 107 is preferably 0.04 g or more and 0.2 g or less per 10 mm of the seal length. In particular, it is desirable to be 0.06 g or more and 0.15 g or less per 10 mm length of the seal. If the amount of the desiccant is too short, the effect of preventing moisture is small and the organic EL layer 15 deteriorates immediately. If the amount is too large, the desiccant becomes an obstacle when sealing, and good sealing cannot be performed. Note that the desiccant 107 may be formed in a sheet shape and disposed between the lid 85 and the EL film. At that time, it is preferable to apply a UV curable resin to the desiccant 107 and irradiate ultraviolet rays after the arrangement to cure and fix the UV resin.

  10 shows a configuration in which sealing is performed using a glass lid 85, but sealing may be performed using a film (a thin film, that is, a thin film sealing film) 111 as illustrated in FIG. For example, as the sealing film (thin film sealing film) 111, it is exemplified to use a film of an electrolytic capacitor obtained by vapor-depositing DLC (diamond-like carbon). This film has very poor moisture permeability (moisture protection). This film is used as the sealing film 111. Needless to say, a structure in which a DLC film or the like is directly deposited on the surface of the electrode 106 is preferable.

  In this case, the positional relationship between the cathode and the anode may be reversed. The film thickness of the thin film is calculated by n · d (where n is the refractive index of the thin film, and when a plurality of thin films are stacked, the refractive indexes thereof are combined (calculate n · d of each thin film)). When the plurality of thin films are laminated, their refractive indexes are calculated together.) Is preferably equal to or less than the emission main wavelength λ of the EL element 15. By satisfying this condition, the light extraction efficiency from the EL element 15 becomes twice or more as compared with the case of sealing with a glass substrate. Further, an alloy or a mixture or a laminate of aluminum and silver may be formed.

A configuration in which sealing is performed with the sealing film 111 without using the lid 85 as described above is referred to as thin film sealing. Thin film encapsulation in the case of “lower extraction (see FIG. 10, the light extraction direction is the arrow direction in FIG. 10)” for extracting light from the substrate 71 side becomes a cathode on the EL film after forming the EL film. An aluminum electrode is formed. Next, a resin layer as a buffer layer is formed on the aluminum film. Examples of the buffer layer include organic materials such as acrylic and epoxy. Further, the film thickness is suitably 1 μm or more and 10 μm or less. More preferably, the film thickness is 2 μm or more and 6 μm or less. A sealing film 74 on the buffer film is formed. Without the buffer film, the structure of the EL film collapses due to the stress, and a line-like defect occurs. As described above, the sealing film 111 is exemplified by DLC (Diamond Like Carbon) or a layer structure of an electric field capacitor (a structure in which dielectric thin films and aluminum thin films are alternately deposited).

The thin film sealing in the case of “light extraction from the EL layer 15 side” (see FIG. 11 above, the light extraction direction is the direction of the arrow in FIG. 11) is the cathode on the EL film 15 after the EL film 15 is formed. An Ag—Mg film serving as an (anode) is formed to a thickness of 20 Å or more and 300 Å. A transparent electrode such as ITO is formed thereon to reduce the resistance. Next, a resin layer as a buffer layer is formed on the electrode film. A sealing film 111 is formed on the buffer film.
Half of the light generated from the organic EL layer 15 is reflected by the reflective film 106 and transmitted through the array substrate 71 to be emitted. However, external light is reflected on the reflective film 106 and a reflection occurs to reduce the display contrast. For this measure, a λ / 4 plate 108 and a polarizing plate (polarizing film) 109 are arranged on the array substrate 71.

  When the pixel is a reflective electrode, the light generated from the EL layer 15 is emitted upward. Therefore, it goes without saying that the phase plate 108 and the polarizing plate 109 are arranged on the light emitting side. The reflective pixel is obtained by forming the pixel electrode 105 with aluminum, chromium, silver, or the like. Further, by providing a convex portion (or a concave-convex portion) on the surface of the pixel electrode 105, the interface with the organic EL layer 15 is widened, the light emission area is increased, and the light emission efficiency is improved. Note that the circularly polarizing plate is not necessary when the reflective film to be the cathode 106 (anode 105) is formed on the transparent electrode or when the reflectance can be reduced to 30% or less. This is because the reflection is greatly reduced. It is also desirable to reduce light interference.

  Further, the contrast of the organic EL display panel can be improved by canceling external light reflection realized by forming a two-layer thin film inside the display by optical interference. Cost can be reduced compared with the case of using a conventional circularly polarizing plate. In addition, the problem of diffuse reflection that the circularly polarizing plate has, the viewing angle dependency of display color, and the film thickness dependency of the organic EL light emitting layer can be solved.

  Between the substrate 71 and the polarizing plate (polarizing film) 109, one or a plurality of phase films 108 (phase plate, phase rotating means, phase difference plate, phase difference film) are arranged. Polycarbonate is preferably used as the phase film. The phase film generates a phase difference between incident light and outgoing light, and contributes to efficient light modulation.

  In addition, as the phase film, an organic resin plate or an organic resin film such as a polyester resin, a PVA resin, a polysulfone resin, a vinyl chloride resin, a ZEONEX resin, an acrylic resin, or a polystyrene resin may be used. In addition, crystals such as quartz may be used. The phase difference of one phase plate is preferably 50 nm or more and 350 nm or less in a uniaxial direction, and more preferably 80 nm or more and 220 nm or less. Needless to say, a circularly polarizing plate (circularly polarizing film) in which the phase film and the polarizing plate are integrated may be used.

  The phase film 108 is preferably colored with a dye or pigment to have a filter function. In particular, the organic EL 15 has poor red (R) purity. Therefore, the color temperature is adjusted by cutting a certain wavelength range with the colored phase film 108. The color filter is generally provided with a pigment dispersion type resin as a dyeing filter. The pigment absorbs light in a specific wavelength band and transmits light in a wavelength band not absorbed.

  As described above, a part or the whole of the phase film 108 may be colored, or a part or the whole may have a diffusion function. Further, the surface may be embossed or an antireflection film may be formed to prevent reflection. In addition, it is preferable to form a light-shielding film or a light absorption film at a location that is not effective or unhindered for image display so as to increase the black level of the display image or to exhibit a contrast enhancement effect by preventing halation. Alternatively, the microlenses may be formed in a kamaboko shape or a matrix shape by forming irregularities on the surface of the phase film. The microlenses are arranged so as to correspond to one pixel electrode or three primary color pixels, respectively.

As described above, the function of the phase film may be given to the color filter. For example, the phase difference can be generated by rolling at the time of forming the color filter or by causing the phase difference to occur in a certain direction by photopolymerization. In addition, a phase difference may be given by photopolymerizing the smoothing film 102. If comprised in this way, it will become unnecessary to comprise or arrange | position a phase film out of a board | substrate, the structure of a display panel will become simple, and cost reduction can be expected. In addition, it cannot be overemphasized that the above matter may be applied to a polarizing plate.

  As the main material constituting the polarizing plate (polarizing film) 109, a TAC film (triacetyl cellulose film) is optimal. This is because the TAC film has excellent optical properties, surface smoothness and processability. As for the production of the TAC film, it is optimal to produce it by a solution casting film forming technique.

  The polarizing plate 109 is exemplified by a resin film obtained by adding iodine or the like to polyvinyl alcohol (PVA) resin. The polarizing plate 109 of the pair of polarization separation means performs polarization separation by absorbing a polarized light component in a direction different from a specific polarization axis direction of incident light, so that the light use efficiency is relatively poor. Therefore, a reflective polarizer that performs polarization separation by reflecting a polarization component (reflective polarizer) in a direction different from a specific polarization axis direction of incident light may be used. If comprised in this way, the utilization efficiency of light will increase with a reflective polarizer, and a brighter display will be attained rather than the above-mentioned example using a polarizing plate.

  In addition to such polarizing plates and reflective polarizers, as the polarization separating means of the present invention, for example, a combination of a cholesteric liquid crystal layer and a (1/4) λ plate 108, utilizing the angle of Brewster. It is also possible to use one that separates into reflected polarized light and transmitted polarized light, one that uses a hologram, a polarization beam splitter (PBS), and the like.

  Although not shown in FIG. 10, the surface of the polarizing plate 109 is provided with an AIR coat. A configuration in which the AIR coat is formed of a dielectric single layer film or a multilayer film is exemplified. In addition, a resin having a low refractive index of 1.35 to 1.45 may be applied. For example, a fluorine-type acrylic resin etc. are illustrated. Particularly, those having a refractive index of 1.37 or more and 1.42 or less have good characteristics.

  The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide wavelength band of visible light, and this is called multi-coat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band, and this is called a V coat. Multi-coat and V-coat are used properly according to the use of the display panel. In addition, it is not limited to two or more layers, and may be a single layer.

In the case of multi-coat, the optical film thickness of aluminum oxide (Al ₂ O ₃ ) is nd = λ / 4, zirconium (ZrO ₂ ) is nd1 = λ / 2, and magnesium fluoride (MgF ₂ ) is nd1 = λ / 4. It is formed by stacking. Usually, a thin film is formed with λ as 520 nm or a value in the vicinity thereof. In the case of V coating, silicon monoxide (SiO) has an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF ₂ ) nd1 = λ / 4, or yttrium oxide (Y ₂ O ₃ ) and magnesium fluoride ( MgF ₂ ) is formed by stacking n d1 = λ / 4. Since SiO has an absorption band on the blue side, it is better to use Y ₂ O ₃ when modulating blue light. Further, Y ₂ O ₃ is more preferable because of its stability. It may also be used SiO ₂ thin film. Of course, a low refractive index resin or the like may be used for the AIR coating. For example, an acrylic resin such as fluorine is exemplified. These are preferably ultraviolet curable types.

  Note that a hydrophilic resin is preferably applied to the surface of the display panel or the like in order to prevent the display panel from being charged with static electricity. In addition, in order to prevent surface reflection, the surface of the polarizing plate 54 may be embossed.

In addition, although a transistor is connected to the pixel electrode 105, the present invention is not limited to this. It goes without saying that the active matrix may be a thin film transistor (transistor) as a switching element, a diode system (TFD), a varistor, a thyristor, a ring diode, a photodiode, a phototransistor, an FET, a MOS transistor, a PLZT element, or the like. That is, any of those constituting the switch element 11 and the drive element 11 can be used. Further, a simple matrix pixel configuration in which a plurality of substantially striped electrodes are arranged may be used.

  The transistor preferably adopts an LDD (low doping drain) structure. The transistor means all elements that perform transistor operation such as switching such as FET. Needless to say, the structure of the EL film, the panel structure, and the like can also be applied to a simple matrix display panel. In this specification, an organic EL element (described by various abbreviations such as OEL, PEL, PLED, and OLED) 15 is described as an example of the EL element, but the present invention is not limited to this. Needless to say, this also applies.

  First, the active matrix method used for the organic EL display panel is as follows. A specific pixel can be selected and given display information can be given. 2. Two conditions must be satisfied that current can flow through the EL element throughout one frame period.

  In order to satisfy these two conditions, in the conventional organic EL pixel configuration shown in FIG. 62, the first transistor 11b is a switching transistor for selecting a pixel, and the second transistor 11a is an EL element (EL film). ) A driving transistor for supplying current to 15.

  Here, compared with the active matrix system used for the liquid crystal, the switching transistor 11b is also necessary for the liquid crystal, but the driving transistor 11a is necessary for lighting the EL element 15. This is because in the case of liquid crystal, the on state can be maintained by applying a voltage, but in the case of the EL element 15, the lighting state of the pixel 16 cannot be maintained unless a current is continuously supplied.

  Therefore, in the EL display panel, the transistor 11a must be kept on in order to keep the current flowing. First, when both the scanning line and the data line are turned on, charges are accumulated in the capacitor 19 through the switching transistor 11b. Since the capacitor 19 continues to apply a voltage to the gate of the driving transistor 11a, even if the switching transistor 11b is turned off, current continues to flow from the current supply line (Vdd), and the pixel 16 can be turned on for one frame period.

  In the case of displaying gradation using this configuration, it is necessary to apply a voltage corresponding to the gradation as the gate voltage of the driving transistor 11a. Therefore, the variation in the on-state current of the driving transistor 11a appears in the display as it is.

The on-current of a transistor is very uniform if it is a transistor formed of a single crystal, but in a low-temperature polycrystalline transistor formed by low-temperature polysilicon technology that can be formed on an inexpensive glass substrate with a formation temperature of 450 degrees or less. The threshold value varies in the range of ± 0.2V to 0.5V. For this reason, the on-current flowing through the driving transistor 11a varies correspondingly, and the display is uneven. These irregularities are caused not only by variations in threshold voltage, but also by transistor mobility, gate insulating film thickness, and the like. The characteristics also change due to deterioration of the transistor 11. Note that the present invention is not limited to low-temperature polysilicon technology, and may be configured using high-temperature polysilicon technology having a process temperature of 450 degrees Celsius or higher, and a semiconductor film grown by solid phase (CGS) may be used. You may use what formed TFT etc. using it. In addition, an organic TFT may be used. A panel is formed using a TFT array formed by amorphous silicon technology. In this specification, TFTs formed by low-temperature polysilicon technology are mainly described. However, the problems such as the occurrence of TFT variations are the same in other systems.

  Therefore, in the method of displaying gray scales in an analog manner, it is necessary to strictly control the device characteristics in order to obtain a uniform display. In the current low-temperature polycrystalline polysilicon transistor, this variation is suppressed within a predetermined range. I can not satisfy the specifications. In order to solve this problem, a method in which four or more transistors are provided in one pixel and a uniform current is obtained by compensating for variations in threshold voltage with a capacitor, and a constant current circuit is formed for each pixel to generate a current. A method for achieving uniformization is also conceivable.

  However, in these methods, since the current to be programmed is programmed through the EL element 15, when the current path changes, the transistor that controls the drive current becomes the source follower for the switching transistor connected to the power supply line, and the drive margin is increased. Narrow. Therefore, there is a problem that the drive voltage becomes high.

  In addition, it is necessary to use a switching transistor connected to a power source in a low impedance region, and there is a problem that this operation range is affected by fluctuations in characteristics of the EL element 15. In addition, when the kink current is generated in the voltage-current characteristic in the saturation region, or when the threshold voltage of the transistor is changed, there is a problem that the stored current value is changed.

  In the EL element structure of the present invention, the transistor 11 that controls the current flowing through the EL element 15 does not have a source follower configuration, and even if the transistor has a kink current, the effect of the kink current is prevented. In this configuration, the fluctuation of the current value that can be minimized and stored can be reduced.

  Specifically, the pixel structure of the EL display device of the present invention is formed by a plurality of transistors 11 and EL elements each having at least four unit pixels as shown in FIG. Note that the pixel electrode is configured to overlap the source signal line. That is, an insulating film or a planarizing film made of an acrylic material is formed on the source signal line 18 for insulation, and the pixel electrode 105 is formed on the insulating film. Such a configuration in which the pixel electrode is overlaid on the source signal line 18 is referred to as a high aperture (HA) structure.

  By making the gate signal line (first scanning line) 17a active (applying an ON voltage), the EL element 15 is driven through the transistor (transistor or switching element) 11a and the transistor (transistor or switching element) 11c. A current value to be supplied to the element 15 is supplied from the source driver circuit 14. In addition, the transistor 11b opens when the gate signal line 17a becomes active (applies an ON voltage) so as to short-circuit between the gate and drain of the transistor 11a, and a capacitor (capacitor, capacitor) connected between the gate and source of the transistor 11a. The gate voltage (or drain voltage) of the transistor 11a is stored in the storage capacitor (additional capacitor) 19 so that the current value flows (see FIG. 3A).

Note that the capacitance (capacitor) 19 between the source (S) and the gate (G) of the transistor 11a is preferably 0.2 pF or more. As another configuration, a configuration in which the capacitor 19 is separately formed is also exemplified. That is, the storage capacitor is formed from the capacitor electrode layer, the gate insulating film, and the gate metal. From the viewpoint of preventing luminance reduction due to leakage of the transistor 11c and stabilizing the display operation, it is preferable to form a separate capacitor in this way. The size of the capacitor (storage capacitor) 19 is 0.2 pF.
The capacitance is preferably 2 pF or less, and the size of the capacitor (storage capacitor) 19 is preferably 0.4 pF or more and 1.2 pF or less.

  Note that the capacitor 19 is preferably formed in a non-display area between adjacent pixels. In general, when the full-color organic EL 15 is formed, since the organic EL layer 15 is formed by mask vapor deposition using a metal mask, the formation position of the EL layer is generated due to mask displacement. When the position shift occurs, there is a risk that the organic EL layers 15 (15R, 15G, 15B) of the respective colors overlap. Therefore, the non-display area between adjacent pixels of each color must be separated by 10 μm or more. This part does not contribute to light emission. Therefore, forming the storage capacitor 19 in this region is an effective means for improving the aperture ratio.

  The metal mask is made of a magnetic material, and the metal mask is attracted by a magnet from the back surface of the substrate 71 with a magnet. Due to the magnetic force, the metal mask adheres closely to the substrate. The above items related to the manufacturing method are also applied to other manufacturing methods of the present invention.

  Next, the gate signal line 17a is inactive (OFF voltage is applied), the gate signal line 17b is active, and the current flowing path is connected to the first transistor 11a and the EL element 15, and the EL element The operation is performed so that the stored current flows through the EL element 15 by switching to the path including 15 (see FIG. 3B).

  This circuit has four transistors 11 in one pixel, and the gate of the transistor 11a is connected to the source of the transistor 11b. The gates of the transistors 11b and 11c are connected to the gate signal line 17a. The drain of the transistor 11 b is connected to the source of the transistor 11 c and the source of the transistor 11 d, and the drain of the transistor 11 c is connected to the source signal line 18. The gate of the transistor 11d is connected to the gate signal line 17b, and the drain of the transistor 11d is connected to the anode electrode of the EL element 15.

  In FIG. 1, all the transistors are P-channel. The P channel has a lower mobility than an N channel transistor, but is preferable because it has a high breakdown voltage and is less likely to deteriorate. However, the present invention is not limited to the configuration of the EL element with the P channel. You may comprise only N channel. Moreover, you may comprise using both N channel and P channel.

  In FIG. 1, the transistors 11c and 11b are preferably configured with the same polarity and configured with an N channel, and the transistors 11a and 11d are preferably configured with a P channel. In general, the P-channel transistor has features such as higher reliability and less kink current compared to the N-channel transistor. For the EL element 15 that obtains the desired light emission intensity by controlling the current. The effect of making the transistor 11a into the P channel is great. Optimally, it is preferable that all the TFTs 11 constituting the pixel are formed by the P channel and the built-in gate driver 12 is also formed by the P channel. By forming the array with TFTs having only P-channels in this way, the number of masks becomes five, and it is possible to realize cost reduction and high yield.

Hereinafter, in order to facilitate the understanding of the present invention, the EL element configuration of the present invention will be described with reference to FIG. The EL device configuration of the present invention is controlled by two timings. The first timing is a timing for storing a necessary current value. When the transistor 11b and the transistor 11c are turned on at this timing, an equivalent circuit is shown in FIG. Here, a predetermined current Iw is written from the signal line. As a result, the gate and drain of the transistor 11a are connected, and a current Iw flows through the transistor 11a and the transistor 11c. Accordingly, the gate-source voltage of the transistor 11a is a voltage V1 at which I1 flows.

  The second timing is a timing at which the transistor 11a and the transistor 11c are closed and the transistor 11d is opened, and the equivalent circuit at that time is shown in FIG. The voltage between the source and gate of the transistor 11a remains held. In this case, since the transistor 11a always operates in the saturation region, the current Iw is constant.

  When operated in this way, it is as shown in FIG. That is, 51a in FIG. 5A indicates a pixel (row) (write pixel row) in the display screen 50 that is current-programmed at a certain time. This pixel (row) 51a is not lit (non-display pixel (row)) as shown in FIG. The other pixel (row) is a display pixel (row) 53 (current flows through the EL element 15 of the non-pixel 53 and the EL element 15 emits light).

  In the case of the pixel configuration of FIG. 1, as shown in FIG. 3A, the program current Iw flows through the source signal line 18 during current programming. The voltage is set (programmed) in the capacitor 19 so that the current Iw flows through the transistor 11a and the current flowing through Iw is maintained. At this time, the transistor 11d is in an open state (off state).

  Next, during a period in which a current flows through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d is operated as shown in FIG. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, an on voltage (Vgl) is applied to the gate signal line 17b, and the transistor 11d is turned on.

  This timing chart is shown in FIG. In FIG. 4 and the like, subscripts in parentheses (for example, (1) and the like) indicate pixel row numbers. That is, the gate signal line 17a (1) indicates the gate signal line 17a of the pixel row (1). Also, * H in the upper part of FIG. 4 (an arbitrary symbol or numerical value is applied to “*” and indicates a horizontal scanning line number) indicates a horizontal scanning period. That is, 1H is the first horizontal scanning period. The above items are for ease of explanation and are not limited (1H number, 1H cycle, order of pixel row numbers, etc.).

  As can be seen from FIG. 4, when a turn-on voltage is applied to the gate signal line 17a in each selected pixel row (selection period is 1H), a turn-off voltage is applied to the gate signal line 17b. Yes. During this period, no current flows through the EL element 15 (non-lighting state). In an unselected pixel row, an off voltage is applied to the gate signal line 17a, and an on voltage is applied to the gate signal line 17b. Further, during this period, a current flows through the EL element 15 (lighting state).

  Note that the gate of the transistor 11a and the gate of the transistor 11c are connected to the same gate signal line 11a. However, the gate of the transistor 11a and the gate of the transistor 11c may be connected to different gate signal lines 11 (see FIG. 32). One pixel has three gate signal lines (the configuration in FIG. 1 is two). By individually controlling the ON / OFF timing of the gate of the transistor 11b and the ON / OFF timing of the gate of the transistor 11c, variation in the current value of the EL element 15 due to variations in the transistor 11a can be further reduced.

  When the gate signal line 17a and the gate signal line 17b are made common and the transistors 11c and 11d have different conductivity types (N channel and P channel), the drive circuit can be simplified and the aperture ratio of the pixel can be improved. .

  With this configuration, the write path from the signal line is turned off as the operation timing of the present invention. That is, when a predetermined current is stored, if there is a branch in the current flow path, an accurate current value is not stored in the capacitance (capacitor) between the source (S) and the gate (G) of the transistor 11a. By making the transistors 11c and 11d have different conductivity types, the transistor 11d can be turned on after the transistor 11c is always turned off at the timing of switching of the scanning lines by controlling the threshold values of the transistors 11c and 11d.

  In this case, however, it is necessary to carefully control each other's thresholds, so care must be taken in the process. Although the circuit described above can be realized with at least four transistors, the transistor 11e is cascade-connected as shown in FIG. 2 to control the timing more accurately or to reduce the mirror effect as described later. The operation principle is the same even when the total number of transistors is 4 or more. With the configuration in which the transistor 11e is added as described above, the current programmed through the transistor 11c can be supplied to the EL element 15 with higher accuracy.

  In the configuration of FIG. 1, it is more preferable that the current value Ids in the saturation region of the first transistor 11a satisfies the condition of the following expression. In the following expression, the value of λ satisfies the condition of 0.06 or less and 0.01 or more between adjacent pixels.

Ids = k × (Vgs−Vth) ² (1 + Vds × λ)
In the present invention, the operating range of the transistor 11a is limited to the saturation region, but generally the transistor characteristics in the saturation region deviate from the ideal characteristics and are affected by the source-drain voltage. This effect is called a mirror effect.

  Consider a case where a threshold shift of ΔVt occurs in each transistor 11a in an adjacent pixel. In this case, the stored current values are the same. If the threshold shift is ΔL, approximately ΔV × λ corresponds to a shift in the current value of the EL element 15 due to a change in the threshold of the transistor 11a. Therefore, in order to suppress the current deviation to x (%) or less, λ must be 0.01 × x / y or less, assuming that y (V) is allowed between adjacent pixels as the threshold shift tolerance. I understand that I have to do it.

This tolerance varies depending on the brightness of the application. In the luminance region where the luminance is from 100 cd / m ² to 1000 cd / m ² , if the variation amount is 2% or more, the human recognizes the varied boundary line. Therefore, it is necessary that the variation amount of the luminance (current amount) is within 2%. When the luminance is higher than 100 cd / cm ² , the luminance change amount of adjacent pixels is 2% or more. When the EL display element of the present invention is used as a mobile terminal display, the required luminance is about 100 cd / m ² . When the pixel configuration of FIG. 1 was actually prototyped and the threshold fluctuation was measured, it was found that the maximum threshold fluctuation was 0.3 V in the transistor 11a of the adjacent pixel. Therefore, λ must be 0.06 or less in order to keep the luminance variation within 2%. However, it is not necessary to make it 0.01 or less. This is because humans cannot recognize changes. Also, in order to achieve this threshold variation, the transistor size must be sufficiently large, which is unrealistic.

  Further, it is preferable that the current value Ids in the saturation region of the first transistor 11a satisfies the following formula. Note that the variation of λ is 5% or less and 1% or more between adjacent pixels.

Ids = k × (Vgs−Vth) ² (1 + Vds × λ)
Even if there is no change in threshold value between adjacent pixels, if there is a change in λ in the above equation, the value of the current flowing through the EL will change. In order to suppress the fluctuation within ± 2%, the fluctuation of λ must be suppressed to ± 5%. However, it is not necessary to make it 1% or less. This is because humans cannot recognize changes. In order to achieve 1% or less, the transistor size needs to be considerably increased, which is unrealistic.

  Further, according to experiments, array trial manufacture, and examination, it is preferable that the channel length of the first transistor 11a is 10 μm or more and 200 μm or less. More preferably, the channel length of the first transistor 11a is 15 μm or more and 150 μm or less. This is considered to be because when the channel length L is increased, the grain boundary included in the channel increases, the electric field is relaxed, and the kink effect is suppressed to a low level.

  Further, the transistor 11 constituting the pixel is formed of a polysilicon transistor formed by a laser recrystallization method (laser annealing), and the channel direction of all the transistors is the same direction as the laser irradiation direction. It is preferable. Further, it is preferable that the laser scans the same portion twice or more to form the semiconductor film.

  The object of the invention of this patent is to propose a circuit configuration in which variations in transistor characteristics do not affect display, and for that purpose four or more transistors are required. When circuit constants are determined based on these transistor characteristics, it is difficult to obtain appropriate circuit constants if the characteristics of the four transistors do not match. When the channel direction is horizontal and vertical with respect to the major axis direction of laser irradiation, the threshold value and mobility of transistor characteristics are different. In both cases, the degree of variation is the same. The average value of mobility and threshold value differs between the horizontal direction and the vertical direction. Therefore, it is desirable that the channel directions of all the transistors constituting the pixel are the same.

  Further, when the capacitance value of the storage capacitor 19 is Cs and the off-current value of the second transistor 11b is Ioff, it is preferable to satisfy the following equation.

3 <Cs / Ioff <24
More preferably, it is preferable to satisfy the following formula.

6 <Cs / Ioff <18
By setting the off-state current of the transistor 11b to 5 pA or less, the change in the current value flowing through the EL can be suppressed to 2% or less. This is because when the leakage current increases, the electric charge stored between the gate and the source (both ends of the capacitor) cannot be held for one field in the voltage non-writing state. Therefore, if the storage capacity of the capacitor 19 is large, the allowable amount of off-current is also large. By satisfying the above equation, the fluctuation of the current value between adjacent pixels can be suppressed to 2% or less.

  In addition, it is preferable that the transistors constituting the active matrix are p-ch polysilicon thin film transistors, and the transistor 11b has a multi-gate structure with dual gates or more. Since the transistor 11b functions as a switch between the source and drain of the transistor 11a, the transistor 11b is required to have as high a ON / OFF ratio as possible. By setting the gate structure of the transistor 11b to a multi-gate structure that is equal to or higher than the dual gate structure, a characteristic with a high ON / OFF ratio can be realized.

The transistors constituting the active matrix are formed of polysilicon thin film transistors, and it is preferable that (channel width W) × (channel length L) of each transistor be 54 μm ² or less. There is a correlation between (channel width W) × (channel length L) and variations in transistor characteristics. The cause of variations in transistor characteristics is largely due to variations in energy due to laser irradiation. Therefore, in order to absorb this, the laser irradiation pitch (generally, several tens of μm) should be set within the channel as much as possible. A structure including many is desirable. By setting (channel width W) × (channel length L) of each transistor to 54 μm ² or less, there is no variation caused by laser irradiation, and a thin film transistor with uniform characteristics can be obtained. If the transistor size is too small, characteristic variations due to area occur. Therefore, (channel width W) × (channel length L) of each transistor is set to 9 μm ² or more. More preferably, (channel width W) × (channel length L) of each transistor is preferably 16 μm ² or more and 45 μm ² or less.

  In addition, it is preferable that the mobility variation of the first transistor 11a in adjacent unit pixels is 20% or less. Due to the lack of mobility, the charging capability of the switching transistor is deteriorated, and the capacity between the gate and the source of M1 cannot be charged until a necessary current value is passed in time. Therefore, by suppressing the variation in movement to within 20%, the variation in luminance between pixels can be made below the recognition limit.

  In the above description, the pixel configuration is described as the configuration in FIG. 1, but the above matters can be applied to other pixel configurations. As an example, the configuration and operation of the pixel configuration in FIG. 38 will be described below.

  When setting a current to flow to the EL element 15, a signal current to flow to the transistor 11a is set to Iw, and a gate-source voltage generated in the transistor 11a as a result is set to Vgs. At the time of writing, the transistor 11d is short-circuited between the gate and the drain of the transistor 11a, so that the transistor 11a operates in the saturation region. Therefore, Iw is given by the following equation.

Iw = μ1 · Cox1 · (W1 / L1) / 2 (Vgs−Vth1) ² (1)
Here, Cox is a gate capacitance per unit area, and is given by Cox = ε ₀ · ε _r / d. Vth is the transistor threshold, μ is the carrier mobility, W is the channel width, L is the channel length, ε ₀ is the vacuum mobility, ε _r is the relative dielectric constant of the gate insulating film, d is the gate insulating film It is thickness.

  Assuming that the current flowing through the EL element 15 is Idd, the current level of Idd is controlled by the transistor 1 b connected in series with the EL element 15. In the present invention, since the voltage between the gate and the source coincides with Vgs in the equation (1), assuming that the transistor 1b operates in the saturation region, the following equation is established.

Idrv = μ 2 · Cox 2 · (W 2 / L 2) / 2 (Vgs−Vth 2) ² (2)
The conditions for the insulated gate field effect thin film transistor (transistor) to operate in the saturation region are generally given by the following equation, where Vds is the drain-source voltage.

| Vds |> | Vgs−Vth | (3)
Here, since the transistor 11a and the transistor 11b are formed close to the inside of a small pixel, they are approximately μ1 = μ2 and Cox1 = Cox2, and it is considered that Vth1 = Vth2 unless particularly devised. Then, at this time, the following expressions are easily derived from the expressions (1) and (2).

Idrv / Iw = (W2 / L2) / (W1 / L1) (4)
It should be noted that in the expressions (1) and (2), the values of μ, Cox, and Vth themselves usually vary from pixel to pixel, from product to product, or from production lot to (4). Since the equation does not include these parameters, the value of Idrv / Iw does not depend on these variations.

  If W1 = W2 and L1 = L2 are designed, Idrv / Iw = 1, that is, Iw and Idrv have the same value. That is, the drive current Idd flowing through the EL element 15 is exactly the same as the signal current Iw regardless of variations in transistor characteristics, and as a result, the light emission luminance of the EL element 15 can be accurately controlled.

  As described above, since Vth1 of the driving transistor 11a and Vth2 of the driving transistor 11b are basically the same, a cut-off level signal voltage is applied to the gates at the common potential of both transistors. Both the transistor 11a and the transistor 11b should be in a non-conductive state. However, in practice, Vth2 may be lower than Vth1 due to factors such as parameter variations within the pixel. At this time, since a sub-threshold level leakage current flows through the driving transistor 11b, the EL element 15 emits slight light emission. This slight light emission reduces the contrast of the screen and impairs display characteristics.

  In the present invention, in particular, the threshold voltage Vth2 of the driving transistor 11b is set not to be lower than the threshold voltage Vth1 of the corresponding driving transistor 11a in the pixel. For example, the gate length L2 of the transistor 11b is made longer than the gate length L1 of the transistor 11a so that Vth2 does not become lower than Vth1 even if the process parameters of these thin film transistors vary. Thereby, a minute current leak can be suppressed. The above matters also apply to the relationship between the transistor 11a and the transistor 11d in FIG.

  As shown in FIG. 38, the pixel circuit and the data line are controlled by controlling the gate signal line 17a1 in addition to the driving transistor 11b for controlling the driving current flowing in the light emitting element including the driving transistor 11a and the EL element 15 through which the signal current flows. The capture transistor 11c that connects or disconnects the data, the switching transistor 11d that short-circuits the gate and drain of the transistor 11a during the writing period under the control of the gate signal line 17a2, and the gate-source voltage of the transistor 11a after the writing is completed The capacitor C19 for holding the EL element 15 as well as the EL element 15 as a light emitting element.

  In FIG. 38, the transistors 11c and 11d are N-channel MOS (NMOS), and the other transistors are P-channel MOS (PMOS), but this is an example, and this is not necessarily the case. The capacitor C has one terminal connected to the gate of the transistor 11a and the other terminal connected to Vdd (power supply potential). However, the capacitor C is not limited to Vdd, and may be any constant potential. The cathode (cathode) of the EL element 15 is connected to the ground potential. Therefore, it goes without saying that the above items also apply to FIG.

  The terminal voltage of the EL element 15 also changes depending on the temperature. Usually, it is high when the temperature is low, and it is low as the temperature is high. This tendency is linear. Therefore, it is preferable to adjust the Vdd voltage by the external temperature (more precisely, by the temperature of the EL element 15). The external temperature is detected by the temperature sensor, and the Vdd voltage or Vk voltage is changed by applying feedback of the Vdd voltage generator or the Vk voltage generator. The Vdd voltage or the like is preferably changed from 2% to 8% with a change of 10 degrees Celsius. Among these, it is preferable to set it to 3% or more and 6% or less.

Note that the Vdd voltage in FIG. 1 and the like is preferably lower than the off-voltage of the transistor 11b (when the transistor is in the P channel). Specifically, Vgh (gate off voltage) should be at least higher than Vdd-0.5 (V). If it is lower than this, off-leakage of the transistor occurs, and the shot unevenness of laser annealing becomes conspicuous. Also, it should be lower than Vdd + 4 (V). If it is too high, the amount of off-leak increases.

  Therefore, the power supply voltage (Vdd in FIG. 1) of the gate off voltage (Vgh in FIG. 1, that is, the voltage side close to the power supply voltage) is −0.5 (V) or more and +4 (V) or less. Should. More preferably, the power supply voltage (Vdd in FIG. 1) should be 0 (V) or more and +2 (V) or less. That is, the off voltage of the transistor applied to the gate signal line is sufficiently turned off. When the transistor is an N channel, Vgl is an off voltage. Therefore, Vgl is set in a range of −4 (V) to 0.5 (V) with respect to the GND voltage. More preferably, it is in the range of −2 (V) to 0 (V).

  The above items have been described with reference to the pixel configuration of the current program in FIG. The Vt offset cancellation of the voltage program is preferably compensated individually for each of R, G, and B.

  The driving transistor 11b receives the voltage level held in the capacitor 19 at the gate, and flows a driving current having a current level corresponding to the voltage level to the EL element 15 through the channel. The gate of the transistor transistor 11a and the gate of the transistor transistor 11b are directly connected to form a current mirror circuit so that the current level of the signal current Iw and the current level of the drive current are in a proportional relationship.

  The transistor 11b operates in a saturation region, and a drive current corresponding to the difference between the voltage level applied to the gate of the transistor 11b and the threshold voltage is supplied to the EL element 15.

  The transistor 11b is set so that its threshold voltage does not become lower than the threshold voltage of the corresponding transistor 11a in the pixel. Specifically, the gate length of the transistor 11b is set so as not to be shorter than the gate length of the transistor 11a. Alternatively, the transistor 11b may be set so that its gate insulating film is not thinner than the gate insulating film of the corresponding transistor 11a in the pixel.

  Alternatively, the transistor 11b may be set so that the threshold voltage does not become lower than the threshold voltage of the corresponding transistor 11a in the pixel by adjusting the impurity concentration injected into the channel. If the threshold voltages of the transistor 11a and the transistor 11b are set to be the same, when a cut-off level signal voltage is applied to the gates of the commonly connected transistors, the transistors 11a and 11b are both turned off. Should be. However, in reality, there are slight variations in process parameters within the pixel, and the threshold voltage of the transistor 11b may be lower than the threshold voltage of the transistor 11a.

  At this time, a weak current of a subthreshold level flows through the driving transistor 11b even with a signal voltage equal to or lower than the cut-off level, so that the EL element 15 emits light and a contrast reduction of the screen appears. Therefore, the gate length of the transistor 11b is set longer than that of the transistor 11a. This prevents the threshold voltage of the transistor 11b from becoming lower than the threshold voltage of the transistor 11a even if the process parameter of the transistor 11 varies within the pixel.

In the short channel effect region A where the gate length L is relatively short, Vth increases as the gate length L increases. On the other hand, in the suppression region B where the gate length L is relatively large, Vth regardless of the gate length L.
Is almost constant. Using this characteristic, the gate length of the transistor 11b is made longer than that of the transistor 11a. For example, when the gate length of the transistor 11a is 7 μm, the gate length of the transistor 11b is set to about 10 μm.

  The gate length of the transistor 11a may belong to the short channel effect region A, while the gate length of the transistor 11b may belong to the suppression region B. Thereby, the short channel effect in the transistor 11b can be suppressed, and the threshold voltage reduction due to the process parameter variation can be suppressed. Thus, the subthreshold level leakage current flowing through the transistor 11b can be suppressed to suppress the slight light emission of the EL element 15 and contribute to the improvement of contrast.

A DC voltage was applied to the EL display element 15 described with reference to FIGS. 1, 2, 38, etc. thus manufactured, and it was continuously driven at a constant current density of 10 mA / cm ² . The EL structure was confirmed to emit light of 7.0 V, 200 cd / cm ² green (emission maximum wavelength λmax = 460 nm). The blue light emitting part has a luminance of 100 cd / cm ² and color coordinates of x = 0.129 and y = 0.105, and the green light emitting part has a luminance of 200 cd / cm ² and the color coordinates of x = 0.340, y = The emission color of 0.625, the red light-emitting portion was 100 cd / cm ² , the color coordinates were x = 0.649, and y = 0.338.

  In full-color organic EL display panels, improvement of the aperture ratio is an important development issue. This is because increasing the aperture ratio increases the light utilization efficiency, leading to higher brightness and longer life. In order to increase the aperture ratio, the area of the transistor that blocks light from the organic EL layer may be reduced. A low-temperature polycrystalline Si transistor has a performance 10 to 100 times that of amorphous silicon and has a high current supply capability, so that the size of the transistor can be made very small. Therefore, in the organic EL display panel, it is preferable that the pixel transistor and the peripheral drive circuit are manufactured by the low temperature polysilicon technology and the high temperature polysilicon technology. Of course, it may be formed by amorphous silicon technology, but the pixel aperture ratio becomes considerably small.

  By forming a driving circuit such as the gate driver circuit 12 or the source driver circuit 14 on the glass substrate 71, it is possible to reduce the resistance which is particularly a problem in the current-driven organic EL display panel. In addition to eliminating the connection resistance of TCP, the lead wire from the electrode is shortened by 2 to 3 mm compared to the case of TCP connection, and the wiring resistance is reduced. Further, it is assumed that there is an advantage that a process for TCP connection is eliminated and a material cost is reduced.

  Next, the EL display panel or EL display device of the present invention will be described. FIG. 6 is an explanatory diagram focusing on the circuit of the EL display device. Pixels 16 are arranged or formed in a matrix. Each pixel 16 is connected to a source driver circuit 14 that outputs a current for current programming of each pixel. A current mirror circuit corresponding to the number of bits of the video signal is formed at the output stage of the source driver circuit 14 (described later). For example, in the case of 64 gradations, 63 current mirror circuits are formed in each source signal line, and a desired current can be applied to the source signal line 18 by selecting the number of these current mirror circuits. Has been.

  The minimum output current of one current mirror circuit is 10 nA or more and 50 nA. In particular, the minimum output current of the current mirror circuit is preferably 15 nA or more and 35 nA. This is to ensure the accuracy of the transistors constituting the current mirror circuit in the driver IC 14.

A precharge or discharge circuit for forcibly releasing or charging the source signal line 18 is incorporated. The voltage (current) output value of the precharge or discharge circuit that forcibly releases or charges the source signal line 18 is preferably configured to be set independently by R, G, and B. This is because the threshold value of the EL element 15 is different from RGB.

  It goes without saying that the pixel configuration, array configuration, panel configuration, and the like described above are applied to the configuration, method, and apparatus described below. In addition, it goes without saying that the pixel configuration, array configuration, panel configuration and the like already described are applied to the configuration, method, and apparatus described below.

  It is known that an organic EL element has a large temperature dependency characteristic (temperature characteristic). In order to adjust the light emission luminance change due to the temperature characteristics, a non-linear element such as a thermistor or a posistor that changes the output current is added to the current mirror circuit, and the temperature characteristics change is adjusted by the thermistor as an analog reference. Create a current.

  In this case, since it is uniquely determined by the EL material to be selected, it is often unnecessary to perform software control such as a microcomputer. That is, it may be fixed to a certain shift amount or the like by a liquid crystal material. What is important is that the temperature characteristics differ depending on the luminescent color material, and it is necessary to perform optimum temperature characteristics compensation for each luminescent color (R, G, B).

  The temperature characteristics of the R, G, and B EL elements must be within a certain range. Needless to say, it is preferable that the R, G, and B EL elements 15 have no temperature characteristics. At least the temperature characteristic directions of R, G, and B are the same or not changed. Further, the change is preferably a change of 10 ° C. for each color, and is preferably changed from 2% to 8%. Among these, it is preferable to set it to 3% or more and 6% or less.

  Further, the temperature special compensation may be performed by a microcomputer. The temperature of the EL display panel is measured with a temperature sensor, and is changed by a microcomputer (not shown) or the like according to the measured temperature. Further, the reference current or the like may be automatically switched by microcomputer control or the like at the time of switching, or control may be performed so that a specific menu display can be displayed. Moreover, it can comprise so that it can switch using a mouse | mouth etc. FIG. Alternatively, the display screen of the EL display device may be a touch panel, and the display may be switched by displaying a menu and pressing a specific location.

  In the present invention, the source driver is formed of a semiconductor silicon chip, and is connected to the terminal of the source signal line 18 of the substrate 71 by glass-on-chip (COG) technology. For the wiring of the signal line such as the source signal line 18, a metal wiring such as chrome, aluminum, or silver is used. This is because a low resistance wiring can be obtained with a narrow wiring width. When the pixel is of a reflective type, the wiring is made of a material that constitutes the reflective film of the pixel, and is preferably formed simultaneously with the reflective film. This is because the process can be simplified.

  The present invention is not limited to the COG technology, and the source driver IC 14 or the like described above may be mounted on the chip-on-film (COF) technology and connected to the signal line of the display panel. Further, the drive IC may have a three-chip configuration by separately producing a power supply IC 82.

  A TCF tape may be used. A film for a TCF tape can be thermocompression bonded with a polyimide film and a copper (Cu) foil without using an adhesive. In addition to the film for TCP tape that attaches Cu to a polyimide film without using an adhesive, there is a method in which a melted polyimide is layered on a Cu foil and cast, and a metal film formed by sputtering on the polyimide film. There is a method of attaching Cu by plating or vapor deposition. Any of these methods may be used, but a method using a TCP tape for attaching Cu to a polyimide film without using an adhesive is most preferable. A lead pitch of 30 μm or less is supported by a Cu beam laminate without using an adhesive. Of Cu beam laminates that do not use an adhesive, the method of forming the Cu layer by plating or vapor deposition is suitable for thinning the Cu layer, and is therefore advantageous in reducing the lead pitch.

  On the other hand, the gate driver circuit 12 is formed by low-temperature polysilicon technology. That is, it is formed by the same process as the pixel transistor. This is because the internal structure is easier and the operating frequency is lower than that of the source driver circuit 14. Therefore, it can be formed easily even if it is formed by a low temperature polysilicon technique, and a narrow frame can be realized. Of course, it goes without saying that the gate driver 12 may be formed of a silicon chip and mounted on the substrate 71 using COG technology or the like. In addition, switching elements such as pixel transistors, gate drivers, and the like may be formed by high-temperature polysilicon technology or organic materials (organic transistors).

  The gate driver 12 includes a shift register circuit 61a for the gate signal line 17a and a shift register circuit 61b for the gate signal line 17b. Each shift register circuit 61 is controlled by positive-phase and negative-phase clock signals (CLKxP, CLKxN) and a start pulse (STx). In addition, it is preferable to add an enable (ENABL) signal for controlling the output and non-output of the gate signal line and an up / down (UPDWM) signal for reversing the shift direction up and down. In addition, it is preferable to provide an output terminal for confirming that the start pulse is shifted to the shift register and output. Note that the shift timing of the shift register is controlled by a control signal from the control IC 81. A level shift circuit for shifting the level of external data is incorporated. It also has a built-in inspection circuit.

  Since the buffer capacity of the shift register circuit 61 is small, the gate signal line 17 cannot be driven directly. For this reason, at least two or more inverter circuits 62 are formed between the output of the shift register circuit 61 and the output gate 63 that drives the gate signal line 17.

  The same applies to the case where the source driver 14 is directly formed on the substrate 71 by a polysilicon technique such as low-temperature polysilicon. Between the gate of an analog switch such as a transfer gate that drives the source signal line 18 and the shift register of the source driver circuit 14. A plurality of inverter circuits are formed. The following items (the output of the shift register and the output stage that drives the signal line (the matter related to the inverter circuit arranged between the output stage such as the output gate or the transfer gate)) are common to the source drive and the gate drive circuit. is there.

  For example, FIG. 6 shows that the output of the source driver 14 is directly connected to the source signal line 18, but actually, the output of the shift register of the source driver is connected to a multi-stage inverter circuit, The output is connected to the gate of an analog switch such as a transfer gate.

  The inverter circuit 62 includes a P-channel MOS transistor and an N-channel MOS transistor. As described above, the inverter circuit 62 is connected in multiple stages to the output terminal of the shift register circuit 61 of the gate driver circuit 12, and its final output is connected to the output gate circuit 63. Note that the inverter circuit 62 may be composed of only the P channel. However, in this case, it may be configured as a simple gate circuit instead of an inverter.

  FIG. 8 is a configuration diagram of signal and voltage supply of the display device of the present invention or a configuration diagram of the display device. Signals (power supply wiring, data wiring, etc.) supplied from the control and roll IC 81 to the source driver circuit 14 a are supplied via the flexible substrate 84.

In FIG. 8, the control signal of the gate driver 12 is generated by the control IC, and after the level shift is once performed by the source driver 14, it is applied to the gate driver 12. Since the drive voltage of the source driver 14 is 4 to 8 (V), the 3.3 (V) amplitude control signal output from the control IC 81 can be converted to 5 (V) amplitude that the gate driver 12 can receive. it can.

  The source driver 14 preferably has an image memory. The image data in the image memory may be stored after the error diffusion process or the dither process. By performing error diffusion processing, dither processing, etc., 260,000 color display data can be converted into 4096 colors and the like, and the capacity of the image memory can be reduced. Error diffusion processing and the like can be performed by the error diffusion controller 81. Further, after the dither process, an error diffusion process may be further performed. The above items also apply to the inverse error diffusion process.

  8 is described as a source driver in FIG. 8 and the like, but not only a driver, but also a power supply circuit, a buffer circuit (including a circuit such as a shift register), a data conversion circuit, a latch circuit, a command decoder, a shift circuit, an address A conversion circuit, an image memory, or the like may be incorporated. Needless to say, the three-side free configuration or configuration described in FIG. 9 or the like, the driving method, or the like can be applied to the configuration described in FIG. 8 or the like.

  When the display panel is used in an information display device such as a mobile phone, the source driver IC (circuit) 14 and the gate driver Ic (circuit) 12 may be mounted (formed) on one side of the display panel as shown in FIG. A form in which the driver IC (circuit) is mounted (formed) on one side is called a three-side free configuration (structure). Conventionally, the gate driver IC 12 is mounted on the X side of the display area, and the Y side The source driver IC 14 was mounted on the device). This is because it is easy to design the center line of the screen 50 to be the center of the display device, and it is easy to mount the driver IC. Note that the gate driver circuit may be fabricated with a three-side free configuration using high-temperature polysilicon or low-temperature polysilicon technology (that is, at least one of the source driver circuit 14 and the gate driver circuit 12 in FIG. 9 is polysilicon). Directly formed on the substrate 71 by technology).

  The three-side free configuration is not only a configuration in which an IC is directly stacked or formed on the substrate 71, but also a film (TCP, TAB technology, etc.) on which a source driver IC (circuit) 14, a gate driver IC (circuit) 12, etc. are attached. ) Is attached to one side (or almost one side) of the substrate 71. In other words, this means a configuration, arrangement, or all similar to that where no IC is mounted or attached to two sides.

  When the gate driver circuit 12 is arranged beside the source driver circuit 14 as shown in FIG. 9, the gate signal line 17 needs to be formed along the side C and to the screen display region 50.

  In FIG. 9 and the like, a portion indicated by a thick solid line indicates a portion where the gate signal lines 17 are formed in parallel. Therefore, the gate signal lines 17 corresponding to the number of scanning signal lines are formed in parallel in the portion b (lower screen), and one gate signal line 17 is formed in the portion a (upper screen).

  The pitch of the gate signal lines 17 formed on the C side is 5 μm or more and 12 μm or less. If it is less than 5 μm, noise will be applied to the adjacent gate signal line due to the influence of parasitic capacitance. According to the experiment, the influence of the parasitic capacitance is remarkably generated at 7 μm or less. Furthermore, if it is less than 5 μm, image noise such as a beat is generated violently on the display screen. In particular, noise generation differs between the left and right sides of the screen, and it is difficult to reduce image noise such as a beat. On the other hand, if the reduction exceeds 12 μm, the frame width D of the display panel becomes too large to be practical.

In order to reduce the image noise described above, a grant pattern (a conductive pattern whose voltage is fixed to a constant voltage or set to a stable potential as a whole) is disposed in the lower layer or upper layer of the portion where the gate signal line 17 is formed. Can be reduced. Further, a separately provided shield plate (shield foil (conductive pattern fixed to a constant voltage or set to a stable potential as a whole)) may be disposed on the gate signal line 17.

  Although the gate signal line 17 on the C side in FIG. 9 may be formed of an ITO electrode, it is preferably formed by laminating ITO and a metal thin film in order to reduce resistance. Moreover, it is preferable to form with a metal film. When laminating with ITO, a titanium film is formed on ITO, and an aluminum or aluminum / molybdenum alloy thin film is formed thereon. Alternatively, a chromium film is formed on ITO. In the case of a metal film, it is formed of an aluminum thin film or a chromium thin film. The above matters are the same in other embodiments of the present invention.

  In FIG. 9 and the like, the gate signal lines 17 and the like are arranged on one side of the display area. However, the present invention is not limited to this and may be arranged on both sides. For example, the gate signal line 17a may be disposed (formed) on the right side of the display area 50, and the gate signal line 17b may be disposed (formed) on the left side of the display area 50. The above matters are the same in other embodiments.

  Further, the source driver IC 14 and the gate driver IC 12 may be integrated into one chip. If one chip is used, only one IC chip needs to be mounted on the display panel. Therefore, the mounting cost can be reduced. Various voltages used in the one-chip driver IC can be generated simultaneously.

  The source driver IC 14 and the gate driver IC 12 are made of a semiconductor wafer such as silicon and mounted on the display panel. However, the present invention is not limited to this, and the display panel is formed by low-temperature polysilicon technology, high-temperature polysilicon technology, or amorphous silicon technology. Needless to say, it may be formed directly on 82.

  In the configuration illustrated in FIG. 1 and the like, the EL element 15 is connected to the Vdd potential via the transistor 11a. However, there is a problem that the driving voltage of the organic EL constituting each color is different. For example, when a current of 0.01 (A) per unit square centimeter is passed, the terminal voltage of the EL element is 5 (V) in blue (B), but 9 (V in green (G) and red (R). ). That is, the terminal voltage differs between B, G, and R. Therefore, the source-drain voltage (SD voltage) of the held transistor 11a is different between B, G, and R. Therefore, the off-leak current between the source and drain voltages (SD voltage) of the transistors is different for each color. When off-leakage current is generated and the off-leakage characteristics are different for each color, a complicated display state in which flicker is generated in a state where the color balance is shifted and the gamma characteristic is shifted in correlation with the emission color.

  In order to cope with this problem, at least one of the R, G, and B colors is configured such that the potential of one cathode electrode is different from the potential of the cathode electrodes of the other colors. Alternatively, one of the R, G, and B colors is configured such that the potential of one Vdd is different from the potential of the other colors Vdd.

  Needless to say, the terminal voltages of the R, G, and B EL elements 15 are preferably matched as much as possible. The material or structure must be selected so that the terminal voltage of the R, G, and B EL elements is 10 (V) or less at least when the white peak luminance is displayed and the color temperature is in the range of 6000 K to 9000 K. There is. Further, among R, G, and B, the difference between the maximum terminal voltage and the minimum terminal voltage of the EL element needs to be within 2.5 (V). More preferably, it must be 1.5 (V) or less. In the above embodiment, the color is RGB, but the present invention is not limited to this. This will be explained later.

  In addition, it is necessary to correct color unevenness. This occurs due to variations in film thickness and characteristics because the EL materials for each color are applied separately. In order to correct this, white raster display is performed at a luminance of 30% or 70%, and the in-plane distribution of each color in the display area 50 is measured. The in-plane distribution is measured at least one point per 30 pixels. The measurement data is stored in a table made of memory, and the stored image is used to correct the input image data and display it on the display screen 50.

  The pixels are R, G, and B primary colors. However, the present invention is not limited to this, and may be cyan, yellow, and magenta. Also, two colors of B and yellow may be used. Of course, it may be a single color. Also, six colors of R, G, B, cyan, yellow, and magenta may be used. Five colors of R, G, B, cyan, and magenta may be used. These are natural colors, and the color reproduction range is expanded to achieve a good display. In addition, four colors of R, G, B, and white may be used. Seven colors of R, G, B, cyan, yellow, magenta, black, and white may be used. Alternatively, white light emitting pixels may be formed (produced) in the entire display area 50, and three primary colors may be displayed using a color filter such as RGB. . In this case, a light emitting material of each color may be stacked on the EL layer. Further, one pixel may be painted separately as B and yellow. As described above, the EL display device of the present invention is not limited to one that performs color display with the three primary colors RGB.

  There are mainly three methods for colorizing an organic EL display panel, and one of them is a color conversion method. It is only necessary to form a blue-only single layer as the light emitting layer, and the remaining green and red colors necessary for full color are generated from blue light by color conversion. Therefore, there is an advantage that it is not necessary to separately coat each layer of RGB, and it is not necessary to prepare organic EL materials of each color of RGB. The color conversion method does not cause a decrease in yield unlike the color separation method. The EL display panel of the present invention can be applied to any of these methods.

  In addition to the three primary colors, white light emitting pixels may be formed. White light-emitting pixels can be realized by forming (forming or configuring) by stacking R, G, and B light-emitting structures. One set of pixels includes three primary colors of RGB and a pixel 16W that emits white light. By forming a pixel emitting white light, white peak luminance can be easily expressed. Accordingly, it is possible to realize a bright image display.

  Even in the case where one set of pixels is used for three primary colors such as RGB, it is preferable that the areas of the pixel electrodes of the respective colors are different as shown in FIG. Of course, if the luminous efficiency of each color is well balanced and the color purity is well balanced, the same area may be used. However, if the balance of one or more colors is bad, it is preferable to adjust the pixel electrode (light emitting area). The electrode area of each color may be determined based on the current density. That is, when the white balance is adjusted in the color temperature range of 6000 K (Kelvin) to 9000 K, the difference in current density of each color is within ± 30%. More preferably, it is within ± 15%. For example, if the current density is 100 A / square meter, the three primary colors are all set to 70 A / square meter or more and 130 A / square meter or less. More preferably, the three primary colors are all set to 85 A / square meter or more and 115 A / square meter or less.

  In addition, it is preferable to arrange the three primary colors to be different in adjacent pixel rows. For example, if the even-numbered row has an arrangement of R, G, B from the left, the odd-numbered row has an arrangement of B, G, R. By arranging in this way, the resolution in the oblique direction of the image is improved even with a small number of pixels. Further, the first row from the left is arranged R, G, B, R, G, B, the second row is arranged G, B, R, G, B, R, the third row is B, R, The pixel arrangement may be different in three or more pixel rows so as to have the arrangement of G, B, R, and G. Of course, it goes without saying that the pixel arrangement of R, G, B or the color arrangement of cyan, yellow, magenta, etc. may be a delta arrangement (an arrangement shifted by 1/2 pixel).

  The organic EL 15 is a self light emitting element. When light emitted by this light emission enters a transistor as a switching element, a photoconductor phenomenon (photoconversion) occurs. “Photocon” refers to a phenomenon in which leakage (off leak) increases when a switching element such as a transistor is turned off by photoexcitation.

  In order to cope with this problem, in the present invention, a light shielding film under the gate driver 12 (in some cases, the source driver 14) and under the pixel transistor 11 is formed. The light-shielding film is formed of a metal thin film such as chromium, and the film thickness is set to 50 nm to 150 nm. If the film thickness is thin, the light shielding effect is poor, and if it is thick, irregularities are generated, making it difficult to pattern the upper transistor 11A1.

  A smoothing film made of an inorganic material of 20 to 100 nm is formed on the light shielding film. One electrode of the storage capacitor 19 may be formed using this light shielding film layer. In this case, it is preferable to make the smooth film as thin as possible to increase the capacitance value of the storage capacitor. Alternatively, the light shielding film may be formed of aluminum, a silicon oxide film may be formed on the surface of the light shielding film using an anodic oxidation technique, and the silicon oxide film may be used as a dielectric film of the storage capacitor 19. A pixel electrode having a high aperture (HA) structure is formed on the smoothing film.

  The driver circuit 12 and the like should suppress light from not only the back surface but also the front surface. This is because malfunction occurs due to the influence of the photocon. Therefore, in the present invention, when the cathode electrode is a metal film, the cathode electrode is also formed on the surface of the driver 12 and the like, and this electrode is used as a light shielding film.

  However, when a cathode electrode is formed on the driver 12, there is a possibility that a malfunction of the driver due to an electric field from the cathode electrode or an electrical contact between the cathode electrode and the driver circuit may occur. In order to cope with this problem, in the present invention, an organic EL film of at least one layer, preferably a plurality of layers, is formed simultaneously with the formation of the organic EL film on the pixel electrode on the driver circuit 12 or the like.

  Since the organic EL film is basically an insulator, the cathode and the driver are isolated by forming the organic EL film on the driver. Therefore, the above-described problem can be solved.

  When the terminals of one or more transistors 11 of the pixel or the transistor 11 and the signal line are short-circuited, the EL element 15 may be a bright spot that is always lit. This bright spot is visually conspicuous and needs to be turned into black (not lit). For the bright spot, the corresponding pixel 16 is detected, and the capacitor 19 is irradiated with laser light to short-circuit the terminals of the capacitor. Therefore, since the capacitor 19 cannot hold the electric charge, the transistor 11a can be prevented from flowing current.

  It corresponds to a position where laser light is irradiated. It is desirable to remove the cathode film. This is to prevent the terminal electrode of the capacitor 19 and the cathode film from being short-circuited by laser irradiation.

The defect of the transistor 11 of the pixel 16 also affects the driver IC 14 and the like. For example, in FIG. 56, when a source-drain (SD) short 562 occurs in the driving transistor 11a, the Vdd voltage of the panel is applied to the source driver IC. Therefore, the power supply voltage of the source driver IC 14 is preferably the same as or higher than the power supply voltage Vdd of the panel. It should be noted that the reference current used in the source driver IC is preferably configured so that it can be adjusted by the electronic volume 561.

  When the SD short 562 occurs in the transistor 11a, an excessive current flows in the EL element 15. That is, the EL element 15 is always lit (bright spot). Bright spots are easily noticeable as defects. For example, in FIG. 56, when the source-drain (SD) short of the transistor 11a occurs, a current always flows from the Vdd voltage to the EL element 15 regardless of the gate (G) terminal potential of the transistor 11a ( When the transistor 11d is on). Therefore, it becomes a bright spot.

  On the other hand, when the SD short 562 occurs in the transistor 11a, the Vdd voltage is applied to the source signal line 18 and the Vdd voltage is applied to the source driver 14 when the transistor 11c is in the on state. If the power supply voltage of the source driver 14 is equal to or lower than Vdd, the source driver 14 may be destroyed beyond the breakdown voltage. Therefore, it is preferable that the power supply voltage of the source driver 14 be equal to or higher than the Vdd voltage (the higher voltage of the panel).

  The SD short 562 and the like of the transistor 11a are not limited to point defects, and may cause destruction of the source driver circuit of the panel. Further, since the bright spot is conspicuous, the panel becomes defective. Therefore, it is necessary to cut the wiring connecting the transistor 11a and the EL element 15 in FIG. 56 to make the bright spot a black spot defect. For this cutting, it is preferable to use an optical means such as a laser beam. The optical means is not limited to a laser, but may be a system in which light generated from a xenon lamp or the like is collected and the wiring is cut with the collected light. Moreover, you may employ | adopt the method of cut | disconnecting to a cutting location by a sandblasting method (a fine particle is sprayed and cut | disconnected). That is, any cutting means may be used. However, a method using an optical means such as a laser is preferable because it can be processed in a non-contact manner at the cut portion.

  In addition, it is preferable to employ | adopt the thing of the pulse oscillation using a Q switch rather than a continuous type laser beam. In addition, a plurality of laser pulses are irradiated to the cutting portion. The laser pulse interval is preferably 0.1 msec (msec, msec) or more and 100 msec (msec, msec) or less. In particular, it is preferably 1 msec or more and 10 msec or less. This is because, at this interval, the melted state of the processed portion by the previously irradiated laser beam continues, and good cutting or processing can be performed. The wavelength of the laser beam is preferably around 1 μm. A YAG laser is exemplified as this wavelength laser. Of course, other lasers may be used. For example, a carbon dioxide laser, an excimer laser, a neon helium laser, etc. are illustrated.

  In the above embodiment, the wiring is cut. However, the present invention is not limited to this in order to display black. For example, as can be seen in FIG. 1, the power supply Vdd of the transistor 11a may be modified so that it is always applied to the gate (G) terminal of the transistor 11a. For example, if the two electrodes of the capacitor 19 are short-circuited, the Vdd voltage is applied to the gate (G) terminal of the transistor 11a. Therefore, the transistor 11a is completely turned off, and current can be prevented from flowing through the EL element 15. In this case, since the capacitor electrode can be short-circuited by irradiating the capacitor 19 with laser light, it can be easily realized. In practice, since the Vdd wiring is disposed below the pixel electrode, the display state of the pixel can be controlled (corrected) by irradiating the Vdd wiring and the pixel electrode with laser light.

In addition, it can be realized by opening the SD (channel) of the transistor 11a. In brief, the transistor 11a is irradiated with laser light to open the channel of the transistor 11a. Similarly, the channel of the transistor 11d may be opened. Of course, even if the channel of the transistor 11b is opened, the corresponding pixel 16 is not selected, so that black display is obtained.

  In order to display the pixel 16 in black, the EL element 15 may be deteriorated. For example, the EL layer 15 is irradiated with laser light so that the EL layer 15 is physically or chemically deteriorated so as not to emit light (always black display). The EL layer 15 can be heated by laser light irradiation and easily deteriorated. Further, if an excimer laser is used, the chemical change of the EL film 15 can be easily performed.

  In the above embodiment, the pixel configuration illustrated in FIG. 1 is illustrated, but the present invention is not limited to this. Needless to say, opening or shorting wirings or electrodes using laser light can be applied to other current-driven pixel configurations such as a current mirror or the voltage-driven pixel configurations shown in FIGS. Yes.

  When the cathode (or anode) electrode is a transparent electrode, a light extraction structure in which the pixel electrode is a reflection type and the common electrode is a transparent electrode (ITO, IZO, etc.) (light is extracted from the glass substrate 71 side, In the case of taking out light from the EL film deposition surface, the sheet resistance value of the transparent electrode becomes a problem. The transparent electrode has a high resistance, but it is necessary to pass a current at a high current density to the cathode of the organic EL. Therefore, when the cathode electrode is formed of a single layer of ITO film, it becomes heated due to heat generation, or extreme brightness gradient occurs on the display screen.

In order to cope with this problem, a low resistance wiring made of a metal thin film may be formed on the surface of the cathode electrode. The low resistance wiring has the same configuration as the black matrix (BM) of the liquid crystal display panel (film thickness of 50 nm to 200 nm with chromium or aluminum material) and the same position (between the pixel electrodes, on the driver 12, etc.). . However, the function of the organic EL is completely different because it is not necessary to form a BM. The resistance-reducing wiring is not limited to the surface of the transparent electrode, and may be formed on the back surface (surface in contact with the organic EL film). Further, as the metal film formed in a BM shape, an alloy such as Mg · Ag, Mg · Li, Al·Li, or a laminated structure such as aluminum, magnesium, indium, copper, or an alloy of each may be used. In order to prevent corrosion or the like, an ITO or IZO film is further laminated on the BM, and an inorganic thin film such as SiN _x or SiO ₂ or an organic thin film such as polyimide is formed.

In the case where light is extracted from the vapor deposition surface of the EL film (upward extraction), it is preferable to form a Mg—Al film on the organic EL film 15 and to form an ITO or IZO film thereon. Further, it is preferable to form an Mg—Al film on the organic EL film 15 and form a black matrix (a black matrix such as a liquid crystal display panel) on the Mg—Al film. This black matrix is formed of chromium, Al, Ag, Au, Cu or the like, and a protective film made of an inorganic insulating film such as SiO ₂ or SiN _x or an organic insulating film such as polyester or acrylic may be formed thereon. preferable. Further, an antireflection film (AIR coat) is formed on the protective film.

The AIR coat has a three-layer structure or a two-layer structure. In the case of a three-layer structure, the optical film thickness of aluminum oxide (Al ₂ O ₃ ) is nd = λ / 4, zirconium (ZrO ₂ ) is nd1 = λ / 2, and magnesium fluoride (MgF ₂ ) is nd1 = λ / Four layers are formed. Usually, a thin film is formed with λ as 520 nm or a value in the vicinity thereof.

In the case of a two-layer structure, silicon monoxide (SiO) has an optical film thickness of nd1 = λ / 4 and magnesium fluoride (MgSO ₂ ), nd1 = λ / 4, or yttrium oxide (Y ₂ O ₃ ) and magnesium fluoride. (MgF ₂ ) is formed by stacking nd1 = λ / 4.

In the case of one layer, it is formed by stacking nd1 = λ / 2 of magnesium fluoride (MgF ₂ ).

  Even in the case of taking out the bottom, it is effective to increase the transmittance of the metal film of the cathode electrode 106. This is because even if the display image is viewed from the substrate 71 side, the reflection of the metal film is high and the reflection is reduced. If the reflection is reduced, the circularly polarizing plate (phase plate) 108 becomes unnecessary. Therefore, the light extraction efficiency may be improved compared to the upper extraction. The transmittance of the metal film is preferably 60% or more and 90% or less. In particular, it is preferably 70% or more and 90% or less. When it is 60% or less, the sheet resistance value of the cathode electrode becomes low. However, the reflection becomes large. Conversely, if it is 90% or more, the sheet resistance value of the cathode electrode becomes high. Therefore, the luminance gradient of the display image is increased.

In order to increase the transmittance of the metal film, a thin Al film is formed. The thickness is 20 nm or more and 100 nm or less. An ITO or IZO film is preferably formed thereon. Moreover, it is preferable to form a black matrix on the Al film. This black matrix is formed of chromium, Al, Ag, Au, Cu or the like, and a protective film made of an inorganic insulating film such as SiO ₂ or SiN _x or an organic insulating film such as polyester or acrylic may be formed thereon. preferable. Furthermore, it is preferable to form an antireflection film (AIR coat) on this protective film.

  Note that the EL film 15 or the pixel electrode 105 is not limited to a circular arc shape, and may be a triangular pyramid shape, a conical shape, a sine curve shape, or a combination thereof. Further, a configuration in which a fine arc, a triangular pyramid shape, a conical shape, or a sine curve shape is formed in one pixel, a combination thereof, or random unevenness may be formed.

  The semiconductor film constituting the transistor 11 of the pixel 16 is generally formed by laser annealing in the low temperature polysilicon technology. Variations in the laser annealing conditions result in variations in transistor 11 characteristics. However, if the characteristics of the transistors 11 in one pixel 16 match, the current programming method shown in FIG. 1 can be driven so that a predetermined current flows through the EL element 15. This is an advantage not found in voltage programming. An excimer laser is preferably used as the laser.

  In the present invention, the formation of the semiconductor film is not limited to the laser annealing method, but may be a thermal annealing method or a method by solid phase (CGS) growth. In addition, the present invention is not limited to the low temperature polysilicon technology, and it goes without saying that a high temperature polysilicon technology or an amorphous silicon technology may be used.

  To deal with this problem, in the present invention, as shown in FIG. 7, a laser irradiation spot (laser irradiation range) 72 at the time of annealing is irradiated in parallel to the source signal line 18. Further, the laser irradiation spot 72 is moved so as to coincide with one pixel column. Of course, the present invention is not limited to one pixel column, and for example, the RGB of FIG. 72 may be irradiated with a unit of one pixel 16 (in this case, it is a three pixel column). In addition, a plurality of pixels may be irradiated simultaneously. It goes without saying that the movement of the laser irradiation range may overlap (usually, the irradiation range of the moving laser light is usually overlapped).

  The pixels are made of three pixels of RGB and have a square shape. Accordingly, each of the R, G, and B pixels has a vertically long pixel shape. Therefore, by annealing the laser irradiation spot 72 in a vertically long shape, the characteristic variation of the transistor 11 can be prevented from occurring within one pixel. Further, the characteristics (mobility, Vt, S value, etc.) of the transistor 11 connected to one source signal line 18 can be made uniform (that is, the characteristics are different from those of the transistor 11 of the adjacent source signal line 18). However, the characteristics of the transistor 11 connected to one source signal line can be made substantially equal).

  In general, the length of the laser irradiation spot 72 is a fixed value such as 10 inches. Since this laser irradiation spot 72 is moved, it is necessary to arrange the panel so that one laser irradiation spot 72 can be moved within a movable range (that is, the laser irradiation spot 72 at the center of the display area 50 of the panel). So that they do n’t overlap.)

  In the configuration of FIG. 7, three panels are formed vertically within the range of the length of the laser irradiation spot 72. The annealing apparatus that irradiates the laser irradiation spot 72 recognizes the positioning markers 73a and 73b of the glass substrate 74 (automatic positioning by pattern recognition) and moves the laser irradiation spot 72. The positioning marker 73 is recognized by a pattern recognition device. An annealing apparatus (not shown) recognizes the positioning marker 73 and extracts the position of the pixel column (makes the laser irradiation range 72 parallel to the source signal line 18). The laser irradiation spot 72 is irradiated so as to overlap the pixel column position, and annealing is sequentially performed.

  The laser annealing method described in FIG. 7 (method of irradiating a line-shaped laser spot in parallel with the source signal line 18) is preferably employed particularly in the current programming method of the organic EL display panel. This is because the characteristics of the transistor 11 match in the direction parallel to the source signal line (the characteristics of the pixel transistors adjacent in the vertical direction are approximate). Therefore, there is little change in the voltage level of the source signal line at the time of current driving, and current writing shortage hardly occurs.

  For example, in the case of white raster display, the current flowing through the transistor 11a of each adjacent pixel is almost the same, so the change in the current amplitude output from the source driver IC 14 is small. If the characteristics of the transistor 11a in FIG. 1 are the same and the current values to be programmed in each pixel are the same in the pixel columns, the potential of the source signal line 18 at the time of current programming is constant. Therefore, the potential fluctuation of the source signal line 18 does not occur. If the characteristics of the transistors 11a connected to one source signal line 18 are almost the same, the potential fluctuation of the source signal line 18 is small. This is the same for other current programming pixel configurations such as FIG. 38 (that is, it is preferable to apply the manufacturing method of FIG. 7). Of course, the present invention is also preferably applied to voltage-programmed pixel configurations such as those shown in FIGS. This is because the TFT characteristics of the pixels 16 along the source signal line 18 become uniform, and the video signal can be easily controlled.

  In addition, uniform image display (since display unevenness due to variations in transistor characteristics is unlikely to occur) can be realized by a method of simultaneously writing a plurality of pixel rows described with reference to FIGS. In FIG. 27 and the like, a plurality of pixel rows are selected at the same time. Therefore, if the transistors in adjacent pixel rows are uniform, the transistor circuit unevenness in the vertical direction can be absorbed by the driver circuit.

  In FIG. 7, the source driver circuit 14 is illustrated as having an IC chip mounted thereon; however, the present invention is not limited to this, and the source driver circuit 14 may be formed in the same process as the pixel 16. Needless to say, the source driver circuit 14 may be formed using low-temperature polysilicon technology, high-temperature polysilicon technology, or CGS technology.

  In order to reduce the characteristic variation of the driving TFT 11a of the pixel 16, it is effective to form a plurality of driving TFTs 11a in the pixel 16 as shown in FIG. In the following embodiments, the pixel configuration described with reference to FIG. 1 will be described as an example. A plurality of driving transistors (transistors that allow current to flow through the EL element 15 or draw current from the EL element 15) are provided in the pixel 16. The technical idea of forming is not limited to the pixel configuration in FIG. For example, the present invention can also be applied to other current programming pixel configurations such as FIG. Needless to say, the present invention can also be applied to voltage-programmed pixel configurations such as those shown in FIGS.

  In FIG. 154, two driving transistors (11 a 1 and 11 a 2) are formed in one pixel 16. As shown in FIG. 153, the driving transistor 11a is above the pixel 16 (disposing the driving transistor 11a1) and below (disposing the driving transistor 11a2). Other configurations are the same as those in FIG.

  As shown in FIG. 153, by disposing a plurality of driving transistors 11a in the pixel 16, the characteristics of the driving transistors 11a of the pixel 16 are averaged, and the characteristic variation is greatly reduced as a whole. Can be made.

  Hereinafter, a driving method of the pixel configuration in FIG. 1 will be described. As shown in FIG. 1, the gate signal line 17a becomes conductive during the row selection period (here, since the transistor 11 of FIG. 1 is a p-channel transistor, it becomes conductive at a low level), and the gate signal line 17b remains in the non-selection period. Sometimes conductive.

  The source signal line 18 has a parasitic capacitance (not shown). The parasitic capacitance is generated by the capacitance of the cross portion between the source signal line 18 and the gate signal line 17, the channel capacitance of the transistors 11b and 11c, and the like.

  The time t required to change the current value of the source signal line 18 is t = C · V / I, where C is the size of the stray capacitance, V is the voltage of the source signal line, and I is the current flowing through the source signal line. The fact that the value can be increased 10 times can shorten the time required for the current value change to nearly 1/10. Or, it shows that the current value can be changed to a predetermined value even when the source capacitance is increased 10 times. Therefore, it is effective to increase the current value in order to write a predetermined current value within a short horizontal scanning period.

  When the input current is increased 10 times, the output current is also increased 10 times, and the luminance of EL is increased 10 times. Therefore, in order to obtain a predetermined luminance, the conduction period of the transistor 17d in FIG. By setting the value to 1/10, a predetermined luminance is displayed.

  That is, it is necessary to output a relatively large current from the source driver 14 in order to sufficiently charge and discharge the parasitic capacitance of the source signal line 18 and to program a predetermined current value in the transistor 11 a of the pixel 16. However, when such a large current flows through the source signal line 18, this current value is programmed in the pixel, and a large current flows through the EL element 15 with respect to a predetermined current. For example, if programming is performed with 10 times the current, naturally, 10 times the current flows through the EL element 15, and the EL element 15 emits light with 10 times the luminance. In order to obtain a predetermined light emission luminance, the time required to flow through the EL element 15 may be reduced to 1/10. By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained.

  It should be noted that although 10 times the current value is written in the pixel transistor 11a (more precisely, the terminal voltage of the capacitor 19 is set) and the on-time of the EL element 15 is reduced to 1/10, this is merely an example. In some cases, a 10 times larger current value may be written in the pixel transistor 11a, and the on-time of the EL element 15 may be reduced to 1/5. On the contrary, there may be a case where a 10 times larger current value is written in the pixel transistor 11a and the on-time of the EL element 15 is halved.

The present invention is characterized in that the pixel write current is set to a value other than a predetermined value and the current flowing through the EL element 15 is driven intermittently. In this specification, for ease of explanation, it is assumed that N times the current value is written in the transistor 11 of the pixel and the on-time of the EL element 15 is 1 / N times. However, the present invention is not limited to this, and it goes without saying that a current value of N1 times may be written to the transistor 11 of the pixel and the ON time of the EL element 15 may be 1 / N2 times (different from N1 and N2). The intermittent interval is not limited to an equal interval. For example, it may be random (as a whole, the display period or the non-display period may be a predetermined value (a constant ratio)). Also, it may be different for RGB. That is, it is only necessary to adjust (set) the R, G, B display period or the non-display period to a predetermined value (a constant ratio) so that the white balance is optimal. For ease of explanation, 1 / N is assumed to be 1F with 1F (1 field or 1 frame) as a reference. However, there is a time during which one pixel row is selected and the current value is programmed (usually, one horizontal scanning period (1H)), and an error occurs depending on the scanning state. Therefore, the above description is only a matter of convenience for ease of explanation, and is not limited to this.

  The organic (inorganic) EL display device also has a problem in that the display method is basically different from a display that displays an image as a set of line displays with an electron gun, such as a CRT. That is, in the EL display device, the current (voltage) written to the pixel is held for a period of 1F (1 field or 1 frame). For this reason, when a moving image is displayed, there is a problem that the outline of the display image is blurred.

  In the present invention, a current is passed through the EL element 15 only during the period of 1F / N, and no current is passed during the other period (1F (N-1) / N). Consider the case where this driving method is implemented and one point on the screen is observed. In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is a temporal display (intermittent display) state. When the moving image data display is viewed in this intermittent display state, the outline of the image is not blurred and a good display state can be realized. That is, a moving image display close to a CRT can be realized. Although intermittent display is realized, the main clock of the circuit is not different from the conventional one. Therefore, the power consumption of the circuit does not increase.

  In the case of a liquid crystal display panel, image data (voltage) for light modulation is held in a liquid crystal layer. Therefore, if black insertion display is to be performed, it is necessary to rewrite data applied to the liquid crystal layer. Therefore, it is necessary to increase the operation clock of the source driver IC 14 and apply the image data and the black display data to the source signal line 18 alternately. Therefore, to achieve black insertion (intermittent display such as black display), it is necessary to increase the main clock of the circuit. In addition, an image memory for performing time axis expansion is also required.

  In the pixel configuration of the EL display panel of the present invention shown in FIGS. 1, 2, 38, etc., image data is held in the capacitor 19. A current corresponding to the terminal voltage of the capacitor 19 is passed through the EL element 15. Therefore, the image data is not held in the light modulation layer like the liquid crystal display panel.

  In the present invention, the current supplied to the EL element 15 is controlled only by turning on or off the switching transistor 11d or the transistor 11e. That is, even when the current Iw flowing through the EL element 15 is turned off, the image data is held in the capacitor 19 as it is. Therefore, if the switching element 11d and the like are turned on at the next timing and a current flows through the EL element 15, the flowing current is the same as the previously flowing current value. In the present invention, it is not necessary to raise the main clock of the circuit even when trying to realize black insertion (intermittent display such as black display). Further, there is no need for an image memory because it is not necessary to perform time axis expansion. In addition, the organic EL element 15 has a short response time from application of current to light emission and a high-speed response. Therefore, it is suitable for moving image display, and further, intermittent display can solve the problem of moving image display, which is a problem of conventional data retention type display panels (liquid crystal display panel, EL display panel, etc.).

  Further, when the source capacity is increased in a large display device, the source current may be increased 10 times or more. In general, when the source current value is increased N times, the conduction period of the gate signal line 17b (transistor 11d) may be set to 1 F / N. Accordingly, the present invention can be applied to a television, a display device for a monitor, and the like.

  Hereinafter, the driving method of the present invention will be described in more detail with reference to the drawings. The parasitic capacitance of the source signal line 18 is generated by a coupling capacitance between adjacent source signal lines 18, a buffer output capacitance of the source drive IC (circuit) 14, a cross capacitance between the gate signal line 17 and the source signal line 18, and the like. This parasitic capacitance is usually 10 pF or more. In the case of voltage driving, a voltage is applied from the driver IC 14 to the source signal line 18 with a low impedance, so that there is no problem in driving even if the parasitic capacitance is somewhat large.

  However, current driving requires that the pixel capacitor 19 be programmed with a minute current of 5 nA or less, particularly for black level image display. Accordingly, when the parasitic capacitance is generated with a magnitude greater than or equal to a predetermined value, the time for programming to one pixel row (usually within 1H, however, it is not limited to within 1H because two pixel rows may be written simultaneously. ) Can not charge and discharge the parasitic capacitance. If charging / discharging is not possible in the 1H period, writing into the pixel is insufficient and the resolution is not high.

  In the case of the pixel configuration of FIG. 1, as shown in FIG. 3A, the program current Iw flows through the source signal line 18 during current programming. The voltage is set (programmed) in the capacitor 19 so that the current Iw flows through the transistor 11a and the current flowing through Iw is maintained. At this time, the transistor 11d is in an open state (off state).

  Next, during a period in which a current flows through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d is operated as shown in FIG. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, an on voltage (Vgl) is applied to the gate signal line 17b, and the transistor 11d is turned on.

    Assuming that the current I1 is N times the current (predetermined value) that flows originally, the current flowing through the EL element 15 in FIG. 3B is also Iw. Therefore, the EL element 15 emits light with a luminance 10 times the predetermined value. That is, as shown in FIG. 12, the higher the magnification N, the higher the display brightness B of the display panel. Therefore, the magnification and the luminance are in a proportional relationship. Conversely, by driving at 1 / N, the luminance and the magnification have an inversely proportional relationship.

  Therefore, if the transistor 11d is turned on only for a period of 1 / N of the time for which the transistor 11d is originally turned on (about 1F) and is turned off for the other periods (N-1) / N, the average brightness of the entire 1F becomes a predetermined brightness. Become. This display state approximates that the CRT is scanning the screen with an electron gun. The difference is that the range in which the image is displayed is 1 / N of the entire screen (the whole screen is 1) is lit (in CRT, the lit range is one pixel row (strictly Is one pixel).

  In the present invention, the 1F / N image display area 53 moves from the top to the bottom of the screen 50 as shown in FIG. In the present invention, current flows through the EL element 15 only during the period of 1F / N, and no current flows during the other period (1F · (N−1) / N). Therefore, each pixel is intermittently displayed. However, since the image is retained by the afterimage to the human eye, the entire screen appears to be displayed uniformly.

As shown in FIG. 13, the writing pixel row 51a is a non-lighting display 52a. However, this is the case of the pixel configuration shown in FIGS. In the pixel configuration of the current mirror illustrated in FIG. 38 and the like, the writing pixel row 51a may be lit. However, in this specification, for ease of explanation, the pixel configuration in FIG. A driving method in which programming is performed with a current larger than the predetermined driving current Iw, such as FIGS. 13 and 16, and intermittent driving is referred to as N-fold pulse driving.

  In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is a temporal display (intermittent display) state. In a liquid crystal display panel (an EL display panel other than the present invention), since data is held in pixels for a period of 1F, even if image data changes in the case of moving image display, the change cannot be followed. The video was blurred (outline blur in the image). However, since the image is intermittently displayed in the present invention, the outline of the image is not blurred and a good display state can be realized. That is, a moving image display close to a CRT can be realized.

  This timing chart is shown in FIG. In the present invention and the like, the pixel configuration when there is no particular notice is assumed to be FIG. As can be seen from FIG. 14, when the on-voltage (Vgl) is applied to the gate signal line 17a in each selected pixel row (the selection period is 1H) (see FIG. 14A). In FIG. 14, an off voltage (Vgh) is applied to the gate signal line 17b (see FIG. 14B). During this period, no current flows through the EL element 15 (non-lighting state). In an unselected pixel row, an off voltage (Vgh) is applied to the gate signal line 17a, and an on voltage (Vgl) is applied to the gate signal line 17b. Further, during this period, a current flows through the EL element 15 (lighting state). In the lighting state, the EL element 15 is lit with a predetermined N times luminance (N · B), and the lighting period is 1 F / N. Therefore, the display luminance of the display panel that averages 1F is (N · B) × (1 / N) = B (predetermined luminance).

  FIG. 15 shows an embodiment in which the operation of FIG. 14 is applied to each pixel row. A voltage waveform applied to the gate signal line 17 is shown. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level). Subscripts such as (1) and (2) indicate the selected pixel row number.

  In FIG. 15, the gate signal line 17 a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11 a of the selected pixel row toward the source driver 14. This program current is N times a predetermined value (for ease of explanation, it is assumed that N = 10. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. .) Therefore, the capacitor 19 is programmed so that 10 times the current flows through the transistor 11a. When the pixel row (1) is selected, in the pixel configuration of FIG. 1, the gate signal line 17b (1) is applied with the off voltage (Vgh), and no current flows through the EL element 15.

  After 1H, the gate signal line 17a (2) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11a in the selected pixel row toward the source driver. This program current is N times a predetermined value (in order to facilitate explanation, explanation will be made assuming that N = 10). Therefore, the capacitor 19 is programmed so that 10 times the current flows through the transistor 11a. When the pixel row (2) is selected, the gate signal line 17b (2) is applied with the off voltage (Vgh) in the pixel configuration of FIG. 1, and no current flows through the EL element 15. However, the off voltage (Vgh) is applied to the gate signal line 17a (1) of the previous pixel row (1), and the on voltage (Vgl) is applied to the gate signal line 17b (1). It has become.

After the next 1H, the gate signal line 17a (3) is selected, the off voltage (Vgh) is applied to the gate signal line 17b (3), and no current flows through the EL elements 15 in the pixel row (3). However, the off voltage (Vgh) is applied to the gate signal lines 17a (1) (2) of the previous pixel rows (1) (2), and the on voltage (Vgl) is applied to the gate signal lines 17b (1) (2). ) Is applied, and is in a lighting state.

  The above operation is displayed in synchronization with the 1H synchronization signal. However, in the driving method of FIG. 15, 10 times of current flows through the EL element 15. Therefore, the display screen 50 is displayed with about 10 times the luminance. Of course, in order to perform a predetermined luminance display in this state, it goes without saying that the program current may be set to 1/10. However, if the current is 1/10, insufficient writing occurs due to parasitic capacitance or the like. Therefore, programming at a high current and obtaining a predetermined luminance by inserting the black screen 52 is the basic gist of the present invention.

  In the driving method of the present invention, the concept is that a current higher than a predetermined current flows in the EL element 15 and the parasitic capacitance of the source signal line 18 is sufficiently charged and discharged. That is, it is not necessary to flow N times the current through the EL element 15. For example, a current path is formed in parallel with the EL element 15 (a dummy EL element is formed, a light shielding film is not formed on the EL element to emit light, etc.), and the current is shunted between the dummy EL element and the EL element 15. May be flushed. For example, when the signal current is 0.2 μA, the program current is set to 2.2 μA, and 2.2 μA is passed through the transistor 11a. Of these currents, a system is exemplified in which a signal current of 0.2 μA is passed through the EL element 15 and 2 μA is passed through a dummy EL element.

  With the configuration as described above, by increasing the current flowing through the source signal line 18 by N times, the driving transistor 11a can be programmed to flow N times as much current, and the current EL element 15 can be programmed. Can flow a current sufficiently smaller than N times. In the above method, as shown in FIG. 5, the entire display area 50 can be used as the image display area 53 without providing the non-lighting area 52.

  FIG. 13A illustrates a writing state on the display image 50. In FIG. 13A, reference numeral 51a denotes a writing pixel row. A program current is supplied from the source driver IC 14 to each source signal line 18. In FIG. 13 and the like, one pixel row is written in the 1H period. However, it is not limited to 1H at all, and may be 0.5H period or 2H period. Although the program current is written to the source signal line 18, the present invention is not limited to the current program method, and the voltage program method that is a voltage may be written to the source signal line 18.

  In FIG. 13A, when the gate signal line 17a is selected, the current flowing through the source signal line 18 is programmed into the transistor 11a. At this time, an off voltage is applied to the gate signal line 17 b and no current flows through the EL element 15. This is because, when the transistor 11d is in the ON state on the EL element 15 side, the capacitance component of the EL element 15 can be seen from the source signal line 18, and the capacitor 19 cannot be sufficiently accurately programmed due to the capacitance. It is. Therefore, taking the configuration of FIG. 1 as an example, a pixel row in which a current is written becomes a non-lighting region 52 as shown in FIG.

Now, if the current is programmed with N times (N = 10 as described above), the screen brightness will be 10 times. Therefore, a 90% range of the display area 50 may be set as the non-lighting area 52. Therefore, if the horizontal scanning lines of the image display area are 220 QCIF (S = 220), 22 lines and the display area 53 may be used, and 220-22 = 198 may be the non-display area 52. Generally speaking, if the horizontal scanning line (number of pixel rows) is S, the S / N area is set as the display area 53, and the display area 53 is caused to emit light with N times the luminance. Then, the display area 53 is scanned in the vertical direction of the screen. Accordingly, the S (N−1) / N region is a non-lighting region 52. This non-lighting area is black display (non-light emitting). The non-light emitting portion 52 is realized by turning off the transistor 11d. Although it is assumed that the light is lit at N times the luminance, it goes without saying that the value is adjusted to N times by brightness adjustment and gamma adjustment.

  Further, in the previous embodiment, if programming was performed with 10 times the current, the brightness of the screen would be 10 times, and 90% of the display area 50 could be the non-lighting area 52. However, this is not limited to the common use of the RGB pixels as the non-lighting region 52. For example, for the R pixel, 1/8 is the non-lighting area 52, for the G pixel, 1/6 is the non-lighting area 52, and for the B pixel, 1/10 is the non-lighting area 52. You may change by. Further, the non-lighting area 52 (or the lighting area 53) may be individually adjusted with RGB colors. In order to realize these, separate gate signal lines 17b are required for R, G, and B. However, by allowing individual adjustment of RGB as described above, it is possible to adjust white balance, and color balance adjustment is facilitated at each gradation (see FIG. 41).

  As shown in FIG. 13B, the pixel row including the writing pixel row 51a is a non-lighting region 52, and the S / N (1F / N in terms of time) range of the upper screen from the writing pixel row 51a is set. The display area 53 is set (if the writing scan is from the top to the bottom of the screen, the opposite is true when the screen is scanned from the bottom to the top). In the image display state, the display area 53 is strip-shaped and moves from the top to the bottom of the screen.

  In the display of FIG. 13, one display area 53 moves downward from the top of the screen. When the frame rate is low, it is visually recognized that the display area 53 moves. In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.

  For this problem, the display area 53 may be divided into a plurality of parts as shown in FIG. If the divided sum is an area of S (N-1) / N, it is equivalent to the brightness of FIG. The divided display areas 53 do not have to be equal (equally divided). Further, the divided non-display areas 52 need not be equal.

  As described above, screen flickering is reduced by dividing display area 53 into a plurality of parts. Therefore, no flicker occurs and a good image display can be realized. The division may be made finer. However, the more divided, the lower the moving image display performance.

  FIG. 17 shows the voltage waveform of the gate signal line 17 and the light emission luminance of EL. As is apparent from FIG. 17, the period (1F / N) during which the gate signal line 17b is set to Vgl is divided into a plurality of numbers (the number of divisions K). That is, a period of 1F / (K / N) is performed K times for the period of Vgl. By controlling in this way, the occurrence of flicker can be suppressed and an image display with a low frame rate can be realized. Further, it is preferable that the number of divisions of the image is variable. For example, this change may be detected and the value of K may be changed by the user pressing a brightness adjustment switch or turning the brightness adjustment volume. Moreover, you may comprise so that a user may adjust a brightness | luminance. You may comprise so that it may change manually or automatically by the content and data of the image to display.

In FIG. 17 and the like, the period (1F / N) in which the gate signal line 17b is set to Vgl is divided into a plurality (number of divisions K), and the period of Vgl is set to 1F / (K / N) K times. However, this is not a limitation. The period of 1F / (K / N) may be performed L (L ≠ K) times. In other words, the present invention displays the image 50 by controlling the period (time) flowing through the EL element 15. Therefore, it is included in the technical idea of the present invention to execute the period of 1F / (K / N) L (L ≠ K) times. Further, by changing the value of L, the brightness of the image 50 can be changed digitally. For example, when L = 2 and L = 3, the luminance (contrast) changes by 50%. Further, when the image display area 53 is divided, the period during which the gate signal line 17b is set to Vgl is not limited to the same period.

  In the above embodiment, the current flowing through the EL element 15 is cut off, and the current flowing through the EL element is connected to turn on and off the display screen 50 (lighting or non-lighting). That is, substantially the same current is caused to flow through the transistor 11a a plurality of times by the charge held in the capacitor 19. The present invention is not limited to this. For example, the display screen 50 may be turned on / off (lighted or not lighted) by charging / discharging the charge held in the capacitor 19.

  FIG. 18 shows voltage waveforms applied to the gate signal line 17 for realizing the image display state of FIG. The difference between FIG. 18 and FIG. 15 is the operation of the gate signal line 17b. The gate signal lines 17b are turned on / off (Vgl and Vgh) corresponding to the number of divided screens. The other points are the same as in FIG.

  In the EL display device, since the black display is completely unlit, there is no reduction in contrast as in the case where the liquid crystal display panel is intermittently displayed. Further, in the configuration of FIG. 1, intermittent display can be realized only by turning on / off the transistor 11d, and in the configuration of FIG. 38, simply turning on / off the transistor element 11e. This is because the image data is stored in the capacitor 19 (the number of gradations is infinite because it is an analog value). That is, the image data is held in each pixel 16 during the period of 1F. Whether or not a current corresponding to the stored image data is supplied to the EL element 15 is realized by controlling the transistors 11d and 11e.

  It is important to maintain the terminal voltage of the capacitor 19. This is because if the terminal voltage of the capacitor 19 changes (charges / discharges) in one field (frame) period, the screen brightness changes, and flickering (flicker or the like) occurs when the frame rate decreases. It is necessary that the current that the transistor 11a passes through the EL element 15 in one frame (one field) period does not decrease to at least 65% or less. This 65% means that when the current written to the pixel 16 and the current flowing to the EL element 15 is 100%, the current flowing to the EL element 15 immediately before writing to the pixel 16 in the next frame (field) is 65% or more. It is to do.

  In the pixel configuration of FIG. 1, there is no change in the number of transistors 11 that constitute one pixel, in the case where intermittent display is realized or not. That is, the current configuration is realized by removing the influence of the parasitic capacitance of the source signal line 18 without changing the pixel configuration. In addition, a moving image display close to a CRT is realized.

  Further, since the operation clock of the gate driver circuit 12 is sufficiently slower than the operation clock of the source driver circuit 14, the main clock of the circuit does not increase. Further, it is easy to change the value of N.

  The image display direction (image writing direction) may be from the top to the bottom in the first field (one frame) and from the bottom to the top in the second field (frame). In other words, the top-to-bottom direction and the bottom-to-top direction are alternately repeated.

  In the first field (one frame), the screen is displayed from the top to the bottom. Once the entire screen is displayed in black (not displayed), the second field (frame) is displayed from the bottom to the top. Also good. Alternatively, the entire screen may be displayed black (not displayed) once.

  In the above description of the driving method, the screen writing method is set from the top to the bottom or from the bottom to the top, but the present invention is not limited to this. The screen writing direction is constantly fixed from top to bottom or from bottom to top, and the non-display area 52 operation direction is from top to bottom in the first field, and from the bottom in the second field. It is good also as an upward direction. The above matters are the same in other embodiments of the present invention.

  The non-display area 52 does not have to be completely unlit. There is no problem in practical use even if weak light emission or light image display is present. That is, it should be interpreted as an area having a lower display luminance than the image display area 53. Further, the non-display area 52 includes a case where only one or two colors of the R, G, and B image displays are in a non-display state.

  Basically, when the brightness (brightness) of the display area 53 is maintained at a predetermined value, the brightness of the screen 50 increases as the area of the display area 53 increases. For example, when the luminance of the display area 53 is 100 (nt), if the ratio of the display area 53 to the entire screen 50 is changed from 10% to 20%, the luminance of the screen is doubled. Therefore, the display brightness of the screen can be changed by changing the area of the display area 53 occupying the entire screen 50.

  The area of the display area 53 can be arbitrarily set by controlling the data pulse (ST2) to the shift register 61. Also, the display state of FIG. 16 and the display state of FIG. 13 can be switched by changing the input timing and period of the data pulse. If the number of data pulses in the 1F cycle is increased, the screen 50 becomes brighter, and if it is decreased, the screen 50 becomes darker. If the data pulse is continuously applied, the display state shown in FIG. 13 is obtained, and if the data pulse is input intermittently, the display state shown in FIG. 16 is obtained.

  FIG. 19A shows a brightness adjustment method when the display area 53 is continuous as shown in FIG. The display brightness of the screen 50 in FIG. 19 (a1) is the brightest. The display brightness of the screen 50 in FIG. 19 (a2) is the next brightest, and the display brightness of the screen 50 in FIG. 19 (a3) is the darkest. The change from FIG. 19 (a1) to FIG. 19 (a3) (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. At this time, it is not necessary to change the Vdd voltage in FIG. That is, it is possible to change the luminance of the display screen 50 without changing the power supply voltage. In addition, the gamma characteristic of the screen does not change at all during the change from FIG. 19 (a1) to FIG. 19 (a3). Therefore, the contrast and gradation characteristics of the display image are maintained regardless of the brightness of the screen 50. This is an effective feature of the present invention. In the conventional screen brightness adjustment, when the brightness of the screen 50 is low, the gradation performance deteriorates. That is, even when 64 gradation display can be realized during high brightness display, only half or less of the number of gradations can be displayed during low brightness display. Compared to this, the driving method of the present invention can realize the highest 64 gradation display without depending on the display brightness of the screen.

  FIG. 19B shows a brightness adjustment method when the display area 53 is dispersed as shown in FIG. The display brightness of the screen 50 in FIG. 19 (b1) is the brightest. The display brightness of the screen 50 in FIG. 19 (b2) is the next brightest, and the display brightness of the screen 50 in FIG. 19 (b3) is the darkest. The change from FIG. 19 (b1) to FIG. 19 (b3) (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. If the display area 53 is dispersed as shown in FIG. 19B, flicker does not occur even at a low frame rate.

In order to prevent flicker from occurring even at a lower frame rate, the display area 53 may be finely dispersed as shown in FIG. However, the display performance of moving images decreases. Therefore, the driving method shown in FIG. 19A is suitable for displaying a moving image. When a still image is displayed and low power consumption is desired, the driving method shown in FIG. 19C is suitable. Switching of the driving method from FIG. 19A to FIG. 19C can be easily realized by controlling the shift register 61.

  FIG. 20 is an explanatory diagram of another embodiment in which the current flowing through the source signal line 18 is increased. Basically, a plurality of pixel rows are selected simultaneously, and a parasitic capacitance of the source signal line 18 is charged / discharged with a current obtained by combining the plurality of pixel rows, thereby greatly improving current writing shortage. However, since a plurality of pixel rows are selected at the same time, the driving current per pixel can be reduced. Therefore, the current flowing through the EL element 15 can be reduced. Here, for ease of explanation, as an example, N = 10 will be described (the current flowing through the source signal line 18 is multiplied by 10).

  In the present invention described with reference to FIG. 20, K pixel rows are simultaneously selected as the pixel rows. From the source driver IC 14, a current N times the predetermined current is applied to the source signal line 18. Each pixel is programmed with a current N / K times the current flowing through the EL element 15. In order to set the EL element 15 to a predetermined light emission luminance, the time flowing through the EL element 15 is set to K / N time of one frame (one field). By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained with good resolution.

  That is, current is passed through the EL element 15 only during the K / N period of one frame (one field), and no current is passed during the other period (1F (N−1) K / N). In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is a temporal display (intermittent display) state. Accordingly, the outline blurring of the image is eliminated and a good moving image display can be realized. Further, since the source signal line 18 is driven with N times the current, it is not affected by the parasitic capacitance and can be applied to a high-definition display panel.

  FIG. 21 is an explanatory diagram of drive waveforms for realizing the drive method of FIG. The signal waveform has an off voltage of Vgh (H level) and an on voltage of Vgl (L level). The subscript of each signal line describes the number of the pixel row ((1) (2) (3) etc.). The number of rows is 220 for the QCIF display panel and 480 for the VGA panel.

  In FIG. 21, the gate signal line 17 a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11 a of the selected pixel row toward the source driver 14. Here, for ease of explanation, first, it is assumed that the writing pixel row 51a is the pixel row (1) -th.

  The program current flowing through the source signal line 18 is N times a predetermined value (for ease of explanation, N = 10 will be described. Of course, since the predetermined value is a data current for displaying an image, white raster display is performed. It is not a fixed value unless it is). Further, description will be made assuming that five pixel rows are simultaneously selected (K = 5). Therefore, ideally, the capacitor 19 of one pixel is programmed so that the current flows through the transistor 11a twice (N / K = 10/5 = 2).

  When the writing pixel row is the (1) pixel row, as shown in FIG. 21, (1), (2), (3), (4), and (5) are selected as the gate signal line 17a. That is, the switching transistors 11b and the transistors 11c in the pixel rows (1), (2), (3), (4), and (5) are on. Further, the gate signal line 17b has an opposite phase to the gate signal line 17a. Accordingly, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are in the off state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52.

  Ideally, each of the five-pixel transistors 11a passes an Iw × 2 current to the source signal line 18 (that is, Iw × 2 × N = Iw × 2 × 5 = Iw × 10 in the source signal line 18). Therefore, when the N-times pulse driving according to the present invention is not performed and the predetermined current Iw is used, a current 10 times as large as Iw flows in the source signal line 18).

  With the above operation (driving method), a double current is programmed in the capacitor 19 of each pixel 16. Here, in order to facilitate understanding, description will be made assuming that the characteristics (Vt, S value) of the transistors 11a are the same.

  Since five pixel rows (K = 5) are selected at the same time, the five drive transistors 11a operate. That is, 10/5 = 2 times the current flows through the transistor 11a per pixel. A current obtained by adding the program currents of the five transistors 11a flows through the source signal line 18. For example, the write current Iw is originally applied to the write pixel row 51 a, and a current of Iw × 10 is supplied to the source signal line 18. This is a pixel row used as an auxiliary to increase the amount of current to the writing pixel row 51b to which the image data is written after the writing pixel row (1). However, there is no problem in the writing pixel row 51b because normal image data is written later.

  Accordingly, the same display as 51a is performed in the four pixel row 51b during the 1H period. Therefore, at least the non-display state 52 is set for the writing pixel row 51a and the pixel row 51b selected to increase the current. However, in the pixel configuration of the current mirror as shown in FIG. 38 and the pixel configuration of other voltage programming methods, the display state may be set depending on circumstances.

  After the next 1H, the gate signal line 17a (1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (6) is selected (Vgl voltage), and a program current flows from the transistor 11a of the selected pixel row (6) to the source driver 14 to the source signal line 18. By operating in this way, regular image data is held in the pixel row (1).

  After the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17 a (7) is selected (Vgl voltage), and a program current flows from the transistor 11 a of the selected pixel row (7) toward the source driver 14 through the source signal line 18. By operating in this way, regular image data is held in the pixel row (2). One screen is rewritten by performing the above operation and scanning while shifting by one pixel row.

  In the driving method of FIG. 20, since each pixel is programmed with twice the current (voltage), the light emission luminance of the EL element 15 of each pixel is ideally doubled. Therefore, the brightness of the display screen is twice the predetermined value. In order to obtain a predetermined luminance, as shown in FIG. 16, a non-display area 52 may be included that includes the writing pixel row 51 and is ½ of the display area 50.

  As in FIG. 13, when one display area 53 moves downward from the top of the screen as shown in FIG. 20, it is visually recognized that the display area 53 moves when the frame rate is low. In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.

  For this problem, the display area 53 may be divided into a plurality of parts as shown in FIG. When the divided non-display area 52 is added to have an area of S (N-1) / N, it is the same as when not divided.

  FIG. 23 shows voltage waveforms applied to the gate signal line 17. The difference between FIG. 21 and FIG. 23 is basically the operation of the gate signal line 17b. The gate signal lines 17b are turned on / off (Vgl and Vgh) corresponding to the number of divided screens. The other points are almost the same as those in FIG.

  As described above, screen flickering is reduced by dividing display area 53 into a plurality of parts. Therefore, no flicker occurs and a good image display can be realized. The division may be made finer. However, the more divided, the less flicker. In particular, since the responsiveness of the EL element 15 is fast, even if it is turned on / off in a time shorter than 5 μsec (μsec), the display luminance does not decrease.

  In the driving method of the present invention, ON / OFF of the EL element 15 can be controlled by ON / OFF of a signal applied to the gate signal line 17b. Therefore, the clock frequency can be controlled at a low frequency on the order of KHz. Further, an image memory or the like is not required to realize black screen insertion (non-display area 52 insertion). Therefore, the drive circuit or method of the present invention can be realized at low cost.

  FIG. 24 shows a case where two pixel rows are selected simultaneously. According to the examination result, in the display panel formed by the low-temperature polysilicon technology, the method of selecting two pixel rows at the same time has practical display uniformity. This is presumably because the characteristics of the driving transistors 11a of the adjacent pixels are very consistent. In addition, when laser annealing was performed, a good result was obtained by irradiating the stripe laser beam in parallel with the source signal line 18.

  This is because the characteristics of the semiconductor film that is annealed in the same time are uniform. That is, the semiconductor film is uniformly formed within the stripe-shaped laser irradiation range, and the Vt and mobility of the TFT using this semiconductor film are almost equal. Therefore, by irradiating a striped laser shot parallel to the formation direction of the source signal line 18 and moving the irradiation position, pixels (pixel columns, pixels in the vertical direction of the screen) along the source signal line 18 are moved. The characteristics are made approximately equal. Therefore, when current programming is performed with multiple pixel rows turned on at the same time, the program current is selected at the same time, and the current obtained by dividing the program current by the number of selected pixels is the same current program. Is done. Therefore, a current program close to the target value can be implemented, and uniform display can be realized. Therefore, there is a synergistic effect between the laser shot direction and the driving method described in FIG.

  As described above, by making the laser shot direction substantially coincide with the formation direction of the source signal line 18, the characteristics of the TFT 11a in the vertical direction of the pixel become substantially the same, and a good current program can be implemented (pixel). Even if the characteristics of the TFTs 11a in the left and right directions do not match. The above operation is performed by shifting the position of the selected pixel row by one pixel row or a plurality of pixel rows in synchronization with 1H (one horizontal scanning period). In the present invention, the direction of the laser shot is made parallel to the source signal line 18, but it need not be parallel. This is because the characteristics of the TFTs 11 a formed in the vertical direction of the pixels along one source signal line 18 are substantially matched even when the laser shot is irradiated obliquely with respect to the source signal line 18. Therefore, irradiating a laser shot parallel to the source signal line means that adjacent pixels above or below any pixel along the source signal line 18 are formed so as to fall within one laser irradiation range. It is. The source signal line 18 is generally a wiring for transmitting a program current or voltage that becomes a video signal.

In the embodiment of the present invention, the writing pixel row position is shifted every 1H. However, the present invention is not limited to this, and the writing pixel row position may be shifted every 2H or shifted every more pixel rows. May be. Moreover, you may shift by arbitrary time units. Further, the shift time may be changed according to the screen position. For example, the shift time at the center of the screen may be shortened and the shift time may be lengthened at the top and bottom of the screen. Further, the shift time may be changed for each frame. Further, the present invention is not limited to selecting a plurality of continuous pixel rows. For example, a pixel row extending to one pixel row may be selected. That is, the first pixel row and the third pixel row are selected in the first horizontal scanning period, and the second pixel row and the fourth pixel row are selected in the second horizontal scanning period. The third pixel row and the fifth pixel row are selected during the third horizontal scanning period, and the fourth pixel row and the sixth pixel row are selected during the fourth horizontal scanning period. This is a driving method. Of course, a driving method of selecting the first pixel row, the third pixel row, and the fifth pixel row in the first horizontal scanning period is also a technical category.

  Note that the combination of the laser shot direction and the selection of a plurality of pixel rows at the same time is not limited to the pixel configurations of FIGS. 1, 2, and 32, and is a pixel configuration of a current mirror. Needless to say, the present invention can be applied to other current-driven pixel configurations such as 38, 42, and 50. The present invention can also be applied to voltage-driven pixel configurations such as those shown in FIGS. 43, 51, 54, and 62. That is, if the characteristics of the TFTs above and below the pixel match, the voltage program can be executed satisfactorily with the voltage value applied to the same source signal line 18.

  In FIG. 24, when the writing pixel row is (1) pixel row, (1) and (2) are selected for the gate signal line 17a (see FIG. 25). That is, the switching transistors 11b and the transistors 11c in the pixel rows (1) and (2) are on. Further, the gate signal line 17b has an opposite phase to the gate signal line 17a. Therefore, at least the switching transistors 11d in the pixel rows (1) and (2) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52. In FIG. 24, the display area 53 is divided into five parts in order to reduce the occurrence of flicker.

  Ideally, the transistors 11a of two pixels (rows) each have Iw × 5 (N = 10. That is, since K = 2, the current flowing through the source signal line 18 is Iw × K × 5 = Iw. A current of × 10) is passed through the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with 5 times the current.

  Since two pixel rows (K = 2) are selected at the same time, the two drive transistors 11a operate. That is, a current of 10/2 = 5 times flows through the transistor 11a per pixel. A current obtained by adding the program currents of the two transistors 11a flows through the source signal line 18.

  For example, the write current Id is originally written in the write pixel row 51 a, and a current of Iw × 10 is passed through the source signal line 18. There is no problem in the writing pixel row 51b because normal image data is written later. The pixel row 51b has the same display as 51a during the 1H period. Therefore, at least the non-display state 52 is set for the writing pixel row 51a and the pixel row 51b selected to increase the current.

  After the next 1H, the gate signal line 17a (1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17 a (3) is selected (Vgl voltage), and a program current flows from the transistor 11 a of the selected pixel row (3) toward the source driver 14 through the source signal line 18. By operating in this way, regular image data is held in the pixel row (1).

After the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (4) is selected (Vgl voltage), and the source driver 1 starts from the transistor 11a in the selected pixel row (4).
A program current flows through the source signal line 18 toward 4. By operating in this way, regular image data is held in the pixel row (2). The above operation and a shift by one pixel row (of course, a plurality of pixel rows may be shifted. For example, if pseudo-interlace driving is used, a shift by two rows will occur. One screen is rewritten by scanning while the same image may be written in the pixel row.

  Although it is the same as FIG. 16, in the driving method of FIG. 24, since each pixel is programmed with a current (voltage) 5 times, the emission luminance of the EL element 15 of each pixel is ideally 5 times. . Therefore, the luminance of the display area 53 is five times higher than the predetermined value. In order to obtain a predetermined luminance, as shown in FIG. 16 and the like, a non-display area 52 may be included that includes a writing pixel row 51 and that is 1/5 of the display screen 1.

  As shown in FIG. 27, two write pixel rows 51 (51a, 51b) are selected and sequentially selected from the upper side to the lower side of the screen 50 (see also FIG. 26. In FIG. 26, the pixel row 16a). And 16b are selected). However, as shown in FIG. 27B, when it reaches the lower side of the screen, the writing pixel row 51a exists, but the 51b disappears. That is, only one pixel row is selected. Therefore, all the current applied to the source signal line 18 is written to the pixel row 51a. Therefore, twice as much current is programmed in the pixel as compared with the pixel row 51a.

  In response to this problem, the present invention forms (arranges) a dummy pixel row 281 on the lower side of the screen 50 as shown in FIG. Therefore, when the selected pixel row is selected up to the lower side of the screen 50, the last pixel row and the dummy pixel row 281 on the screen 50 are selected. Therefore, a prescribed current is written into the write pixel row in FIG.

  FIG. 28 shows the state of FIG. As is clear from FIG. 28, when the selected pixel rows are selected up to the pixel 16c row on the lower side of the screen 50, the last pixel row 281 of the screen 50 is selected. The dummy pixel row 281 is arranged outside the display area 50. That is, the dummy pixel row 281 is configured not to be lit, not lit, or not displayed as a display even when lit. For example, the contact hole between the pixel electrode and the TFT 11 is eliminated, or the EL film is not formed in the dummy pixel row.

  In FIG. 27, the dummy pixels (rows) 281 are provided (formed or arranged) on the lower side of the screen 50, but the present invention is not limited to this. For example, as shown in FIG. 29A, when scanning from the lower side to the upper side of the screen (upside down scanning), the dummy pixel row 281 is also formed on the upper side of the screen 50 as shown in FIG. Should be formed (see FIG. 157 (a)). That is, the dummy pixel row 281 is formed (arranged) on each of the upper side and the lower side of the screen 50. With the configuration described above, it is possible to cope with upside down scanning of the screen. In the above embodiment, two pixel rows are selected simultaneously.

The present invention is not limited to this. For example, a method of simultaneously selecting five pixel rows (see FIG. 23) may be used. That is, in the case of simultaneous driving of five pixel rows, four dummy pixel rows 281 may be formed. The dummy pixel row configuration or dummy pixel row driving according to the present invention is a method using at least one dummy pixel row. Of course, it is preferable to use a combination of the dummy pixel row driving method and N-times pulse driving. This configuration is illustrated in FIG. FIG. 157 (a) shows a configuration in which one pixel row is arranged above and below the screen 50 for the dummy pixel row 281. FIG. Similarly, FIG. 157 (b) shows a configuration in which two pixel rows are arranged above and below the screen 50. FIG. FIG. 157 (b) can be implemented up to simultaneous selection of three pixel rows. FIG. 157 (c) shows a configuration in which three pixel rows are arranged above and below the screen 50. FIG. FIG. 157 (c) can be implemented up to simultaneous selection of four pixel rows (two-pixel row simultaneous selection, three-pixel row simultaneous selection, and four-pixel row simultaneous selection can also be performed). FIG. 157 (d) shows a configuration in which four pixel rows are arranged at the top and bottom of the screen 50.

  As described above, the dummy pixel row 281 may be formed by subtracting 1 from the number D of the simultaneously selected pixel rows 51, but forming a prime number (that is, the number of dummy pixel rows formed is D-1). When the image is flipped up and down, dummy pixel rows are arranged at the top and bottom of the screen 50. When the image is not flipped up and down (only in one direction), the dummy pixel row may be formed on one of the top and bottom (D-1). .

  Further, the dummy pixel row 281 illustrated and described with reference to FIGS. 28, 157, etc. is formed, and adjacent multiple pixel rows (not necessarily limited to selecting adjacent multiple pixel rows) are selected simultaneously. When the driving method is performed, it is preferable to adopt the laser annealing method described in FIG. In the laser annealing method of FIG. 7, the laser irradiation spot 72 region is scanned in parallel with the source signal line 18. By implementing the manufacturing method of FIG. 7, the TFT characteristics (Vt, S value, etc.) of adjacent pixel rows become substantially equal. Therefore, even when a plurality of pixel rows are simultaneously selected by the driving method of FIG. 28, the programming current Iw is applied to the plurality of pixel rows on average, so that accurate current writing can be realized.

  The dummy pixel row 281 does not need to display an image. Therefore, basically, it is not necessary to form the pixel electrode 105. This is because the dummy pixel row 281 is necessary only when the program current Iw is written. Therefore, in the pixel configuration of FIG. 1, the driving TFT 11a, TFT 11b, and TFT 11c are necessary, and the TFT 11d, the EL element 15, and the like are unnecessary. Further, in the pixel configuration of the current mirror of FIG. 38, the TFT 11a, TFT 11c, and TFT 11d are necessary, but the TFT 11b, the TFT 11e, the EL element 15, and the like are unnecessary. That is, in the current programming type pixel configuration, it is sufficient if there is a TFT or the like that forms a path through which the programming current Iw flows when a pixel row is selected.

  If a large number of dummy pixel rows 281 are formed, securing a space for forming the dummy pixel rows 281 becomes a problem. Therefore, the dummy pixel row 281 needs to be formed as small as possible. In the present invention, as shown in FIG. 156, the pixel electrode 105 and the EL element 15 are not formed in the dummy pixel row 281, but a TFT necessary for the path through which the program current Iw flows is formed and disposed in the dummy pixel row 281. ing. FIG. 156 shows an example in which the dummy pixel row 281 is a five-pixel row.

  A pixel transistor formation region 1561 is a formation region of a transistor that drives a pixel. In the pixel configuration of FIG. 1, it is not necessary for the TFT 11d to generate a path for the program current Iw. However, if the TFT layout pattern of the pixel for displaying an image is different from the layout pattern of the dummy pixel row 281, the TFT characteristics of the pixel 16 and the TFT characteristics of the dummy pixel 281 are caused by a difference in laser annealing conditions or etching conditions during TFT formation. There is a case where it is shifted. In order to eliminate this problem, in the present invention, the layout pattern of the dummy pixel 281 employs a configuration in which the pixel electrode 105 is removed from the layout pattern of the pixel 16. As described above, the TFT configuration of the dummy pixel 281 is preferably the same as or similar to the TFT configuration of the pixel 16. It is preferable that at least WL of each TFT is substantially the same and the channel forming direction is also the same. More preferably, the capacitor 19 is also formed. It is also preferable to leave a pattern such as a TFT 11d that is not necessary for the path of the program current Iw. Furthermore, it is preferable to form a pixel electrode 105 on the TFT. In this case, a contact hole connecting the drain terminal of the TFT 11d and the pixel electrode 105 is not formed.

In the present invention, the dummy pixel 281 has the pixel electrode 105 removed from the pixel 16 (because it is not necessary to form the EL element 15). Precisely, the pixel electrode 105 on the TFT remains, and the pixel opening (the portion from which the light emitted from the EL element 15 is emitted) is deleted. By eliminating the pixel openings, the formation region of the dummy pixel row 281 can be reduced as shown in FIG.

  In the driving method of selecting a plurality of pixel rows at the same time, it becomes more difficult to absorb the characteristic variation of the transistor 11a as the number of pixel rows to be selected simultaneously increases. However, when the number of selected lines decreases, the current programmed in one pixel increases, and a large current flows through the EL element 15. If the current passed through the EL element 15 is large, the EL element 15 is likely to deteriorate.

  FIG. 30 solves this problem. The basic concept of FIG. 30 is a method of simultaneously selecting a plurality of pixel rows in 1 / 2H (1/2 of the horizontal scanning period) as described in FIGS. Subsequent 1 / 2H (1/2 of the horizontal scanning period) is a combination of methods for selecting one pixel row as described with reference to FIGS. By combining in this way, it is possible to absorb the characteristic variation of the transistor 11a, and to improve the in-plane uniformity at high speed.

  In FIG. 30, for ease of explanation, it is assumed that five pixel rows are simultaneously selected in the first period and one pixel row is selected in the second period. First, in the first period (1 / 2H in the first half), five pixel rows are simultaneously selected as shown in FIG. Since this operation has been described with reference to FIG. As an example, the current flowing through the source signal line 18 is 25 times the predetermined value. Accordingly, the transistor 11a of each pixel 16 (in the case of the pixel configuration in FIG. 1) is programmed with a current that is five times (25/5 pixel row = 5). Since the current is 25 times, the parasitic capacitance generated in the source signal line 18 and the like is charged and discharged in a very short time. Therefore, the potential of the source signal line 18 becomes the target potential in a short time, and the terminal voltage of the capacitor 19 of each pixel 16 is also programmed to flow 5 times the current. The application time of the 25 times current is set to 1 / 2H in the first half (1/2 of one horizontal scanning period).

  As a matter of course, since the same image data is written in the five pixel rows of the writing pixel row, the transistors 11d in the five pixel rows are turned off so as not to be displayed. Therefore, the display state is as shown in FIG.

  In the next ½H period of the second half, one pixel row is selected and current (voltage) programming is performed. This state is shown in FIG. 30 (b1). The write pixel row 51a is programmed with a current (voltage) so as to pass a current that is five times the current as before. 30A1 and FIG. 30B1 have the same current flowing through each pixel so that the change in the terminal voltage of the programmed capacitor 19 can be reduced so that the target current can flow faster. It is to do.

  That is, in FIG. 30 (a1), a current is passed through a plurality of pixels and is brought close to a value at which an approximate current flows at a high speed. In this first stage, since programming is performed by the plurality of transistors 11a, an error due to transistor variation occurs with respect to the target value. In the next second stage, only a pixel row in which data is written and held is selected, and a complete program is executed from a rough target value to a predetermined target value.

  The scanning of the non-lighting area 52 from the top to the bottom of the screen and the scanning of the writing pixel row 51a from the top to the bottom of the screen are the same as in the embodiment of FIG. .

  FIG. 31 shows drive waveforms for realizing the drive method of FIG. As can be seen in FIG. 31, 1H (one horizontal scanning period) is composed of two phases. These two phases are switched by the ISEL signal. The ISEL signal is illustrated in FIG.

  First, the ISEL signal will be described. The driver circuit 14 implementing FIG. 30 includes a current output circuit A and a current output circuit B. Each current output circuit includes a DA circuit that performs DA conversion on 8-bit grayscale data, an open amplifier, and the like. In the embodiment of FIG. 30, the current output circuit A is configured to output a current 25 times larger. On the other hand, the current output circuit B is configured to output five times the current. The outputs of the current output circuit A and the current output circuit B are applied to the source signal line 18 by controlling the switch circuit formed (arranged) in the current output unit by the ISEL signal. This current output circuit is disposed on each source signal line.

  When the ISEL signal is at the L level, the current output circuit A that outputs a current 25 times larger is selected, and the current from the source signal line 18 is absorbed by the source driver IC 14 (more suitably, formed in the source driver circuit 14). Absorbed by the current output circuit A). It is easy to adjust the magnitude of the current output circuit current such as 25 times or 5 times. This is because it can be easily configured with a plurality of resistors and analog switches.

  As shown in FIG. 30, when the writing pixel row is the (1) pixel row (see the column 1H in FIG. 30), the gate signal line 17a is (1) (2) (3) (4) (5) Is selected (in the case of the pixel configuration in FIG. 1). That is, the switching transistors 11b and the transistors 11c in the pixel rows (1), (2), (3), (4), and (5) are on. Further, since ISEL is at the L level, the current output circuit A that outputs a 25-fold current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b. Accordingly, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are in the off state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52.

  Ideally, each of the five-pixel transistors 11 a allows a current of Iw × 2 to flow through the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with 5 times the current. Here, in order to facilitate understanding, description will be made assuming that the characteristics (Vt, S value) of the transistors 11a are the same.

  Since five pixel rows (K = 5) are selected at the same time, the five drive transistors 11a operate. That is, a current of 25/5 = 5 times flows to the transistor 11a per pixel. A current obtained by adding the program currents of the five transistors 11a flows through the source signal line 18. For example, when the current Iw to be written to the pixel by the conventional driving method is set in the write pixel row 51a, a current of Iw × 25 is passed through the source signal line 18. This is a pixel row used as an auxiliary to increase the amount of current to the writing pixel row 51b to which the image data is written after the writing pixel row (1). However, there is no problem in the writing pixel row 51b because normal image data is written later.

  Therefore, the pixel row 51b has the same display as 51a during the 1H period. Therefore, at least the non-display state 52 is set for the writing pixel row 51a and the pixel row 51b selected to increase the current.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the writing pixel row 51a is selected. That is, (1) only the pixel row is selected. As apparent from FIG. 31, only the gate signal line 17a (1) is applied with the ON voltage (Vgl), and the gate signal lines 17a (2), (3), (4), and (5) are applied with OFF (Vgh). Has been. Therefore, the transistors 11a in the pixel row (1) are in an operating state (a state in which current is supplied to the source signal line 18), but the switching transistors 11b in the pixel rows (2), (3), (4), and (5), The transistor 11c is off. That is, it is a non-selection state. Further, since ISEL is at the H level, the current output circuit B that outputs a 5-fold current is selected, and the current output circuit B and the source signal line 18 are connected. Further, the state of the gate signal line 17b is not changed from the previous state of 1 / 2H, and an off voltage (Vgh) is applied. Therefore, the switching transistors 11d in the pixel rows (1), (2), (3), (4), and (5) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52.

  From the above, the transistors 11a in the pixel row (1) flow Iw × 5 current to the source signal line 18, respectively. Then, the capacitor 19 in each pixel row (1) is programmed with 5 times the current.

  In the next horizontal scanning period, one pixel row and a writing pixel row are shifted. That is, the writing pixel row is (2) this time. In the first ½H period, when the writing pixel row is the (2) pixel row as shown in FIG. 31, the gate signal line 17a is (2) (3) (4) (5) (6). Is selected. That is, the switching transistors 11b and the transistors 11c in the pixel rows (2), (3), (4), (5), and (6) are on. Further, since ISEL is at the L level, the current output circuit A that outputs a 25-fold current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b. Therefore, the switching transistors 11d in the pixel rows (2), (3), (4), (5), and (6) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52. On the other hand, since the Vgl voltage is applied to the gate signal line 17b (1) of the pixel row (1), the transistor 11d is on, and the EL element 15 of the pixel row (1) is lit.

  Since five pixel rows (K = 5) are selected at the same time, the five drive transistors 11a operate. That is, a current of 25/5 = 5 times flows to the transistor 11a per pixel. A current obtained by adding the program currents of the five transistors 11a flows through the source signal line 18.

  In the next 1 / 2H (1/2 of the horizontal scanning period), only the writing pixel row 51a is selected. That is, (2) only the pixel row is selected. As apparent from FIG. 31, only the gate signal line 17a (2) is applied with the ON voltage (Vgl), and the gate signal lines 17a (3), (4), (5), and (6) are applied with OFF (Vgh). Has been. Therefore, the transistors 11a in the pixel rows (1) and (2) are in an operating state (the pixel row (1) supplies current to the EL element 15 and the pixel row (2) supplies current to the source signal line 18). However, the switching transistors 11b and 11c in the pixel rows (3), (4), (5), and (6) are in an off state. That is, it is a non-selection state. In addition, since ISEL is at the H level, the current output circuit B that outputs a 5-fold current is selected, and the current output circuit 1222b and the source signal line 18 are connected. Further, the state of the gate signal line 17b is not changed from the previous state of 1 / 2H, and an off voltage (Vgh) is applied. Therefore, the switching transistors 11d in the pixel rows (2), (3), (4), (5), and (6) are in the OFF state, and no current flows through the EL elements 15 in the corresponding pixel rows. That is, it is a non-lighting state 52.

  From the above, the transistors 11 a in the pixel row (2) flow a current of Iw × 5 to the source signal line 18. Then, the capacitor 19 in each pixel row (2) is programmed with 5 times the current. One screen can be displayed by sequentially performing the above operations.

The driving method described with reference to FIG. 30 selects G pixel rows (G is 2 or more) in the first period, and performs programming so that N times the current flows in each pixel row. In the second period after the first period, a B pixel row (B is smaller than G and 1 or more) is selected, and the pixel is programmed to flow N times as much current.

  However, there are other strategies. In the first period, G pixel rows (G is 2 or more) are selected and programmed so that the total current of each pixel row is N times the current. In the second period after the first period, a B pixel row (B is smaller than G and is 1 or more) is selected, and the total current of the selected pixel rows (however, when the selected pixel row is 1, In this method, the current of one pixel row is programmed to be N times. For example, in FIG. 30 (a1), five pixel rows are selected simultaneously, and twice the current flows through the transistor 11a of each pixel. Therefore, the current of 5 × 2 = 10 times flows through the source signal line 18. In the next second period, one pixel row is selected in FIG. A 10-fold current flows through the transistor 11a of one pixel.

  In FIG. 31, the period for simultaneously selecting a plurality of pixel rows is set to 1 / 2H and the period for selecting one pixel row is set to 1 / 2H. However, the present invention is not limited to this. The period for selecting a plurality of pixel rows at the same time may be 1 / 4H, and the period for selecting one pixel row may be 3 / 4H. In addition, the period including the period for simultaneously selecting a plurality of pixel rows and the period for selecting one pixel row is set to 1H, but the present invention is not limited to this. For example, it may be a 2H period or a 1.5H period.

  In FIG. 30, the period for simultaneously selecting five pixel rows may be set to 1 / 2H, and two pixel rows may be simultaneously selected in the next second period. Even in this case, it is possible to realize an image display that is practically satisfactory.

  In FIG. 30, the first period for selecting five pixel rows at the same time is ½H, and the second period for selecting one pixel row is ½H. However, the present invention is not limited to this. Absent. For example, the first stage may select three pixel rows at the same time, the second period may select three pixel rows among the five pixel rows, and finally select one pixel row. . That is, the image data may be written in the pixel row at a plurality of stages.

  In the N-fold pulse driving method of the present invention described above, the waveform of the gate signal line 17b is made the same in each pixel row, and is applied while being shifted at an interval of 1H. By scanning in this way, it is possible to sequentially shift the pixel rows to be lit while prescribing the time during which the EL element 15 is lit to 1 F / N. Thus, it is easy to realize that the waveform of the gate signal line 17b is the same and shifted in each pixel row. This is because it is only necessary to control ST1 and ST2 which are data applied to the shift register circuits 61a and 61b in FIG. For example, if Vgl is output to the gate signal line 17b when the input ST2 is at L level, and Vgh is output to the gate signal line 17b when the input ST2 is at H level, ST2 applied to the shift register 17b is output. Input is made at the L level only for the period of 1F / N, and is set to the H level for the other periods. The input ST2 is simply shifted by the clock CLK2 synchronized with 1H.

  Note that the cycle of turning on and off the EL element 15 needs to be 0.5 msec or more. When this period is short, the image is not completely displayed due to the afterimage characteristics of the human eye, and the image becomes blurred, as if the resolution is lowered. Further, the display state of the data holding type display panel is set. However, when the on / off cycle is 100 msec or more, it appears to blink. Therefore, the on / off cycle of the EL element should be 0.5 μsec or more and 100 msec or less. More preferably, the on / off cycle should be 2 msec or more and 30 msec or less. More preferably, the on / off cycle should be 3 msec or more and 20 msec or less.

If the number of divisions of the black screen 152 is 1, good video display can be realized, but the screen flickering can be easily seen. Therefore, it is preferable to divide the black insertion portion into a plurality. However, if the number of divisions is too large, motion blur will occur. The number of divisions should be between 1 and 8. More preferably, it is 1 or more and 5 or less.

  It should be noted that the number of divisions of the black screen is preferably configured so that it can be changed between a still image and a moving image. With N = 4, 75% is a black screen and 25% is an image display. At this time, the division number is 1 to scan the 75% black display portion in the vertical direction of the screen in the 75% black belt state. The number of divisions is 3 for scanning with 3 blocks of a 25% black screen and a 25/3% display screen. Increase the number of divisions for still images. Reduce the number of divisions for movies. Switching may be performed automatically (moving image detection or the like) according to the input image, or may be performed manually by the user. Further, it may be configured to switch the video of the display device in accordance with the input outlet.

  For example, in a mobile phone or the like, the number of divisions is set to 10 or more on the wallpaper display and input screen (extremely, it may be turned on / off every 1H). When displaying NTSC moving images, the number of divisions is set to 1 or more and 5 or less. It should be noted that the number of divisions is preferably configured so that it can be switched to multiple stages of 3 or more. For example, no division number, 2, 4, 8, etc.

  The ratio of the black screen to the total display screen is preferably 0.2 or more and 0.9 or less (1.2 or more and 9 or less if displayed in N) when the area of the entire screen is 1. In particular, it is preferably 0.25 or more and 0.6 or less (in the case of N, it is 1.25 or more and 6 or less). If it is 0.20 or less, the improvement effect in moving image display is low. If it is 0.9 or more, the luminance of the display portion increases, and it is easy to visually recognize that the display portion moves up and down.

  The number of frames per second is preferably 10 or more and 100 or less (10 Hz or more and 100 Hz or less). Furthermore, 12 or more and 65 or less (12 Hz or more and 65 Hz or less) are preferable. If the number of frames is small, the flickering of the screen becomes conspicuous. If the number of frames is too large, writing from the driver circuit 14 and the like becomes difficult and the resolution deteriorates.

  In any case, in the present invention, the brightness of the image can be changed by controlling the gate signal line 17. However, it goes without saying that the brightness of the image may be obtained by changing the current (voltage) applied to the source signal line 18. It goes without saying that the control of the gate signal line 17 described above (using FIGS. 33, 35, etc.) and the change of the current (voltage) applied to the source signal line 18 may be combined. Yes.

  Needless to say, the above items can be applied to the pixel configuration of the current program shown in FIG. 38 and the pixel configuration of the voltage program shown in FIGS. 43, 51, and 54. In FIG. 38, the transistor 11d, the transistor 11d in FIG. 43, and the transistor 11e in FIG. In this way, by turning on and off the wiring for supplying current to the EL element 15, the N-fold pulse driving of the present invention can be easily realized.

  Further, the time to set Vgl only during the period of 1F / N of the gate signal line 17b may be any time in the period of 1F (not limited to 1F; it may be a unit period). This is because a predetermined average luminance is obtained by turning on the EL element 15 for a predetermined period of time in the unit time. However, it is better to set the gate signal line 17b to Vgl immediately after the current program period (1H) and cause the EL element 15 to emit light. This is because it is less susceptible to the retention characteristics of the capacitor 19 of FIG.

Further, it is preferable that the number of divisions of the image is variable. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume, this change is detected and the value of K is changed. You may comprise so that it may change manually or automatically by the content and data of the image to display.

  In this way, it is possible to easily change the value of K (the number of divisions of the image display unit 53). This is because the timing of data to be applied to ST in FIG. 6 (when it is set to L level at 1F) can be adjusted or varied.

  In FIG. 16 and the like, the period (1F / N) for setting the gate signal line 17b to Vgl is divided into a plurality (number of divisions K), and the period for setting the Vgl is 1F / (K / N) K times. However, this is not a limitation. The period of 1F / (K / N) may be performed L (L ≠ K) times. In other words, the present invention displays the image 50 by controlling the period (time) flowing through the EL element 15. Therefore, it is included in the technical idea of the present invention to execute the period of 1F / (K / N) L (L ≠ K) times. Further, by changing the value of L, the brightness of the image 50 can be changed digitally. For example, when L = 2 and L = 3, the luminance (contrast) change is 50%. It goes without saying that these controls can also be applied to other embodiments of the present invention (of course, the present invention described later can also be applied). These are also the N-fold pulse drive of the present invention.

  In the above embodiment, the transistor 11d as a switching element is disposed (formed) between the EL element 15 and the driving transistor 11a, and the screen 11 is displayed on and off by controlling the transistor 11d. . By this driving method, current writing shortage in the black display state of the current programming method is eliminated, and a good resolution or black display is realized. That is, in the current program method, it is important to realize a good black display. The driving method described below is to reset the driving transistor 11a to realize good black display. Hereinafter, the embodiment will be described with reference to FIG.

  FIG. 32 basically shows the pixel configuration of FIG. In the pixel configuration of FIG. 32, the programmed Iw current flows through the EL element 15, and the EL element 15 emits light. In other words, the driving transistor 11a retains the ability to flow current by being programmed. A method of resetting (turning off) the transistor 11a using this current flowing capability is the driving method of FIG. Hereinafter, this driving method is referred to as reset driving.

  In order to realize reset driving with the pixel configuration of FIG. 1, it is necessary to configure the transistor 11b and the transistor 11c so that they can be controlled on and off independently. That is, as shown in FIG. 32, the gate signal line 11a (gate signal line WR) for controlling on / off of the transistor 11b and the gate signal line 11c (gate signal line EL) for controlling on / off of the transistor 11c can be controlled independently. To. The gate signal line 11a and the gate signal line 11c may be controlled by two independent shift registers 61 as shown in FIG.

  The driving voltages of the gate signal line WR and the gate signal line EL are preferably changed. The amplitude value of the gate signal line WR (difference between the on voltage and the off voltage) is made smaller than the amplitude value of the gate signal line EL. Basically, if the amplitude value of the gate signal line is large, the punch-through voltage between the gate signal line and the pixel increases, and black floating occurs. The amplitude of the gate signal line WR may be controlled so that the potential of the source signal line 18 is not applied to the pixel 16 (applied (when selected)). Since the potential fluctuation of the source signal line 18 is small, the amplitude value of the gate signal line WR can be reduced. On the other hand, the gate signal line EL needs to perform EL on / off control. Therefore, the amplitude value becomes large. In order to cope with this, the output voltages of the shift registers 61a and 61b are changed. When the pixel is formed of a P-channel TFT, the shift registers 61a and 61b have substantially the same Vgh (off voltage), and the Vgl (on voltage) of the shift register 61a is larger than the Vgl (on voltage) of the shift register 61b. make low.

  Hereinafter, the reset driving method will be described with reference to FIG. FIG. 33 is a diagram for explaining the principle of reset driving. First, as illustrated in FIG. 33A, the transistors 11c and 11d are turned off and the transistor 11b is turned on. Then, the drain (D) terminal and the gate (G) terminal of the driving transistor 11a are short-circuited, and an Ib current flows. Generally, the transistor 11a is current-programmed in the previous field (frame) and has a capability of flowing current. In this state, when the transistor 11d is turned off and the transistor 11b is turned on, the drive current Ib flows to the gate (G) terminal of the transistor 11a. Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the transistor 11a is reset (a state in which no current flows).

  The reset state (state in which no current flows) of the transistor 11a is equivalent to a state in which the offset voltage of the voltage offset canceller system described in FIG. That is, in the state of FIG. 33A, the offset voltage is held between the terminals of the capacitor 19. This offset voltage has a different voltage value depending on the characteristics of the transistor 11a. Therefore, by performing the operation of FIG. 33A, the transistor 11a does not pass current through the capacitor 19 of each pixel (that is, the black display current (almost equal to 0) is held. .

  Note that before the operation in FIG. 33A, it is preferable to perform an operation in which the transistor 11b and the transistor 11c are turned off, the transistor 11d is turned on, and a current is supplied to the driving transistor 11a. This operation is preferably performed in a short time as much as possible. This is because a current flows through the EL element 15 and the EL element 15 is lit, which may reduce the display contrast. This operation time is preferably 0.1% or more and 10% or less of 1H (one horizontal scanning period). More preferably, it is preferably 0.2% or more and 2% or less. Alternatively, it is preferable to be 0.2 μsec or more and 5 μsec or less. Further, the above-described operation (operation performed before FIG. 33A) may be performed collectively on the pixels 16 of the entire screen. By performing the above operation, the drain (D) terminal voltage of the driving transistor 11a is lowered, and a smooth Ib current can flow in the state of FIG. The above matters also apply to other reset driving methods of the present invention.

  As the execution time of FIG. 33A is lengthened, the Ib current flows and the terminal voltage of the capacitor 19 tends to decrease. Therefore, the execution time of FIG. 33 (a) needs to be a fixed value. According to experiments and studies, it is preferable that the execution time of FIG. Note that this period is preferably different for R, G, and B pixels. This is because the EL material is different for each color pixel, and the rising voltage of the EL material is different. For each pixel of RGB, the most optimal period is set according to the EL material. In the embodiment, this period is set to 1H or more and 5H or less, but it goes without saying that it may be 5H or more in a driving method mainly for black insertion (writing a black screen). Note that the longer the period, the better the black display state of the pixel.

  After performing FIG. 33A, the state shown in FIG. 33B is obtained in a period of 1H to 5H. FIG. 33B shows a state in which the transistors 11c and 11b are turned on and the transistor 11d is turned off. The state shown in FIG. 33B is a state in which current programming is performed as described above. That is, the program current Iw is output (or absorbed) from the source driver circuit 14, and this program current Iw is supplied to the driving transistor 11a. The potential of the gate (G) terminal of the driving transistor 11a is set so that the program current Iw flows (the set potential is held in the capacitor 19).

If the program current Iw is 0 (A), the transistor 11a converts the current to that shown in FIG.
Since the state in which the current of a) does not flow is kept, good black display can be realized. In addition, even when white display current programming is performed in FIG. 33B, even if there is a variation in the characteristics of the driving transistors of each pixel, the current programming is performed from the offset voltage in the black display state completely. . Therefore, the time programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to the characteristic variation of the transistor 11a, and a good image display can be realized.

  After current programming in FIG. 33B, as shown in FIG. 33C, the transistors 11b and 11c are turned off, the transistor 11d is turned on, and the program current Iw (= Ie) from the driving transistor 11a is turned on. Is caused to flow through the EL element 15 to cause the EL element 15 to emit light. Since FIG. 33 (c) has been described previously with reference to FIG.

  That is, in the driving method (reset driving) described in FIG. 33, the driving transistor 11a and the EL element 15 are disconnected (the current does not flow), and the drain (D) terminal and the gate (G) ) Terminal (or source (S) terminal and gate (G) terminal, more generally, two terminals including the gate (G) terminal of the driving transistor), Thereafter, a second operation of performing current (voltage) programming on the driving transistor is performed. At least the second operation is performed after the first operation. In order to perform reset driving, the transistor 11b and the transistor 11c must be configured to be independently controlled as in the configuration of FIG.

  The image display state (if an instantaneous change can be observed), first, the pixel row for which current programming is performed is in the reset state (black display state), and current programming is performed after 1H (at this time) Is also in a black display state because the transistor 11d is off.) Next, a current is supplied to the EL element 15, and the pixel row emits light with a predetermined luminance (programmed current). That is, it should appear that the black pixel row moves from the top to the bottom of the screen, and the image is rewritten at the position where the pixel row passes. Although current programming is performed 1H after reset, this period may be within about 5H. This is because it takes a relatively long time for the reset of FIG. If this period is 5H, 5 pixel rows should be displayed in black (6 pixel rows if a current program pixel row is included).

  In addition, the reset state is not limited to performing one pixel row at a time, and the reset state may be simultaneously performed for a plurality of pixel rows. Alternatively, scanning may be performed while simultaneously resetting and overlapping each pixel row. For example, if four pixel rows are simultaneously reset, the pixel rows (1), (2), (3), and (4) are reset in the first horizontal scanning period (one unit), and the next second horizontal scan is performed. In the scanning period, the pixel rows (3), (4), (5), and (6) are reset, and in the next third horizontal scanning period, the pixel rows (5), (6), (7), and (8) are reset. Put it in a state. In addition, a driving state in which the pixel rows (7), (8), (9), and (10) are reset in the next fourth horizontal scanning period is exemplified. Of course, the drive states of FIGS. 33B and 33C are also performed in synchronization with the drive state of FIG.

Further, it goes without saying that the driving shown in FIGS. 33B and 33C may be carried out after all the pixels of one screen are reset at the same time or in the scanning state. Needless to say, the interlace drive state (interlaced scanning of one pixel row or a plurality of pixel rows) may be set to the reset state (interlace of one pixel row or a plurality of pixel rows). Moreover, you may implement a random reset state. Further, the description of the reset driving according to the present invention is a method of manipulating pixel rows (that is, controlling the vertical direction of the screen). However, the concept of reset driving does not limit the control direction to pixel rows. For example, it goes without saying that reset driving may be performed in the pixel column direction.

  Note that the reset driving in FIG. 33 can be combined with the N-fold pulse driving of the present invention or with interlaced driving to realize better image display. In particular, the configuration of FIG. 22 is intermittent N / K double pulse driving (a driving method in which a plurality of lighting regions are provided on one screen. This driving method is easy by controlling the gate signal line 17b and turning on / off the transistor 11d. (This has been described before.) Can be easily realized, so that a good image display can be realized without occurrence of flicker. This is an excellent feature of FIG. 22 or its modified configuration. Further, it goes without saying that further excellent image display can be realized by combining with other driving methods, for example, a reverse bias driving method, a precharge driving method, a punch-through voltage driving method, and the like described later. As described above, it is needless to say that reset driving can be performed in combination with other embodiments of the present specification as in the present invention.

  FIG. 34 is a configuration diagram of a display device that realizes reset driving. The gate driver circuit 12a controls the gate signal line 17a and the gate signal line 17b in FIG. The transistor 11b is on / off controlled by applying an on / off voltage to the gate signal line 17a. Further, the transistor 11d is on / off controlled by applying an on / off voltage to the gate signal line 17b. The gate driver circuit 12b controls the gate signal line 17c in FIG. The transistor 11c is on / off controlled by applying an on / off voltage to the gate signal line 17c.

  Therefore, the gate signal line 17a is operated by the gate driver circuit 12a, and the gate signal line 17c is operated by the gate driver circuit 12b. Therefore, the timing at which the transistor 11b is turned on to reset the driving transistor 11a and the timing at which the transistor 111c is turned on to perform current programming on the driving transistor 11a can be freely set. Other configurations are the same as or similar to those previously described, and thus description thereof is omitted.

  FIG. 35 is a timing chart of reset driving. When a turn-on voltage is applied to the gate signal line 17a to turn on the transistor 11b and the driving transistor 11a is reset, a turn-off voltage is applied to the gate signal line 17b and the transistor 11d is turned off. Therefore, the state shown in FIG. During this period, an Ib current flows.

  In the timing chart of FIG. 35, the reset time is 2H (the on-voltage is applied to the gate signal line 17a and the transistor 11b is turned on), but the invention is not limited to this. It may be 2H or more. If the reset can be performed at a very high speed, the reset time may be less than 1H. In addition, how long the reset period is set can be easily changed by the DATA (ST) pulse period input to the gate driver circuit 12. For example, if DATA input to the ST terminal is set to H level for 2H period, the reset period output from each gate signal line 17a becomes 2H period. Similarly, if DATA input to the ST terminal is set to the H level during the 5H period, the reset period output from each gate signal line 17a becomes the 5H period.

  After the reset of the 1H period, the ON voltage is applied to the gate signal line 17c (1) of the pixel row (1). When the transistor 11c is turned on, the program current Iw applied to the source signal line 18 is written to the driving transistor 11a via the transistor 11c.

After current programming, a turn-off voltage is applied to the gate signal line 17c of the pixel (1), the transistor 11c is turned off, and the pixel is disconnected from the source signal line. At the same time, a turn-off voltage is applied to the gate signal line 17a, and the reset state of the driving transistor 11a is canceled (in this period, it is more appropriate to express the current program state than the reset state). is there). Further, an on-voltage is applied to the gate signal line 17b, the transistor 11d is turned on, and a current programmed in the driving transistor 11a flows through the EL element 15. The pixel row (2) and subsequent pixels are the same as the pixel row (1), and the operation is obvious from FIG.

  In FIG. 35, the reset period is a 1H period. FIG. 36 shows an embodiment in which the reset period is 5H. The number of reset periods can be easily changed by the DATA (ST) pulse period input to the gate driver circuit 12. FIG. 36 shows an embodiment in which DATA input to the ST1 terminal of the gate driver circuit 12a is set to H level for 5H periods, and the reset period output from each gate signal line 17a is 5H periods. The longer the reset period, the more complete the reset and the better black display can be realized. However, the display luminance is reduced for the ratio of the reset period.

  FIG. 36 shows an example in which the reset period is 5H. Moreover, this reset state was a continuous state. However, the reset state is not limited to being performed continuously. For example, the signal output from each gate signal line 17a may be turned on / off every 1H. Such an on / off operation can be easily realized by operating an enable circuit (not shown) formed in the output stage of the shift register. Further, it can be easily realized by controlling the DATA (ST) pulse input to the gate driver circuit 12.

  In the circuit configuration of FIG. 34, the gate driver circuit 12a requires at least two shift register circuits (one for controlling the gate signal line 17a and the other for controlling the gate signal line 17b). Therefore, there is a problem that the circuit scale of the gate driver circuit 12a is increased. FIG. 37 shows an embodiment in which the gate driver circuit 12a has one shift register. A timing chart of an output signal obtained by operating the circuit of FIG. 37 is as shown in FIG. Note that FIG. 35 and FIG. 37 are different in the symbol of the gate signal line 17 output from the gate driver circuits 12a and 12b.

  As is apparent from the addition of the OR circuit 371 in FIG. 37, the output of each gate signal line 17a is ORed with the preceding stage output of the shift register circuit 61a. That is, the ON voltage is output from the gate signal line 17a during the 2H period. On the other hand, the output of the shift register circuit 61a is output as it is to the gate signal line 17c. Therefore, the on-voltage is applied during the 1H period.

  For example, when the second H level signal is output from the shift register circuit 61a, an ON voltage is output to the gate signal line 17c of the pixel 16 (1), and the pixel 16 (1) is in a current (voltage) program state. It is. At the same time, an on-voltage is output to the gate signal line 17a of the pixel 16 (2), the transistor 11b of the pixel 16 (2) is turned on, and the driving transistor 11a of the pixel 16 (2) is reset.

  Similarly, when the third H level signal is output from the shift register circuit 61a, an on-voltage is output to the gate signal line 17c of the pixel 16 (2), and the pixel 16 (2) is subjected to the current (voltage) program. State. At the same time, an ON voltage is also output to the pixel 16 (3 gate signal line 17a, the pixel 16 (3) transistor 11b is turned on, and the pixel 16 (3) driving transistor 11a is reset. An on-voltage is output from the gate signal line 17a, and an on-voltage is output to the gate signal line 17c for 1H period.

  In the programmed state, when the transistor 11b and the transistor 11c are turned on at the same time (FIG. 33 (b)), the transistor 11c is preceded by the transistor 11b when shifting to the non-programmed state (FIG. 33 (c)). When it is turned off, the reset state shown in FIG. In order to prevent this, the transistor 11c needs to be turned off after the transistor 11b. For this purpose, it is necessary to control the gate signal line 17a so that the ON voltage is applied before the gate signal line 17c.

  The above example is an example related to the pixel configuration of FIG. 32 (basically, FIG. 1). However, the present invention is not limited to this. For example, the pixel configuration of a current mirror as shown in FIG. 38 can be implemented. In FIG. 38, the N-fold pulse driving illustrated in FIGS. 13 and 15 can be realized by on / off controlling the transistor 11e. FIG. 39 is an explanatory diagram of an embodiment in the pixel configuration of the current mirror of FIG. Hereinafter, the reset driving method in the pixel configuration of the current mirror will be described with reference to FIG.

  As illustrated in FIG. 39A, the transistor 11c and the transistor 11e are turned off, and the transistor 11d is turned on. Then, the drain (D) terminal and the gate (G) terminal of the current programming transistor 11b are short-circuited, and an Ib current flows as shown in the figure. In general, the transistor 11b is current-programmed in the previous field (frame) and has the ability to flow current (the gate potential is held in the capacitor 19 for 1F period and is displayed as a matter of course. , Current does not flow when full black display is performed). In this state, when the transistor 11e is turned off and the transistor 11d is turned on, the drive current Ib flows in the direction of the gate (G) terminal of the transistor 11a (the gate (G) terminal and the drain (D) terminal are short-circuited). ) Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the transistor 11a is reset (a state in which no current flows). Further, since the gate (G) terminal of the driving transistor 11b is common to the gate (G) terminal of the current programming transistor 11a, the driving transistor 11b is also reset.

  The reset state (state in which no current flows) of the transistors 11a and 11b is equivalent to the state in which the offset voltage of the voltage offset canceller system described in FIG. That is, in the state of FIG. 39 (a), an offset voltage (starting voltage at which current starts to flow) is applied between the terminals of the capacitor 19. By applying a voltage higher than the absolute value of this voltage, current flows through the transistor 11. Will be held. This offset voltage has a different voltage value depending on the characteristics of the transistors 11a and 11b. Therefore, by performing the operation of FIG. 39A, the capacitor 19 of each pixel is maintained in a state in which no current flows through the transistor 11a and the transistor 11b (that is, a black display current (almost equal to 0)). (Reset to the starting voltage at which current begins to flow).

  39A, as in FIG. 33A, the Ib current flows and the terminal voltage of the capacitor 19 tends to decrease as the reset execution time increases. Therefore, the execution time of FIG. 39A needs to be a fixed value. According to experiments and examinations, it is preferable that the execution time of FIG. 39A is 1H or more and 10H (10 horizontal scanning periods) or less. Furthermore, it is preferable to set it to 1H or more and 5H or less. Alternatively, it is preferably 20 μsec or more and 2 msec or less. The same applies to the driving method shown in FIG.

The same applies to FIG. 33A, but when the reset state of FIG. 39A and the current program state of FIG. 39B are performed in synchronization, the reset state of FIG. Since the period until the current programming state in FIG. 39B is a fixed value (constant value), there is no problem (the value is fixed). That is, the period from the reset state of FIG. 33A or FIG. 39A to the current program state of FIG. 33B or FIG. 39B is set to 1H or more and 10H (10 horizontal scanning periods) or less. It is preferable. Furthermore, it is preferable to set it to 1H or more and 5H or less. Alternatively, it is preferably 20 μsec or more and 2 msec or less. If this period is short, the driving transistor 11 is not completely reset. If it is too long, the driving transistor 11 is completely turned off, and this time, it takes a long time to program the current. In addition, the brightness of the screen 50 also decreases.

  After performing FIG. 39A, the state shown in FIG. FIG. 39B shows a state where the transistors 11c and 11d are turned on and the transistor 11e is turned off. The state shown in FIG. 39B is a state where current programming is performed. That is, the program current Iw is output (or absorbed) from the source driver circuit 14, and this program current Iw is supplied to the current programming transistor 11a. The potential of the gate (G) terminal of the driving transistor 11b is set in the capacitor 19 so that the program current Iw flows.

  If the program current Iw is 0 (A) (black display), the transistor 11b remains in a state where no current flows as shown in FIG. 33A, so that a good black display can be realized. . Further, in the case of performing white display current programming in FIG. 39B, even if there is a variation in the characteristics of the driving transistors in each pixel, the offset voltage in the completely black display state (in the characteristics of each driving transistor). A current program is performed from the start voltage at which the set current flows accordingly. Therefore, the time programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to the characteristic variation of the transistor 11a or the transistor 11b, and a good image display can be realized.

  After the current programming in FIG. 39B, as shown in FIG. 39C, the transistors 11c and 11d are turned off, the transistor 11e is turned on, and the program current Iw (= Ie) from the driving transistor 11b is turned on. Is caused to flow through the EL element 15 to cause the EL element 15 to emit light. Also with respect to FIG. 39 (c), since it has been described previously, details are omitted.

  In the driving method (reset driving) described with reference to FIGS. 33 and 39, the driving transistor 11a or 11b and the EL element 15 are disconnected (the current does not flow. Performed by the transistor 11e or the transistor 11d) and the driving is performed. Between a drain (D) terminal and a gate (G) terminal of a transistor for driving (or a source (S) terminal and a gate (G) terminal, more generally two terminals including a gate (G) terminal of a driving transistor)) A first operation for short-circuiting and a second operation for performing a current (voltage) program on the driving transistor after the operation are performed. At least the second operation is performed after the first operation. Note that the operation of disconnecting the driving transistor 11a or the transistor 11b and the EL element 15 in the first operation is not necessarily an essential condition. If the driving transistor 11a or the transistor 11b and the EL element 15 in the first operation are not disconnected, the first operation of shorting between the drain (D) terminal and the gate (G) terminal of the driving transistor is performed. This is because there may be a case where a slight variation in the reset state may occur. This is determined by examining the transistor characteristics of the fabricated array.

  The pixel configuration of the current mirror in FIG. 39 is a driving method in which the current transistor transistor 11b is reset as a result by resetting the current program transistor 11a.

In the pixel configuration of the current mirror in FIG. 39, it is not always necessary to disconnect the driving transistor 11b and the EL element 15 in the reset state. Accordingly, the drain (D) terminal and the gate (G) terminal (or the source (S) terminal and the gate (G) terminal) of the current programming transistor a, or more generally, the gate (G) terminal of the current programming transistor. A first operation for short-circuiting between the two terminals including the first terminal and the second terminal including the gate (G) terminal of the driving transistor), and a second program for performing current (voltage) programming on the current programming transistor after the first operation. Operation. At least the second operation is performed after the first operation.

  In the image display state (if an instantaneous change can be observed), first, the pixel row for which current programming is performed is in a reset state (black display state), and current programming is performed after a predetermined H. From the top to the bottom of the screen, the black pixel row should move, and the image should appear to be rewritten at the position where this pixel row has passed.

  Although the above embodiments have been described with a focus on the pixel configuration of the current program, the reset driving of the present invention can also be applied to the pixel configuration of the voltage program. FIG. 43 is an explanatory diagram of the pixel configuration (panel configuration) of the present invention for performing reset driving in the pixel configuration of the voltage program.

  In the pixel configuration of FIG. 43, a transistor 11e for resetting the driving transistor 11a is formed. When a turn-on voltage is applied to the gate signal line 17e, the transistor 11e is turned on, and the gate (G) terminal and the drain (D) terminal of the driving transistor 11a are short-circuited. A transistor 11d that cuts off the current path between the EL element 15 and the driving transistor 11a is formed. Hereinafter, the reset driving method of the present invention in the pixel configuration of the voltage program will be described with reference to FIG.

  As illustrated in FIG. 44A, the transistor 11b and the transistor 11d are turned off, and the transistor 11e is turned on. The drain (D) terminal and the gate (G) terminal of the driving transistor 11a are short-circuited, and an Ib current flows as shown in the figure. Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the driving transistor 11a is reset (a state in which no current flows). Before resetting the transistor 11a, as described in FIG. 33 or FIG. 39, in synchronization with the HD synchronization signal, the transistor 11d is first turned on, the transistor 11e is turned off, and a current flows through the transistor 11a. Keep it. Thereafter, the operation shown in FIG.

  The reset state (state in which no current flows) of the transistors 11a and 11b is equivalent to the state in which the offset voltage of the voltage offset canceller system described in FIG. That is, in the state of FIG. 44A, the offset voltage (reset voltage) is held between the terminals of the capacitor 19. This reset voltage has a different voltage value depending on the characteristics of the driving transistor 11a. That is, by performing the operation of FIG. 44A, the driving transistor 11a does not pass a current through the capacitor 19 of each pixel (that is, a state where a black display current (almost equal to 0)) is maintained. (Reset to the starting voltage at which current begins to flow).

  In the voltage-programmed pixel configuration, as in the current-programmed pixel configuration, the Ib current flows and the terminal voltage of the capacitor 19 tends to decrease as the reset execution time in FIG. . Therefore, the execution time of FIG. 44 (a) needs to be a fixed value. The implementation time is preferably 0.2H or more and 5H (5 horizontal scanning periods) or less. Furthermore, it is preferable to set it to 0.5H or more and 4H or less. Or it is preferable to set it as 2 to 400 microseconds.

The gate signal line 17e is preferably shared with the gate signal line 17a in the previous pixel row. That is, the gate signal line 17e and the gate signal line 17a of the previous pixel row are formed in a short state. This configuration is called a pre-stage gate control system. Note that the pre-stage gate control method uses a gate signal line waveform of a pixel row selected at least 1H before the target pixel row. Therefore, it is not limited to one pixel row before. For example, the driving transistor 11a of the pixel of interest may be reset using the signal waveform of the gate signal line two rows before.

  A more specific description of the pre-stage gate control method is as follows. A pixel row of interest is an (N) pixel row, and its gate signal lines are a gate signal line 17e (N) and a gate signal line 17a (N). The pixel row in the previous stage selected 1H before is the (N-1) pixel row, and the gate signal lines are the gate signal line 17e (N-1) and the gate signal line 17a (N-1). . A pixel row selected after 1H after the pixel row of interest is an (N + 1) pixel row, and its gate signal lines are a gate signal line 17e (N + 1) and a gate signal line 17a (N + 1).

  In the (N−1) H period, when the ON voltage is applied to the gate signal line 17a (N−1) of the (N−1) th pixel row, the gate signal line 17e (N) of the (N) th pixel row. ) Is also applied with an ON voltage. This is because the gate signal line 17e (N) and the gate signal line 17a (N-1) in the previous pixel row are formed in a short state. Therefore, the transistor 11b (N-1) of the pixel in the (N-1) th pixel row is turned on, and the voltage of the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N-1). At the same time, the transistor 11e (N) of the pixel in the (N) th pixel row is turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N) are short-circuited, and the driving transistor 11a (N ) Is reset.

  In the (N) period following the (N−1) H period, when the ON voltage is applied to the gate signal line 17a (N) of the (N) pixel row, the gate signal of the (N + 1) pixel row. The on-voltage is also applied to the line 17e (N + 1). Accordingly, the transistor 11b (N) of the pixel in the (N) th pixel row is turned on, and the voltage applied to the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N). At the same time, the transistor 11e (N + 1) of the pixel in the (N + 1) th pixel row is turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N + 1) are short-circuited, and the driving transistor 11a (N + 1) ) Is reset.

  Similarly, in the (N + 1) period subsequent to the (N) H period, when the ON voltage is applied to the gate signal line 17a (N + 1) of the (N + 1) pixel row, the (N + 2) pixel row The on-voltage is also applied to the gate signal line 17e (N + 2). Accordingly, the transistor 11b (N + 1) of the pixel in the (N + 1) th pixel row is turned on, and the voltage applied to the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N + 1). At the same time, the transistor 11e (N + 2) of the pixel in the (N + 2) th pixel row is turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N + 2) are short-circuited, and the driving transistor 11a (N + 2) ) Is reset.

  In the above-described pre-stage gate control system of the present invention, the driving transistor 11a is reset for 1H period, and then the voltage (current) program is executed.

The same applies to FIG. 33A, but when the reset state of FIG. 44A and the voltage program state of FIG. 44B are performed in synchronization, the reset state of FIG. There is no problem because the period until the current programming state in FIG. 44 (b) is a fixed value (constant value). If this period is short, the driving transistor 11 is not completely reset. If it is too long, the driving transistor 11a is completely turned off, and this time, it takes a long time to program the current. In addition, the brightness of the screen 12 is also reduced.

  After implementing FIG. 44A, the state shown in FIG. 44B is obtained. FIG. 44B shows a state in which the transistor 11b is turned on and the transistors 11e and 11d are turned off. The state shown in FIG. 44B is a state where voltage programming is performed. That is, a program voltage is output from the source driver circuit 14, and this program voltage is written to the gate (G) terminal of the driving transistor 11a (the potential of the gate (G) terminal of the driving transistor 11a is set in the capacitor 19). In the case of the voltage programming method, it is not always necessary to turn off the transistor 11d during voltage programming. Further, it is a combination of the N-fold pulse drive shown in FIGS. 13 and 15 or the like, or the intermittent N / K-fold pulse drive as described above (a drive method in which a plurality of lighting regions are provided on one screen. The transistor 11e is not necessary unless the transistor 11e is easily turned on / off. Since this has been described before, the description is omitted.

  When the voltage program for white display is performed by the configuration of FIG. 43 or the driving method of FIG. 44, the offset voltage of each black display state (each driving transistor is completely different even if the characteristics of the driving transistor for each pixel vary. The voltage program is performed from the starting voltage at which a current set according to the characteristics of the current flows. Therefore, the time programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to the characteristic variation of the transistor 11a, and a good image display can be realized.

  After the current programming of FIG. 44B, as shown in FIG. 44C, the transistor 11b is turned off, the transistor 11d is turned on, and the program current from the driving transistor 11a is supplied to the EL element 15, and the EL The element 15 is caused to emit light.

  As described above, in the reset driving of the present invention in the voltage program of FIG. 43, first, in synchronization with the HD synchronization signal, the transistor 11d is first turned on, the transistor 11e is turned off, and the current flows through the transistor 11a. 1, the transistor 11 a and the EL element 15 are disconnected, and the drain (D) terminal and the gate (G) terminal (or the source (S) terminal and the gate (G) terminal of the driving transistor 11 a, In other words, a second operation for short-circuiting between the gate (G) terminals of the driving transistor) and a third operation for performing voltage programming on the driving transistor 11a after the above operation are performed. To do.

  In the above embodiment, the transistor 11d is turned on / off to control the current flowing from the driving transistor element 11a (in the pixel configuration of FIG. 1) to the EL element 15. In order to turn on and off the transistor 11d, it is necessary to scan the gate signal line 17b, and the shift register 61 (gate circuit 12) is necessary for scanning. However, the shift register 61 is large in scale and cannot be narrowed by using the shift register 61 to control the gate signal line 17b. The method described in FIG. 40 solves this problem.

  Although the present invention will be described mainly by exemplifying the pixel configuration of the current program illustrated in FIG. 1 and the like, the present invention is not limited to this, and other current program configurations described in FIG. Needless to say, the present invention can be applied to a pixel configuration. Needless to say, the technical concept of turning on / off in a block can be applied to the pixel configuration of the voltage program shown in FIG. Further, since the present invention is a system in which the current flowing through the EL element 15 is intermittent, it goes without saying that the present invention can be combined with a system for applying a reverse bias voltage described with reference to FIG. As described above, the present invention can be implemented in combination with other embodiments.

  FIG. 40 shows an embodiment of the block drive system. First, for ease of explanation, the description will be made assuming that the gate driver circuit 12 is formed directly on the substrate 71 or the gate driver IC 12 of a silicon chip is mounted on the substrate 71. Further, the source driver 14 and the source signal line 18 are omitted because the drawing becomes complicated.

  In FIG. 40, the gate signal line 17a is connected to the gate driver circuit 12. On the other hand, the gate signal line 17 b of each pixel is connected to the lighting control line 401. In FIG. 40, four gate signal lines 17b are connected to one lighting control line 401.

  Needless to say, blocking with the four gate signal lines 17b is not limited to this, and may be more than that. In general, the display area 50 is preferably divided into at least five or more. More preferably, it is preferably divided into 10 or more. Furthermore, it is preferable to divide into 20 or more. When the number of divisions is small, flicker is easy to see. If the number of divisions is too large, the number of lighting control lines 401 increases, and the layout of the control lines 401 becomes difficult.

  Therefore, in the case of the QCIF display panel, since the number of vertical scanning lines is 220, it is necessary to block at least 220/5 = 44 or more, and preferably block at 220/10 = 11 or more. There is a need to. However, when two blocks are formed on the odd and even lines, the occurrence of flicker is relatively small even at a low frame rate, and thus two blocks may be sufficient.

  In the embodiment of FIG. 40, an ON voltage (Vgl) or an OFF voltage (Vgh) is sequentially applied to the lighting control lines 401a, 401b, 401c, 401d. The current that flows is turned on and off.

  In the embodiment of FIG. 40, the gate signal line 17b and the lighting control line 401 do not cross each other. Therefore, a short defect between the gate signal line 17b and the lighting control line 401 does not occur. Further, since the gate signal line 17b and the lighting control line 401 are not capacitively coupled, the capacitance addition when the gate signal line 17b side is viewed from the lighting control line 401 is extremely small. Therefore, it is easy to drive the lighting control line 401.

  A gate signal line 17 a is connected to the gate driver 12. By applying an on voltage to the gate signal line 17a, a pixel row is selected, the transistors 11b and 11c of each selected pixel are turned on, and the current (voltage) applied to the source signal line 18 is supplied to each pixel. Program the capacitor 19. On the other hand, the gate signal line 17b is connected to the gate (G) terminal of the transistor 11d of each pixel. Therefore, when the on-voltage (Vgl) is applied to the lighting control line 401, a current path is formed between the drive transistor 11a and the EL element 15, and conversely, when the off-voltage (Vgh) is applied, the EL element 15 Open the anode terminal.

  Note that the control timing of the on / off voltage applied to the lighting control line 401 and the timing of the pixel row selection voltage (Vgl) output from the gate driver circuit 12 to the gate signal line 17a are synchronized with one horizontal scanning clock (1H). It is preferable. However, the present invention is not limited to this.

The signal applied to the lighting control line 401 simply turns on and off the current to the EL element 15. Further, it is not necessary to be synchronized with the image data output from the source driver 14. This is because the signal applied to the lighting control line 401 controls the current programmed in the capacitor 19 of each pixel 16. Therefore, it is not necessarily required to be synchronized with the pixel row selection signal. Even in the case of synchronization, the clock is not limited to the 1H signal, and may be 1 / 2H or 1 / 4H.

  Even in the pixel configuration of the current mirror shown in FIG. 38, the transistor 11e can be controlled to be turned on / off by connecting the gate signal line 17b to the lighting control line 401. Therefore, block driving can be realized.

  In FIG. 41, ON / OFF voltages (Vgl, Vgh) are applied to the lighting control line 401 to control lighting of the EL elements 15 in units of block pixel rows. However, the present invention is not limited to this. As illustrated in FIG. 158, a lighting control line driver 1581 may be formed in the lighting control line 401.

  The lighting control line driver 1581 is exemplified by the output stage of the gate driver 12 (inverter circuit, output buffer, etc.). The lighting control line driver 1581 is supplied with a driving voltage (Vgh, Vgl) and an on / off switching signal by the driver control line. The lighting control line 1581 outputs an on / off voltage to the lighting control line 401 by an on / off switching signal. The image display state and driving method are the same as or similar to those in FIG. That is, the lighting control line 401 is controlled by the lighting control line driver 1581 made of a semiconductor circuit.

  A plurality of lighting control line drivers 1581 may be formed on one lighting control line 401. Alternatively, a large number of lighting control lines 401 may be formed (increasing the number of block divisions), and one or a plurality of lighting control line drivers 1581 may be arranged or formed on each lighting control line 401.

  The lighting control driver 1581 may be formed separately using a semiconductor silicon chip in addition to a method of forming directly on the substrate 71 using low-temperature polysilicon technology or the like, and this chip IC may be mounted on the substrate 71 using COG technology or the like. Good.

  The lighting control line driver 1581 can be regarded as a gate driver circuit 12b having a small number of output terminals. That is, the gate signal line 17b is commonly connected (short-circuited) to the lighting control line 401 for each block, and the gate driver circuit 12b that regards the lighting control line 401 as the gate signal line 17b is formed or arranged.

  By forming or arranging the lighting control line driver 1581, the driving capability of the lighting control line 401 is improved. In the configuration of FIG. 40, a luminance gradient or the like may occur, but in the configuration of FIG. 158, it does not occur at all. . In addition, since the number of block divisions can be increased, there is no block boundary. Further, since the formation area of the lighting control line driver 1581 can be very small, a narrow frame can be realized.

  In FIG. 32, if the gate signal line 17a is connected to the lighting control line 401 and resetting is performed, the block driving can be realized. That is, the block driving of the present invention is a driving method in which a plurality of pixel rows are simultaneously not lit (or black display) with one control line.

  In the above embodiment, one selected pixel row is arranged (formed) for each pixel row. The present invention is not limited to this, and one selection gate signal line may be arranged (formed) in a plurality of pixel rows.

FIG. 41 shows an example. In order to facilitate the description, the pixel configuration will be described mainly using the case of FIG. In FIG. 41, the pixel row selection gate signal line 17a simultaneously selects three pixels (16R, 16G, 16B). The symbol R means a red pixel relationship, and G
The symbol B means green pixel relation, and the symbol B means blue pixel relation.

  Therefore, by selecting the gate signal line 17a, the pixel 16R, the pixel 16G, and the pixel 16B are simultaneously selected to enter a data writing state. The pixel 16R writes data from the source signal line 18R to the capacitor 19R, and the pixel 16G writes data from the source signal line 18G to the capacitor 19G. The pixel 16B writes data from the source signal line 18B to the capacitor 19B.

  The transistor 11d of the pixel 16R is connected to the gate signal line 17bR. The transistor 11d of the pixel 16G is connected to the gate signal line 17bG, and the transistor 11d of the pixel 16B is connected to the gate signal line 17bB. Accordingly, the EL element 15R of the pixel 16R, the EL element 15G of the pixel 16G, and the EL element 15B of the pixel 16B can be separately controlled on and off. That is, the EL element 15R, the EL element 15G, and the EL element 15B can individually control the lighting time and the lighting cycle by controlling the gate signal lines 17bR, 17bG, and 17bB.

  In order to realize this operation, in the configuration of FIG. 6, the shift register circuit 61 that scans the gate signal line 17a, the shift register circuit 61 that scans the gate signal line 17bR, and the shift register that scans the gate signal line 17bG. It is appropriate to form (place) four circuits 61 and shift register circuit 61 that scans gate signal line 17bB.

  Although a current N times the predetermined current is supplied to the source signal line 18 and a current N times the predetermined current is supplied to the EL element 15 for a period of 1 / N, this cannot be realized in practice. This is because the signal pulse applied to the gate signal line 17 actually penetrates the capacitor 19 and a desired voltage value (current value) cannot be set in the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set for the capacitor 19. For example, even if it is driven to set a current value 10 times, only about 5 times the current is set in the capacitor 19. For example, even when N = 10, the current that actually flows through the EL element 15 is the same as when N = 5. Therefore, the present invention is a method of setting the current value N times and driving the EL element 15 so that a current proportional to or corresponding to the N times flows through the EL element 15. Alternatively, it is a driving method in which a current larger than a desired value is applied to the EL element 15 in a pulse shape.

  Further, a current (voltage) program is performed on the drive transistor 11a (in the case of FIG. 1) with a current that is higher than a desired value (a current that is higher than the desired luminance when a current is continuously passed through the EL element 15 as it is). The light emission luminance of the desired EL element is obtained by intermittently flowing the current flowing through the EL element 15.

  Note that a compensation circuit that penetrates the capacitor 19 is introduced into the source driver circuit 14. This will be explained later.

  Further, the switching transistors 11b, 11c, etc. in FIG. 1 and the like are preferably formed of an N channel. This is because the penetration voltage to the capacitor 19 is reduced. Further, since the off-leakage of the capacitor 19 is also reduced, it can be applied to a low frame rate of 10 Hz or less.

  Further, depending on the pixel configuration, when the punch-through voltage acts in the direction of increasing the current flowing through the EL element 15, the white peak current increases and the contrast of the image display increases. Therefore, a good image display can be realized.

  On the other hand, a method of making the black display better by generating a punch-through by setting the switching transistors 11b and 11c in FIG. 1 to the P channel is also effective. When the P-channel transistor 11b is turned off, the voltage becomes Vgh. Therefore, the terminal voltage of the capacitor 19 is slightly shifted to the Vdd side. For this reason, the gate (G) terminal voltage of the transistor 11a rises, resulting in a black display. In addition, since the current value for the first gradation display can be increased (a constant base current can be made to flow until gradation 1), a shortage of write current can be reduced by the current programming method.

  In addition, a configuration in which a capacitor 19b is positively formed between the gate signal line 17a and the gate (G) terminal of the transistor 11a to increase the penetration voltage is also effective (see FIG. 42A). The capacity of the capacitor 19b is preferably set to 1/50 or more and 1/10 or less of the capacity of the regular capacitor 19a. Furthermore, it is preferable to set it to 1/40 or more and 1/15 or less. Alternatively, the capacitance is set to be 1 to 10 times the source-gate (source-drain (SG) or gate-drain (GD)) capacitance of the transistor 11b. More preferably, it is preferable to be 2 times or more and 6 times or less of the SG capacity. Note that the capacitor 19b may be formed or disposed between one terminal of the capacitor 19a (the gate (G) terminal of the transistor 11a) and the source (S) terminal of the transistor 11d. Also in this case, the capacity and the like are the same as the values described above.

The capacitance of the penetration voltage generating capacitor 19b (capacitance is Cb (pF)) is the capacitance of the charge holding capacitor 19a (capacitance and Ca (pF)) and the white peak current of the transistor 11a (image) When the current of black display is applied to the gate (G) terminal voltage Vw of the display maximum luminance (white raster at the maximum brightness) (basically, the current is 0. That is, when black display is used for image display). The gate (G) terminal voltage Vb is related. These relationships are
Ca / (200Cb) ≦ | Vw−Vb | ≦ Ca / (8Cb)
It is preferable to satisfy the following conditions. Note that | Vw−Vb | is the absolute value of the difference between the terminal voltage at the time of white display and the terminal voltage at the time of black display of the driving transistor (that is, the changing voltage width).

More preferably,
Ca / (100Cb) ≦ | Vw−Vb | ≦ Ca / (10Cb)
It is preferable to satisfy the following conditions.

  The transistor 11b is a P channel, and this P channel is at least a double gate or more. This is more than a triple gate. More preferably, the number of gates is 4 or more. And it is preferable to form or arrange | position the capacitor | condenser of 1 to 10 times the capacity | capacitance (capacitance when the transistor is on) of the transistor 11b in parallel in the source-gate (SG or gate-drain (GD)) capacity.

  The above items are effective not only in the pixel configuration of FIG. 1 but also in other pixel configurations. For example, as shown in FIG. 42B, in the pixel configuration of the current mirror, a capacitor for generating a penetration is disposed or formed between the gate signal line 17a or 17b and the gate (G) terminal of the transistor 11a. The N channel of the switching transistor 11c is made more than a double gate. Alternatively, the switching transistors 11c and 11d are P-channel and have a triple gate or more.

In the voltage program configuration 41, a punch-through voltage generating capacitor 19c is formed or arranged between the gate signal line 17c and the gate (G) terminal of the driving transistor 11a. The switching transistor 11c is a triple gate or more. The penetration voltage generating capacitor 19c is connected to the drain (D) terminal (capacitor 19c) of the transistor 11c.
b side) and the gate signal line 17a. The punch-through voltage generating capacitor 19c may be disposed between the gate (G) terminal of the transistor 11a and the gate signal line 17a. Further, the penetration voltage generating capacitor 19c may be disposed between the drain (D) terminal (capacitor 19b side) of the transistor 11c and the gate signal line 17c.

  Further, the capacitance of the charge holding capacitor 19a is Ca, the source-gate capacitance Cc of the switching transistor 11c or 11d) (a value obtained by adding the capacitance if there is a penetration capacitor), and the gate signal When a high voltage signal (Vgh) applied to the line is used and a low voltage signal (Vgl) applied to the gate signal line is used, a satisfactory black display can be realized by configuring so as to satisfy the following conditions. .

0.05 (V) ≦ (Vgh−Vgl) × (Cc / Ca) ≦ 0.8 (V)
More preferably, it is preferable to satisfy the following conditions.

0.1 (V) ≦ (Vgh−Vgl) × (Cc / Ca) ≦ 0.5 (V)
The above items are also effective for the pixel configuration shown in FIG. In the pixel configuration of the voltage program of FIG. 43, a penetration voltage generating capacitor 19b is formed or disposed between the gate (G) terminal of the transistor 11a and the gate signal line 17a.

  Note that the capacitor 19b for generating a penetration voltage is formed by a source wiring and a gate wiring of a transistor. However, since the source width of the transistor 11 is widened and overlapped with the gate signal line 17, the transistor 11 may not be clearly separated from the transistor in practice.

  In addition, a method of forming a capacitor 19b for punch-through voltage by forming the switching transistors 11b and 11c (in the case of the configuration of FIG. 1) larger than necessary is also within the scope of the present invention. The switching transistors 11b and 11c are often formed with a channel width W / channel length L = 6/6 μm. Increasing this to W also constitutes a punch-through voltage capacitor 19b. For example, a configuration in which the ratio of W: L is 2: 1 or more and 20: 1 or less is exemplified. Preferably, the W: L ratio is 3: 1 or more and 10: 1 or less.

  Further, the penetration voltage capacitor 19b is preferably changed in size (capacitance) depending on R, G, and B modulated by the pixel. This is because the drive currents of the R, G, and B EL elements 15 are different. This is also because the cut-off voltage of the EL element 15 is different. Therefore, the voltage (current) programmed in the gate (G) terminal of the driving transistor 11a of the EL element 15 is different. For example, when the capacitor 11bR of the R pixel is 0.02 pF, the capacitors 11bG and 11bB of the other colors (G and B pixels) are 0.025 pF. Further, when the capacitor 11bR of the R pixel is set to 0.02 pF, the capacitor 11bG and 0.03 pF of the G pixel are set, and the capacitor 11bB of the B pixel is set to 0.025 pF. Thus, the drive current of the offset can be adjusted for each RGB by changing the capacitance of the capacitor 11b for each of the R, G, and B pixels. Therefore, the black display level of each RGB can be set to an optimum value.

In the above description, the capacitance of the punch-through voltage generating capacitor 19b is changed. However, the punch-through voltage is a relative value of the capacities of the holding capacitor 19a and the punch-through voltage generating capacitor 19b. Therefore, the capacitor 19b is not limited to being changed between R, G, and B pixels. That is, the capacitance of the holding capacitor 19a may be changed. For example, if the capacitor 11aR of the R pixel is 1.0 pF, the capacitor 11aG and 1.2 pF of the G pixel are set, and the capacitor 11aB of the B pixel is 0.9 pF. At this time, the capacitance of the penetration capacitor 19b is a common value for R, G, and B. Therefore, in the present invention, the capacitance ratio between the holding capacitor 19a and the punch-through voltage generating capacitor 19b is different from at least one of the R, G, and B pixels. Note that both the capacitance of the holding capacitor 19a and the capacitance of the penetration voltage generating capacitor 19b may be changed in the R, G, and B pixels.

  Further, the capacitance of the penetration voltage capacitor 19b may be changed on the left and right of the screen 50. Since the pixel 16 located near the gate driver 12 is arranged on the signal supply side, the rise of the gate signal is fast (because the slew rate is high), so that the penetration voltage becomes large. The pixel arranged (formed) at the end of the gate signal line 17 has a dull signal waveform (because the gate signal line 17 has a capacity). This is because the rise of the gate signal is slow (the slew rate is slow), and thus the punch-through voltage becomes small. Therefore, the penetration voltage capacitor 19b of the pixel 16 close to the connection side with the gate driver 12 is reduced. Further, the end of the gate signal line 17 enlarges the capacitor 19b. For example, the capacitance of the capacitor is changed by about 10% on the left and right sides of the screen.

  The punch-through voltage generated is determined by the capacitance ratio of the holding capacitor 19a and the punch-through voltage generating capacitor 19b. Therefore, although the size of the penetration voltage generating capacitor 19b is changed between the left and right sides of the screen, the present invention is not limited to this. The penetration voltage generating capacitor 19b may be constant on the left and right sides of the screen, and the capacitance of the charge holding capacitor 19a may be changed on the left and right sides of the screen. Needless to say, both the penetration voltage generating capacitor 19b and the capacitance of the charge holding capacitor 19a may be changed on the left and right sides of the screen.

  The problem of the N-fold pulse drive of the present invention is that the current applied to the EL element 15 is instantaneous, but is N times larger than the conventional one. If the current is large, the life of the EL element may be reduced. In order to solve this problem, it is effective to apply a reverse bias voltage Vm to the EL element 15.

  In the EL element 15, electrons are injected from the cathode (cathode) into the electron transport layer and simultaneously holes are also injected from the anode (anode) into the hole transport layer. The injected electrons and holes move to the counter electrode by the applied electric field. At that time, carriers are trapped in the organic layer or carriers are accumulated due to a difference in energy level at the interface of the light emitting layer.

  When space charge is accumulated in the organic layer, the molecule is oxidized or reduced, and the generated radical anion molecule or radical cation molecule is unstable. It is known that this causes an increase in driving voltage. In order to prevent this, the device structure is changed as an example, and a reverse voltage is applied.

  When a reverse bias voltage is applied, a reverse current is applied, so that injected electrons and holes are extracted to the cathode and the anode, respectively. Thereby, it becomes possible to extend the lifetime by eliminating the formation of space charge in the organic layer and suppressing the electrochemical degradation of the molecules.

  FIG. 45 shows changes in the reverse bias voltage Vm and the terminal voltage of the EL element 15. This terminal voltage is when a rated current is applied to the EL element 15. FIG. 45 shows the case where the current passed through the EL element 15 is a current density of 100 A / square meter, but the tendency of FIG. 45 is almost the same as the case where the current density is 50 to 100 A / square meter. Therefore, it is estimated that it can be applied in a wide range of current densities.

The vertical axis represents the ratio of the initial terminal voltage of the EL element 15 to the terminal voltage after 2500 hours. For example, the terminal voltage when a current density of 100 A / square meter is applied at an elapsed time of 0 hour is 8 (V), and the terminal current is applied when a current density of 100 A / square meter is applied at an elapsed time of 2500 hours. If the voltage is 10 (V), the terminal voltage ratio is 10/8 = 1.25.

  The horizontal axis represents the ratio of the rated terminal voltage V0 to the product of the reverse bias voltage Vm and the time t1 when the reverse bias voltage is applied in one cycle. For example, if the reverse bias voltage Vm is applied for 1/2 (half) at 60 Hz (in particular, 60 Hz is meaningless), t1 = 0.5. If the terminal voltage (rated terminal voltage) when the current density of 100 A / square meter is applied at the elapsed time of 0 hour is 8 (V) and the reverse bias voltage Vm is 8 (V), Bias voltage × t1 | / (rated terminal voltage × t2) = | −8 (V) × 0.5 | / (8 (V) × 0.5) = 1.0.

  According to FIG. 45, when | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.0 or more, the terminal voltage ratio does not change (it does not change from the initial rated terminal voltage). The effect of applying the reverse bias voltage Vm is well demonstrated. However, the terminal voltage ratio tends to increase when | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 or more. Therefore, the magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or the ratio between t1 and t2) are set so that | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.0 or more. It is good to decide. Preferably, the magnitude of the reverse bias voltage Vm, the application time ratio t1, and the like are determined so that | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 or less.

  However, when bias driving is performed, it is necessary to alternately apply the reverse bias Vm and the rated current. When trying to make the average luminance per unit time equal between samples A and B as shown in FIG. 46, when applying a reverse bias voltage, it is necessary to flow a higher current instantaneously than when not applying it. . Therefore, the terminal voltage of the EL element 15 when the reverse bias voltage Vm is applied (sample A in FIG. 46) also increases.

  However, in FIG. 45, even in a driving method in which a reverse bias voltage is applied, the rated terminal voltage V0 is a terminal voltage that satisfies the average luminance (that is, a terminal voltage that turns on the EL element 15). According to the example, it is the terminal voltage when a current density of 200 A / square meter is applied, but since it is ½ duty, the average luminance in one cycle is the luminance at a current density of 200 A / square meter. ).

  The above items assume that the EL element 15 is in a white raster display (when a maximum current is applied to the EL elements on the entire screen). However, when displaying an image on an EL display device, it is a natural image and a gradation display is performed. Therefore, the white peak current of the EL element 15 (current flowing in the maximum white display. In the specific example of the present specification, the average current density of 100 A / square meter) is not constantly flowing.

  In general, when video display is performed, the current applied to each EL element 15 (current flowing) is a white peak current (current flowing at the rated terminal voltage. According to a specific example of the present specification, the current density is 100 A. / Square meter current).

Therefore, in the embodiment of FIG. 45, it is necessary to multiply the value on the horizontal axis by 0.2 when performing video display. Therefore, the magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or the ratio between t1 and t2) so that | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 0.2 or more. ) Should be determined. Preferably, the magnitude and the application time ratio of the reverse bias voltage Vm are such that | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 × 0.2 = 0.35 or less. It is good to determine t1 etc.

  That is, on the horizontal axis of FIG. 45 (| reverse bias voltage × t1 | / (rated terminal voltage × t2)), the value of 1.0 needs to be 0.2. Therefore, when an image is displayed on the display panel (this use state is normal. A white raster will not always be displayed) | reverse bias voltage × t1 | / (rated terminal voltage × t2) The reverse bias voltage Vm is applied for a predetermined time t1 so that becomes larger than 0.2. Further, even if the value of | reverse bias voltage × t1 | / (rated terminal voltage × t2) increases, the increase in the terminal voltage ratio is not large as shown in FIG. Therefore, the upper limit value may be set so that the value of | reverse bias voltage × t1 | / (rated terminal voltage × t2) satisfies 1.75 or less in consideration of performing white raster display.

  Hereinafter, the reverse bias system of the present invention will be described with reference to the drawings. The present invention is basically based on the application of the reverse bias voltage Vm (current) during a period when no current flows through the EL element 15. However, the present invention is not limited to this. For example, the reverse bias voltage Vm may be forcibly applied while a current is flowing through the EL element 15. In this case, as a result, no current flows through the EL element 15, and the non-lighting state (black display state) will occur. The present invention will be described mainly with respect to the application of the reverse bias voltage Vm in a current-programmed pixel configuration, but the present invention is not limited to this.

  In the reverse bias drive pixel configuration, the transistor 11g is N-channel as shown in FIG. Of course, the P channel may be used.

  In FIG. 47, when the voltage applied to the gate potential control line 473 is made higher than the voltage applied to the reverse bias line 471, the transistor 11g (N) is turned on, and the reverse bias voltage is applied to the anode electrode of the EL element 15. Vm is applied.

  47, the gate potential control line 473 may be operated with the potential fixed at all times. For example, in FIG. 47, when the Vk voltage is 0 (V), the potential of the gate potential control line 473 is set to 0 (V) or higher (preferably 2 (V) or higher). Note that this potential is Vsg. In this state, when the potential of the reverse bias line 471 is set to the reverse bias voltage Vm (0 (V) or less, preferably -5 (V) or less smaller than Vk), the transistor 11 g (N) is turned on, and the EL element 15 A reverse bias voltage Vm is applied to the anode. When the voltage of the reverse bias line 471 is higher than the voltage of the gate potential control line 473 (that is, the gate (G) terminal voltage of the transistor 11g), the transistor 11g is in an off state, and thus the EL element 15 has a reverse bias voltage Vm. Is not applied. Of course, it goes without saying that the reverse bias line 471 may be in a high impedance state (open state or the like) in this state.

  In addition, as illustrated in FIG. 48, a gate driver circuit 12c for controlling the reverse bias line 471 may be separately formed or arranged. The gate driver circuit 12c sequentially shifts in the same manner as the gate driver circuit 12a, and the position where the reverse bias voltage is applied is shifted in synchronization with the shift operation.

  In the above driving method, the reverse bias voltage Vm can be applied to the EL element 15 only by fixing the potential of the gate (G) of the transistor 11g and changing the potential of the reverse bias line 471. Therefore, application control of the reverse bias voltage Vm is easy. Further, the voltage applied between the gate (G) terminal and the source (S) terminal of the transistor 11g can be reduced. This is the same when the transistor 11g is a P channel.

  The reverse bias voltage Vm is applied when no current is passed through the EL element 15. Therefore, the transistor 11d may be turned on when the transistor 11d is not turned on. That is, the reverse of the on / off logic of the transistor 11d may be applied to the gate potential control line 473. For example, in FIG. 47, the gate (G) terminals of the transistors 11d and 11g may be connected to the gate signal line 17b. Since the transistor 11d is a P channel and the transistor 11g is an N channel, the on / off operation is reversed.

  FIG. 49 is a timing chart of reverse bias driving. In the chart diagram, subscripts such as (1) and (2) indicate pixel rows. For ease of explanation, (1) indicates the first pixel row and (2) indicates the second pixel row. However, the present invention is not limited to this. It may be considered that (1) indicates the Nth pixel row and (2) indicates the (N + 1) th pixel row. The above is the same in other embodiments except for special cases. In the embodiment of FIG. 49 and the like, the pixel configuration of FIG. 1 and the like will be described as an example, but the present invention is not limited to this. For example, the present invention can also be applied to the pixel configuration shown in FIGS.

  When the on-voltage (Vgl) is applied to the gate signal line 17a (1) of the first pixel row, the off-voltage (Vgh) is applied to the gate signal line 17b (1) of the first pixel row. . That is, the transistor 11 d is off and no current flows through the EL element 15.

  A Vsl voltage (a voltage at which the transistor 11g is turned on) is applied to the reverse bias line 471 (1). Therefore, the transistor 11g is turned on, and a reverse bias voltage is applied to the EL element 15. The reverse bias voltage is applied after a predetermined period (a period longer than 1/200 of 1H or 0.5 μsec) after the off voltage (Vgh) is applied to the gate signal line 17b. In addition, the reverse bias voltage is turned off before a predetermined period (period longer than 1/200 of 1H, or 0.5 μsec) when the ON voltage (Vgl) is applied to the gate signal line 17b. This is to prevent the transistor 11d and the transistor 11g from being turned on at the same time.

  In the next horizontal scanning period (1H), the off voltage (Vgh) is applied to the gate signal line 17a, and the second pixel row is selected. That is, an on-voltage is applied to the gate signal line 17b (2). On the other hand, an ON voltage (Vgl) is applied to the gate signal line 17b, the transistor 11d is turned on, a current flows from the transistor 11a to the EL element 15, and the EL element 15 emits light. Further, the off-voltage (Vsh) is applied to the reverse bias line 471 (1), and the reverse bias voltage is not applied to the EL elements 15 in the first pixel row (1). The Vsl voltage (reverse bias voltage) is applied to the reverse bias line 471 (2) of the second pixel row.

  By sequentially repeating the above operations, an image on one screen is rewritten. In the above embodiment, the reverse bias voltage is applied during the period programmed in each pixel. However, the circuit configuration of FIG. 48 is not limited to this. It is obvious that a reverse bias voltage can be applied continuously to a plurality of pixel rows. Obviously, block driving (see FIG. 40), N-fold pulse driving, reset driving, and dummy pixel driving can be combined.

  The above embodiment is the case of the pixel configuration of FIG. 1, but it goes without saying that the present invention can be applied to other configurations in which a reverse bias voltage is applied as shown in FIGS. For example, FIG. 50 shows a pixel configuration of a current programming method.

FIG. 50 shows a pixel configuration of the current mirror. The transistor 11c is a pixel selection element. The transistor 11c is turned on by applying an on voltage to the gate signal line 17a1. The transistor 11d is a switch element having a reset function and a function of short-circuiting (GD short-circuit) between the drain (D) and gate (G) terminals of the driving transistor 11a. The transistor 11d is turned on by applying a turn-on voltage to the gate signal line 17a2.

  The transistor 11d is turned on at least 1H (one horizontal scanning period, that is, one pixel row) before the pixel is selected. Preferably, it is turned on 3H before. If 3H before, the transistor 11d is turned on 3H before, and the gate (G) terminal and the drain (D) terminal of the transistor 11a are short-circuited. Therefore, the transistor 11a is turned off. Therefore, no current flows through the transistor 11b, and the EL element 15 is not lit.

  When the EL element 15 is not lit, the transistor 11g is turned on, and a reverse bias voltage is applied to the EL element 15. Therefore, the reverse bias voltage is applied while the transistor 11d is on. Therefore, in terms of logic, the transistor 11d and the transistor 11g are turned on simultaneously.

  The gate (G) terminal of the transistor 11g is fixed by applying a Vsg voltage. By applying a reverse bias voltage that is sufficiently smaller than the Vsg voltage to the reverse bias line 471, the transistor 11g is turned on.

  Thereafter, when a horizontal scanning period in which a video signal is applied (written) to the corresponding pixel comes, a turn-on voltage is applied to the gate signal line 17a1, and the transistor 11c is turned on. Therefore, the video signal voltage output from the source driver circuit 14 to the source signal line 18 is applied to the capacitor 19 (the transistor 11d is kept on).

  When the transistor 11d is turned on, black display is obtained. The longer the ON period of the transistor 11d in one field (one frame) period, the longer the ratio of the black display period. Therefore, even if there is a black display period, it is necessary to increase the luminance of the display period in order to set the average luminance of one field (one frame) to a desired value. That is, it is necessary to increase the current flowing through the EL element 15 during the display period. This operation is the N-fold pulse driving according to the present invention. Therefore, combining the N-fold pulse driving and the driving for turning on the transistor 11d to display black is one characteristic operation of the present invention. In addition, a characteristic configuration (system) of the present invention is that a reverse bias voltage is applied to the EL element 15 while the EL element 15 is not lit.

  In the above embodiments, the reverse bias voltage is applied when the pixel is not lit when displaying an image. However, the configuration for applying the reverse bias voltage is not limited to this. If a reverse bias voltage is applied without displaying an image, there is no need to form a reverse bias TFT 11g in each pixel. The non-lighting state is a configuration in which a reverse bias voltage is applied after the use of the display panel is finished or before the use.

  For example, in the pixel configuration of FIG. 1, the pixel 16 is selected (TFT 11b and TFT 11c are turned on), and a low voltage V0 (for example, GND voltage) that the source driver IC can output is output from the source driver IC (circuit) 14. Applied to the drain terminal (D) of the driving TFT 11a. If the TFT 11d is also turned on in this state, the V0 voltage is applied to the anode terminal of the EL. At the same time, if a voltage Vm that is −5 to −15 (V) lower than the V0 voltage is applied to the cathode Vk of the EL element 15, a reverse bias voltage is applied to the EL element 15. In addition, when the voltage Vdd is 0 to -5 (V) lower than the voltage V0, the TFT 11a is also turned off. As described above, a reverse bias voltage can be applied to the EL element 15 by outputting a voltage from the source driver circuit 14 and controlling the gate signal line 17.

  In the N-fold pulse drive, a predetermined current (programmed current (depending on the voltage held in the capacitor 19) is applied to the EL element 15 again even if black display is performed once within one field (one frame) period. ). However, in the configuration of FIG. 50, once the transistor 11d is turned on, the charge of the capacitor 19 is discharged (including a decrease), so that a predetermined current (programmed current cannot flow through the EL element 15). The circuit operation is easy.

  In the above embodiment, the pixel has a current-programmed pixel configuration. However, the present invention is not limited to this, and may be applied to other current-type pixel configurations as shown in FIGS. Can do. Further, the present invention can be applied to a pixel configuration of a voltage program as shown in FIGS. 51, 54, and 62.

  FIG. 51 generally shows the pixel configuration of the simplest voltage program. The transistor 11 b is a selective switching element, and the transistor 11 a is a driving transistor that applies a current to the EL element 15. With this configuration, a reverse bias voltage applying transistor (switching element) 11g is disposed (formed) on the anode of the EL element 15.

  In the pixel configuration of FIG. 51, a current flowing through the EL element 15 is applied to the source signal line 18 and is applied to the gate (G) terminal of the transistor 11a when the transistor 11b is selected.

  First, in order to describe the configuration of FIG. 51, the basic operation will be described with reference to FIG. The pixel configuration in FIG. 51 is a voltage offset canceller, and operates in four stages: an initialization operation, a reset operation, a program operation, and a light emission operation.

  After the horizontal synchronization signal (HD), an initialization operation is performed. A turn-on voltage is applied to the gate signal line 17b, turning on the transistor 11g. Further, an on-voltage is applied to the gate signal line 17a, and the transistor 11c is turned on. At this time, the Vdd voltage is applied to the source signal line 18. Therefore, the Vdd voltage is applied to the a terminal of the capacitor 19b. In this state, the driving transistor 11 a is turned on, and a slight current flows through the EL element 15. This current causes the drain (D) terminal of the driving transistor 11a to have an absolute voltage value that is at least larger than the operating point of the transistor 11a.

  Next, a reset operation is performed. A turn-off voltage is applied to the gate signal line 17b, and the transistor 11e is turned off. On the other hand, a turn-on voltage is applied to the gate signal line 17c during the period T1, and the transistor 11b is turned on. This period T1 is a reset period. Further, an on-voltage is continuously applied to the gate signal line 17a for a period of 1H. Note that T1 is preferably 20% to 90% of the 1H period. Alternatively, the time is preferably 20 μsec to 160 μsec. The ratio of the capacitance of the capacitor 19b (Cb) to the capacitor 19a (Ca) is preferably Cb: Ca = 6: 1 or more and 1: 2 or less.

  In the reset period, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a are short-circuited by turning on the transistor 11b. Therefore, the gate (G) terminal voltage and the drain (D) terminal voltage of the transistor 11a become equal, and the transistor 11a enters an offset state (reset state: no current flows). This reset state is a state in which the gate (G) terminal of the transistor 11a is in the vicinity of the start voltage at which current starts to flow. The gate voltage that maintains this reset state is held at the b terminal of the capacitor 19b. Therefore, the capacitor 19 holds the offset voltage (reset voltage).

  In the next program state, a turn-off voltage is applied to the gate signal line 17c and the transistor 11b is turned off. On the other hand, the DATA voltage is applied to the source signal line 18 during the period Td. Accordingly, the gate (G) terminal of the driving transistor 11a is applied with the data voltage plus the offset voltage (reset voltage). Therefore, the driving transistor 11a can pass a programmed current.

  After the program period, a turn-off voltage is applied to the gate signal line 17a, the transistor 11c is turned off, and the driving transistor 11a is disconnected from the source signal line 18. Further, a turn-off voltage is also applied to the gate signal line 17c, the transistor 11b is turned off, and this off state is maintained for a period of 1F. On the other hand, an ON voltage and an OFF voltage are periodically applied to the gate signal line 17b as necessary. That is, a better image display can be realized by combining with the N-fold pulse driving shown in FIGS. 13 and 15 or the interlace driving.

  In the driving method of FIG. 52, the capacitor 19 holds the starting current voltage (offset voltage, reset voltage) of the transistor 11a in the reset state. Therefore, the darkest black display state is when the reset voltage is applied to the gate (G) terminal of the transistor 11a. However, black floating (decrease in contrast) occurs due to coupling between the source signal line 18 and the pixel 16, penetration voltage to the capacitor 19, or penetration of the transistor. Therefore, with the driving method described in FIG. 53, the display contrast cannot be increased.

  In order to apply the reverse bias voltage Vm to the EL element 15, it is necessary to turn off the transistor 11a. In order to turn off the transistor 11a, a short circuit may be provided between the Vdd terminal and the gate (G) terminal of the transistor 11a. This configuration will be described later with reference to FIG.

  Alternatively, a Vdd voltage or a voltage for turning off the transistor 11a may be applied to the source signal line 18, and the transistor 11b may be turned on and applied to the gate (G) terminal of the transistor 11a. This voltage turns off the transistor 11a (or puts it in a state where almost no current flows (substantially off state: the transistor 11a is in a high impedance state)). Thereafter, the transistor 11 g is turned on, and a reverse bias voltage is applied to the EL element 15. The application of the reverse bias voltage Vm may be performed simultaneously for all pixels. That is, a voltage that substantially turns off the transistor 11a is applied to the source signal line 18 to turn on the transistors 11b in all (a plurality of) pixel rows. Therefore, the transistor 11a is turned off. Thereafter, the transistor 11 g is turned on, and a reverse bias voltage is applied to the EL element 15. Thereafter, a video signal is sequentially applied to each pixel row, and an image is displayed on the display device.

  Next, reset driving in the pixel configuration of FIG. 51 will be described. FIG. 53 shows an example. As shown in FIG. 53, the gate signal line 17a connected to the gate (G) terminal of the transistor 11c of the pixel 16a is also connected to the gate (G) terminal of the resetting transistor 11b of the next pixel 16b. Similarly, the gate signal line 17a connected to the gate (G) terminal of the transistor 11c of the pixel 16b is connected to the gate (G) terminal of the reset transistor 11b of the next pixel 16c.

Therefore, when an on-voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11c of the pixel 16a, the pixel 16a enters the voltage programming state and the reset transistor 11b of the next-stage pixel 16b is turned on. The driving transistor 11a of the pixel 16b is reset. Similarly, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11c of the pixel 16b, the pixel 16b enters the current program state, and the reset transistor 11b of the next-stage pixel 16c turns on. Then, the driving transistor 11a of the pixel 16c is reset. Therefore, it is possible to easily realize reset driving by the pre-stage gate control method. In addition, the number of gate signal lines drawn out per pixel can be reduced.

  This will be described in more detail. It is assumed that a voltage is applied to the gate signal line 17 as shown in FIG. That is, it is assumed that an on-voltage is applied to the gate signal line 17a of the pixel 16a and an off-voltage is applied to the gate signal line 17a of the other pixel 16. The gate signal line 17b is assumed to have an off voltage applied to the pixels 16a and 16b and an on voltage applied to the pixels 16c and 16d.

  In this state, the pixel 16a is not lit in the voltage program state, the pixel 16b is not lit in the reset state, the pixel 16c is lit in the holding state of the program current, and the pixel 16d is lit in the holding state of the program current.

  After 1H, the data in the shift register circuit 61 of the control gate driver circuit 12 is shifted by 1 bit, resulting in the state of FIG. 53 (b). In the state of FIG. 53B, the pixel 16a is lit in the program current holding state, the pixel 16b is not lit in the current program state, the pixel 16c is not lit in the reset state, and the pixel 16d is lit in the program holding state.

  From the above, it can be seen that, in each pixel, the driving transistor 11a of the pixel in the next stage is reset by the voltage of the gate signal line 17a applied in the previous stage, and the voltage program is sequentially performed in the next horizontal scanning period.

  The pre-stage gate control can also be realized by the pixel configuration of the voltage program shown in FIG. FIG. 54 shows an embodiment in which the pixel configuration of FIG. 43 is connected in the previous gate control system.

  As shown in FIG. 54, the gate signal line 17a connected to the gate (G) terminal of the transistor 11b of the pixel 16a is connected to the gate (G) terminal of the reset transistor 11e of the next stage pixel 16b. Similarly, the gate signal line 17a connected to the gate (G) terminal of the transistor 11b of the pixel 16b is connected to the gate (G) terminal of the reset transistor 11e of the next stage pixel 16c.

  Therefore, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11b of the pixel 16a, the pixel 16a enters the voltage program state and the reset transistor 11e of the next pixel 16b turns on. The driving transistor 11a of the pixel 16b is reset. Similarly, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11b of the pixel 16b, the pixel 16b enters the current program state, and the reset transistor 11e of the next-stage pixel 16c turns on. Then, the driving transistor 11a of the pixel 16c is reset. Therefore, it is possible to easily realize reset driving by the pre-stage gate control method.

  This will be described in more detail. It is assumed that a voltage is applied to the gate signal line 17 as shown in FIG. That is, it is assumed that an on-voltage is applied to the gate signal line 17a of the pixel 16a and an off-voltage is applied to the gate signal line 17a of the other pixel 16. Further, it is assumed that all the reverse bias transistors 11g are in an off state.

  In this state, the pixel 16a is in a voltage program state, the pixel 16b is in a reset state, the pixel 16c is in a program current holding state, and the pixel 16d is in a program current holding state.

  After 1H, the data in the shift register circuit 61 of the control gate driver circuit 12 is shifted by 1 bit, resulting in the state of FIG. 55 (b). In the state of FIG. 55B, the pixel 16a is in the program current holding state, the pixel 16b is in the current programming state, the pixel 16c is in the reset state, and the pixel 16d is in the program holding state.

  From the above, it can be seen that, in each pixel, the driving transistor 11a of the pixel in the next stage is reset by the voltage of the gate signal line 17a applied in the previous stage, and the voltage program is sequentially performed in the next horizontal scanning period.

  Hereinafter, the current driver type source driver IC (circuit) 14 of the present invention will be described. First, FIG. 72 shows an example of a conventional current-driven driver circuit. However, such a current driver IC does not exist, but is a principle for explaining the current driver type source driver IC of the present invention.

  In FIG. 72, reference numeral 721 denotes a D / A converter. An n-bit data signal is input to the D / A converter 721, and an analog signal is output from the D / A converter based on the input data. This analog signal is input to the operational amplifier 722. The operational amplifier 722 is input to the N-channel transistor 631a, and a current flowing through the transistor 631a flows through the resistor 691. The terminal voltage of the resistor R becomes the negative input of the operational amplifier 722, and the negative terminal voltage and the positive terminal of the operational amplifier 722 are the same voltage. Therefore, the output voltage of the D / A converter 721 becomes the terminal voltage of the resistor 691.

  If the resistance value of the resistor 691 is 1 MΩ and the output of the D / A converter 721 is 1 (V), a current of 1 (V) / 1 MΩ = 1 (μA) flows through the resistor 691. This is a constant current circuit. Therefore, the analog output of the D / A converter 721 changes according to the value of the data signal, and a predetermined current flows through the resistor 691 based on the value of this analog output.

  Transistors 631p1 and 631p2 form a current mirror circuit. Note that the transistor 631p is a P-channel transistor. On the other hand, 633n is an n-channel transistor constituting a current mirror. The same current flows through the source-drain (SD) of the driving transistor 631a, the same current value flows through the current mirror circuit composed of 631p1 and 631p2, and the same current also flows through the current mirror circuit composed of each transistor 633n. Since the value flows, the output terminals O1, O2, O3, O4, O5,... Become constant current output terminals through which the same current flows (when the current magnification is equal).

  However, even if the IC is manufactured based on the same process from the same mask, the electrical characteristics of each element such as a transistor and a resistor formed on the semiconductor chip are different, and the output current of the driver IC is the same. Even in an IC, there is a variation between outputs between constant current output terminals. In this case, if the output current value of each constant current output terminal varies, the light emission amount of the light emitting element varies and display unevenness occurs on the display panel. Therefore, when driving the light emitting element such as the organic EL display panel using the driver IC 14, it is necessary to minimize the variation between the constant current output terminals as much as possible.

  The present invention has been made in view of this point, and provides a current-driven driver IC (circuit) 14 having a circuit configuration and a layout configuration for minimizing output current variation between constant current output terminals as much as possible. .

FIG. 63 shows a configuration diagram of a current driver type source driver IC (circuit) 14 of the present invention. FIG. 1 shows a multi-stage current mirror circuit when the current source has a three-stage configuration (631, 632, 633) as an example.

  In FIG. 63, the current value of the first-stage current source 631 is copied to N (where N is an arbitrary integer) second-stage current sources 632 by a current mirror circuit. Furthermore, the current value of the second stage current source 632 is copied to M (where M is an arbitrary integer) third stage current sources 633 by a current mirror circuit. With this configuration, as a result, the current value of the first stage current source 631 is copied to N × M third stage current sources 633.

  For example, when the driver signal 14 is used to drive the source signal line 18 of the QCIF format display panel, the output is 176 (because the source signal line needs 176 outputs for each RGB). In this case, N is 16 and M = 11. Therefore, 16 × 11 = 176, which corresponds to 176 outputs. In this way, by setting one of N or M to 8 or 16, or a multiple thereof, the layout design of the current source of the driver IC is facilitated.

  In a conventional current-driven source driver IC (assumed virtually), the current value of the first stage current source 631 is directly copied to the N × M third stage current sources by the current mirror circuit. When there is a difference between the transistor characteristics of the first-stage current source 631 and the transistor characteristics of the third-stage current source, this results in variations in the current value and appears as display unevenness on the display panel. In particular, since the source driver IC 14 has an elongated shape with a width of about 2 mm and a length of about 20 mm, there is a large variation in transistor characteristics between the center and both ends, and such a problem is considered to be significant.

  In response to this problem, in the current driver type source driver IC (circuit) 14 using the multi-stage current mirror circuit of the present invention, as described above, the current value of the first stage current source 631 is directly set to N × M first. Instead of copying to the three-stage current source 633 by the current mirror circuit, the second-stage current source 632 is provided in the middle, so that variations in transistor characteristics can be absorbed there.

  In particular, the present invention is characterized in that the first stage current mirror circuit (current source 631) and the second stage current mirror circuit (current source 632) are closely arranged. If the first-stage current source 631 to the third-stage current source 633 (that is, the two-stage configuration of the current mirror circuit), the number of second-stage current sources 633 connected to the first-stage current source is In many cases, the first-stage current source 631 and the third-stage current source 633 cannot be closely arranged.

  Like the source driver circuit 14 of the present invention, the current of the first stage current mirror circuit (current source 631) is copied to the second stage current mirror circuit (current source 632), and the second stage current mirror circuit ( In this configuration, the current of the current source 632) is copied to the current mirror circuit (current source 632) in the third stage. In this configuration, the number of second-stage current mirror circuits (current sources 632) connected to the first-stage current mirror circuits (current sources 631) is small. Therefore, the first-stage current mirror circuit (current source 631) and the second-stage current mirror circuit (current source 632) can be closely arranged.

  If the transistors constituting the current mirror circuit can be arranged in close proximity, naturally, the variation of the transistors is reduced, so that the variation in the copied current value is also reduced. Further, the number of third-stage current mirror circuits (current sources 633) connected to the second-stage current mirror circuits (current sources 632) is also reduced. Therefore, the second-stage current mirror circuit (current source 632) and the third-stage current mirror circuit (current source 633) can be closely arranged.

That is, as a whole, the transistors in the current receiving section of the first stage current mirror circuit (current source 631), the second stage current mirror circuit (current source 632), and the third stage current mirror circuit (current source 633) Can be placed closely. Accordingly, since the transistors constituting the current mirror circuit can be closely arranged, the variation of the transistors is reduced, and the variation of the current signal from the output terminal is extremely reduced (high accuracy).

  In this example, the multi-stage current mirror circuit has been described in a three-stage configuration for simplicity, but it goes without saying that the larger the number of stages, the smaller the current variation of the source driver IC 14 of the current-driven display panel. Therefore, the number of stages of the current mirror circuit is not limited to three, but may be three or more.

  In the present invention, they are expressed as current sources 631, 632, and 633 or as current mirror circuits. These are used synonymously. That is, the current source is a basic configuration concept of the present invention, and when the current source is specifically configured, it becomes a current mirror circuit. Therefore, the current source is not limited to the current mirror circuit alone, and may be a current circuit including a combination of an operational amplifier 722, a transistor 631, and a resistor R as illustrated in FIG.

  FIG. 64 is a more specific structural diagram of the source driver IC (circuit) 14. FIG. 64 illustrates a portion of the third current source 633. That is, the output unit is connected to one source signal line 18. As the final stage current mirror configuration, a plurality of current mirror circuits of the same size (current source 634 (one unit)) are configured, and the number of bits is weighted corresponding to the bits of the image data.

  The transistors constituting the source driver IC (circuit) 14 of the present invention are not limited to the MOS type but may be a bipolar type. Moreover, it is not limited to a silicon semiconductor, and a gallium arsenide semiconductor may be used. Further, a germanium semiconductor may be used. Further, the substrate may be formed directly by polysilicon technology such as low-temperature polysilicon or amorphous silicon technology.

  As is apparent from FIG. 64, a case of 6-bit digital input is shown as one embodiment of the present invention. That is, since it is 2 6, it is a 64 gradation display. By mounting this source driver IC 14 on the array substrate, red (R), green (G), and blue (B) have 64 gradations, so that 64 × 64 × 64 = about 260,000 colors can be displayed. Become.

  In FIG. 64, D0 indicates the LSB input, and D5 indicates the MSB input. When the D0 input terminal is at the H level (at the time of positive logic), the switch 641a (on / off means. Of course, it may be constituted by a single transistor or an analog switch in which a P channel transistor and an N channel transistor are combined). ) Turns on. Then, a current flows toward a current source (1 unit) 634 constituting the current mirror. This current flows through the internal wiring 643 in the IC 14. Since the internal wiring 643 is connected to the source signal line 18 via the terminal electrode of the IC 14, the current flowing through the internal wiring 643 becomes the program current of the pixel 16.

  When the D1 input terminal is at the H level (positive logic), the switch 641b is turned on. Then, current flows toward the two current sources (one unit) 634 constituting the current mirror. This current flows through the internal wiring 643 in the IC 14. Since the internal wiring 643 is connected to the source signal line 18 via the terminal electrode of the IC 14, the current flowing through the internal wiring 643 becomes the program current of the pixel 16.

The same applies to the other switches 641. When the D2 input terminal is at the H level (positive logic), the switch 641c is turned on. Then, current flows toward the four current sources (1 unit) 634 constituting the current mirror. When the D5 input terminal is at the H level (positive logic), the switch 641f is turned on. Then, current flows toward 32 current sources (1 unit) 634 constituting the current mirror.

  As described above, according to data (D0 to D5) from the outside, a current flows toward the corresponding current source (1 unit). Therefore, the current flows from 0 to 63 current sources (one unit) according to the data. In the present invention, for ease of explanation, the number of current sources is 63, which is 6 bits. However, the present invention is not limited to this. In the case of 8 bits, 255 unit current sources 634 may be formed (arranged). In the case of 4 bits, 15 unit current sources 634 may be formed (arranged). The transistors 634 constituting the unit current source have the same channel width W and channel width L. By configuring with the same transistor in this way, an output stage with little variation can be configured.

  Further, all the current sources 634 are not limited to flowing the same current. For example, each current source 634 may be weighted. For example, a current output circuit may be configured by mixing one unit of current source 634, twice the current source 634, four times the current source 634, and the like. However, if the current sources 634 are weighted, the weighted current sources do not have a weighted ratio, and variations may occur. Therefore, even in the case of weighting, each current source is preferably configured by forming a plurality of transistors serving as one unit of current source.

  The configuration of FIG. 64 is the third-stage current mirror unit shown in FIG. Therefore, the first current source 631 and the second-stage current source 632 are separately formed, and these are arranged densely (closely or adjacently). The second-stage current source 632 and the current mirror transistor 633a constituting the third-stage current source are also arranged densely (closely or adjacently).

  In particular, the current sources (one unit) 634 are densely arranged and a minute current flows. Therefore, when light (emitted light) emitted from an EL display panel or the like is irradiated on the current source 634 (in addition, 631, 632, 633 should be taken into consideration), a photoconductor phenomenon (photocon) is caused. Causes malfunction. In order to cope with this problem, a light shielding film is formed on the back surface of the chip. Further, a light-shielding film is formed at a place to be mounted on a substrate and at a place where a chip current source is formed (a light absorption film made of a metal thin film, an organic material, an inorganic material, or the like is formed on the surface of the panel substrate). . This light-shielding film can be easily formed and reduced in cost if it is configured by routing anode wiring and cathode wiring for supplying current to the EL element 15 (routed under the IC chip). This configuration is not limited to the IC chip. The present invention is also applied to the source driver circuit 14 using low temperature polysilicon, high temperature polysilicon, a semiconductor film (CGS) formed by solid phase growth, or amorphous silicon technology. That is, a light shielding film is formed on the back surface of the source driver circuit 14.

  The current flowing through the second-stage current mirror circuit 632 is copied to the transistor 633a constituting the third-stage current mirror circuit, and when the current mirror magnification is 1, this current flows through the transistor 633b. This current is copied to the final stage transistor 634.

Since the portion corresponding to D0 is composed of one transistor 634, it is the value of the current flowing through the transistor 633 of the final stage current source. Since the portion corresponding to D1 is composed of two transistors 634, the current value is twice that of the final stage current source. Since D2 is composed of four transistors 634, the current value is four times that of the final stage current source, D,
Since the portion corresponding to 5 is composed of 32 transistors, the current value is 32 times that of the final stage current source. Therefore, the program current Iw is output to the source signal line through the switch controlled by the 6-bit image data D0, D1, D2,..., D5 (current is drawn). Therefore, in response to the ON / OFF of the 6-bit image data D0, D1, D2,..., D5, the output line is 1 time, 2 times, 4 times,. A current of 32 times is added and output. That is, a current value 0 to 63 times that of the final stage current source 633 is output from the output line by 6-bit image data D0, D1, D2,..., D5 (current is drawn from the source signal line 18).

  As described above, the current value can be controlled with higher precision than the conventional proportional distribution of W / L by the configuration of the integral multiple of the final stage current source 633 (the output variation of each terminal is eliminated).

  However, this configuration is a case where the driving TFT 11a configuring the pixel 16 is configured by a P channel and the current source (one unit) unit 634 configuring the source driver IC 14 is configured by an N channel transistor. In other cases (for example, when the driving TFT 11a of the pixel 16 is composed of an N-channel transistor), it goes without saying that the program current Iw can be a discharge current. ).

  It is assumed that the current of 0 to 63 times that of the final stage current source 633 is output, but this is when the current mirror magnification of the final stage current source 633 is 1. When the current mirror magnification is 2, the current of 0 to 126 times that of the final stage current source 633 is output, and when the current mirror magnification is 0.5, the current of the final stage current source 633 is 0 to 31.5 times. Current is output. As described above, according to the present invention, the current value of the output can be easily changed by changing the current mirror magnification of the final-stage current source 633 or the previous-stage current source (631, 632, etc.). In addition, it is also preferable to change (make different) the current mirror magnification for each of R, G, and B as described above. For example, for only R, the current mirror magnification of one of the current sources may be changed (different) with respect to another color (for a current source circuit corresponding to the other color). In particular, the EL display panel has different emission efficiency for each color (R, G, B or cyan, yellow, magenta). Therefore, the white balance can be improved by changing the current mirror magnification for each color.

  The matter of changing (differentiating) the current mirror magnification of the current source with respect to another color (with respect to the current source circuit corresponding to the other color) is not limited to a fixed one. Variable is also included. The variable can be realized by forming a plurality of transistors constituting a current mirror circuit in the current source and switching the number of the transistors through which the current current flows according to an external signal. By configuring in this way, it is possible to adjust to an optimal white balance while observing the light emission state of each color of the manufactured EL display panel. In particular, the present invention has a configuration in which current sources (current mirror circuits) are connected in multiple stages. Therefore, when the current mirror magnification of the first-stage current source 631 and the second-stage current source 632 is changed, the output currents of a large number of outputs can be easily changed with a small number of coupling parts (current mirror circuit or the like). Of course, it is possible to easily change the output current of a large number of outputs with a small number of coupling parts (such as a current mirror circuit) rather than changing the current mirror magnification of the second stage current source 632 and the third stage current source 633. Needless to say.

  The concept of changing the current mirror magnification is to change (adjust) the current magnification. Therefore, the present invention is not limited only to the current mirror circuit. For example, it can be realized by a current output operational amplifier circuit, a current output D / A circuit, or the like.

  Needless to say, the matters described above can be applied to other embodiments of the present invention.

  FIG. 65 shows an example of a circuit diagram of 176 outputs (N × M = 176) by a three-stage current mirror circuit. In FIG. 65, the current source 631 based on the first stage current mirror circuit is referred to as a parent current source, the current source 632 based on the second stage current mirror circuit is referred to as a child current source, and the current source 633 based on the third stage current mirror circuit is referred to as a grandchild current source. ing. With a configuration of an integral multiple of the current source by the third stage current mirror circuit which is the final stage current mirror circuit, variation in 176 outputs is suppressed as much as possible, and highly accurate current output is possible. Of course, it should not be forgotten that the current sources 531, 632, 633 are arranged densely.

  Note that the dense arrangement means that the first current source 631 and the second current source 632 are arranged at a distance of at least 8 mm (current or voltage output side and current or voltage input side). . Furthermore, it is preferable to arrange within 5 mm. This is because, if it is within this range, it is arranged in the silicon chip by examination, and the difference in transistor characteristics (Vt, mobility (μ)) hardly occurs. Similarly, the second current source 632 and the third current source 633 (current output side and current input side) are also arranged at a distance of at least 8 mm. More preferably, it is preferable to arrange at a position within 5 mm. Needless to say, the above matters also apply to other embodiments of the present invention.

  The current or voltage output side and the current or voltage input side mean the following relationship. In the case of the voltage delivery in FIG. 66, the relation is that the transistors 631 (output side) of the (I) -th current source and the transistors 632a (input side) of the (I + 1) -th current source are closely arranged. In the case of current delivery in FIG. 67, the transistors 631a (output side) of the (I) -th current source and the transistors 632b (input side) of the (I + 1) -th current source are closely arranged.

  Here, a silicon chip is used, which means a semiconductor chip. Accordingly, the same applies to chips formed on a gallium substrate, other semiconductor chips formed on a germanium substrate, and the like.

  Furthermore, the present invention is also applied to a source driver circuit using low-temperature polysilicon, high-temperature polysilicon, a semiconductor film (CGS) formed by solid phase growth, or amorphous silicon technology. However, in this case, the panel is often relatively large. If the panel is large, even if there is some output variation from the source signal line 18, it is difficult to visually recognize. Therefore, in a display panel in which the source driver circuit 14 is formed simultaneously with the pixel TFT on the above glass substrate or the like, the first current source 631 and the second current source 632 are at least within a distance of 30 mm or less. (Current output side and current input side). Furthermore, it is preferable to arrange within 20 mm. This is because, within this range, a difference in characteristics (Vt, mobility (μ)) of transistors arranged in this range hardly occurs due to examination. Similarly, the second current source 632 and the third current source 633 (current output side and current input side) are also disposed at a distance of at least 30 mm. More preferably, it is preferable to arrange at a position within 20 mm.

  In the above description, in order to facilitate understanding or to facilitate the description, the current mirror circuit is described as passing a signal by voltage. However, by using a current transfer configuration. A driver circuit (IC) 14 for driving a current-driven display panel with less variation can be realized.

FIG. 67 shows an embodiment of a current delivery configuration. FIG. 66 shows an example of a voltage delivery configuration. 66 and 67 are the same circuit diagrams, and the layout configuration, that is, the way of wiring is different. In FIG. 66, reference numeral 631 denotes a first stage current source Nch transistor,
632a is a second-stage current source Nch transistor, and 632b is a second-stage current source Pch transistor.

In FIG. 67, 631a is a first-stage current source Nch transistor, 632a is a second-stage current source Nch transistor, and 632b is a second-stage current source Pch transistor.
In FIG. 66, the gate voltage of the first stage current source composed of the variable resistor 651 (used to change the current) and the Nch transistor 631 is received by the gate of the Nch transistor 632a of the second stage current source. Since it is passed, the layout configuration is a voltage delivery system.

  On the other hand, in FIG. 67, the gate voltage of the first stage current source composed of the variable resistor 651 and the Nch transistor 631a is applied to the gate of the Nch transistor 632a of the adjacent second stage current source, and as a result, the current flowing through the transistor Since the value is transferred to the Pch transistor 632b of the second-stage current source, the layout configuration is a current transfer method.

  In the embodiment of the present invention, the relationship between the first current source and the second current source is mainly described for the sake of easy explanation or easy understanding. However, the present invention is not limited to this. Needless to say, the present invention can also be applied (applicable) in the relationship between the second current source and the third current source, or in the relationship with other current sources.

  66, the Nch transistor 631 of the first-stage current source and the Nch transistor 632a of the second-stage current source that form the current mirror circuit are separated (separated). Therefore, the transistor characteristics of the two are likely to be different. Therefore, the current value of the first stage current source is not accurately transmitted to the second stage current source, and variations tend to occur.

  On the other hand, in the layout configuration of the current transfer type current mirror circuit of FIG. 67, the Nch transistor 631a of the first stage current source and the Nch transistor 632a of the second stage current source that constitute the current mirror circuit are adjacent to each other ( Therefore, the transistor characteristics of the two are hardly different, the current value of the first-stage current source is accurately transmitted to the second-stage current source, and variations are less likely to occur.

From the above, as the circuit configuration of the multi-stage current mirror circuit of the present invention (source driver circuit (IC) 14 of the current drive system of the present invention), by adopting a layout configuration that provides current delivery instead of voltage delivery, It is preferable because the variation can be reduced. It goes without saying that the above embodiment can be applied to other embodiments of the present invention.
For convenience of explanation, the case of the first stage current source to the second stage current source is shown, but the second stage current source to the third stage current source, the third stage current source to the fourth stage current source,. It goes without saying that the same applies to the case of.

  68 shows an example in which the current mirror circuit (three-stage current source) having the three-stage configuration shown in FIG. 65 is configured as a current delivery system (therefore, FIG. 65 shows a circuit configuration of the voltage delivery system. ).

In FIG. 68, first, a reference current is created by the variable resistor 651 and the Nch transistor 631a. Although the reference current is adjusted by the variable resistor 651, the source voltage of the transistor 631a is actually set by an electronic volume circuit formed (or arranged) in the source driver IC (circuit) 14. Configured to be adjusted. Alternatively, the reference current is adjusted by supplying the current output from the current-type electronic volume composed of a large number of current sources (one unit) 634 as shown in FIG. 64 directly to the source terminal of the transistor 631. (See FIG. 69).

  The gate voltage of the first stage current source by the transistor 631a is applied to the gate of the Nch transistor 632a of the adjacent second stage current source, and as a result, the current value flowing through the transistor is received by the Pch transistor 632b of the second stage current source. Passed. Further, the gate voltage of the second current source transistor 6312b is applied to the gate of the Nch transistor 633a of the adjacent third-stage current source, and as a result, the value of the current flowing through the transistor becomes the Nch transistor 633b of the third-stage current source. Is passed on. A large number of current sources 634 shown in FIG. 64 are formed (arranged) at the gate of the Nch transistor 633b of the third stage current source according to the required number of bits.

  In FIG. 69, the first-stage current source 631 of the multi-stage current mirror circuit includes a current value adjusting element. With this configuration, the output current can be controlled by changing the current value of the first stage current source 631.

  The Vt variation (characteristic variation) of the transistor varies about 100 mV within one wafer. However, the Vt variation of transistors formed close to each other within 100 μm is at least 10 mV (actual measurement). That is, by forming transistors in close proximity to form a current mirror circuit, output current variation of the current mirror circuit can be reduced. Therefore, variation in output current at each terminal of the source driver IC of the present invention can be reduced.

  FIG. 110 shows the measurement results of the transistor formation area (square millimeter) and the output current variation (3σ) of the single transistor. The output current variation is a current variation at the Vt voltage. Black spots are transistor output current variations of evaluation samples (10 to 200) produced within a predetermined formation area. The transistor formed in the region A (formation area within 0.5 square millimeter) in FIG. 110 has almost no output current variation (almost only an output current variation in an error range. That is, a constant output current is Output). Conversely, in the C region (formation area of 2.4 square millimeters or more), the variation in output current with respect to the formation area tends to increase rapidly. In the region B (formation area of 0.5 square millimeters or greater and 2.4 square millimeters or less), the variation in output current with respect to the formation area is in a substantially proportional relationship.

  However, the absolute value of the output current varies from wafer to wafer. However, this problem can be dealt with by adjusting the reference current or setting it to a predetermined value in the source driver circuit (IC) 14 of the present invention. Moreover, it can respond (solve) by circuit devices, such as a current mirror circuit.

  The present invention changes (controls) the amount of current flowing through the source signal line 18 by switching the number of currents flowing through the unit transistor 634 according to the input digital data (D). If the number of gradations is 64 gradations or more, 1/64 = 0.015, so theoretically, it is necessary to make the output current variation within 1-2%. In addition, it is difficult to visually discriminate output variations within 1%, and it is almost impossible to discriminate below 0.5% (appears uniform).

In order to make the output current variation (%) within 1%, it is necessary to make the formation area of the transistor group (transistors for which the occurrence of variation is suppressed) within 2 square millimeters as shown in the result of FIG. . More preferably, output current variation (that is, transistor Vt variation) is preferably within 0.5%. As shown in the result of FIG. 110, the formation area of the transistor group 681 may be within 1.2 square millimeters. The formation area is an area of length × width. For example, as an example, 1.2 mm2 is 1 mm × 1.2 mm.

  The above is particularly the case of 8 bits (256 gradations) or more. In the case of 256 gradations or less, for example, in the case of 6 bits (64 gradations), the variation in output current may be about 2% (the actual state is not problematic in image display). In this case, the transistor group 681 may be formed within 5 square millimeters. Further, both the transistor groups 681 (two transistors groups 681a and 681b are shown in FIG. 68) do not need to satisfy this condition. If at least one (one or more transistor groups 681 when there are three or more) is configured to satisfy this condition, the effect of the present invention is exhibited. In particular, it is preferable to satisfy this condition for the lower-order transistor group 681 (681a is the upper order and 681b is the lower-order relation). This is because a problem in image display is less likely to occur.

  A parent, child, and grandchild transistor group is formed or arranged within the predetermined area range. The transistor group is preferably composed of multiples of 8 (8, 16, 24,...). This is because the circuit configuration becomes easy and the number of wiring lines can be reduced. In the present invention, N = 16 (8 × 2) and M = 11 (176/16).

  The above matters are also applied to other embodiments of the present invention, and can be combined with the display panel, array, display device and the like of the present invention.

  In the source driver circuit (IC) 14 of the present invention, as shown in FIG. 68, at least a plurality of current sources such as a parent, a child, and a grandchild are connected in multiple stages, and each current source is closely arranged (of course, A two-stage connection of a parent and a child may be used). In addition, a current is passed between the current sources (between the transistor groups 681). Specifically, the range surrounded by the dotted line in FIG. 68 (transistor group 681) is densely arranged. This transistor group 681 is in a voltage transfer relationship. Further, the parent current source 631 and the child current source 632a are formed or arranged at substantially the center of the source driver IC 14 chip. This is because the distance between the transistor 632a constituting the child current source arranged on the left and right of the chip and the transistor 632b constituting the child current source can be made relatively short. That is, the uppermost transistor group 681a is arranged at the substantially central portion of the IC chip. Then, lower transistor groups 681b are arranged on the left and right sides of the IC chip 14. Preferably, the lower transistor group 681b is arranged, formed or manufactured so that the number of the lower transistor groups 681b is substantially equal on the left and right of the IC chip. The above items are not limited to the IC chip 14 but also apply to the source driver circuit 14 formed directly on the substrate 71 by the low temperature or high temperature polysilicon technology. The same applies to other matters.

  In the present invention, one transistor group 681a is configured, arranged, formed, or formed at a substantially central portion of the IC chip 14, and eight transistor groups 681b are formed on the left and right sides of the chip (N = 8 + 8, FIG. 63). The child transistor group 681b is equal to the left and right of the chip, or the number of transistor groups 681b formed or arranged on the left side and the position formed or arranged on the right side of the chip with respect to the position where the parent at the center of the chip is formed. It is preferable that the difference between the number of transistor groups 681b formed is 4 or less. Furthermore, it is preferable that the difference between the number of transistor groups 681b formed or arranged on the left side of the chip and the number of transistor groups 681b formed or arranged on the right side of the chip be within one. . The same applies to the transistor group (not shown in FIG. 68) as a grandchild.

A voltage is passed (voltage connection) between the parent current source 631 and the child current source 632a. Therefore, it is easily affected by the Vt variation of the transistor. Therefore, the transistor group 681a is densely arranged. The formation area of the transistor group 681a is formed within 2 square millimeters as shown in FIG. More preferably, it is formed within 1.2 mm 2. Of course, when the number of gradations is 64 gradations or less, it may be within 5 square millimeters.

  Since the transistor group 681a exchanges data with current between the child transistors 632b (current exchange), the distance may flow somewhat. This distance range (for example, the distance from the output terminal of the upper transistor group 681a to the input terminal of the lower transistor 681b) is the same as that of the transistor 632a constituting the second current source (child) as described above. The transistor 632b constituting the second current source (child) is arranged at a distance of at least 10 mm. This is preferably arranged or formed within 8 mm. Furthermore, it is preferable to arrange within 5 mm. This is because the difference in the characteristics (Vt, mobility (μ)) of the transistors arranged in the silicon chip by examination will hardly affect the current delivery. In particular, this relationship is preferably implemented by a lower-order transistor group. For example, if the transistor group 681a is higher, the transistor group 681b is lower, and the transistor group 681c is lower, the current transfer between the transistor group 681b and the transistor group 681c is satisfied. Therefore, the present invention is not limited to all the transistor groups 681 satisfying this relationship. It suffices that at least one transistor group 681 satisfies this relationship. This is because the number of transistor groups 681 increases especially in the lower order.

  The same applies to the transistor 633a constituting the third current source (grandchild) and the transistor 633b constituting the third current source. Needless to say, the present invention can also be applied to voltage transfer.

  The transistor group 681b is formed, fabricated, or arranged in the left-right direction of the chip (longitudinal direction, that is, at a position facing the output terminal 761). The transistor group 681b is formed, fabricated, or arranged in the left-right direction of the chip (longitudinal direction, that is, at a position facing the output terminal 761). The number M of the transistor groups 681b is 11 in the present invention (see FIG. 63).

  A voltage is passed (voltage connection) between the child current source 632b and the grandchild current source 633a. Therefore, the transistor group 681b is densely arranged as in the transistor group 681a. The formation area of the transistor group 681b is formed within an area of 2 square millimeters as shown in FIG. More preferably, it is formed within 1.2 mm 2. However, if the Vt of the transistor group 681b varies slightly, it is easily recognized as an image. Therefore, it is preferable that the formation area be an A region (within 0.5 square millimeters) in FIG. 110 so that the variation hardly occurs.

  Since data is exchanged (current exchange) between the grandchild transistor 633a and the transistor 633b in the transistor group 681b, a slight distance may flow. This distance range is the same as described above. The transistor 633a constituting the third current source (grandchild) and the transistor 633b constituting the second current source (grandchild) are arranged at a distance of at least 8 mm. Furthermore, it is preferable to arrange within 5 mm.

  FIG. 69 shows a case where the current value control element is composed of an electronic regulator. The electronic volume includes a resistor 691 (which creates a current limit and each reference voltage. The resistor 691 is formed of polysilicon), a decoder 692, a level shifter 693, and the like. The electronic volume outputs a current. The transistor 641 functions as an analog switch circuit.

The electronic volume circuit is formed (or arranged) according to the number of colors of the EL display panel. For example, in the case of three primary colors of RGB, it is preferable to form (or arrange) three electronic volume circuits corresponding to each color so that each color can be adjusted independently. However, when one color is used as a reference (fixed), an electronic volume circuit of −1 number of colors is formed (or arranged).

  FIG. 76 shows a configuration in which a resistance element 651 that controls the reference current independently for the three primary colors RGB is formed (arranged). Of course, it goes without saying that the resistance element 651 may be replaced with an electronic regulator. A basic current source such as a current source 631 and a current source 632 and a parent current source and a child current source are densely arranged in the current output circuit 704 in an area shown in FIG. By arranging them densely, output variations from the source signal lines 18 are reduced. As shown in FIG. 76, by arranging the current output circuit 704 at the center of the IC chip (circuit) 14, current is evenly distributed from the current sources 631 and 632 to the left and right of the IC chip (circuit) 14. Becomes easy. Therefore, left and right output variations are unlikely to occur.

  The current output circuit 704 is formed (arranged) for each of R, G, and B, and the RGB current output circuits 704R, 704G, and 704B are also arranged close to each other. Further, for each color (R, G, B), the reference current INL in the low current region shown in FIG. 73 is adjusted, and the reference current INH in the low current region shown in FIG. 74 is adjusted (also in FIG. 79). See Accordingly, the R current output circuit 704R is provided with a volume (or an electronic volume for voltage output or current output) 651RL for adjusting the reference current INL in the low current region, and a volume (for adjusting the reference current INH in the high current region). Alternatively, a voltage output or current output electronic volume) 651RH is disposed. Similarly, the G current output circuit 704G is provided with a volume (or an electronic volume for voltage output or current output) 651GL for adjusting the reference current INL in the low current region, and a volume for adjusting the reference current INH in the high current region. (Or an electronic volume for voltage output or current output) 651GH is arranged. The current output circuit 704B of B is provided with a volume (or an electronic volume for voltage output or current output) 651BL for adjusting the reference current INL in the low current region, and a volume (for adjusting the reference current INH in the high current region). Alternatively, a voltage output or current output electronic volume) 651BH is disposed.

  Note that the volume 651 and the like are preferably configured to change with temperature so that the temperature characteristics of the EL element 15 can be compensated. Further, in the gamma characteristic of FIG. 79, when there are two or more bending points, it goes without saying that three or more electronic volumes or resistors for adjusting the reference current of each color may be used.

  An output pad 761 is formed or arranged at the output terminal of the IC chip. This output pad is connected to the source signal line 18 of the display panel. The output pad 761 has bumps (projections) formed by a plating technique or a nail head bonder technique. The height of the protrusion is set to be 10 μm or more and 40 μm or less.

The bumps and the source signal lines 18 are electrically connected via a conductive bonding layer (not shown). The conductive bonding layer is mainly composed of epoxy, phenol, etc. as an adhesive, and mixed with flakes such as silver (Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO ₂ ). Or ultraviolet curable resin. The conductive bonding layer is formed on the bump by a technique such as transfer. Further, the bump and the source signal line 18 are thermocompression bonded with an ACF resin. The connection between the bump or output pad 761 and the source signal line 18 is not limited to the above method. Alternatively, the film carrier technology may be used without mounting the IC 14 on the array substrate. Further, the source signal line 18 or the like may be connected using a polyimide film or the like.

  In FIG. 69, the input 4-bit current value control data (DI) is decoded by a 4-bit decoder circuit 692 (of course, if the number of divisions is 64, it is set to 6 bits. (For ease of explanation, explanation will be made with 4 bits). The output is boosted from a logic level voltage value to an analog level voltage value by a level shifter circuit 693 and input to an analog switch 641.

  The main component of the electronic volume circuit is composed of a fixed resistor R0691a and 16 unit resistors r691b. The output of the decoder circuit 692 is connected to one of the 16 analog switches 641, and the resistance value of the electronic volume is determined by the output of the decoder circuit 692. That is, for example, if the output of the decoder circuit 692 is 4, the resistance value of the electronic volume is R0 + 5r. The resistance of the electronic volume is a load of the first stage current source 631 and is pulled up to the analog power supply AVdd. Therefore, when the resistance value of the electronic volume changes, the current value of the first stage current source 631 changes, and as a result, the current value of the second stage current source 632 changes. As a result, the third stage current source 633 changes. The current value of the driver IC also changes, and the output current of the driver IC is controlled.

  For convenience of explanation, the current value control data is assumed to be 4 bits. However, this is not fixed to 4 bits, and it goes without saying that the greater the number of bits, the greater the variable number of current values. Yes. Further, the configuration of the multi-stage current mirror has been described as being three stages, but it is needless to say that the number of stages is not limited to three and may be any number.

  Further, with respect to the problem that the light emission luminance of the EL element changes due to temperature change, it is preferable to provide an external resistor 691a whose resistance value changes with temperature as the configuration of the electronic volume circuit. Examples of the external resistor whose resistance value changes with temperature include a thermistor and a posistor. In general, a light-emitting element whose luminance changes according to the current flowing through the element has temperature characteristics, and even when the same current value is supplied, the light emission luminance changes depending on the temperature. Therefore, by attaching an external resistor 691a whose resistance value changes depending on the temperature to the electronic volume, the current value of the constant current output can be changed depending on the temperature, and the light emission luminance is always kept constant even if the temperature changes. Can do.

  The multistage current mirror circuit is preferably separated into three systems for red (R), green (G), and blue (B). In general, a current-driven light emitting element such as an organic EL has different light emission characteristics for R, G, and B. Therefore, in order to obtain the same luminance in R, G, and B, it is necessary to adjust the current value that flows through the light emitting element by R, G, and B, respectively. Further, in a current drive type light emitting element such as an organic EL display panel, the temperature characteristics of R, G, and B are different. Therefore, the characteristics of the external auxiliary element such as the thermistor for correcting the temperature characteristics need to be adjusted by R, G, and B, respectively.

  In the present invention, since the multi-stage current mirror circuit is separated into three systems for R, G, and B, light emission characteristics and temperature characteristics can be adjusted by R, G, and B, respectively. It is possible to obtain a good white balance.

As described above, in the current driving method, the current written to the pixel is small during black display. For this reason, if the source signal line 18 or the like has a parasitic capacitance, there is a problem that a sufficient current cannot be written to the pixel 16 in one horizontal scanning period (1H). In general, a current-driven light-emitting element has a weak black level current value of about several nA, and thus it is difficult to drive a parasitic capacitance (wiring load capacitance) that seems to be about several tens of pF in its signal value. . In order to solve this problem, before writing image data to the source signal line 18, a precharge voltage is applied, and the potential level of the source signal line 18 is set to the black display current of the TFT 11a of the pixel (basically, the TFT 11a is It is effective to turn it off. For the formation (creation) of the precharge voltage, it is effective to output a constant voltage at the black level by decoding the upper bits of the image data.

  FIG. 70 shows an example of a current output type source driver circuit (IC) 14 having a precharge function of the present invention. FIG. 70 shows a case where a precharge function is mounted in the output stage of a 6-bit constant current output circuit. In FIG. 70, the precharge control signal is a dot clock CLK that is decoded by the NOR circuit 702 when the upper 3 bits D3, D4, D5 of the image data D0 to D5 are all 0 and has a reset function by the horizontal synchronization signal HD. The AND circuit 703 with the output of the counter circuit 701 is taken, and the black level voltage Vp is output for a certain period. In other cases, the output current from the current output stage 704 described in FIG. 68 and the like is applied to the source signal line 18 (the program current Iw is absorbed from the source signal line 18). With this configuration, when the image data is in the 0th to 7th gradations close to the black level, a voltage corresponding to the black level is written only for a certain period at the beginning of one horizontal period, and the burden of current driving is reduced. It becomes possible to make up for insufficient writing. The complete black display is the 0th gradation, and the complete white display is the 63rd gradation (in the case of 64 gradation display).

  Note that the gradation for precharging should be limited to the black display area. That is, the writing image data is determined, and the black region gradation (low luminance, that is, the writing current is small (small) in the current driving method) is selected and precharged (selective precharge). When pre-charging is performed on all gradation data, this time, a decrease in luminance (not reaching the target luminance) occurs in the white display area. In addition, vertical stripes are displayed in the image.

  Preferably, selective precharge is performed with gradations in the range of gradations 0 to 1/8 of gradation data (for example, in the case of 64 gradations, the image data from the 0th gradation to the 7th gradation is stored). At that time, after precharging, the image data is written). Further, it is preferable that selective precharge is performed with gradations in a region of gradations 0 to 1/16 of gradation data (for example, in the case of 64 gradations, images from the 0th gradation to the 3rd gradation are used. Data and time, precharge and then write image data).

  In particular, in order to increase the contrast in black display, it is also effective to detect only the gradation 0 and precharge. The black display is extremely good. The problem is that the screen appears to float black when the entire screen has gradations 1 and 2. Therefore, selective precharge is performed in the range of gradations 0 to 1/8 of the gradation data and in a certain range.

  It is also effective to vary the precharge voltage and gradation range for R, G, and B. This is because the EL display element 15 has different emission start voltages and emission luminances for R, G, and B. For example, R is a selective precharge with the gradation of the gradation data from 0 to 1/8 of the gradation data (for example, in the case of 64 gradations, the images from the 01st gradation to the 7th gradation are used. When data, pre-charge and then write image data). Other colors (G, B) are selectively precharged with gradations in the range of gradations 0 to 1/16 of gradation data (for example, in the case of 64 gradations, the 3rd floor from the 0th gradation) The image data up to the time of the adjustment and the control such as writing the image data after precharging are performed. As for the precharge voltage, if R is 7 (V), a voltage of 7.5 (V) is written to the source signal line 18 for the other colors (G, B). The optimum precharge voltage is often different depending on the production lot of the EL display panel. Therefore, it is preferable that the precharge voltage is configured to be adjustable with an external volume or the like. This adjustment circuit can also be easily realized by using an electronic volume circuit.

In addition, the 0th mode in which no precharge is performed, the first mode in which only the gradation 0 is precharged, the second mode in which the precharge is performed in the range from the gradation 0 to the gradation 3, and the precharging is performed in the range from the gradation 0 to the gradation 7. It is preferable that a third mode to be charged, a fourth mode to be precharged in a range of all gradations, and the like are set, and these are switched by a command. These can be easily realized by configuring (designing) a logic circuit in the source driver circuit (IC) 14.

  FIG. 75 is a specific configuration diagram of the selective precharge circuit section. PV is a precharge voltage input terminal. An external input or an electronic volume circuit is used, and individual precharge voltages are set for R, G, and B. Note that although individual precharge voltages are set for R, G, and B, the present invention is not limited to this. R, G, and B may be common. This is because the precharge voltage correlates with Vt of the driving TFT 11a of the pixel 16, and this pixel 16 is the same for the R, G, and B pixels. Conversely, when the W / L ratio of the driving TFT 11a of the pixel 16 is different between R, G, and B (having different designs), the precharge voltage is adjusted corresponding to different designs. It is preferable to do. For example, as L increases, the diode characteristics of the TFT 11a deteriorate and the source-drain (SD) voltage increases. Therefore, the precharge voltage needs to be set lower than the source potential (Vdd).

  The precharge voltage PV is input to the analog switch 731. The analog switch W (channel width) needs to be 10 μm or more in order to reduce the on-resistance. However, if W is too large, the parasitic capacitance increases, so the thickness is made 100 μm or less. More preferably, the channel width W is preferably 15 μm or more and 60 μm or less. The above items also apply to the analog switch 731 of the switch 641b in FIG. 75 and the analog switch 731 in FIG.

  The switch 641a is controlled by a precharge enable (PEN) signal, a selection precharge signal (PSL), and the upper 3 bits (H5, H4, H3) of the logic signal of FIG. The meaning of the upper 3 bits (H5, H4, H3) of the logic signal as an example is that the selective precharge is performed when the upper 3 bits are “0”. That is, the precharge is performed by selecting the time when the lower 3 bits are “1” (gradation 0 to gradation 7).

  Note that this selective precharge may be fixed by precharging only gradation 0 or precharging in the range of gradation 0 to gradation 7, but the low gradation basin (gradation 0 in FIG. 79). To gradation R1 or gradation (R1-1)) may be linked to the low gradation area. That is, the selective precharge is performed in this range when the low gradation region is from gradation 0 to gradation R1, and is performed in this range when the low gradation region is from gradation 0 to gradation R2. Implement in conjunction. Note that this control method has a smaller hardware scale than other methods.

  The on / off control of the switch 641a is performed according to the application state of the above signal, and the precharge voltage PV is applied to the source signal line 18 when the switch 641a is on. The time for applying the precharge voltage PV is set by a separately formed counter (not shown). This counter is configured to be set by a command. The precharge voltage application time is preferably set to 1/100 or more and 1/5 or less of one horizontal scanning period (1H). For example, if 1H is 100 μsec, it is 1 μsec or more and 20 μsec. More preferably, it is 2 μsec or more and 10 μsec.

Also, good results can be obtained by changing the precharge application time for R, G, and B. For example, the R precharge time is made longer than the G and B precharge times. This is because, in an organic EL or the like, the light emission start time is different for each RGB material. A good result can also be obtained by varying the precharge voltage PV application time according to the image data applied to the source signal line 18 next time. For example, the application time is lengthened in gradation 0 for full black display, and shorter than that in gradation 4. It is also possible to obtain a good result by setting the application time in consideration of the difference between the image data before 1H and the image data to be applied next. For example, when writing a current to display a pixel in white on the source signal line 1H before and writing a current to display a black in the pixel to the next 1H, the precharge time is lengthened. This is because the black display current is very small. On the other hand, when writing the current to make the pixel display black on the source signal line 1H before, and writing the current to make the black display on white next 1H, shorten the precharge time or precharge the current. Stop (do not do). This is because the white display write current is large.

  It is also effective to change the precharge voltage according to the image data to be applied. This is because the writing current for black display is very small and the writing current for white display is large. Therefore, the precharge voltage is increased as the low gradation region is reached (relative to Vdd. When the pixel TFT 11a is in the P channel), and the precharge voltage is decreased as the high gradation region is reached (the pixel TFT 11a). Is P channel).

  When the program current open terminal (PO terminal) is “0”, the switch 641b is turned off, and the IL terminal, the IH terminal, and the source signal line 18 are disconnected (the Iout terminal is connected to the source signal line 18). ) Therefore, the program current Iw does not flow through the source signal line 18. The PO terminal is set to “1” when the program current Iw is applied to the source signal line, turns on the switch 641b, and causes the program current Iw to flow through the source signal line 18.

  “0” is applied to the PO terminal and the switch 641b is opened when no pixel row in the display area is selected. The current source 634 does not keep current based on the input data (D0 to D5) and is drawn from the source signal line 18. This current is a current that flows from the Vdd terminal of the selected pixel 16 to the source signal line 18 via the TFT 11a. Therefore, when no pixel row is selected, there is no path for current to flow from the pixel 16 to the source signal line 18. The time when no pixel row is selected occurs between the time when an arbitrary pixel row is selected and the next pixel row is selected. Note that a state in which no pixel (pixel row) is selected and there is no path for flowing into (flowing out) the source signal line 18 is referred to as an all non-selection period.

  When the IOUT terminal is connected to the source signal line 18 in this state, the unit current source 634 that is turned on (actually, the switch 641 that is controlled by the data of the D0 to D5 terminals is turned on. Current). For this reason, the charge charged in the parasitic capacitance of the source signal line 18 is discharged, and the potential of the source signal line 18 rapidly decreases.

  As described above, when the potential of the source signal line 18 is lowered, it takes time to restore the original potential due to the current originally written in the source signal line 18.

  In order to solve this problem, the present invention applies “0” to the PO terminal during all non-selection periods, turns off the switch 641b in FIG. 75, and disconnects the IOUT terminal and the source signal line 18. By disconnecting, no current flows from the source signal line 18 to the current source 634, so that the potential change of the source signal line 18 does not occur during the entire non-selection period. As described above, good current writing can be performed by controlling the PO terminal during the entire non-selection period and disconnecting the current source from the source signal line 18.

In addition, the area of white display area (area with constant brightness) (white area) and the area of black display area (area with luminance below predetermined) (black area) are mixed on the screen. It is effective to add a function of stopping the precharge when the ratio is in a certain range (appropriate precharge). This is because vertical stripes occur in the image within this certain range. Of course, conversely, precharging may be performed within a certain range. Also, when the image moves, the image becomes noise-like. Appropriate precharging can be easily realized by counting (calculating) data of pixels corresponding to the white area and the black area with an arithmetic circuit. It is also effective to make the appropriate precharge different for R, G, and B. This is because the EL display element 15 has different emission start voltages and emission luminances for R, G, and B. For example, R is the ratio of the white area of the predetermined luminance: the black area of the predetermined luminance is stopped or started when the ratio is 1:20 or more, and G and B are the ratio of the white area of the predetermined luminance: the black area of the predetermined luminance. Is a configuration in which precharge is stopped or started at 1:16 or more. According to the experiment and examination results, in the case of the organic EL panel, the precharge is performed when the ratio of the white area of the predetermined luminance to the black area of the predetermined luminance is 1: 100 or more (that is, the black area is 100 times or more of the white area). Is preferably stopped. Furthermore, it is preferable to stop the precharge when the ratio of the white area with the predetermined luminance to the black area with the predetermined luminance is 1: 200 or more (that is, the black area is 200 times or more of the white area).

  When the driving TFT 11a of the pixel 16 is a P-channel, the precharge voltage PV needs to be output from the source driver circuit (IC) 14 near Vdd (see FIG. 1). However, as the precharge voltage PV is closer to Vdd, the driver circuit (IC) 14 needs to use a semiconductor with a high breakdown voltage process (even if the high breakdown voltage is referred to, it is 5 (V) to 10 (V). However, when the breakdown voltage exceeds 5 (V), the problem is that the cost of the semiconductor process becomes high, so it is necessary to use a high-definition, low-cost process by adopting the 5 (V) breakdown voltage process. Can do).

  When the diode characteristics of the driving TFT 11a of the pixel 16 are good and an on-current for white display is ensured, if it is 5 (V) or less, the source driver IC 14 can also use the 5 (V) process, so no problem occurs. However, when the diode characteristics exceed 5 (V), it becomes a problem. In particular, since it is necessary to apply a precharge voltage PV close to the source voltage Vdd of the TFT 11a, the precharge cannot be output from the IC.

  FIG. 92 shows a panel configuration that solves this problem. In FIG. 92, a switch circuit 641 is formed on the array 71 side. The source driver IC 14 outputs an on / off signal for the switch 641. This on / off signal is boosted by a level shift circuit 693 formed in the array 71 to turn on / off the switch 641. Note that the switch 641 and the level shift circuit 693 are formed simultaneously or sequentially in the process of forming the pixel TFT. Of course, it may be formed separately by an external circuit (IC) and mounted on the array 71.

  The on / off signal is output from the terminal 761a of the IC 14 based on the precharge condition described above (FIG. 75, etc.). Therefore, it goes without saying that the precharge voltage application and driving method can also be applied to the embodiment of FIG. The voltage (signal) output from the terminal 761a is as low as 5 (V) or less. The amplitude of this voltage (signal) is increased by the level shifter circuit 693 to the on / off logic level of the switch 641.

  With the configuration described above, the source driver circuit (IC) 14 has a power supply voltage in the operating voltage range that can drive the program current Iw. The precharge voltage PV is eliminated by the array substrate 71 having a high operating voltage. Therefore, the precharge can be sufficiently applied up to the Vdd voltage.

  If the switch circuit 641 of FIG. 89 is also formed (arranged) in the source driver circuit (IC) 14, the breakdown voltage becomes a problem. For example, when the Vdd voltage of the pixel 16 is higher than the power supply voltage of the IC 14, there is a danger that a voltage that destroys the IC 14 is applied to the terminal 761 of the IC 14.

  An embodiment for solving this problem is the configuration of FIG. A switch circuit 641 is formed (arranged) on the array substrate 71. The configuration and the like of the switch circuit 641 are the same as or similar to the configuration and specifications described in FIG.

  The switch 641 is arranged before the output of the IC 14 and in the middle of the source signal line 18. When the switch 641 is turned on, a current Iw for programming the pixel 16 flows into the source driver circuit (IC) 14. When the switch 641 is turned off, the source driver circuit (IC) 14 is disconnected from the source signal line 18. By controlling the switch 641, the drive method shown in FIG. 90 can be implemented.

  Similarly to FIG. 92, the voltage (signal) output from the terminal 761a is as low as 5 (V) or less. The amplitude of this voltage (signal) is increased by the level shifter circuit 693 to the on / off logic level of the switch 641.

  With the configuration described above, the source driver circuit (IC) 14 has a power supply voltage in the operating voltage range that can drive the program current Iw. Further, since the switch 641 also operates with the power supply voltage of the array 71, the switch 641 is not destroyed even when the Vdd voltage is applied from the pixel 16 to the source signal line 18, and the source driver circuit (IC) 14 is destroyed. It is never done.

  Note that it goes without saying that both the switch 641 (prepared) arranged in the middle of the source signal line 18 of FIG. 91 and the precharge voltage PV application switch 641 may be formed (placed) on the array substrate 71 (FIG. 91). 91 + configuration of FIG. 92).

  As described before, when the driving TFT 11a and the selection TFT (11b, 11c) of the pixel 16 are P-channel TFTs as shown in FIG. 1, a punch-through voltage is generated. This is because the potential fluctuation of the gate signal line 17a penetrates to the terminal of the capacitor 19 through the GS capacitance (parasitic capacitance) of the selection TFT (11b, 11c). When the P-channel transistor 11b is turned off, the voltage becomes Vgh. Therefore, the terminal voltage of the capacitor 19 is slightly shifted to the Vdd side. For this reason, the gate (G) terminal voltage of the transistor 11a rises, resulting in a black display.

  On the other hand, complete black display of the first gradation can be realized, but the second gradation and the like are difficult to display. Alternatively, a large gradation jump occurs from the first gradation to the second gradation, or blackout occurs in a specific gradation range.

  The configuration for solving this problem is the configuration of FIG. It has a function of raising the output current value. The main purpose of the raising circuit 711 is to compensate for the punch-through voltage. Further, even when the image data has a black level of 0, a certain amount of current (several tens of nA) flows, and can be used for black level adjustment.

  Basically, FIG. 71 is obtained by adding a raising circuit (portion surrounded by a dotted line in FIG. 71) to the output stage of FIG. FIG. 71 assumes that the current value raising control signal is 3 bits (K0, K1, K2), and outputs a current value 0 to 7 times the current value of the grandchild current source by this 3-bit control signal. It is possible to add to the current.

  The above is the basic outline of the source driver circuit (IC) 14 of the present invention. Hereinafter, the source driver circuit (IC) 14 of the present invention will be described in more detail.

  There is a linear relationship between the current I (A) flowing through the EL element 15 and the light emission luminance B (nt). That is, the current I (A) flowing through the EL element 15 is proportional to the light emission luminance B (nt). In the current driving method, one step (gradation step) is a current (current source 634 (one unit)).

  Human vision of brightness has a square characteristic. That is, when changing with a square curve, the brightness is recognized as changing linearly. However, in the relationship shown in FIG. 83, the current I (A) flowing through the EL element 15 and the light emission luminance B (nt) are proportional to each other in both the low luminance region and the high luminance region. Therefore, if the step is changed step by step, the luminance change for one step is large (black skip occurs) in the low gradation part (black region). Since the high gradation portion (white region) substantially coincides with the linear region of the square curve, the luminance change for one step is recognized as changing at equal intervals. From the above, the black display region becomes a problem in the current driving method (in the case where one step is a current step) (in the current driving source driver circuit (IC) 14).

  In order to solve this problem, the present invention reduces the slope of the current output in the low gradation region (gradation 0 (full black display) to gradation (R1)) as shown in FIG. The slope of the current output from (gradation (R1) to maximum gradation (R)) is increased. In other words, in the low gradation region, the current amount is increased with a small amount (one step) per gradation. In the high gradation region, the current amount increases with one gradation (one step). By varying the amount of current that changes per step in the two gradation regions in FIG. 79, the gradation characteristics become close to a square curve, and blackout does not occur in the low gradation region. The gradation-current characteristic curve illustrated in FIG. 79 and the like is referred to as a gamma curve.

  In the above embodiment, the current gradient has two steps of the low gradation region and the high gradation region. However, the present invention is not limited to this. Needless to say, there may be three or more stages. However, it is needless to say that the case of two stages is preferable because the circuit configuration is simplified.

  The technical idea of the present invention is a circuit that performs gray scale display with current output in a current-driven source driver circuit (IC) or the like. Therefore, the display panel is limited to an active matrix type. In other words, a simple matrix type is also included.) In other words, there are a plurality of current increase amounts per gradation step.

  In a current-driven display panel such as an EL, display luminance changes in proportion to the amount of current applied. Therefore, in the source driver circuit (IC) 14 of the present invention, the luminance of the display panel can be easily adjusted by adjusting the reference current that flows to one current source (one unit) 634.

  In the EL display panel, the luminous efficiency is different between R, G, and B, and the color purity with respect to the NTSC standard is shifted. Therefore, in order to optimize the white balance, it is necessary to appropriately adjust the RGB ratio. Adjustment is performed by adjusting the respective reference currents of RGB. For example, the R reference current is set to 2 μA, the G reference current is set to 1.5 μA, and the B reference current is set to 3.5 μA. In the driver of the present invention, the current of the first stage current source 631 in FIG. 67 is reduced (for example, if the reference current is 1 μA, the reference current is 1/100 of the current flowing through the transistor 632b. 10 nA, etc.), the adjustment accuracy of the reference current to be adjusted from the outside can be made rough, and the accuracy of the minute current in the chip can be adjusted efficiently.

In order to realize the gamma curve of FIG. 79, a reference current adjustment circuit in a low gradation region and a reference current adjustment circuit in a high gradation region are provided. Further, a reference current adjustment circuit for a low gradation region and a reference current adjustment circuit for a high gradation region are provided for each RGB so that the RGB can be adjusted independently. Of course, when adjusting the white balance by fixing one color and adjusting the reference currents of the other colors, the lower floors that adjust two colors (for example, R and B when G is fixed). A reference current adjusting circuit in the gray scale region and a reference current adjusting circuit in the high gradation region may be provided.

  In the current driving method, as shown in FIG. 83, the relationship between the current I passed through the EL and the luminance is linear. Therefore, the white balance adjustment by mixing RGB only needs to adjust the RGB reference current at one point of predetermined luminance. That is, if the RGB reference current is adjusted at one point with a predetermined luminance and the white balance is adjusted, the white balance is basically achieved over all gradations.

  However, in the case of the gamma curve of FIG. First, in order to obtain RGB white balance, it is necessary to make the bending position of the gamma curve (gradation R1) the same in RGB (in other words, in the current drive method, the relative relationship of the gamma curve is changed). It can be the same in RGB). In addition, the ratio between the slope of the low gradation area and the slope of the high gradation area must be constant in RGB (that is, the current drive method allows the relative relationship of the gamma curves to be the same in RGB. become). For example, 10 nA per gradation is increased in the low gradation area (gamma curve inclination in the low gradation area), and 50 nA is increased per gradation in the high gradation area (gamma curve inclination in the high gradation area) ( Note that the increase in current per gradation in the high gradation region / the increase in current per gradation in the low gradation region is referred to as a gamma current ratio, and in this embodiment, the gamma current ratio is 50 nA / 10 nA = 5. ). Then, the gamma current ratio is made the same for RGB. That is, the RGB is configured to adjust the current flowing through the EL element 15 with the same gamma current ratio.

  FIG. 80 shows an example of the gamma curve. In FIG. 80A, the current increase per gradation is large in both the low gradation part and the high gradation part. In FIG. 80 (b), the current increase per gradation is small in both the low gradation part and the high gradation part compared to FIG. 80 (a). However, the gamma current ratio is the same in FIGS. 80 (a) and 80 (b). In this way, adjusting the gamma current ratio while maintaining the same RGB value means that for each color, a constant current circuit that generates a reference current to be applied to the low gradation portion and a reference current to be applied to the high gradation portion. This is because a constant current circuit to be generated is manufactured, and a volume for adjusting the current flowing relatively to these is prepared (arranged).

  FIG. 77 shows a circuit configuration for varying the output current while maintaining the gamma current ratio. The current control circuit 772 changes the current flowing through the current sources 633L and 633H while maintaining the gamma current ratio between the reference current source 771L in the low current region and the reference current source 771H in the high current region.

  In addition, as shown in FIG. 78, it is preferable to detect the relative temperature of the display panel with a temperature detection circuit 781 formed in the IC chip (circuit) 14. This is because the organic EL element has different temperature characteristics depending on the materials constituting RGB. This temperature detection utilizes the fact that the state of the junction of the bipolar transistor changes with temperature, and the output current changes with temperature. The detected temperature is fed back to the temperature control circuit 782 arranged (formed) for each color, and the current control circuit 772 performs temperature compensation.

  It is appropriate that the gamma ratio has a relationship of 3 or more and 10 or less by examination. More preferably, a relationship of 4 or more and 8 or less is appropriate. In particular, the gamma current ratio preferably satisfies the relationship of 5 or more and 7 or less. This is called the first relationship.

Further, it is appropriate to set the change point (gradation R1 in FIG. 79) between the low gradation portion and the high gradation portion to 1/32 or more and 1/4 or less of the maximum gradation number K (for example, the maximum If the number of gradations K is 64 bits with 6 bits, 64/32 = 2 gradations or more and 64/4 = 16 gradations or less). More preferably, the change point (gradation R1 in FIG. 79) between the low gradation part and the high gradation part is
It is appropriate to set it to 1/16 or more and 1/4 or less of the maximum gradation number K (for example, if the maximum gradation number K is 64 bits of 6 bits, 64/16 = fourth gradation or more) 64/4 = 16th gradation or less). More preferably, it is appropriate to set it to 1/10 or more and 1/5 or less of the maximum number of gradations K (Note that if the decimal point is generated by calculation, it is rounded down. For example, the maximum number of gradations K is 6 bits. 64/10 = 6 gradations or more and 64/5 = 12 gradations or less). The above relationship is referred to as a second relationship. The above explanation is the relationship between the gamma current ratios of the two current regions. However, the second relationship described above is also applied when there are gamma current ratios of three or more current regions (that is, there are two or more bending points). In other words, for three or more inclinations, the relationship may be applied to any two inclinations.

  By satisfying both the first relationship and the second relationship at the same time, it is possible to realize a good image display without blackout.

  FIG. 82 shows an embodiment in which a plurality of current-driven source driver circuits (ICs) 14 according to the present invention are used in one display panel. The source driver IC 14 of the present invention includes a slave / master (S / M) terminal that is assumed to use a plurality of driver ICs 14. By operating the S / M terminal at the H level, it operates as a master chip, and outputs a reference current from a reference current output terminal (not shown). This current is the current that flows through the INL and INH terminals in FIGS. 73 and 74 of the slave IC 14 (14a, 14c). By setting the S / M terminal to the L level, the IC 14 operates as a slave chip, and receives the reference current of the master chip from a reference current input terminal (not shown). This current is the current that flows through the INL and INH terminals in FIGS.

  The reference current passed between the reference current input terminal and the reference current output terminal is of two systems, a low gradation region and a high gradation region for each color. Therefore, with 3 colors of RGB, there are 6 systems of 3 × 2. In the above-described embodiment, each color has two systems. However, the present invention is not limited to this, and there may be three or more systems for each color.

  In the current drive system of the present invention, as shown in FIG. 81, the bending point (gradation R1 etc.) can be changed. In FIG. 81 (a), the low gradation part and the high gradation part are changed at gradation R1, and in FIG. 81 (b), the low gradation part and the high gradation part are changed at gradation R2. In this way, the bending position can be changed at a plurality of locations.

  Specifically, the present invention can realize 64-gradation display. The bending point (R1) is none, the second gradation, the fourth gradation, the eighth gradation, and the sixteenth gradation. Since the complete black display has gradation 0, the bending points are 2, 4, 8, and 16. If the complete black display gradation is gradation 1, the bending point is 3, 5, 9, 17, 33. As described above, it is possible to simplify the circuit configuration by configuring the bent position so that it can be performed at a location that is a multiple of 2 (or a location that is a multiple of 2 plus 1 when the complete black display is gradation 1). An effect occurs.

  FIG. 73 is a configuration diagram of a current source circuit section in a low current region. FIG. 74 is a configuration diagram of the current source section and the raised current circuit section in the high current region. As shown in FIG. 73, a reference current INL is applied to the low current source circuit unit. Basically, this current becomes a unit current, and the necessary number of current sources 634 are operated by the input data L0 to L4. The program current IwL of the low current part flows.

As shown in FIG. 74, a reference current INH is applied to the high current source circuit unit. Basically, this current becomes a unit current, and the necessary number of current sources 634 are operated by the input data H0 to L5. As a sum, the program current IwH of the low current portion flows.

The raising current circuit section is the same, and a reference current INH is applied as shown in FIG. 74. Basically, this current becomes a unit current, and the necessary number of current sources 634 are operated by the input data AK0 to AK2. As a sum, the current IwK corresponding to the raised current flows. The program current Iw flowing in the source signal line 18 is Iw = IwH + IwL + IwK. It should be noted that the ratio of IwH and IwL, that is, the gamma current ratio satisfies the first relationship described above.

  73 and 74, the on / off switch 641 includes an inverter 732, an analog switch 731 including a P-channel transistor and an N-channel transistor. As described above, the switch 641 includes the analog switch 731 including the inverter 732, the P-channel transistor, and the N-channel transistor, so that the on-resistance can be reduced, and the voltage drop between the current source 634 and the source signal line 18 is reduced. It can be made extremely small.

  The operation of the low current circuit unit in FIG. 73 and the high current circuit unit in FIG. 74 will be described. The source driver circuit (IC) 14 of the present invention is composed of 5 bits of low current circuit portions L0 to L4 and 6 bits of high current circuit portions H0 to H5. Note that data input from the outside of the circuit is 6 bits of D0 to D5 (64 gradations for each color). The 6-bit data is converted into 5 bits L0 to L4 and 6 bits of the high current circuit portions H0 to H5, and a program current Iw corresponding to the image data is applied to the source signal line. That is, the input 6-bit data is converted into 5 + 6 = 11-bit data. Therefore, a highly accurate gamma curve can be formed.

  As described above, the input 6-bit data is converted into 5 + 6 = 11-bit data. In the present invention, the number of bits (H) of the circuit in the high current region is the same as the number of bits of the input data (D), and the number of bits (L) of the circuit in the low current region is the number of bits of the input data (D). -1. Note that the bit number (L) of the circuit in the low current region may be the bit number −2 of the input data (D). With this configuration, the gamma curve in the low current region and the gamma curve in the high current region are optimal for image display on the EL display panel.

  Hereinafter, a method of controlling the circuit control data (L0 to L4) in the low current region and the circuit control data (H0 to H4) in the high current region will be described with reference to FIGS.

  The present invention is characterized by the operation of the current source 634a connected to the L4 terminal of FIG. 73 in FIG. This 634a is composed of one transistor which is a current source of one unit. By turning this transistor on and off, the program current Iw can be easily controlled (on / off control).

  FIG. 84 shows applied signals to the low current side signal line (L) and the high current side signal line (H) when the low current region and the high current region are switched at gradation 4. In FIGS. 84 to 86, gradations 0 to 18 are shown, but there are actually up to the 63rd gradation. Therefore, the gradation 18 or higher is omitted in each drawing. Further, the switch 641 is turned on when “1” in the table, the current source 634 and the source signal line 18 are connected, and the switch 641 is turned off when “0” in the table.

  In FIG. 84, in the case of gradation 0 of complete black display, (L0 to L4) = (0, 0, 0, 0, 0), and (H0 to H5) = (0, 0, 0, 0, 0). Accordingly, all the switches 641 are in the OFF state, and the program current Iw = 0 in the source signal line 18.

  In gradation 1, (L0 to L4) = (1, 0, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, one unit current source 634 in the low current region is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

  In gradation 2, (L0 to L4) = (0, 1, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, the two unit current sources 634 in the low current region are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

  In gradation 3, (L0 to L4) = (1, 1, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Accordingly, the two switches 641 La and 641 Lb in the low current region are turned on, and the three unit current sources 634 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

  In gradation 4, (L0 to L4) = (1, 1, 0, 0, 1), and (H0 to H5) = (0, 0, 0, 0, 0). Accordingly, the three switches 641La, 641Lb, and 641Le in the low current region are turned on, and the four unit current sources 634 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

  At gradation 5 or higher, the low current region (L0 to L4) = (1, 1, 0, 0, 1) has no change. However, in the high current region, (H0 to H5) = (1, 0, 0, 0, 0) in gradation 5, the switch 641Ha is turned on, and one unit current source 641 in the high current region is the source signal. Connected to line 18. In gradation 6, (H0 to H5) = (0, 1, 0, 0, 0), the switch 641Hb is turned on, and the two unit current sources 641 in the high current region are connected to the source signal line 18. The Similarly, in gradation 7, (H0 to H5) = (1, 1, 0, 0, 0), two switches 641Ha switch 641Hb are turned on, and three unit current sources 641 in the high current region are source signals. Connected to line 18. Further, in gradation 8, (H0 to H5) = (0, 0, 1, 0, 0), one switch 641Hc is turned on, and four unit current sources 641 in the high current region are connected to the source signal line 18. Connected. Thereafter, as shown in FIG. 84, the switch 641 is sequentially turned on and off, and the program current Iw is applied to the source signal line 18.

  What has been characterized by the above operation is a bending point (a switching point between a low current region and a high current region, more precisely, as a program current Iw, a low current IwL is added in the case of gradation in a high current region. Therefore, the expression “switching point” is not correct (and the raised current IwK is also added.) In other words, in the gradation of the high gradation part, it is added to the current of the low gradation part and the step (level) of the high gradation part. The current corresponding to the tone is the program current Iw, and the control bit (L in the low current region) is defined by the gradation of one step (which should be the point or point or position where the current changes). Also, at this time, the L4 terminal in FIG.73 becomes "1", the switch 641e is turned on, and a current flows through the transistor 634a. In tone 4, four low-gradation unit transistors (current sources) 634 operate, and in gradation 5, four low-gradation unit transistors (current sources) 634 operate. One gradation transistor (current source) 634 operates, and similarly, in gradation 6, four low gradation unit transistors (current sources) 634 operate and high gradation part transistors. Two current sources 634 operate, and therefore, at the gradation level 5 or higher, which is the bending point, the current source 634 in the low gradation area below the folding point is turned on for the gradation level (in this case, 4). In addition, the current sources 634 in the high gradation part are sequentially turned on in accordance with the gradation.

Therefore, it can be seen that one of the transistors 634a at the L4 terminal in FIG. Without this transistor 634a, after the gradation 3, one transistor 634 in the high gradation part is turned on. Therefore, the switching point is not a multiplier of 2, such as 4, 8, and 16. The multiplier of 2 is a state in which only one signal is “1”. Therefore, it is easy to perform the condition determination that the weighting signal line of 2 is “1”. Therefore, the hardware scale for condition determination can be reduced. That is, the logic circuit of the IC chip is simplified, and as a result, an IC having a small chip area can be designed (cost reduction is possible).

  FIG. 85 is an explanatory diagram of signals applied to the low current side signal line (L) and the high current side signal line (H) when the low current region and the high current region are switched at gradation 8.

  In FIG. 85, in the case of gradation of 0 for complete black display, it is the same as FIG. 84, (L0 to L4) = (0, 0, 0, 0, 0), and (H0 to H5) = (0 , 0, 0, 0, 0). Accordingly, all the switches 641 are in the OFF state, and the program current Iw = 0 in the source signal line 18.

  Similarly, in gradation 1, (L0 to L4) = (1, 0, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, one unit current source 634 in the low current region is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

  In gradation 2, (L0 to L4) = (0, 1, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, the two unit current sources 634 in the low current region are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

  In gradation 3, (L0 to L4) = (1, 1, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Accordingly, the two switches 641 La and 641 Lb in the low current region are turned on, and the three unit current sources 634 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

  Similarly, in the gradation 4, (L0 to L4) = (0, 0, 1, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). In gradation 5, (L0 to L4) = (1, 0, 1, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). In gradation 6, (L0 to L4) = (0, 1, 1, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). In gradation 7, (L0 to L4) = (1, 1, 1, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0).

  Gradation 8 is the switching point (folding position). In gradation 8, (L0 to L4) = (1, 1, 1, 0, 1) and (H0 to H5) = (0, 0, 0, 0, 0). Accordingly, the four switches 641La, 641Lb, 641Lc, and 641Le in the low current region are turned on, and the eight unit current sources 634 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

  At the gradation 8 or higher, the low current region (L0 to L4) = (1, 1, 1, 0, 1) is not changed. However, in the high current region, in gradation 9, (H0 to H5) = (1, 0, 0, 0, 0), the switch 641Ha is turned on, and one unit current source 641 in the high current region is the source signal. Connected to line 18.

Hereinafter, similarly, the number of transistors 634 in the high current region increases by one according to the gradation step. That is, at gradation 10, (H0 to H5) = (0, 1, 0, 0, 0), the switch 641Hb is turned on, and the two unit current sources 641 in the high current region are connected to the source signal line 18. The Similarly, in gradation 11, (H0 to H5) = (1, 1, 0, 0, 0), the two switches 641Ha switch 641Hb are turned on, and the three unit current sources 641 in the high current region are the source signals. Connected to line 18. Further, in gradation 12, (H0 to H5) = (0, 0, 1, 0, 0), one switch 641Hc is turned on, and four unit current sources 641 in the high current region are connected to the source signal line 18. Connected. Thereafter, as shown in FIG. 84, the switch 641 is sequentially turned on and off, and the program current Iw is applied to the source signal line 18.

  FIG. 86 is an explanatory diagram of signals applied to the low current side signal line (L) and the high current side signal line (H) when the low current region and the high current region are switched at gradation 16. In this case, the basic operation is the same as that shown in FIGS.

  That is, in FIG. 86, in the case of gradation 0 for complete black display, it is the same as in FIG. 85, and (L0 to L4) = (0, 0, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Accordingly, all the switches 641 are in the OFF state, and the program current Iw = 0 in the source signal line 18. Similarly, from gradation 1 to gradation 16, high gradation region (H0 to H5) = (0, 0, 0, 0, 0). Therefore, one unit current source 634 in the low current region is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18. That is, only (L0 to L4) in the low gradation region changes.

  In other words, (L0 to L4) = (1, 0, 0, 0, 0) in gradation 1, and (L0 to L4) = (0, 1, 0, 0, 0) in gradation 2. Yes, in gradation 3, (L0-L4) = (1, 1, 0, 0, 0), and in gradation 2, (L0-L4) = (0, 0, 1, 0, 0) is there. Thereafter, the gradation is sequentially counted up to gradation 16. That is, in gradation 15, (L0 to L4) = (1, 1, 1, 1, 0), and in gradation 16, (L0 to L4) = (1, 1, 1, 1, 1). is there. In gradation 16, only one fifth bit (D4) of D0 to D5 indicating gradation is turned on, so that the content expressed by data D0 to D5 is 16, indicating that one data signal line ( It can be determined by the determination of D4). Therefore, the hardware scale of the logic circuit can be reduced.

  Gradation 16 is a switching point (bending position) (or gradation 17 may be a switching point). In gradation 16, (L0 to L4) = (1, 1, 1, 1, 1) and (H0 to H5) = (0, 0, 0, 0, 0). Accordingly, the four switches 641La, 641Lb, 641Lc, 641d, and 641Le in the low current region are turned on, and the 16 unit current sources 634 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.

  At gradation 16 or higher, the low current region (L0 to L4) = (1, 1, 1, 0, 1) has no change. However, in the high current region, at gradation 17, (H0 to H5) = (1, 0, 0, 0, 0), the switch 641Ha is turned on, and one unit current source 641 in the high current region is the source signal. Connected to line 18. Hereinafter, similarly, the number of transistors 634 in the high current region increases by one according to the gradation step. That is, at the gradation 18, (H0 to H5) = (0, 1, 0, 0, 0), the switch 641Hb is turned on, and the two unit current sources 641 in the high current region are connected to the source signal line 18. The Similarly, in gradation 19, (H0 to H5) = (1, 1, 0, 0, 0), the two switches 641Ha switch 641Hb are turned on, and the three unit current sources 641 in the high current region are the source signals. Connected to line 18. Further, in gradation 20, (H0 to H5) = (0, 0, 1, 0, 0), one switch 641Hc is turned on, and four unit current sources 641 in the high current region are connected to the source signal line 18. Connected.

  As described above, at the switching point (bending position), the current source (unit 1) 634 of the number of multipliers is turned on or connected to the source signal line 18 (in contrast, a configuration in which the current source 634 is turned off is also conceivable). Logic processing is extremely easy. For example, as shown in FIG. 84, when the bent position is gradation 4 (4 is a multiplier of 2), the four current sources (one unit) 634 are configured to operate. In addition, in the gradation beyond that, the current source (one unit) 634 in the high current region is added. Also, as shown in FIG. 85, if the bending position is gradation 8 (8 is a multiplier of 2), the eight current sources (one unit) 634 are configured to operate. In addition, in the gradation beyond that, the current source (one unit) 634 in the high current region is added. If the configuration of the present invention is adopted, a gamma control circuit with a small hardware configuration can be configured with any gradation expression, not limited to 64 gradations (16 gradations: 4096 colors, 256 gradations: 16.7 million colors, etc.).

  In the embodiments described with reference to FIGS. 84, 85, and 86, the gradation of the switching point is a multiplier of 2. This is the case where the complete black gradation is gradation 0. When gradation 1 is to be displayed completely black, +1 is necessary. However, these are matters for convenience. What is important in the present invention is to have a plurality of current regions (low current region, high current region, etc.), and to make a determination (processing) with few signal inputs at the switching points. As an example thereof, the technical idea is that the hardware scale becomes extremely small because it is only necessary to detect one signal line if it is a multiplier of 2. In order to facilitate the processing, a current source 634a is added.

  Therefore, in the case of negative logic, the switching point may be set at the gradations 1, 3, 7, 15. Further, although gradation 0 is set to be completely black, the present invention is not limited to this. For example, in the case of 64-gradation display, gradation 63 may be in a completely black display state, and gradation 0 may be the maximum white display. In this case, the switching point may be processed in consideration of the reverse direction. Therefore, there may be a different configuration from the multiplier of 2.

  Further, the switching point (bending position) is not limited to one gamma curve. Even when there are a plurality of bent positions, the circuit of the present invention can be configured. For example, the folding position can be set to gradation 4 and gradation 16. It is also possible to set 3 points or more, such as gradation 4, gradation 16, and gradation 32.

  In the above embodiment, the gradation is set to a multiplier of 2. However, the present invention is not limited to this. For example, the bending points may be set with multipliers 2 and 8 (2 + 8 = 10th gradation, that is, two signal lines required for determination). Bending points may be set at 2 and 8 and 16 (2 + 8 + 16 = 26th gradation, that is, three signal lines required for determination), which are multipliers of 2 or more. In this case, the hardware scale required for determination or processing is somewhat increased, but it can be adequately handled in terms of circuit configuration. Needless to say, the above-described matters are included in the technical category of the present invention.

  As shown in FIG. 87, the source driver circuit (IC) 14 of the present invention is composed of three parts of a current output circuit 704. A high current region current output circuit 704a that operates in a high gradation region, a low current region current output circuit 704b that operates in a low current region and a high gradation region, and a current raising current output circuit 704b that outputs a raising current.

  The high current region current output circuit 704a and the current raising current output circuit 704c operate using the reference current source 771a that outputs a high current as a reference current, and the low current region current output circuit 704b uses the reference current source 771b that outputs a low current as a reference. Operates as a current.

As described above, the current output circuit 704 includes a high current region current output circuit 704a,
The present invention is not limited to the low current region current output circuit 704b and the current raising current output circuit 704c, and may be two high current region current output circuits 704a and low current region current output circuits 704b, or three or more. The current output circuit 704 may be configured. The reference current source 771 may be arranged or formed corresponding to each current region current output circuit 704, or may be common to all current region current output circuits 704.

  The current output circuit 704 described above corresponds to the gradation data, and the internal transistor 634 operates to absorb current from the source signal line 18. The transistor 634 operates in synchronization with a signal for one horizontal scanning period (1H). In other words, during the period of 1H, a current based on the corresponding gradation data is input (when the transistor 634 is an N channel).

  On the other hand, the gate driver circuit 12 basically selects one gate signal line 17a sequentially in synchronization with the 1H signal. That is, in synchronization with the 1H signal, the gate signal line 17a (1) is selected during the first H period, the gate signal line 17a (2) is selected during the second H period, and the gate signal line 17a is selected during the third H period. (3) is selected, and the gate signal line 17a (4) is selected in the fourth H period.

  However, after the first gate signal line 17a is selected, during the period when the next second gate signal line 17a is selected, no gate signal line 17a is selected (non-selection period, t1 in FIG. 88). To be provided). The non-selection period requires a rising period and a falling period of the gate signal line 17a, and is provided to ensure an on / off control period of the TFT 11d.

  If an on voltage is applied to any one of the gate signal lines 17a and the TFTs 11b and 11c of the pixel 16 are on, the program current Iw is applied to the source signal line 18 from the Vdd power supply (anode voltage) through the driving TFT 11a. Flowing. This program current Iw flows through the transistor 634 (period t2 in FIG. 88). A parasitic capacitance C is generated in the source signal line 18 (parasitic capacitance is generated due to a cross-point capacitance between the gate signal line and the source signal line).

  However, when no gate signal line 17a is selected (non-selection period t1 period in FIG. 88), there is no current path flowing through the TFT 11a. Since the transistor 634 allows current to flow, the transistor 634 absorbs charge from the parasitic capacitance of the source signal line 18. As a result, the potential of the source signal line 18 decreases (part A in FIG. 88). When the potential of the source signal line 18 decreases, it takes time to write a current corresponding to the next image data.

  In order to solve this problem, a switch 641a is formed at the output end of the source terminal 761, as shown in FIG. Further, a switch 641b is formed or arranged at the output stage of the raised current / current output circuit 704c.

  In the non-selection period t1, a control signal is applied to the control terminal S1, and the switch 641a is turned off. In the selection period t2, the switch 641a is turned on (conductive state). In the on state, a program current Iw = IwH + IwL + IwK flows. When the switch 641a is turned off, no Iw current flows. Therefore, as shown in FIG. 90, the potential as shown by A in FIG. 88 is lowered (no change). Note that the channel width W of the analog switch 731 of the switch 641 is set to 10 μm or more and 100 μm or less. The analog switch W (channel width) needs to be 10 μm or more in order to reduce the on-resistance. However, if W is too large, the parasitic capacitance increases, so the thickness is made 100 μm or less. More preferably, the channel width W is preferably 15 μm or more and 60 μm or less.

The switch 641b is a switch that controls only low gradation display. Low gradation display (black display)
In some cases, the gate potential of the TFT 11a of the pixel 16 needs to be close to Vdd (thus, in the black display, the potential of the source signal line 18 needs to be close to Vdd). In the black display, the program current Iw is small, and once the potential drops as shown in FIG. 88A, it takes a long time to return to the normal potential.

  Therefore, in the case of low gradation display, it must be avoided that the non-selection period t1 occurs. On the contrary, in the high gradation display, since the program current Iw is large, there is often no problem even if the non-selection period t1 occurs. Therefore, in the present invention, in high gradation display image writing, both the switch 641a and the switch 641b are turned on even in the non-selection period. Further, the raising current IwK needs to be cut off. This is to achieve black display as much as possible. In the low gradation display image writing, the switch 641a is turned on during the non-selection period, and the switch 641b is turned off. The switch 641b is controlled by the terminal S2.

  Needless to say, in both the low gradation display and the high gradation display, driving may be performed such that the switch 641a is turned off (non-conducting state) and the switch 641b is kept on (conducting) during the non-selection period t1. Needless to say, in both the low gradation display and the high gradation display, driving in which both the switch 641a and the switch 641b are turned off (non-conduction) may be performed in the non-selection period t1.

  In any case, the switch 641 can be controlled by controlling the control terminals S1 and S2. The control terminals S1 and S2 are controlled by command control.

  For example, the control terminal S2 sets the t3 period to the “0” logic level so as to overlap the non-selection period t1. By controlling in this way, the state of A in FIG. 88 does not occur. Further, when the gray level is a black display level above a certain level, the control terminal S1 is set to the “0” logic level. Then, the raising current IwK is stopped, and more black display can be realized.

  The above embodiment has been described as an embodiment on the assumption that one source driver IC 14 is mounted on the display panel. However, the present invention is not limited to this configuration. A plurality of source driver ICs 14 may be stacked on one display panel. For example, FIG. 93 shows an embodiment of a display panel on which three source driver ICs 14 are mounted.

  As described with reference to FIGS. 73, 74, 76, 77 and the like, the source driver IC 14 of the present invention includes at least two systems of a reference current in a low gradation region and a reference current in a high gradation region. This was also explained in FIG.

  As described with reference to FIG. 82, the current-driven source driver circuit (IC) 14 of the present invention includes a slave / master (S / M) terminal that is assumed to use a plurality of driver ICs 14. By operating the S / M terminal at the H level, it operates as a master chip, and outputs a reference current from a reference current output terminal (not shown). Of course, the logic of the S / M terminal may have a reverse polarity. Further, it may be switched by a command to the source driver IC 14. The reference current is transmitted through the skate current connection line 931. By setting the S / M terminal to the L level, the IC 14 operates as a slave chip, and receives the reference current of the master chip from a reference current input terminal (not shown). This current is the current that flows through the INL and INH terminals in FIGS.

The reference current is generated by the current output circuit 704 in the central portion (middle portion) of the IC chip 14. The reference current of the master chip is adjusted and applied from the outside by an external resistor or a current step type electronic volume arranged or configured inside the IC.
A control circuit (command decoder or the like) is also formed (arranged) at the center of the IC chip 14. The reason why the reference current source is formed at the center of the chip is to shorten the distance between the reference current generating circuit and the program current output terminal 761 as much as possible.

  In the configuration of FIG. 93, the reference current is transmitted from the master chip 14b to the two slave chips (14a, 14c). The slave chip receives a reference current, and generates a parent, a child, and a grandchild current based on this current. Note that the reference current transferred from the master chip 14b to the slave chip is performed by current transfer in the current mirror circuit (see FIG. 67). By performing the current transfer, there is no deviation in the reference current among the plurality of chips, and the dividing lines on the screen are not displayed.

  FIG. 94 conceptually illustrates the position of a reference current transfer terminal. A reference current signal line 932 is connected to the signal input terminal 941i disposed at the center of the IC chip. The current applied to the reference current signal line 932 (in some cases, it may be a voltage; see FIG. 76) is a temperature characteristic compensation of the EL material. Further, compensation is made due to deterioration of the life of the EL material.

  Based on the current (voltage) applied to the reference current signal line 932, each current source (631, 632, 633, 634) is driven in the chip. This reference current is output as a reference current to the slave chip via the current mirror circuit. The reference current to the slave chip is output from the terminal 941o. At least one terminal 941o is disposed (formed) on the left and right sides of the reference current generating circuit 704. In FIG. 94, two are arranged (formed) on the left and right. This reference current is transmitted to the slave chip 14 through the cascade signal lines 931a1, 931a2, 931b1, and 931b2. The circuit may be configured so that the reference current applied to the slave chip 14a is fed back to the master chip 14b to correct the shift amount.

  In the current output method of the present invention described above (the source driver of the liquid crystal display panel is a voltage output method (a signal is a voltage step)), a plurality of unit currents proportional to the reference current are combined based on the reference current. The program current Iw is output. Therefore, it is important that the reference current can be accurately generated without variation between chips.

  FIG. 144 shows an example. In FIG. 68, a reference current is created by a resistor 651. In FIG. 144, the resistor 651 in FIG. 68 is replaced with a transistor 631a, and a current flowing through the transistor 1444 forming a current mirror circuit with the transistor 631a is controlled by using an operational amplifier 722 or the like. Transistor 1444 and transistor 631a form a current mirror circuit. If the current mirror magnification is 1, the current flowing through the transistor 1443 becomes the reference current. Note that 704 described in FIG. 144 and the like is a circuit for generating the program current Iw.

  The output voltage of the operational amplifier 722 is input to the N-channel transistor 1443, and the current flowing through the transistor 1443 flows through the external resistor 691. The resistor 691a is a fixed chip resistor. Basically, only the resistor 691a is required. The resistor 691b is a resistor element whose resistance value changes with temperature, such as a posistor or a thermistor. The resistor 691a is used to compensate for the temperature characteristics of the EL element 15. The resistor 691a is inserted or arranged in parallel or in series with the resistor 691b in accordance with the temperature of the EL element 15 particularly (to compensate). In the following description, the resistor 691a and the resistor 691b are regarded as one resistor 691 for ease of explanation.

The resistor 691 is a chip resistor. Therefore, those with an accuracy of 1% or more can be easily obtained. If the resistor is configured in the IC using diffusion resistance technology or a polysilicon pattern, the resistance value accuracy is very poor. Therefore, it is preferable that the resistor 691 that determines the reference current is a highly accurate external resistor. The chip resistor 691 is attached to the input terminal 761a. In particular, in the EL display panel, the temperature characteristics of the EL element 15 are different for each RGB. Therefore, three external resistors 691 for each RGB are required.

  The terminal voltage of the resistor 691 becomes the negative input of the operational amplifier 722, and the voltage of the negative terminal and the positive terminal of the operational amplifier 722 are the same voltage. Therefore, if the + input voltage of the operational amplifier 722 is V1, the voltage divided by the resistor 691 is the current flowing through the transistor 1444. This current becomes the reference current.

  If the resistance value of the resistor 691 is 100 KΩ and the input voltage at the + terminal of the operational amplifier 722 is V1 = 1 (V), a reference current of 1 (V) / 100 KΩ = 10 (μA) flows through the resistor 691. . The magnitude of the reference current is preferably set to 2 μA or more and 30 μA or less. More preferably, it is set to 5 μA or more and 20 μA or less. If the reference current flowing through the parent transistor 63 is small, the accuracy of the unit current source 634 is deteriorated. If the reference current is too large, the current mirror magnification converted in the IC (in this case, the reduction direction) becomes large, the variation in the current mirror circuit becomes large, and the accuracy of the unit current source 634 deteriorates as before.

  According to the above configuration, if the accuracy of the + input terminal of the operational amplifier 722 is good and the resistance value accuracy 691 is good, an extremely accurate reference current (size and variation accuracy) can be formed. The reference voltage Vref from the reference voltage circuit 1441 is applied to the + terminal of the operational amplifier 722. Many types of ICs for the reference voltage circuit 1441 for outputting the reference voltage are available from Maxim Corporation. The reference voltage Vref can also be formed in the source driver circuit 14 (incorporation of the reference voltage Vref). The range of the reference voltage Vref is preferably 1 (V) or more and 3 (V) or less.

  The reference voltage is input from the connection terminal 761a. Basically, this Vref voltage may be input to the + terminal of the operational amplifier 722. The reason why the electronic volume circuit 561 is arranged between the connection terminal 761a and the + terminal is that the EL element 15 has different luminous efficiency in RGB. In other words, this is for adjusting the current flowing through the RGB EL elements 15 to achieve white balance. Of course, when adjustment can be made with the resistor 691, adjustment with the electronic volume 561 is not necessary. Utilization of the electronic volume 561 is the white balance adjustment again because the EL element 15 is RGB and the deterioration rate is different. In particular, B is easily deteriorated in the EL element 15. For this reason, when an EL display panel is used, the B EL element 15 becomes dark over many years, and the screen turns yellow. In this case, the electronic balance 561 for B is adjusted to perform white balance. Of course, luminance compensation or white balance compensation of the EL element may be implemented by interlocking the electronic volume 561 with the temperature sensor 781 (see FIG. 78 and its description).

  The electronic volume 561 is built in the IC (circuit) 14 (formed directly on the substrate 71). A plurality of unit resistors (R1, R2, R3, R4,... Rn) are formed by patterning polysilicon and connected in series. Further, analog switches (S1, S2, S2,... Sn + 1) are arranged between the unit resistors, and the reference voltage Vref is divided to output a voltage.

  In FIG. 144, the transistor 1443 is illustrated as a bipolar transistor; however, the present invention is not limited to this. FIG. 145 (a) shows an embodiment in which the transistor 1443 is an FET. Needless to say, the transistor 1443 need not be built in the IC 14 and may be disposed outside the IC. Further, a generation circuit such as a power supply may be built in the gate driver circuit 12 and a transistor 1443 may be built in.

  Further, instead of the reference voltage circuit 1441 as shown in FIG. 144, a reference voltage Vref may be generated by a Zener diode 1451 and a resistor 691 as shown in FIG. 145 (b). Of course, it is not necessary to use the operational amplifier 722 as shown in FIG. The Zener diode 1451 may adopt a variable type of reference voltage.

  When the number of pixels of the EL display panel is large, it is necessary to load a plurality of source driver ICs (circuits) 14 on one EL display panel. In this case, it is necessary to use the reference voltage so as to be common to a plurality of source driver ICs. Simply, a plurality of source driver ICs 14 using the reference voltage Vref from one reference voltage circuit 1441 may be input. A problem arises when the electronic voltage 561 in FIG. 144 is scanned and the reference voltage input to the operational amplifier 722 changes. Hereinafter, for ease of explanation, a voltage input to the + terminal of the operational amplifier is referred to as an adjustment reference voltage Vrs. Vrs is a voltage obtained by adjusting the reference voltage Vref to a voltage used in the IC 14.

  As described above, according to the present invention, in a current output (source) driver circuit (IC), a reference voltage is generated internally or input from the outside, and a reference current is generated from the reference voltage. A plurality of unit current sources 634 are configured, and an output (absorbed) current is changed by switching the number of unit current sources 634 according to an external video (image) data signal.

  When the adjustment reference voltage Vrs is used, it is necessary to use this adjustment reference voltage Vrs in another source driver 14. FIG. 146 shows an example. The reference voltage Vref from the reference voltage circuit 1441 is adjusted by the electronic volume circuit 561a to become the adjusted reference voltage Vrs. This adjustment reference voltage Vrs is input to the buffer circuit 1462. The reason why the buffer circuit 1462 is arranged is to suppress the fluctuation of the Vrs voltage due to the connection of the other source driver 14 to the adjustment reference voltage output wiring 1453. The output Vrs of the buffer circuit 1462 is applied to the + terminal of the operational amplifier 722 and also applied to the adjustment reference voltage output wiring 1463.

  The adjustment reference voltage output wiring 1463 is connected to the adjustment reference voltage output terminal 1471. A wiring 1461 is connected to the adjustment reference voltage output terminal 1471, and the adjustment reference voltage Vrs is supplied to the other source driver circuit 14 through this wiring 1461.

  In FIG. 146, an electronic volume 561b is formed or arranged between the terminal 761b and the emitter terminal of the transistor 1443. The configuration of the electronic volume 561b is the same as that of the electronic volume 561a. However, the electronic volume 561b changes the magnitude of the reference current depending on the magnitude of the resistance value. That is, the electronic volume 561b changes the number of series resistors by turning on and off an internal switch. The magnitude of the reference current varies depending on the resistance value of the electronic volume 561b + the resistance 691 and the Vrs voltage. The maximum resistance of the electronic volume 561b is set to 1/5 or less of the resistance of the resistor 691. This is because variation in the resistance value of the electronic volume 561b results in variation in the reference current. The electronic volume 561b is mainly used for temperature characteristic compensation of the EL element 15.

In order to realize full color display on an EL display panel, it is necessary to form (create) a reference current for each of RGB. White balance can be adjusted by the ratio of RGB reference currents. In the case of the current driving method, as shown in FIG. 83, the current I and the luminance B have a linear relationship. Further, according to the present invention, a current value that the unit current source 634 flows is determined from one reference current. Therefore, if the magnitude of the reference current is determined, the current that the unit current source 634 flows can be determined. For this reason, if R, G, and B reference currents are set, white balance can be obtained in all gradations. The above matter is a significant feature of the source driver circuit 14 being current step output (current drive). Therefore, the point is how to set the magnitude of the RGB reference current.

  The luminous efficiency of the EL element is determined (dominant) by the thickness of the deposited or applied EL material. The film thickness is almost constant from lot to lot. Therefore, if the formed film thickness of the EL element 15 is managed as a lot, the relationship between the current passed through the EL element 15 and the emission luminance is determined. That is, the current value for white balance is fixed for each lot. For example, if the current flowing through the R EL element 15 is Ir (A), the current flowing through the G EL element 15 is Ig (A), and the current flowing through the B EL element 15 is Ib (A), then Ir: Ig : It can be seen that white balance can be obtained when Ib = 1: 2: 4. Therefore, the value of the fixed resistor 691 is determined so that this current flows. If the resistor 691R of the R circuit is Rr (Ω), the resistor 691G of the G circuit is Rg (Ω), the resistor 691B of the B circuit is Rb (Ω), and the adjustment reference voltage Vrs is common to RGB, Rr: Rg: The resistance value 691 may be set so that Rb = 4: 2: 1. By simply setting in this way, the EL display panel of the present invention can achieve white balance over all gradations. This is a very effective effect.

  The configuration described above is illustrated in FIG. A reference voltage Vref from one reference voltage circuit 1441 is input to the source driver circuit 14 through a terminal 761a. This voltage is adjusted by the RGB electronic volume circuits 561a (561Ra, 561Ga, 561Ba) as necessary, and the adjustment reference voltage Vrs (VrsR for the R circuit, VrsG for the G circuit, VrsB for the B circuit) is each RGB. To the operational amplifier 722.

  The adjustment reference voltage VrsR of the R circuit is connected to the adjustment reference voltage output terminal 1471R for cascading with other source driver circuits 14. Similarly, the adjustment reference voltage VrsG of the G circuit is also connected to the adjustment reference voltage output terminal 1471G for cascade connection with the other source driver circuits 14. Further, the adjustment reference voltage VrsB of the B circuit is also connected to the adjustment reference voltage output terminal 1471B in order to cascade-connect with the other source driver circuit 14. The other points are the same as in FIG.

  In the embodiment of FIG. 147, the adjustment reference voltages (VrsR, VrsG, VrsB) are output from the terminal 1471 for each of RGB, but the present invention is not limited to this. When adjustment is not necessary in the electronic volume circuit 561a (561Ra, 561Ga, 561Ba) for each RGB (for example, when white balance adjustment, temperature compensation, etc. can be performed with the fixed resistor 691 arranged or formed for each RGB) The output of the adjustment reference voltage Vrs for each RGB is not necessary. Needless to say, when the reference voltage Vref from the outside can be used as it is (when the + terminal input of the operational amplifier 722 is set to Vref), the electronic volume circuits 561a (561Ra, 561Ga, 561Ba) for each RGB are not necessary. .

  The source driver circuit (IC) 14 needs to switch between using the reference voltage Vref or adjusting reference voltage Vrs for cascade connection. FIG. 148 shows an embodiment of the source driver circuit (IC) 14 of the present invention in which a reference voltage changeover switch 1482 is built.

  In order to set whether to use the reference voltage Vref or the adjustment reference voltage Vrs, in the present invention, a switching terminal (not shown) of the switch 1482 is provided as an IC terminal, and the logic voltage applied to this terminal Switch 1482 can be switched. This is also used as a master / slave selector switch of the IC 14. Since the master / slave function is described in FIGS. 82, 93, 94, etc., the description thereof is omitted.

  The reference voltage changeover switch 1482 switches whether the output voltage V2 of the electronic volume circuit 561 in the IC 14 is input to the operational amplifier 722 or the external reference voltage V1 applied to the terminal 1483 is input to the operational amplifier 722. When the V2 voltage is input to the operational amplifier 722, the IC (circuit) 14 is used in the master mode. In this case, the V2 voltage is output from the terminal 1471, and the adjustment reference voltage input terminal 1483 of the source driver IC (circuit) 14 serving as the slave is connected to the wiring 1461 connected to the terminal 1471. As described above, when the plurality of source driver circuits (IC) 14 operate using the reference voltage Vref from one reference voltage circuit 1441 as an input without distinguishing between master and slave, the changeover switch 1482 is It is unnecessary. This is because the reference voltage Vref or the adjustment reference voltage Vrs generated inside the IC becomes the + terminal input of the operational amplifier 722 of each IC. In addition, since other matters have been described above, description thereof will be omitted.

  An important matter in FIG. 148 is that two adjustment reference voltage input terminals 1483 are provided. Inside the IC 14, terminals 1483a and 1483b are connected. This point will be described with reference to FIG.

  FIG. 149 conceptually illustrates a state where a plurality of source driver circuits (ICs) 14 are mounted. The drawing shows a state observed through the back surface of the substrate 71 (observed from the back surface of the IC 14). Note that items related to the base anode wiring 951, the common anode wiring 962, and the like have been described with reference to FIGS. 97, 99, 103, and the like, and thus description thereof will be omitted. The above matters are the same for FIGS. 150 and 151.

  In FIG. 149, the terminals 1471 and 1483 are arranged at the center of the IC 14 chip and arranged (formed) so as to be parallel to the forming direction of the source signal line 18 (parallel to the short side direction of the IC chip). ing. As described above, the wiring is formed so that the wiring 1461 connected to the terminal does not intersect.

  A reference voltage Vref is applied from the reference voltage circuit 1441 to the terminal 761a to the IC 14a through the wiring 992. Therefore, the IC 14a operates as a master. The changeover switch 1482 in the IC is in an input state of the V2 voltage (see FIG. 148). The ICs 14b and 14c mounted adjacent to the IC 14a operate as slaves. The changeover switch 1482 of the ICs 14b and 14c is in the V1 voltage input state (see FIG. 148).

  In FIG. 149, the adjustment voltage Vrs from the IC 14a is output from each RGB adjustment reference voltage output terminal 1471 (1471R, 1471G, 1471B), and the adjustment voltage input terminal 1483 (1483R) of the IC 14b, IC 14c via the wiring 1461 or 1481. , 1483G, 1483B). This voltage is the V2 voltage.

  If the RGB terminals 1471 and 1483 are arranged as shown in FIG. 149, the wirings 1481 and 1461 do not cross each RGB. Therefore, the wiring layout is facilitated. Further, since only the reference current flows through the wirings 1471 and 1481, there is no potential change as in the video signal line. Therefore, it can be used as a light shielding pattern as well as the base anode line 951. That is, even if it is arranged on the back surface of the IC 14, noise or the like is generated and the IC 14 is not affected. This effect can be applied as it is by replacing the base anode line 951 with the wiring 1471 (1481) in the matters described with reference to FIG.

FIG. 150 is an explanatory diagram of the effect of forming a plurality of adjustment reference voltage input terminals 1483 described in FIG. 150, unlike FIG. 149, terminals 1471 and 1483 are formed at the edge of the IC chip 14. In FIG. That is, they are formed or arranged on the same side as the video signal input terminal and control terminal of the IC.

  In the IC 14a, the reference voltage Vref from the reference voltage circuit 1441 is applied to the terminal 761a through the wiring 992. Therefore, the IC 14a operates as a master. The changeover switch 1482 in the IC is in an input state of the V2 voltage (see FIG. 148). The ICs 14b and 14c mounted adjacent to the IC 14a operate as slaves. The changeover switch 1482 of the ICs 14b and 14c is in the V1 voltage input state (see FIG. 148).

  In FIG. 150, the adjustment voltage Vrs from the IC 14a is output from the adjustment reference voltage output terminal 1471. Although not shown in FIG. 148, one adjustment reference voltage output terminal 1471 is formed on the left and right sides of the reference voltage input terminal 761a (1471a and 1471b). The adjustment reference voltage Vrs is input to the adjustment voltage input terminal 1483 (1483a, 1483b) of the IC 14b and IC 14c via the wiring 1461 or 1481. This voltage is the V2 voltage.

  The adjustment reference voltage input terminals 1483a and 1483b are electrically connected as shown in FIG. Therefore, the voltage Vrs output from the terminal 1471a of the IC 14a is applied to the terminal 1483b of the IC 14b, and this voltage Vrs is output to the terminal 1483a through the IC 16b. In addition, the terminal 1483a is input to the terminal 1483 in another IC 14 mounted adjacently. Similarly, the voltage Vrs output from the terminal 1471b of the IC 14a is applied to the terminal 1483a of the IC 14c, and this voltage Vrs is output to the terminal 1483b through the IC 16c. In addition, the terminal 1483b is input to the terminal 1483 in another IC 14 mounted adjacently. By arranging or connecting the terminals 1483 and 1471 as described above, ICs can be connected in cascade.

  If the terminals 1471 and 1483 are arranged as shown in FIG. 150 and the wirings 1481 and 1461 are formed on the back surface of the IC, the wirings 1481 and 1461 do not cross each other. Therefore, the wiring layout is facilitated. Similarly to FIG. 149, since only the reference current flows through the wirings 1471 and 1481, there is no potential change as in the video signal line. Therefore, it can be used as a light shielding pattern as well as the base anode line 951. That is, even if it is arranged on the back surface of the IC 14, noise or the like is generated and the IC 14 is not affected. This effect can be applied as it is by replacing the base anode line 951 with the wiring 1471 (1481) in the matters described with reference to FIG.

  In FIG. 150, for ease of explanation, the EL display device is illustrated in a single color. The EL display device is composed of three colors of RGB. Therefore, terminals 1471 and 1483 are necessary for each RGB. FIG. 151 is a configuration diagram in which terminals 1471 and 1483 are arranged for each RGB.

  The IC 14a operates as a master, and the reference voltage Vref from the reference voltage circuit 1441 is applied to the terminal 761a. Adjusted reference voltage output terminals 1471 are arranged on the left and right sides of the reference voltage input terminal 761a. Each RGB adjustment reference voltage output terminal 1471 is arranged at a line-symmetrical position around the reference voltage input terminal 761a. That is, the left and right terminals of the input terminal 761a are 1471Ra and 1471Rb, and 1471Ga and 1471Gb are arranged outside the terminals. Further, 1471Ba and 1471Bb are arranged outside thereof. The terminals 1471Ra and 1471Rb are connected inside the IC 14a. Similarly, the terminals 1471Ga and 1471Gb are also connected inside the IC 14a. Terminals 1471Ba and 1471Bb are also connected inside the IC 14a.

  The IC 14b operates as a slave, and the adjustment reference voltage Vrs from the IC 14a is input to the IC 14b. Adjusted reference voltage input terminals 1483 are arranged on the left and right sides of the reference voltage input terminal 761a. Each RGB adjustment reference voltage input terminal 1483 is arranged at a line-symmetrical position with respect to the reference voltage input terminal 761a. That is, the left and right terminals of the input terminal 761a are 1483Ra and 1483Rb, and 1483Ga and 1483Gb are arranged outside the terminals. Further, 1483Ba and 1483Bb are arranged outside thereof. The terminals 1483Ra and 1483Rb are connected inside the IC 14a. Similarly, the terminals 1483Ga and 1483Gb are also connected inside the IC 14a. Terminals 1483Ba and 1483Bb are also connected inside the IC 14a (see FIG. 148).

  The voltage Vrs output from the terminal 1471Bb of the IC 14a is applied to the terminal 1483Ba of the IC 14b, and this voltage Vrs is output to the terminal 1483Bb through the IC 16b. Further, the terminal 1483Bb is input to the terminal 1483 in another IC 14 mounted adjacently. The voltage Vrs output from the terminal 1471Gb of the IC 14a is applied to the terminal 1483Ga of the IC 14b, and this voltage Vrs is output to the terminal 1483Gb through the IC 16b. In addition, the terminal 1483Gb is input to the terminal 1483 in another IC 14 mounted adjacently. Similarly, the voltage Vrs output from the terminal 1471Rb of the IC 14a is applied to the terminal 1483Ra of the IC 14b, and this voltage Vrs is output to the terminal 1483Rb through the IC 16b. Further, the terminal 1483Rb is input to the terminal 1483 in another IC 14 mounted adjacently. By arranging or connecting the terminals 1483 and 1471 as described above, the IC can be easily connected to the cascade.

  If the terminals 1471 and 1483 are disposed as shown in FIG. 151 and the wirings 1481 and 1461 are formed on the back surface of the IC, the wirings 1481 and 1461 do not cross each other. Therefore, the wiring layout is facilitated. Similarly to FIG. 149, since only the reference current flows through the wirings 1471 and 1481, there is no potential change as in the video signal line. Therefore, it can be used as a light shielding pattern as well as the base anode line 951. That is, even if it is arranged on the back surface of the IC 14, noise or the like is generated and the IC 14 is not affected. This effect can be applied as it is by replacing the base anode line 951 with the wiring 1471 (1481) in the matters described with reference to FIG.

  73, 74, 79, 80, 81, etc., the gamma current ratio has been described. This is the ratio of the current flowing through the unit current source 634 in the low gradation part of FIG. 73 to the current flowing through the unit current source 634 in the high gradation part of FIG. It is preferable to set the reference current of the high gradation part to INH and the reference current of the low gradation part to INL, and to set this ratio (gamma current ratio) within a predetermined range, while the reference current is basically Therefore, it is preferable to reduce the adjustment to one current as much as possible (if the reference current for the high gradation part is INH and the reference current for the low gradation part is INL, two reference currents for each RGB) Adjustment is required).

  FIG. 152 shows a configuration in which each RGB has a single reference current Ib. The upper circuit in FIG. 152 is a current source for high gradation, and the lower is a current source for low gradation (more precisely, the current of the low gradation current source also flows in the high gradation portion). The left part of FIG. 152 is the circuit configuration of FIGS. 146 and 148.

An original reference current Ib flows through the transistor 1443. At least one variable magnification transistor 1522 is formed or arranged in parallel with the high gradation parent transistor 631aH. The low-gradation parent transistor 631aL forms a current mirror circuit with the transistor 1444 as it is. Therefore, the current mirror circuit for high gradation is composed of the transistor 1444 and the transistor 1522 + the transistor 631aH. A variable magnification switch 1521 is formed or arranged in series with the transistor 1522. The switch 1521 is exemplified by an analog switch.

  By controlling on / off of the switch 1521, the current flowing through the transistor 631bH can be changed. When the switch 1521b is turned on, two transistors 1522 + current flowing through the transistor 631aH flows through the transistor 631bH. When the switch 1521a is turned on, one transistor 1522 + a current flowing through the transistor 631aH flows through the transistor 631bH. When the switches 1521a and 1521b are turned on at the same time, three transistors 1522 + current flowing through the transistor 631aH flows through the transistor 631bH. The switch 1521 is switched by a command to the IC 14. As described above, the gamma current ratio can be changed by the control of the switch 1521. Also, since the reference current is only Ib, the white balance can be adjusted very easily. Other configurations have been described with reference to FIGS. 68, 146, 148, 73, 74, 79, 80, 81, and the like, and will not be described.

  When modularizing the organic EL display panel, there is a problem of resistance values of routing (arrangement) of the anode wiring 951 and the cathode wiring as a problem. The organic EL display panel has a large current flowing through the EL element 15, although the drive voltage of the EL element 15 is relatively low. Therefore, it is necessary to thicken the anode wiring and cathode wiring for supplying current to the EL element 15. As an example, even in a 2-inch class EL display panel, in a polymer EL material, it is necessary to pass a current of 200 mA or more to the anode wiring 951. Therefore, in order to prevent a voltage drop of the anode wiring 951, it is necessary to reduce the resistance of the anode wiring to 1Ω or less. However, in the array substrate 71, since the wiring is formed by thin film deposition, it is difficult to reduce the resistance. Therefore, it is necessary to increase the pattern width. However, in order to transmit a current of 200 mA with almost no voltage drop, there is a problem that the wiring width becomes 2 mm or more.

  FIG. 105 shows a configuration of a conventional EL display panel. Built-in gate drivers 12 a and 12 b are formed (arranged) on the left and right sides of the display area 50. The source driver circuit 14p is also formed by the same process as the TFT of the pixel 16 (built-in source driver circuit).

  The anode wiring 951 is arranged on the right side of the panel. A Vdd voltage is applied to the anode wiring 951. The width of the anode wiring 951 is 2 mm or more as an example. The anode wiring 951 is branched from the lower end of the screen to the upper end of the screen. The number of branches is the number of pixel columns. For example, in the QCIF panel, 176 columns × RGB = 528 lines. On the other hand, the source signal line 18 is output from the built-in source driver 14p. The source signal line 18 is arranged (formed) from the upper end of the screen to the lower end of the screen. The power supply wiring 1051 of the built-in gate driver 12 is also arranged on the left and right of the screen.

  Therefore, the frame on the right side of the display panel cannot be narrowed. At present, narrowing the frame is important for display panels used in mobile phones and the like. It is also important to make the left and right picture frames uniform. However, it is difficult to narrow the frame with the configuration of FIG.

In order to solve this problem, in the display panel of the present invention, as shown in FIG. 106, the anode wiring 951 is disposed (formed) at a position located on the back surface of the source driver IC 14 and on the array surface. The source driver circuit (IC) 14 is formed (manufactured) by a semiconductor chip and mounted on the substrate 71 by a COG (chip on glass) technique. The reason why the anode wiring 951 can be arranged (formed) in the source driver IC 14 is that there is a space of 10 μm to 30 μm on the back surface of the chip 14 in the direction perpendicular to the substrate. When the source driver circuit 14p is directly formed on the array substrate 71 as shown in FIG. 105, anode wiring (base anode line, anode) is formed on the lower layer or upper layer of the source driver circuit 14p due to mask number problems, yield problems, and noise problems. It is difficult to form a voltage line (basic anode line) 951.

  Also, as shown in FIG. 106, a common anode line 962 is formed, and the base anode line 951 and the common anode line 962 are short-circuited by the connection anode line 961. In particular, the point is that the connection anode line 961 at the center of the IC chip is formed. By forming the connection anode line 961, the potential difference between the base anode line 951 and the common anode line 962 is eliminated. The point is that the anode wiring 952 branches off from the common anode line 962. By adopting the above configuration, the anode wiring 951 is not routed as shown in FIG. 105, and a narrow frame can be realized.

  If the common anode line 962 is 20 mm long, the wiring width is 150 μm, and the sheet resistance of the wiring is 0.05Ω / □, the resistance value is 20000 (μm) / 150 (μm) × 0.05Ω = about 7Ω. Become. If both ends of the common anode line 962 are connected to the base anode line 951 by the connection anode line 961c, both sides are fed to the common anode line 962, so that the apparent resistance value is 7Ω / 2 = 3.5Ω, If the concentrated distribution multiplier is replaced, the apparent resistance value of the common anode line 962 is ½, so that it is at least 2Ω or less. Even if the anode current is 100 mA, the voltage drop in the common anode line 962 is 0.2 V or less. Further, if a short circuit is caused by the connecting anode line 961b in the central portion, almost no voltage drop can be generated.

  In the present invention, the base anode line 951 is formed under the IC 14, the common anode line 962 is formed, the common anode line 962 and the base anode line 951 are electrically connected (connection anode line 961), and the common anode The anode wiring 952 is branched from the line 962. The anode line can be replaced with a cathode line.

  Further, in order to reduce the resistance of the anode lines (base anode line 951, common anode line 962, connection anode line 961, anode wiring 952, etc.), after forming a thin film wiring or before patterning, an electroless plating technique, electrolytic Using a plating technique or the like, a conductive material may be laminated to increase the thickness. By increasing the film thickness, the cross-sectional area of the wiring becomes wider and the resistance can be reduced. The same applies to the cathode. The present invention can also be applied to the gate signal line 17 and the source signal line 18.

  Therefore, the effect of the configuration in which the common anode line 962 is formed and the common anode line 962 is fed on both sides with the connection anode line 961 is highly effective, and the connection anode line 961b (961c) is formed at the center portion to further increase the effect. Becomes higher. In addition, since the base anode line 951, the common anode line 962, and the connection anode line 961 form a loop, an electric field input to the IC 14 can be suppressed.

  The common anode line 962 and the base anode line 951 are preferably formed of the same metal material, and the connection anode line 961 is preferably formed of the same metal material. Further, these anode lines are realized by a metal material or a structure having the lowest resistance value that forms the array. Generally, it is realized by the metal material and the configuration (SD layer) of the source signal line 18. A portion where the common anode line 962 and the source signal line 18 intersect cannot be formed of the same material. Therefore, the intersecting portion is formed of another metal material (the same material and configuration as the gate signal line 17 and a GE layer) and is electrically insulated by the insulating film. Of course, the anode line may be formed by laminating a thin film made of the constituent material of the source signal line 18 and a thin film made of the constituent material of the gate signal line 17.

Although wiring for supplying current to the EL element 15 such as anode wiring (cathode wiring) is laid (arranged or formed) on the back surface of the source driver IC 14, it is not limited to this. For example, the gate driver circuit 12 may be formed by an IC chip and this IC may be COG mounted. An anode wiring and a cathode wiring are arranged (formed) on the back surface of the gate driver IC 12. As described above, according to the present invention, in an EL display device or the like, a drive IC is formed (manufactured) with a semiconductor chip, this IC is directly mounted on a substrate such as the array substrate 71, and the back surface of the IC chip is formed in a space portion. A power source or a ground pattern such as an anode wiring and a cathode wiring is formed (manufactured).

  The above items will be described in more detail with reference to other drawings. FIG. 95 is an explanatory diagram of part of the display panel of the present invention. In FIG. 95, a dotted line is a position where the IC chip 14 is disposed. That is, the base anode line (anode voltage line, ie, the anode wiring before branching) is formed (arranged) on the back surface of the IC chip 14 and on the array substrate 71. In the embodiment of the present invention, it will be described that the pre-branching anode wiring 951 is formed on the back surface of the IC chip (12, 14), but this is for ease of explanation. For example, a cathode wiring or cathode film before branching may be formed (arranged) instead of the anode wiring 951 before branching. In addition, the power supply wiring 1051 of the gate driver circuit 12 may be arranged or formed.

  The IC chip 14 is connected to a current output (current input) terminal 741 and a connection terminal 953 formed in the array 71 by COG technology. The connection terminal 953 is formed at one end of the source signal line 18. The connection terminals 953 are in a staggered arrangement such as 953a and 953b. Note that a connection terminal 953 is formed at one end of the source signal line, and a check terminal electrode is formed at the other end.

  In the present invention, the IC chip is a current-driven driver IC (a method for programming a pixel with a current). However, the present invention is not limited to this. For example, the present invention can also be applied to an EL display panel (device) on which a voltage-driven driver IC for driving pixels of the voltage program shown in FIGS. 43 and 53 is mounted.

  An anode wiring 952 (branched anode wiring) is arranged between the connection terminals 953a and 953b. That is, the anode wiring 952 branched from the thick, low-resistance base anode line 951 is formed between the connection terminals 953 and arranged along the 16 columns of pixels. Therefore, the anode wiring 952 and the source signal line 18 are formed (arranged) in parallel. With the configuration (formation) as described above, the Vdd voltage can be supplied to each pixel without drawing the base anode line 951 across the screen as shown in FIG.

  FIG. 96 is more specifically illustrated. A difference from FIG. 95 is that the anode wiring is not disposed between the connection terminals 953 but is branched from a separately formed common anode line 962. The common anode line 962 and the base anode line 951 are connected by a connection anode line 961.

  FIG. 96 shows the state of the back surface as seen through the IC chip 14. The IC chip 14 is provided with a current output circuit 704 that outputs a program current Iw to an output terminal 761. Basically, the output terminal 761 and the current output circuit 704 are regularly arranged. In the central part of the IC chip 14, a circuit for producing a basic current of the parent current source and a control circuit are formed. Therefore, the output terminal 761 is not formed at the center of the IC chip (because the current output circuit 704 cannot be formed at the center of the IC chip).

In the present invention, the output terminal 761 is not formed on the IC chip in the central portion 704a of FIG. 96 (because there is no output circuit. Note that a control circuit or the like is provided in the central portion of the IC chip such as a source driver. There are many cases where the output circuit is not formed). The IC chip of the present invention pays attention to this point, and does not form (arrange) the output terminal 761 in the central part of the IC chip (a control circuit or the like is formed in the central part of the IC chip such as a source driver). Even if it is not formed, it is common that a dummy pad is provided at the center and an output terminal (pad) is formed), and a common anode line 961 is formed at this position ( However, the common anode line 961 is formed on the surface of the array substrate 71). The connection anode line 961 has a width of 50 μm or more and 1000 μm or less. The resistance (maximum resistance) value with respect to the length is set to 100Ω or less.

  By short-circuiting the base anode line 951 and the common anode line 962 with the connection anode line 961, a voltage drop caused by a current flowing through the common anode line 962 is suppressed as much as possible. That is, the connection anode line 961 which is a constituent element of the present invention effectively utilizes the point that there is no output circuit in the central portion of the IC chip. In addition, by removing the output terminal 761 conventionally formed as a dummy pad at the center of the IC chip, the IC chip is electrically affected by the contact between the dummy pad and the connection anode line 961. Is preventing. However, when this dummy pad is electrically insulated from the base substrate (chip ground) of the IC chip and other components, there is no problem even if the dummy pad contacts the connection anode line 961. Therefore, it goes without saying that the dummy pad may be formed in the central portion of the IC chip.

  More specifically, the connection anode line 961 and the common anode line 962 are formed (arranged) as shown in FIG. First, the connection anode line 961 has a thick part (961a) and a thin part (961b). The thick part (961a) is for reducing the resistance value. The thin portion (961b) is for forming a connection anode line 961b between the output terminals 963 and connecting to the common anode line 962.

  Further, the connection between the base anode line 951 and the common anode line 962 is short-circuited not only at the central connection anode line 961b but also at the left and right connection anode lines 961c. Therefore, the common anode line 962 and the base anode line 951 are short-circuited by the three connection anode lines 961. Therefore, even if a large current flows through the common anode line 962, a voltage drop is unlikely to occur in the common anode line 962. This is because the IC chip 14 usually has a width of 2 mm or more, and the line width of the base anode line 951 formed under the IC 14 can be increased (impedance can be reduced). For this reason, since the low-impedance base anode line 951 and the common anode line 962 are short-circuited by the connection anode line 961 at a plurality of locations, the voltage drop of the common anode line 962 becomes small.

  As described above, the voltage drop in the common anode line 962 can be reduced because the base anode line 951 can be disposed (formed) under the IC chip 14 and the left and right positions of the IC chip 14 are used. The connection anode line 961b can be disposed (formed) in the central portion of the IC chip 14.

  In FIG. 99, a base anode line 951 and a cathode power supply line (base cathode line) 991 are stacked with an insulating film 102 interposed therebetween. The laminated portion forms a capacitor (this configuration is referred to as an anode capacitor configuration). This capacitor functions as a power supply pass capacitor. Therefore, a rapid current change in the base anode line 951 can be absorbed. The capacitance of the capacitor preferably satisfies a relationship of M / 200 ≦ C ≦ M / 10 or less, where the display area of the EL display device is S square millimeters and the capacitance of the capacitor is C (pF). Furthermore, it is preferable to satisfy the relationship of M / 100 ≦ C ≦ M / 20 or less. If C is small, it is difficult to absorb a change in current. If C is large, the capacitor formation area becomes too large, which is not practical.

In the embodiment shown in FIG. 99 and the like, the base anode line 951 is disposed (formed) under the IC chip 14, but it goes without saying that the anode line may be a cathode line. In FIG. 99, the base cathode line 991 and the base anode line 951 may be interchanged. The technical idea of the present invention is that a driver is formed of a semiconductor chip, the semiconductor chip is mounted on an array substrate 71 or a flexible substrate, and a power source such as an EL element 15 or a ground potential (current) is supplied to the lower surface of the semiconductor chip. The point is to arrange (form) wiring and the like.

  Therefore, the semiconductor chip is not limited to the source driver 14, but may be the gate driver 12 or a power supply IC. Also included is a configuration in which a semiconductor chip is mounted on a flexible substrate, and a power source or a ground pattern such as an EL element 15 is wired (formed) on the surface of the flexible substrate and the lower surface of the semiconductor chip. Of course, both the source driver IC 14 and the gate driver IC 12 may be configured by semiconductor chips, and COG mounting may occur on the substrate 71. A power supply or ground pattern may be formed on the lower surface of the chip. Further, although the power source or the grant pattern for the EL element 15 is used, the present invention is not limited to this. Further, the present invention is not limited to an EL display device, and can be applied to a liquid crystal display device. In addition, the present invention can be applied to display panels such as FED and PDP. The above matters are the same in other embodiments of the present invention.

  FIG. 97 shows another embodiment of the present invention. 95 differs from the main FIG. 95, FIG. 96, and FIG. 99 in that the anode wiring 952 is arranged between the output terminals 953 in FIG. 95, whereas in FIG. 961d is branched, and the connection anode line 961d is short-circuited to the common anode line 962. Further, the thin connection anode line 961d and the source signal line 18 connected to the connection terminal 953 are stacked with the insulating film 102 interposed therebetween.

  The anode line 961d is connected to the base anode line 951 through a contact hole 971a, and the anode wiring 952 is connected to the common anode line 962 through a contact hole 971b. Other points (connection anode lines 961a, 961b, 961c, anode capacitor configuration, etc.) are the same as those in FIGS.

A sectional view taken along line aa ′ of FIG. 99 is shown in FIG. In FIG. 98 (a), the source signal line 18 having substantially the same width is laminated with the connecting anode line 961d through the insulating film 102a.
The thickness of the insulating film 102a is set to be 500 Å or more and 3000 Å (Å) or less. More preferably, it is 800 angstroms or more and 2000 angstroms (Å) or less. If the film thickness is thin, the parasitic capacitance between the connection anode line 961d and the source signal line 18 becomes large, and a short circuit between the connection anode line 961d and the source signal line 18 is likely to occur, which is not preferable. On the other hand, if it is thick, it takes a long time to form the insulating film, resulting in a longer manufacturing time and higher cost. In addition, it is difficult to form the upper wiring. The insulating film 102 is exemplified by the same material as an organic material such as polybiphenyl alcohol (PVA) resin, epoxy resin, polypropylene resin, phenol resin, acrylic resin, polyimide resin, etc. In addition, SiO ₂ , SiN _x Inorganic materials such as are exemplified. Needless to say, Al ₂ O ₃ , Ta ₂ O _{3 and the} like may be used. In addition, as shown in FIG. 98A, an insulating film 102b is formed on the outermost surface to prevent corrosion and mechanical damage of the wiring 961 and the like.

In FIG. 98B, a connection anode line 961d having a line width narrower than that of the source signal line 18 is laminated on the source signal line 18 with an insulating film 102a interposed therebetween. By configuring as described above, it is possible to suppress a short circuit between the source signal line 18 and the connection anode line 961d due to a step of the source signal line 18. In the configuration of FIG. 98B, the line width of the connection anode line 961d is preferably narrower by 0.5 μm or more than the line width of the source signal line 18. Furthermore, it is preferable that the line width of the connection anode line 961 d be narrower by 0.8 μm or more than the line width of the source signal line 18.

  In FIG. 98B, the connection anode line 961d having a line width narrower than that of the source signal line 18 is stacked on the source signal line 18 via the insulating film 102a. As described above, the source signal line 18 having a line width narrower than that of the connection anode signal line 961d may be stacked on the connection anode line 961d via the insulating film 102a. Since other matters are the same as those of the other embodiments, description thereof is omitted.

  FIG. 100 is a cross-sectional view of the IC chip 14 part. Basically, the configuration shown in FIG. 99 is used as a reference, but the same applies to FIGS. 96 and 97. Or it can be applied similarly.

  FIG. 100B is a cross-sectional view taken along AA ′ in FIG. As is clear from FIG. 100B, the output pad 761 is not formed (arranged) in the central portion of the IC chip 14. This output pad is connected to the source signal line 18 of the display panel. The output pad 761 has bumps (projections) formed by a plating technique or a nail head bonder technique. The height of the protrusion is set to be 10 μm or more and 40 μm or less. Of course, it goes without saying that the protrusions may be formed by a gold plating technique (electrolysis or electroless).

The protrusions and the source signal lines 18 are electrically connected via a conductive bonding layer (not shown). The conductive bonding layer is mainly composed of epoxy, phenol, etc. as an adhesive, and mixed with flakes such as silver (Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO ₂ ). Or ultraviolet curable resin. The conductive bonding layer (connection resin) 1001 is formed on the bump by a technique such as transfer. Alternatively, the protrusion and the source signal line 18 are thermocompression bonded with the ACF resin 1001. Note that the connection between the protrusion or output pad 761 and the source signal line 18 is not limited to the above method. Alternatively, the film carrier technology may be used without mounting the IC 14 on the array substrate. Further, the source signal line 18 or the like may be connected using a polyimide film or the like. FIG. 100A is a cross-sectional view of a portion where the source signal line 18 and the common anode line 962 overlap each other (see FIG. 98).

  An anode wiring 952 is branched from the common anode line 962. In the case of a QCIF panel, the anode wiring 952 is 176 × RGB = 528. The Vdd voltage (anode voltage) illustrated in FIG. 1 and the like is supplied through the anode wiring 952. When the EL element 15 is made of a low molecular material, a current of about 200 μA at the maximum flows through one anode wiring 952. Therefore, a current of about 100 mA flows through the common anode wiring 962 at 200 μA × 528.

  Therefore, in order to make the voltage drop in the common anode wiring 962 within 0.2 (V), the resistance value of the maximum path through which the current flows needs to be 2Ω (assuming 100 mA flows) or less. In the present invention, as shown in FIG. 99, the connection anode lines 961 are formed at three places. Therefore, when the circuit is placed again in the lumped distribution circuit, the resistance value of the common anode line 962 can be easily designed to be extremely small. If a large number of connection anode lines 961d are formed as shown in FIG. 97, the voltage drop in the common anode line 962 is almost eliminated.

  The problem is the influence of parasitic capacitance (referred to as common anode parasitic capacitance) at the overlapping portion of the common anode line 962 and the source signal line 18. Basically, in the current driving method, it is difficult to write the black display current if the source signal line 18 for writing current has a parasitic capacitance. Therefore, it is necessary to make the parasitic capacitance as small as possible.

The common anode parasitic capacitance needs to be 1/10 or less of the parasitic capacitance (referred to as display parasitic capacitance) generated in at least one source signal line 18 in the display region. For example, if the display parasitic capacitance is 10 (pF), it must be 1 (pF) or less. More preferably, it should be 1/20 or less (referred to as display parasitic capacitance). If the display parasitic capacitance is 10 (pF), it must be 0.5 (pF) or less. Considering this point, the line width of the common anode line 962 (M in FIG. 103) and the film thickness of the insulating film 102 (see FIG. 101) are determined.

  The base anode line 951 is formed (arranged) under the IC chip 14. It goes without saying that the line width to be formed should be as thick as possible from the viewpoint of reducing resistance. In addition, the base anode wiring 951 preferably has a light shielding function. This explanatory diagram is shown in FIG. Needless to say, if the base anode wiring 951 is formed of a metal material with a predetermined film thickness, there is a light shielding effect. In addition, when the base anode line 951 cannot be made thick or is formed of a transparent material such as ITO, a light absorption film or a light reflection film is laminated under the IC chip 14 on the base anode line 951 or in multiple layers ( Basically, it is formed on the surface of the array 71. Further, the light shielding film (base anode line 951) in FIG. 102 does not need to be a complete light shielding film. There may be an opening in the part. Moreover, what exhibits a diffraction effect and a scattering effect may be used. Further, a light shielding film made of an optical interference multilayer film may be formed or disposed by being laminated on the base anode line 951.

  Of course, it goes without saying that a reflecting plate (sheet) made of metal foil, a plate or a sheet, and a light absorbing plate (sheet) may be arranged, inserted or formed in the space between the array substrate 71 and the IC chip 14. Needless to say, the present invention is not limited to metal foil, and a reflecting plate (sheet) made of an organic material or an inorganic material, a plate or sheet, and a light absorbing plate (sheet) may be arranged, inserted, or formed. Further, a light absorbing material or a light reflecting material made of gel or liquid may be injected or disposed in the space between the array substrate 71 and the IC chip 14. Furthermore, it is preferable to cure the light absorbing material and the light reflecting material made of the gel or liquid by heating or light irradiation. For ease of explanation, the base anode line 951 is described as a light shielding film (reflection film).

  As shown in FIG. 102, the base anode line 951 is not limited to the surface of the array substrate 71 (note that the base anode line 951 is not limited to the surface. Accordingly, it is needless to say that the base anode line 951 or the like may be formed on the inner surface or the inner layer of the substrate 71. Further, the base anode line 951 (reflecting film, light) may be formed on the back surface of the substrate 71. The back surface of the array substrate 71 may be used as long as it is possible to prevent or suppress light from entering the IC 14 by forming a structure or structure that functions as an absorption film.

  In FIG. 102 and the like, the light shielding film and the like are formed on the array substrate 71. However, the present invention is not limited to this, and the light shielding film and the like may be formed directly on the back surface of the IC chip 14. In this case, an insulating film 102 (not shown) is formed on the back surface of the IC chip 14, and a light shielding film or a reflective film is formed on the insulating film. Further, in the case of a configuration in which the source driver circuit 14 is formed directly on the array substrate 71 (a driver configuration using a low temperature polysilicon technology, a high temperature polysilicon technology, a solid phase growth technology, an amorphous silicon technology), a light shielding film, a light absorption film, or A reflective film may be formed on the substrate 71, and the driver circuit 14 may be formed (arranged) thereon.

The IC chip 14 is formed with a large number of transistor elements, such as a current source 634, through which a very small current flows (circuit formation portion 1021 in FIG. 102). When light is incident on a transistor element through which a minute current flows, a photoconductor phenomenon occurs, and the output current (program current Iw), the parent current amount, the child current amount, and the like become abnormal values (such as variations). In particular, in a self-luminous element such as an organic EL, light generated from the EL element 15 in the substrate 71 is irregularly reflected, and therefore, strong light is emitted from locations other than the display region 50. The emitted light is converted into the circuit forming portion 1 of the IC chip 14.
When incident on 021, a photoconductor phenomenon occurs. Therefore, the countermeasure against the photoconductor phenomenon is a countermeasure specific to the EL display device.

  In order to deal with this problem, in the present invention, the base anode line 951 is formed on the substrate 71 to form a light shielding film. The formation region of the base anode line 951 covers the circuit forming portion 1021 as shown in FIG. As described above, the photoconductor phenomenon can be completely prevented by forming the light shielding film (base anode line 951). In particular, in the EL power source line such as the base anode wiring 951, a current flows and a certain potential changes as the screen is rewritten. However, since the amount of potential change changes little by little at 1H timing, it can be regarded as a ground potential (meaning that the potential does not change). Therefore, the base anode line 951 or the base cathode line exhibits not only a light shielding function but also a shielding effect.

  In a self-luminous element such as an organic EL, light generated from the EL element 15 in the substrate 71 is diffusely reflected, and therefore, strong light is emitted from locations other than the display area 50. In order to prevent or suppress this irregularly reflected light, as shown in FIG. 101, a light absorption film 1011 is formed at a location (ineffective region) where light effective for image display does not pass (in contrast, the effective region is a display region). 50 in the vicinity thereof). The portions where the light absorption film is formed are the outer surface of the sealing lid 85 (light absorption film 1011a), the inner surface of the sealing lid 85 (light absorption film 1011c), the side surface of the substrate 70 (light absorption film 1011d), and the image display of the substrate. Other than the region (light absorption film 1011b) or the like. In addition, it is not limited to a light absorption film | membrane, A light absorption sheet may be attached and a light absorption wall may be sufficient. In addition, the concept of light absorption includes a system or structure that diverges light by scattering light, and a system or structure that confines light by reflection in a broad sense.

Substances that make up the light absorption film include organic materials such as acrylic resins containing carbon, black pigments or pigments dispersed in organic resins, and gelatin or casein as a color filter. What was dye | stained with the acid dye is illustrated. In addition, a single black fluoran dye may be used, and a color scheme black obtained by mixing a green dye and a red dye may also be used. Examples thereof include a PrMnO ₃ film formed by sputtering and a phthalocyanine film formed by plasma polymerization.

  The above materials are all black materials, but as the light absorption film, a material having a complementary color with respect to the light color generated by the display element may be used. For example, a light-absorbing material for a color filter may be used so as to obtain desired light absorption characteristics. Basically, a material obtained by dyeing a natural resin with a pigment may be used in the same manner as the black absorbing material described above. Further, a material in which a pigment is dispersed in a synthetic resin can be used. The selection range of the pigment is wider than the black pigment, and may be one suitable from azo dye, anthraquinone dye, phthalocyanine dye, triphenylmethane dye, or a combination of two or more of them.

  Further, a metal material may be used as the light absorption film. For example, hexavalent chromium is exemplified. Hexavalent chromium is black and functions as a light absorbing film. In addition, light scattering materials such as opal glass and titanium oxide may be used. This is because scattering the light is equivalent to absorbing the light as a result.

  Note that the sealing lid 85 adheres the substrate 71 and the sealing lid 85 using a sealing resin 1031 containing resin beads 1012 having a size of 4 μm or more and 15 μm or less. The lid 85 is arranged and fixed without applying pressure.

In the embodiment of FIG. 99, the common anode line 962 is shown to be formed (arranged) in the vicinity of the IC chip 14, but the present invention is not limited to this. For example, it may be formed in the vicinity of the display area 50 as shown in FIG. Moreover, it is preferable to form. because,
This is because the portion where the source signal line 18 and the anode wiring 952 are arranged (formed) in a short distance and in parallel is reduced. This is because parasitic capacitance is generated between the source signal line 18 and the anode wiring 952 when the source signal line 18 and the anode wiring 952 are arranged in a short distance and in parallel. If the common anode line 962 is arranged in the vicinity of the display area 50 as shown in FIG. The distance K (see FIG. 103) from the screen display region 50 to the common anode line 962 is preferably 1 mm or less.

    The common anode line 962 is preferably formed of a metal material for forming the source signal line 18 in order to reduce the resistance as much as possible. In the present invention, a Cu thin film, an Al thin film, a laminated structure of Ti / Al / Ti, or a metal material (SD metal) made of an alloy or amalgam is used. Therefore, a portion where the source signal line 18 and the common anode line 962 intersect is replaced with a metal material (GE metal) constituting the gate signal line 17 in order to prevent a short circuit. The gate signal line is formed of a metal material having a Mo / W laminated structure.

  In general, the sheet resistance of the gate signal line 17 is higher than the sheet resistance of the source signal line 18. This is common in liquid crystal display devices. However, in the organic EL display panel and the current driving method, the current flowing through the source signal line 18 is as small as 1 to 5 μA. Therefore, even if the wiring resistance of the source signal line 18 is high, a voltage drop hardly occurs and a good image display can be realized. In the liquid crystal display device, image data is written to the source signal line 18 with a voltage. Therefore, if the resistance value of the source signal line 18 is high, an image cannot be written in one horizontal scanning period.

  However, in the current driving method of the present invention, even if the resistance value of the source signal line 18 is high (that is, the sheet resistance value is high), there is no problem. Therefore, the sheet resistance of the source signal line 18 may be higher than the sheet resistance of the gate signal line 17. Therefore, in the EL display panel of the present invention (conceptually in a current-driven display panel or display device), as shown in FIG. 104, the source signal line 18 is formed (formed) with GE metal, and the gate The signal line 17 may be made (formed) with SD metal (opposite to the liquid crystal display panel).

  FIG. 107 shows a configuration in which a power supply wiring 1051 for driving the gate driver circuit 12 is arranged in addition to the configurations of FIGS. 99 and 103. The power supply wiring 1051 is routed from the right end of the display area 50 of the panel → the lower side → the left end of the display area 50. That is, the power sources of the gate drivers 12a and 12b are the same.

  However, the gate driver circuit 12a for selecting the gate signal line 17a (the gate signal line 17a controls the TFT 11b and the TFT 11c) and the gate driver circuit 12b for selecting the gate signal line 17b (the gate signal line 17b controls the TFT 11d) The control of the current flowing through the EL element 15 is preferably different from the power supply voltage. In particular, the amplitude (on voltage-off voltage) of the gate signal line 17a is preferably small. This is because the penetration voltage to the capacitor 19 of the pixel 16 decreases as the amplitude of the gate signal line 17a decreases (see FIG. 1 and the like). On the other hand, since the gate signal line 17b needs to control the EL element 15, the amplitude cannot be reduced.

  Therefore, as shown in FIG. 108, the applied voltage of the gate driver 12a is Vha (the off voltage of the gate signal line 17a) and Vla (the on voltage of the gate signal line 17a), and the applied voltage of the gate driver 12a is Vhb ( The off voltage of the gate signal line 17b) and Vla (the on voltage of the gate signal line 17b). It is assumed that Vla <Vlb. Note that Vha and Vhb may be substantially matched.

The gate driver circuit 12 is normally composed of an N channel transistor and a P channel transistor, but is preferably formed of only a P channel transistor. This is because the number of masks required for manufacturing the array is reduced, and the manufacturing yield and throughput can be improved. Therefore, as illustrated in FIGS. 1 and 2 and the like, the TFT constituting the pixel 16 is a P-channel transistor, and the gate driver circuit 12 is also formed or constituted by a P-channel transistor. If the gate driver circuit is composed of an N-channel transistor and a P-channel transistor, the required number of masks is 10. However, if only a P-channel transistor is formed, the required number of masks is 5.

  However, if the gate driver circuit 12 or the like is composed of only P-channel transistors, a level shifter circuit cannot be formed on the array substrate 71. This is because the level shifter circuit is composed of an N channel transistor and a P channel transistor.

  In response to this problem, the present invention incorporates a level shifter circuit function in the power supply IC 1091. FIG. 109 shows an example. The power supply IC 1091 generates a drive voltage for the gate driver circuit 12, an anode / cathode voltage for the EL element 15, and a drive voltage for the source driver circuit 14.

  Since the power supply IC 1091 generates the anode and cathode voltages of the EL elements 15 of the gate driver circuit 12, it is necessary to use a semiconductor process with a high breakdown voltage. With this withstand voltage, the level can be shifted to the signal voltage driven by the gate driver circuit 12.

  Therefore, the level shift and the drive of the gate driver circuit 12 are performed with the configuration of FIG. Input data (image data, command, control data) 992 is input to the source driver IC 14. The input data includes control data for the gate driver circuit 12. The source driver IC 14 has a withstand voltage (operating voltage) of 5 (V). On the other hand, the gate driver circuit 12 has an operating voltage of 15 (V). The signal output from the source driver circuit 14 to the gate driver circuit 12 needs to be level-shifted from 5 (V) to 15 (V). This level shift is performed by a power supply circuit (IC) 1091. In FIG. 109, the data signal for controlling the gate driver circuit 12 is also a power supply IC control signal 1092.

  The power supply circuit 1091 shifts the level of a data signal 1092 for controlling the input gate driver circuit 12 by a built-in level shifter circuit and outputs it as a gate driver circuit control signal 1093 to control the gate driver circuit 12.

  Hereinafter, the gate driver 12 of the present invention in which the gate driver circuit 12 built in the substrate 71 is composed of only P-channel transistors will be described. As described above, the pixel 16 and the gate driver circuit 12 are formed by only P-channel transistors (that is, all transistors formed on the substrate 71 are P-channel transistors. Conversely, N-channel transistors are formed. This is because the number of masks required for manufacturing the array is reduced, and the manufacturing yield and throughput are expected to be improved. Moreover, since it is possible to work on improving only the performance of the P-channel transistor, it is easy to improve characteristics as a result. For example, the Vt voltage can be reduced (for example, closer to 0 (V)) and the Vt variation can be reduced more easily than the CMOS structure (configuration using P-channel and N-channel transistors).

As an example, as shown in FIG. 106, in the present invention, the gate driver circuit 12 is arranged, formed, or configured on the left and right sides of the display area 50, one phase (shift register). The gate driver circuit 12 and the like (including the transistor of the pixel 16) are described as being formed or configured by a low-temperature polysilicon technology having a process temperature of 450 degrees (Celsius) or lower, but are not limited thereto. A high-temperature polysilicon technique having a process temperature of 450 degrees Celsius or higher may be used, or a TFT formed with a semiconductor film grown by solid phase (CGS) may be used. In addition, you may form with organic TFT. Further, it may be a TFT formed or constituted by amorphous silicon technology.

  One is a gate driver circuit 12a on the selection side. An on / off voltage is applied to the gate signal line 17 a to control the pixel TFT 11. The other gate driver circuit 12b controls (turns on and off) the current flowing through the EL element 15. In the embodiment of the present invention, the pixel configuration of FIG. 1 will be mainly described as an example, but the present invention is not limited to this. Needless to say, the present invention can also be applied to other pixel configurations such as FIG. 50, FIG. 51, and FIG. Further, the configuration of the gate driver circuit 12 of the present invention or the driving method thereof exhibits a more characteristic effect in combination with the display panel, display device or information display device of the present invention. However, it goes without saying that a characteristic effect can be exhibited in other configurations.

  Note that the configuration or arrangement of the gate driver 12 described below is not limited to a self-luminous device such as an organic EL display panel. The present invention can also be used for a liquid crystal display panel or an electromagnetic floating display panel. For example, in the liquid crystal display panel, the configuration or system of the gate driver circuit 12 of the present invention may be adopted as control of the pixel selection switching element. Further, when the gate driver circuit 12 is used in two phases, one phase may be used for selecting a switching element of the pixel, and the other may be connected to one terminal of the storage capacitor in the pixel. This method is called independent CC drive. Needless to say, the configuration described in FIGS. 111 and 113 can be applied not only to the gate driver circuit 12 but also to the shift register circuit of the source driver circuit 14.

  The gate driver circuit 12 of the present invention has the above-described FIGS. 6, 13, 16, 20, 20, 22, 24, 26, 27, 28, 29, 34, 37, and 37. Implemented or adopted as the gate driver circuit 12 such as 40, 41, 48, 82, 91, 92, 93, 103, 104, 105, 106, 107, 108, 109 It is preferable to do.

  FIG. 111 is a block diagram of the gate driver circuit 12 of the present invention. For ease of explanation, only four stages are shown, but basically, unit gate output circuits 1111 corresponding to the number of gate signal lines 17 are formed or arranged.

  As shown in FIG. 111, in the gate driver circuit 12 (12a, 12b) of the present invention, four clock terminals (SCK0, SCK1, SCK2, SCK3), one start terminal (data signal (SSTA)), shift It is composed of signal terminals of two inverting terminals (DIRA and DIRB, which apply signals of opposite phases) that control the direction upside down. In addition, the power supply terminal includes an L power supply terminal (VBB) and an H power supply terminal (Vd).

Since the gate driver circuit 12 of the present invention is composed of P-channel TFTs (transistors), a level shifter circuit (a circuit that converts a low-voltage logic signal into a high-voltage logic signal) is used as the gate driver circuit. Cannot be built in. Therefore, a level shifter circuit is arranged or formed in the power supply circuit (IC) 1091 shown in FIG. The power supply circuit (IC) 1091 generates a voltage having a potential necessary for an on voltage (selection voltage of the pixel 16 TFT) and an off voltage (non-selection voltage of the pixel 16 TFT) output from the gate driver circuit 12 to the gate signal line 17. Therefore, the semiconductor withstand voltage process used by the power supply IC (circuit) 1091 has a sufficient withstand voltage. Therefore, it is convenient to level shift (LS) the logic signal with the power supply IC 1091. Therefore, the control signal of the gate driver circuit 12 output from the controller (not shown) is input to the power supply IC 1091 and level-shifted, and then input to the gate driver circuit 12 of the present invention. A control signal of the source driver circuit 14 output from a controller (not shown) is directly input to the source driver circuit 14 of the present invention (no need for level shift).

  However, the present invention is not limited to forming all the transistors formed on the array substrate 71 with P-channel. By forming the gate driver circuit 12 with a P channel as shown in FIGS. 111 and 113 described later, the frame can be narrowed. In the case of a 2.2 inch QCIF panel, the width of the gate driver circuit 12 can be set to 600 μm when the 6 μm rule is adopted. Even if the power supply wiring of the gate driver circuit 12 to be supplied is included, it can be configured to 700 μm. If a similar circuit configuration is constituted by CMOS (N-channel and P-channel transistors), it becomes 1.2 mm. Therefore, by forming the gate driver circuit 12 with the P channel, a characteristic effect of narrowing the frame can be exhibited.

  Further, by configuring the pixel 16 with a P-channel transistor, matching with the gate driver circuit 12 formed with the P-channel transistor is improved. P-channel transistors (TFTs 11b, 11c, and TFT 11d in the pixel configuration of FIG. 1) are turned on with an L voltage. On the other hand, the L voltage is also the selection voltage in the gate driver circuit 12. The P-channel gate driver can be seen from the configuration of FIG. 113, but matching is good when the L level is the selection level. This is because the L level cannot be maintained for a long time. On the other hand, the H voltage can be held for a long time.

  Further, the driving TFT for supplying current to the EL element 15 (TFT 11a in FIG. 1) is also formed of a P channel, so that the cathode of the EL element 15 can be formed as a solid electrode of a metal thin film. In addition, a current can flow through the EL element 15 in the forward direction from the anode potential Vdd. From the above, it is preferable that the transistor of the pixel 16 be a P channel and the transistor of the gate driver 12 be a P channel. From the above, the matter that the transistor (driving TFT, switching TFT) constituting the pixel 16 of the present invention is formed by the P channel and the transistor of the gate driver circuit 12 is constituted by the P channel is not merely a design matter. .

  In this sense, a level shifter (LS) circuit may be formed directly on the substrate 71. That is, a level shifter (LS) circuit is formed by N-channel and P-channel transistors. A logic signal from a controller (not shown) is boosted by a level shifter circuit formed directly on the substrate 71 so as to conform to the logic level of the gate driver circuit 12 formed of a P-channel transistor. The boosted logic voltage is applied to the gate driver circuit 12.

  Note that the level shifter circuit may be formed of a semiconductor chip and mounted on the substrate 71 by COG. The source driver circuit 14 is basically formed of a semiconductor chip and is COG mounted on the substrate 71 as shown in FIG. However, the source driver circuit 14 is not limited to being formed of a semiconductor chip, and may be formed directly on the substrate 71 using polysilicon technology. When the transistor 11 constituting the pixel 16 is configured by a P channel, the program current flows in the direction from the pixel 16 to the source signal line 18. Therefore, the unit current circuit 634 of the source driver circuit (see FIG. 73, FIG. 74, etc.) needs to be composed of N-channel transistors. In other words, the source driver circuit 14 needs to be configured to draw the program current Iw.

Therefore, when the driving TFT 11a of the pixel 16 (in the case of FIG. 1) is a P-channel transistor, the unit current source 634 is configured by an N-channel transistor so that the source driver circuit 14 always draws the program current Iw. In order to form the source driver circuit 14 on the array substrate 71, it is necessary to use both an N channel mask (process) and a P channel mask (process). Describing conceptually, the display panel (display device) of the present invention comprises the pixel 16 and the gate driver 12 as P-channel transistors, and the source driver's pull-in current source transistor as an N-channel.

  For ease of explanation, in the embodiment of the present invention, the pixel configuration of FIG. However, the technical idea of the present invention such that the selection transistor (TFT 11c in FIG. 1) of the pixel 16 is configured by a P channel and the gate driver circuit 12 is configured by a P channel transistor is limited to the pixel configuration of FIG. It is not something. For example, the current-driven pixel configuration can be applied to the current mirror pixel configuration shown in FIG. In addition, the voltage-driven pixel configuration can be applied to two TFTs as illustrated in FIG. 143 (a) (the selection transistor is TFT 11b and the drive transistor is TFT 11a). Needless to say, the present invention can also be applied to a pixel configuration using four TFTs (selection transistor TFT 11c and drive transistor TFT 11a) as shown in FIG. Of course, the configuration of the gate driver circuit 12 of FIGS. 111 and 113 can also be applied, and a device or the like can be configured in combination. Therefore, the items described above and the items described below are not limited to the pixel configuration.

  Further, the configuration in which the selection transistor of the pixel 16 is configured by a P channel and the gate driver circuit is configured by a P channel transistor is not limited to a self-luminous device (display panel or display device) such as an organic EL. For example, it can be applied to a liquid crystal display device.

  A common signal is applied to the inverting terminals (DIRA and DIRB) to each unit gate output circuit 1111. As can be understood from the equivalent circuit diagram of FIG. 113, the inverting terminals (DIRA and DIRB) input voltage values having opposite polarities. When the scanning direction of the shift register is reversed, the polarity of the voltage applied to the inverting terminals (DIRA, DIRB) is reversed.

  In the circuit configuration of FIG. 111, the number of clock signal lines is four. Four is the optimum number in the present invention, but the present invention is not limited to this. Four or less may be sufficient.

  Inputs of clock signals (SCK0, SCK1, SCK2, and SCK3) are made different between adjacent unit gate output circuits 1111. For example, in the unit gate output circuit 1111a, the clock terminal SCK0 is input to OC and SCK2 is input to RST. This state is the same for the unit gate output circuit 1111c. In the unit gate output circuit 1111b (next unit gate output circuit) adjacent to the unit gate output circuit 1111a, the clock terminal SCK1 is input to OC and SCK3 is input to RST. Therefore, as for the clock terminal input to the unit gate output circuit 1111, SCK0 is input to OC, SCK2 is input to RST, and in the next stage, SCK1 of the clock terminal is input to OC, SCK3 is input to RST, and further to the next stage. The clock terminals input to the unit gate output circuit 1111 are alternately changed such that SCK0 is input to OC and SCK2 is input to RST.

FIG. 113 shows a circuit configuration of the unit gate output circuit 1111. The transistors to be configured are composed of only the P channel. FIG. 114 is a timing chart for explaining the circuit configuration of FIG. FIG. 112 illustrates a timing chart for a plurality of stages in FIG. Therefore, the overall operation can be understood by understanding FIG. 113. The understanding of the operation is achieved by understanding the timing chart of FIG. 114 with reference to the equivalent circuit diagram of FIG. 113 rather than the description of the text. Therefore, detailed description of the operation of each transistor is omitted.

  If a driver circuit configuration is created using only the P channel, it is basically possible to maintain the gate signal line 17 at the H level (Vd voltage in FIG. 113). However, it is difficult to maintain the L level (VBB voltage in FIG. 113) for a long time. However, it can be sufficiently maintained for a short period, such as when a pixel row is selected. N1 changes depending on the signal input to the IN terminal and the SCK clock input to the RST terminal, and n2 becomes an inverted signal state of n1. Although the potential of n2 and the potential of n4 have the same polarity, the potential level of n4 is further lowered by the SCK clock input to the OC terminal. Corresponding to this lowering level, the Q terminal is maintained at the L level during that period (ON voltage is output from the gate signal line 17). The signal output to the SQ or Q terminal is transferred to the unit gate output circuit 1111 in the next stage.

  In the circuit configurations of FIGS. 111 and 113, one gate signal line 17 is selected as shown in FIG. 115A by controlling the timing of the applied signals at the IN (INA, INb) terminals and clock terminals. The state and the state of selecting the two-gate signal line 17 as shown in FIG. 115B can be realized by using the same circuit configuration. In the gate driver circuit 12a on the selection side, the state shown in FIG. 115A is a driving method in which one pixel row (51a) is simultaneously selected (normal driving). Further, the selected pixel row is shifted by one row. FIG. 115B shows a configuration in which two pixel rows are selected. This driving method is the simultaneous selection driving (a method of forming a dummy pixel row) of a plurality of pixel rows (51a, 51b) described with reference to FIGS. The selected pixel row is shifted by one pixel row, and two adjacent pixel rows are selected simultaneously. In particular, in the driving method of FIG. 115B, the pixel row 51b is precharged with respect to the pixel row (51a) holding the final video. Therefore, the pixel 16 can be easily written. In other words, the present invention can be realized by switching between the two driving methods by a signal applied to the terminal.

  FIG. 115 (b) shows a method of selecting 16 adjacent pixel rows. However, as shown in FIG. 116, 16 pixel rows other than adjacent pixels may be selected (FIG. 116 shows three pixel rows). This is an embodiment in which pixel rows at distant positions are selected). In the configuration of FIG. 113, control is performed with a set of four pixel rows. Of the four pixel rows, it is possible to control whether one pixel row is selected or two consecutive pixel rows are selected. This is a restriction that four clocks (SCK) are used. If eight clocks (SCK) are used, control can be performed with a set of eight pixel rows. Therefore, as apparent from the configuration of FIG. 113, a pixel row can be selected as shown in FIG.

  In FIG. 29, the driving method in which dummy pixel rows are formed and two or more pixel rows are simultaneously selected has been described. The drive method of FIG. 29 can also be implemented in FIG. FIG. 155 (a2) illustrates a driving method for simultaneously selecting two pixel rows. By scanning (manipulating) the gate driver 12a, an ON voltage is applied to the adjacent two gate signal lines 17a (write pixel rows 51a and 51b). The dummy pixel rows are formed or arranged on the upper side (281a) and the lower side (281b) of the screen 50. By providing the dummy pixel row 281 in this way, the driving method of FIG. 29 can be realized. In addition, by realizing the configurations of FIGS. 111 and 113, switching to normal driving (driving method of sequentially selecting one gate signal line 17a (write pixel row 51)) in FIG. 155 (a1) can be realized. it can. As described above, the present invention can be implemented by combining the methods, apparatuses, configurations, and the like described in this specification in a timely manner.

In FIG. 118 (a), one pixel row can be selected as a set of four pixel rows (one pixel row is selected in the set of four pixel rows, but whether or not it is selected at all is input of IN data) State and shift state). In FIG. 118 (b), it is possible to select two pixel rows that are consecutive in a group of four pixel rows (two pixel rows are selected in a set of four pixel rows, but whether or not they are selected at all is IN data. Input state and shift state). In the present invention, a pixel row equal to the number of clocks is taken as a set, and in this set of pixel rows, one pixel row or a number less than half of the set of pixel rows (for example, a set of 4 pixel rows) 4/2 = 2 pixel rows). Therefore, a non-selected pixel row is always generated in the pixel row group. Note that FIG. 118 is realized by operating the TFT 11d on the EL side (in the case of FIG. 1). The operation of the TFT 11d can be easily realized by controlling the gate driver 12b.

  In FIG. 115A in which one pixel row is selected, the program current Iw flows to one pixel 16 as illustrated in FIG. 117A. The driving method for simultaneously selecting two pixel rows as shown in FIGS. 115B and 116 is the same as the driving method described in FIGS. The program current Iw is divided into two pixel rows and written to the pixels 16 as shown in FIG. However, it is not limited to this. For example, as shown in FIG. 117 (b), a program current Iw × 2 may be applied, and the same current may be supplied to two selected pixels (16a, 16b).

  The operation of the gate driver 12a on the selection side is the operation of FIG. As shown in FIG. 115A, one pixel row is selected, and the selected position is shifted by one pixel row in synchronization with one horizontal synchronizing signal. In addition, as shown in FIG. 115B, two pixel rows are selected, and the selected position is shifted by one pixel row in synchronization with one horizontal synchronization signal.

  FIG. 118 is an explanatory diagram for explaining the operation of the gate driver 12b for controlling the gate signal line 17b for turning on / off the EL element 15. FIG. FIG. 118A shows a state in which an on-voltage is applied to the gate signal line 17b of one pixel row in a set of four pixel rows (hereinafter, such a set of pixel rows is referred to as a pixel row set). The position of the display pixel row 53 is shifted by one pixel row in synchronization with the horizontal synchronization signal (HD). Of course, an on-voltage is applied to the gate signal line 17b corresponding to one pixel row in the four-pixel row set (an off-voltage is applied to the gate signal line 17b corresponding to the other three pixel rows) or four pixels. Whether the off voltage is applied to all of the row sets (the off voltage is applied to the gate signal lines 17b corresponding to the four pixel rows) can be arbitrarily selected. Since the shift register is configured, the set selection state is shifted in synchronization with the horizontal synchronization signal.

  FIG. 118B shows a state in which an ON voltage is applied to the gate signal line 17b in the two pixel rows of the four pixel row group. The position of the display pixel row 53 is shifted by one pixel row in synchronization with the horizontal synchronization signal (HD). Of course, an on voltage is applied to the gate signal line 17b corresponding to the two pixel rows in the four pixel row group (an off voltage is applied to the gate signal line 17b corresponding to the other two pixel rows), or four pixels. Whether the off voltage is applied to all of the row sets (the off voltage is applied to the gate signal lines 17b corresponding to the four pixel rows) can be arbitrarily selected. Since the shift register is configured, the set selection state is shifted in synchronization with the horizontal synchronization signal.

  FIG. 118A shows a state in which an on-voltage is applied to the gate signal line 17b of one pixel row in a group of four pixel rows. FIG. 118B shows a state in which an ON voltage is applied to the gate signal line 17b in the two pixel rows of the four pixel row group. However, the present invention is not limited to this configuration (system). For example, as shown in FIG. 141 (a), the ON voltage is applied to the gate signal line 17b of one pixel row in a group of six pixel rows. FIG. 141 (b) shows a state in which an on-voltage is applied to the gate signal line 17b in the two pixel rows of the eight pixel row group. That is, it is not limited to FIG. Further, the on / off state may be changed in RGB. For example, R is in the display state of FIG. 141 (a), G and B are in the display state of FIG. 118 (a), and so on.

Further, as shown in FIG. 155 (b), one pixel row may be selected for two pixel rows (maximum ½ lighting). The brightness adjustment is controlled by whether or not one pixel row of the two-pixel row set is lit. Further, by increasing the black insertion portion (the continuous area continues for 4 msec or more), it is possible to improve the motion blur as described with reference to FIG. In FIG. 155 (b), the adjacent pixel rows are always in the lighting state (selected state) or in the non-lighting state (non-selected state). That is, the upper and lower sides of the selected pixel row are always non-selected pixel rows. By performing such an operation, power consumption can be reduced. When two adjacent pixel rows are simultaneously selected as shown in FIG. 118 (b) (referred to as 2/4 lighting control), the gate driver for selecting adjacent pixel rows can be easily understood from the circuit configurations of FIGS. 111 and 113. A through current flows in the circuit 12b. This through current increases power consumption. However, if driving is performed as shown in FIG. 115B (referred to as 1/2 lighting control), no through current is generated in the gate driver circuit 12b that selects adjacent pixel rows, and the power consumption is approximately Only power necessary for charging and discharging the gate signal line 12b is obtained. Therefore, the driving method for controlling the lighting of the EL element 15 may employ a driving method in which adjacent pixel rows are not selected at the same time, such as ½ lighting in FIG. 155 (b) and ¼ lighting in FIG. 118 (a). preferable.

  FIG. 119 shows the state of the voltage output to the gate signal line 17b in the driving state of FIG. 118 (a). As described above, the subscript indicated by () of the signal line 17b indicates a pixel row. For ease of explanation, the pixel rows are from (1). The numbers in the upper part of the table indicate the numbers of the horizontal scanning period.

  As shown in FIG. 119, the gate signal lines 17b (1) to 17b (4) and the gate signal lines 17b (5) to 17b (8) have the same waveform. That is, the same operation is performed in the 4-pixel row group.

  FIG. 120 shows the state of the voltage output to the gate signal line 17b in the driving state of FIG. 118 (b). As shown in FIG. 120, the gate signal lines 17b (1) to 17b (4) and the gate signal lines 17b (5) to 17b (8) have the same waveform. That is, the same operation is performed in the 4-pixel row group.

  In the example of FIG. 118, the brightness of the display screen 50 can be adjusted by increasing or decreasing the number of pixels in the display state at an arbitrary time. In the case of the QCIF panel, the number of vertical pixels is 220 dots. Therefore, in FIG. 118A, 220/4 = 55 pixel rows can be displayed. That is, in white raster display, the maximum brightness is obtained when 55 pixel rows are displayed. The brightness of the screen is the number of display pixel lines 55 → 54 → 53 → 52 → 51 → ... 5 → 4 → 3 → 2 → 1 → 0 → By changing the above, the display screen can be darkened. Conversely, 0 → 1 → 2 → 3 → 4 → 5 → → 50 → 51 → 52 → 53 → 54 → 55 , Can brighten the screen. Therefore, multi-level brightness adjustment can be realized.

  In this brightness adjustment, the screen brightness is proportional to the number of display pixels, and the change is linear. In addition, there is no change in the gamma characteristic corresponding to the brightness (the number of gradations is maintained regardless of whether the screen is bright or dark).

  In the above embodiment, the change in the number of display pixel rows for adjusting the brightness of the display screen 50 is set to be one by one. However, the present invention is not limited to this. 54-> 52-> 50-> 48-> 46-> ... 6-> 4-> 2-> 2-> 0. Further, 55, 50, 45, 40, 35,..., 15, 10, 10, 5, and 0 may be changed.

Similarly, in FIG. 118B, 220/2 = 110 pixel rows can be displayed on the QCIF panel. That is, in white raster display, the maximum brightness is when 110 pixel rows are displayed. The brightness of the screen is 110 → 108 → 106 → 104 → 102 → 10 → 8 → 6 → 4 → 2 → → 0 By changing the above, the display screen can be darkened. Conversely, 0 → 2 → 4 → 6 → 8 → 10 → → 100 → 102 → 104 → 106 → 108 → 110 , Can brighten the screen. Therefore, multi-level brightness adjustment can be realized. Although the change in the number of display pixel rows for adjusting the brightness of the display screen 50 is made every two, it is not limited to this. It may be every four or four or more. In order to adjust the brightness, the display pixel rows are thinned out so as to be dispersed as much as possible, rather than being concentrated at one place. This is to suppress the occurrence of flicker.

  The brightness adjustment is not a unit of the number of pixel rows (a drive in which the pixel rows are turned on or off for substantially the entire period of one horizontal scanning period), and the lighting time per horizontal scanning period is also adjusted. Can do. That is, the brightness of the display screen is adjusted by turning on a part of one horizontal scanning period (for example, 1/8 period of 1H, 15/16 period of 1H).

  This adjustment (control) is performed using the main clock (MCLK) of the display panel. In the QCIF panel, MCLK is about 2.5 MHz. That is, 176 clocks can be counted in one horizontal scanning period (1H). Therefore, by counting MCLK and controlling the period during which the ON voltage (Vgl) is applied to the gate signal line 17b based on this count value, the EL elements 15 in each pixel row can be turned on / off.

  Specifically, in the timing charts shown in FIGS. 112 and 114, this can be realized by controlling the position of the clock (SCK) at the L level and the period of the L level. The shorter the period during which SCK is at the L level, the shorter the period during which the output Q terminal is at the L level (Vgl).

  In the drive method of FIG. 118 (a), as shown in FIG. 121, the period during which Vgl (ON voltage) is symmetrically reduced in the 1H period is shortened. In FIG. 121, (a) is a period in which all of the 1H period outputs Vgl (ON voltage) (however, in the configuration of the P-channel gate driver circuit 12 in FIG. 113, an L level output is output in all of the 1H period. There is a period of Vgh voltage (off voltage) between 1H and the next 1H.For ease of explanation, FIG. Yes.

  Similarly, FIG. 121 (b) illustrates that the period during which Vgl is output to the gate signal line 17b is shortened by two clocks (compared to (a)). Further, FIG. 121 (c) illustrates that the period during which Vgl is output to the gate signal line 17b is shortened by two clocks (compared to (b)). Hereinafter, since it is the same, description is abbreviate | omitted.

  In the driving method of FIG. 118 (b), as shown in FIG. 122, the period during which Vgl (ON voltage) is symmetrically shortened in the 2H period is shortened. In FIG. 122, (a) is a period in which all of the 1H period outputs Vgl (ON voltage) (however, in the P channel gate driver circuit 12 configuration of FIG. 113, L level output is output in all of the 2H period. A period of Vgh voltage (off voltage) is generated between 2H and the next 2H, which is the same as in FIG.

Similarly, FIG. 122B illustrates that the period during which Vgl is output to the gate signal line 17b is 2H, and MCLK is shortened by two clocks (compared to (a)). ing. Further, FIG. 122 (c) shows that the period during which Vgl is output to the gate signal line 17b is shortened by two clocks (compared to (b)).
Hereinafter, since it is the same, description is abbreviate | omitted.

  If the configuration of the gate driver circuit 12 is slightly changed and the clock is adjusted, as shown in FIG. 123, the application period of the gate signal line 17b in FIG. 121 can be continuously performed for 2H periods.

  In FIG. 13, FIG. 14, etc., the driving method for solving the moving image blur has been described. This is a method in which an image is intermittently displayed, so that the outline blur of the image is eliminated and a good display state can be realized. That is, a display state close to that of a CRT is realized, and an excellent moving image display is realized.

  Even with the driving method shown in FIG. 118, good moving image display can be realized. However, in FIG. 13, the display area 53 is continuous and the non-display area 52 is continuous, whereas in FIG. 118, the display area 53 is not continuous. Display state of whether ON voltage is applied to one pixel row in a 4-pixel row set (FIG. 118 (a)) or ON voltage is applied to two consecutive pixel rows in a 4-pixel row set (FIG. 118 (b)) Because it becomes. Of course, by changing or improving the circuit configuration illustrated in FIGS. 113 and 111, the display pixel row with respect to the clock (SCK) can be changed or changed. For example, it can be displayed by skipping one pixel line. It is also possible to light up by skipping 6 pixel rows. However, in a driver circuit (shift register) configured or formed with P-channel transistors, at least display pixel rows 52 that are not lit are arranged (inserted) between the display pixel rows 53.

  FIG. 124 shows a driving method for displaying moving images when the gate driver circuit 12 is formed of P-channels as shown in FIG. As previously described, in order to prevent image display deterioration due to moving image blur, it is necessary to perform intermittent display. That is, it is necessary to insert black (display a black or low-brightness display screen). Drive (display) like a CRT display. That is, when an image is displayed in an arbitrary pixel row, black (low luminance) display is performed after display for a predetermined period. This pixel row blinks (image display and non-display (black display or low luminance display) are repeated alternately). The black display period needs to be 4 msec or more. Alternatively, black display (low luminance display) is performed for a period of 1/4 or more of one frame (one field). Preferably, black display (low luminance display) is performed for a period of ½ or more of one frame (one field). This condition depends on the afterimage characteristics of the human eye. That is, an image that blinks faster than a predetermined period appears to be continuously lit due to the afterimage characteristics of human eyes. This leads to motion blur. However, although the image blinking later than the predetermined period seems to be continuous visually, the non-lighting (black display) state inserted between them can be recognized, and the display image is displayed. It will be in a state of flying (but it doesn't feel strange visually). For this reason, images are skipped in moving image display, and image blurring does not occur. That is, there is no moving image blur.

  In FIG. 124A, the area A is in a state where one pixel row is displayed (lighted state) in four pixel rows. Therefore, it is turned on once in 4 horizontal scanning periods (4H) (lights up for 1H period in 4H period). This period (a period from when the pixel row is lit, when it is not lit, and when it is next lit) is 4 msec or less. Therefore, it seems to the human eye that the image is displayed completely continuously (arbitrary pixel rows do not persist and are not much different from being lit). In the area B of FIG. 124A, black is inserted (low luminance display) so that the pixel row is displayed for 4 msec or more, preferably 8 msec or more after it is displayed. Therefore, the image is skipped and a good moving image display can be realized.

In addition, although it demonstrated as the area | region A or the area | region B in the above description, the above matter is for making description easy. In FIG. 124, the area A is sequentially scanned in the direction of the arrow (from the top to the bottom of the screen). It is like scanning an electron beam with a CRT. That is, the image is rewritten sequentially (refer to FIG. 125 for FIG. 124A) and scanned (driven) as shown in FIG. 125A → (b) → (c) → (a). (B) refer to Fig. 126. Scanning (driving is performed as shown in Fig. 126 (a)->(b)->(c)-> (a)).

  As described above, in the driving method of the present invention, an arbitrary pixel row is displayed in 4H for 1H in a period of 4 msec (preferably 8 msec) in one field (one frame) in FIG. 124 (a). In other periods (the remaining period of one field (one frame)), the non-lighting state (black display (black insertion) or low luminance display) is continuously maintained. Therefore, in order to facilitate the explanation, it is expressed as the A region or the B region, but it is more appropriate to express the A period or the B period from the viewpoint of time. That is, area A (period A) is a period in which images are continuously lit, and area B (period B) is a period in which pixel rows (screen 50) are intermittently displayed. The above matters are the same in FIG. 124B or other embodiments of the present invention.

  In FIG. 124 (b), the two pixel rows are continuously lit, and then the two pixel rows are not lit. That is, in the A region (A period), it is repeatedly turned on for a period of 2H and is not lit for a period of 2H. In the B region (B period), the non-lighting state is continuously maintained for a predetermined period. Also in the driving method of FIG. 124 (b), the A area is apparently a continuous display state, and the B area is apparently intermittent display.

  As described above, when the display state is observed by paying attention to an arbitrary pixel row (pixel), the driving method of the present invention has a period of less than 4 msec (or a period of less than ¼ of one frame (one field)). In the first period in which image display and non-display (black display or low luminance display below a predetermined level) are repeated at least once, and the pixel row (pixel) is not displayed (black display or low below a predetermined level) from the display state. (Brightness display) state, and the second display period (or a period of 1/4 or more of one frame (one field)) in which the period of the next display state is 4 msec or more is performed. By performing the above driving, it is possible to realize a good moving image display, and the configuration of the control circuit (gate driver circuit 12 and the like) is easy, so that the cost can be reduced.

  Also in FIG. 124, the brightness of the screen 50 can be adjusted (changed) by changing the number of lighting pixel rows (the display pixel number 53 may be changed or adjusted as in FIG. 118). Further, by changing the ratio of the black insertion area (B area in FIG. 124), the optimum state can be obtained according to the image display state. For example, in a still image, it should be avoided that the B area becomes long. This is because flickering occurs. In the case of a still image, the display pixel rows 53 should be displayed dispersedly (arranged in the screen 50). For example, in the case of a QCIF panel, the number of pixel rows is 220. Among these, if 55 pixel rows are displayed as a still image, 220/44 = 4, and therefore, one pixel row may be displayed every four pixel rows. If 10 pixel rows of 220 pixel rows are displayed, one pixel row may be displayed on 220/10 = 22 pixel rows. In FIG. 124, one B region (B period) is used, but the present invention is not limited to this, and it is needless to say that it may be divided or distributed into two or more (plural).

However, in FIG. 124 (a), it is only possible to display whether or not one pixel row is lit in a 4-pixel row group. Therefore, one pixel row cannot be lit in 22 pixel rows. Therefore, 4 pixel row sets are displayed 5 times = one pixel row is displayed on 20 pixel rows (that is, one pixel row is displayed on 20 pixel rows. In other words, four of the four pixel row sets have no pixel rows at all. One pixel row of one pixel row group is set to a lighting state without being turned on). All of the remaining 20 pixel rows (220−4 × 5 = 200) are turned off. In other words, according to the present invention, the number of pixel row groups to be lit in this block within the combination (block) of the pixel row set, with the pixel row set being restricted (restricted or regulated) as one unit. Control whether or not. The above matters are also applied to FIG. 124 (b), and also to other embodiments of the present invention.

  Conversely, in the case of moving image display, it is necessary to perform black insertion of at least 4 msec or more as described with reference to FIG. Also, the moving image display state can be changed (adjusted to the optimum state) by changing the ratio of black insertion (black display continuous time, black display area with respect to the display screen). For very high-speed moving image display (such as when the movement of the image is intense), the black insertion area should be increased. At this time, a decrease in luminance due to a decrease in the number of pixels displaying an image is dealt with by increasing the emission luminance of one pixel row. Further, it is preferable to lengthen the period during which black display continues. When the ratio of the moving image display area to the entire screen is relatively small, or when the movement of the moving image is relatively slow, the ratio of black insertion may be reduced. In this case, the increase in display luminance due to the increase in the number of lit pixel rows 53 can be easily adjusted by reducing the light emission luminance per pixel row. This is because this adjustment can be changed by the program current Iw or the like. Alternatively, the black insertion period may be distributed over a plurality of times. Flicker is reduced and good image display can be realized.

  Even in moving image display as described above, a more optimal image display can be realized by changing or adjusting the black insertion state. Needless to say, the above matters also apply to the following embodiments.

  Moving image detection (ID detection) of the input video signal is performed, and in the case of a moving image or an image with many moving images, the driving method (intermittent display by black insertion) of FIG. 124 is performed. In the case of a still image, the driving method shown in FIG. 118 (lighted pixel row positions are dispersed as much as possible) is performed. Of course, switching may be performed according to the use of the display panel or display device of the present invention. For example, in the case of a still image such as a computer monitor, the driving method shown in FIG. 118 is adopted. In the case of AV use such as a television, the driving method shown in FIG. 124 is adopted. The switching of the driving method can be easily changed by the SSTA data of the gate driver circuit 12b. This is because only the TFT that turns on and off the current flowing through the EL element 15 shown in FIG. 1 is controlled. Switching between FIG. 124 and FIG. 118 (moving image support or still image support, or more moving image support or still image support) may be performed according to the situation, such as a changeover switch that can be operated by the user, The manufacturer of the display panel of the present invention may implement it. Alternatively, the ambient environment state may be detected using a photo sensor or the like, and the switching may be performed automatically. In addition, a control signal (switching signal) may be put on the video signal received by the present invention in advance, and the display state (driving method) may be switched by detecting this control signal.

  FIG. 127 shows an output waveform of the gate signal line 17b in the case of the driving method of FIG. 124 (a). In the pixel configuration of FIG. 1, the TFT 11d is on / off controlled by an on / off signal (Vgh is an off voltage, Vgl is an on voltage) applied to the gate signal line 17b, and the current flowing through the EL element 15 is turned on / off. In FIG. 1, the upper part shows the horizontal scanning period, and the L symbol shows the number of pixel rows L (L = 220 in the case of the QCIF panel). 118 and 124, the driving method of the present invention is not limited to the pixel configuration of FIG. For example, it goes without saying that the present invention can be applied to other pixel configurations (FIG. 54 and the like).

  As can be seen from FIG. 127, in the A period (A region), the ON voltage (Vhl) is applied to each gate signal line 17b at a rate of 1H period in 4H period. In the B period (B region), the off voltage (Vgh) is continuously applied. Therefore, no current flows through the EL element 15 during this period. Then, the ON voltage position of each gate signal line 17b is scanned for each pixel row.

In the above embodiment, scanning is performed for each pixel row, but the present invention is not limited to this. For example, in interlace scanning, scanning is performed by skipping one pixel line. That is, even pixel rows are scanned in the first frame. In the second frame, odd-numbered pixel rows are scanned. When the first frame is rewritten, the image written in the second frame is held as it is. However, the blinking operation is performed (not necessary). When the second frame is rewritten, the image written in the first frame is held as it is. Of course, the blinking operation may be performed as in the embodiment of FIG.

  Interlaced scanning is normally performed in 2 frames and 1 field in CRT. However, the present invention is not limited to this. For example, 4 frames = 1 field may be sufficient. In this case, in the first frame, an image of (4N + 1) pixel rows (where N is an integer greater than or equal to) is rewritten. In the second frame, the image of (4N + 2) pixel rows is rewritten. In the next third frame, the image of (4N + 3) pixel rows is rewritten. In the last fourth frame, the image of (4N + 4) pixel rows is rewritten. As described above, according to the present invention, writing to a pixel row is not limited to only sequential scanning. The above matters also apply to other embodiments. In the present invention, interlaced scanning means wide and general interlaced scanning, and is not limited to 2 frames = 1 field. That is, multiple frames = 1 field.

  In FIGS. 127 and 128, the current flowing through the EL element 15 is controlled within one horizontal scanning period (1H) or a plurality of horizontal scanning periods as shown in FIGS. It goes without saying that a driving method for adjusting the brightness of the display screen 50 can be used together by controlling the brightness.

  FIG. 128 shows the waveform applied to the gate signal line 17b in FIG. 124 (b), as in FIG. The difference from FIG. 127 is that in the period A (refer to the region A, FIG. 118B), the ON voltage (Vgl) is applied to each gate signal line 17b for two horizontal scanning periods (2H). Thereafter, an off voltage (Vgh) is applied for a period of 2H. The on-voltage and off-voltage are repeated alternately. In the B period (B region), the off voltage is continuously applied. The ON voltage application position of each gate signal line 17b is scanned every 1H.

  FIG. 127 shows an output waveform of the gate signal line 17b in the case of the driving method of FIG. 124 (a). In the pixel configuration of FIG. 1, the TFT 11d is on / off controlled by an on / off signal (Vgh is an off voltage, Vgl is an on voltage) applied to the gate signal line 17b, and the current flowing through the EL element 15 is turned on / off. In FIG. 1, the upper part shows the horizontal scanning period, and the L symbol shows the number of pixel rows L (L = 220 in the case of the QCIF panel). 118 and 124, the driving method of the present invention is not limited to the pixel configuration of FIG. For example, it goes without saying that the present invention can be applied to other pixel configurations (FIG. 54 and the like).

  As can be seen from FIG. 127, in the A period (A region), the ON voltage (Vhl) is applied to each gate signal line 17b at a rate of 1H period in 4H period. In the B period (B region), the off voltage (Vgh) is continuously applied. Therefore, no current flows through the EL element 15 during this period. Then, the ON voltage position of each gate signal line 17b is scanned for each pixel row.

  In the above embodiment, scanning is performed for each pixel row, but the present invention is not limited to this. For example, in interlace scanning, scanning is performed by skipping one pixel line. That is, even pixel rows are scanned in the first frame. In the second frame, odd-numbered pixel rows are scanned. When the first frame is rewritten, the image written in the second frame is held as it is. However, the blinking operation is performed (not necessary). When the second frame is rewritten, the image written in the first frame is held as it is. Of course, the blinking operation may be performed as in the embodiment of FIG.

  Interlaced scanning is normally performed in 2 frames and 1 field in CRT. However, the present invention is not limited to this. For example, 4 frames = 1 field may be sufficient. In this case, in the first frame, an image of (4N + 1) pixel rows (where N is an integer greater than or equal to) is rewritten. In the second frame, the image of (4N + 2) pixel rows is rewritten. In the next third frame, the image of (4N + 3) pixel rows is rewritten. In the last fourth frame, the image of (4N + 4) pixel rows is rewritten. As described above, according to the present invention, writing to a pixel row is not limited to only sequential scanning. The above matters also apply to other embodiments. In the present invention, interlaced scanning means wide and general interlaced scanning, and is not limited to 2 frames = 1 field. That is, multiple frames = 1 field.

  In FIGS. 127 and 128, the current flowing through the EL element 15 is controlled within one horizontal scanning period (1H) or a plurality of horizontal scanning periods as shown in FIGS. It goes without saying that a driving method for adjusting the brightness of the display screen 50 can be used together by controlling the brightness.

  FIG. 128 shows the waveform applied to the gate signal line 17b in FIG. 124 (b), as in FIG. The difference from FIG. 127 is that in the period A (refer to the region A, FIG. 118B), the ON voltage (Vgl) is applied to each gate signal line 17b for two horizontal scanning periods (2H). Thereafter, an off voltage (Vgh) is applied for a period of 2H. The on-voltage and off-voltage are repeated alternately. In the B period (B region), the off voltage is continuously applied. The ON voltage application position of each gate signal line 17b is scanned every 1H. Other items are the same as or similar to those in FIG.

  In the above embodiment, the driving method is such that the A region and the B region are mixed in the display screen 50. That is, in any period of the screen display state, the A area is always the B area (of course, the location of the A area is different). This means that there are an A period and a B period within one field (one frame, that is, a screen rewriting cycle). However, in order to improve the moving image display, black insertion (black display or low luminance display) may be performed. Therefore, the driving method is not limited to that shown in FIG.

  For example, the drive method of FIG. 129 is illustrated. In order to facilitate understanding, it is assumed that FIG. 129 includes four display periods ((a), (b), (c), and (d)). Also, 4 frames = 1 field, FIG. 129 (a) is the first frame, FIG. 129 (b) is the second frame, FIG. 129 (c) is the third frame, and FIG. 129 (d) is the fourth frame. . The display is repeated in the order of FIG. 129 (a) → (b) → (c) → (d) → (a) → (b) →.

  In the first frame, as shown in FIG. 129 (a), even-numbered pixel rows are sequentially selected and the image is rewritten. When the rewriting of the first frame is completed, as shown in FIG. 129 (b), black display is sequentially performed from the top of the screen 50 (FIG. 129 (b) is a state in which the black display writing is completed). In the next third frame, as shown in FIG. 129 (c), images are sequentially written in the odd-numbered pixel rows from the top of the screen 50. That is, odd-numbered images are sequentially displayed from the top of the screen. In the next fourth frame, the image is turned off (black display) from the top of the screen 50 (FIG. 129 (d) also shows the state when the light is completely turned off).

In FIGS. 129 and 129, (a) and (c) express that an image is written and display an image, but the present invention is basically characterized in a state of displaying (lighting) an image. . Therefore, writing an image (implementing a program) and displaying an image are not necessarily the same. That is, in FIGS. 129 (a) and 129 (c), it may be considered that the current flowing through the EL element 15 is controlled by the control of the gate signal line 17b so as to be turned on or off. Therefore, switching between the state of FIG. 129 (a) and the state of FIG. 129 (b) can be performed in a lump (for example, in the 1H period). For example, it can be implemented by controlling the enable terminal (the shift register of the gate driver 12b holds an on / off state (in FIG. 129 (a), the shift register corresponding to the even-numbered pixel row is on data)). When it is off, the state of FIGS. 129 (b) and (d) is displayed, and the display state of FIG. 129 (a) is obtained by turning on the enable terminal. Therefore, the display shown in FIGS. 129 (a) and (c) can be performed in the on / off state of the gate signal line 17b (the image data is held in the capacitor 19 in advance in the pixel configuration shown in FIG. 1). In the above description, it is assumed that the states (a), (b), (c), and (d) in FIG. 129 are implemented for each 1 l frame period.

  However, the present invention is not limited to this display state. This is because the black insertion state shown in FIGS. 129 (b) and 129 (d) should be carried out for a period of 4 msec in order to improve or improve the moving image display state at least. Therefore, in the embodiment of the present invention, the shift register circuit of the gate driver circuit 12b is used to scan the gate signal line 17b to realize the display state of FIGS. 129 (a) and 129 (c). Absent. Odd-numbered gate signal lines 17b (referred to as odd-numbered gate signal line sets) are connected together, and even-numbered gate signal lines 17b (referred to as even-numbered gate signal line sets) are connected together and odd-numbered gates. The on / off voltage may be applied alternately between the signal line set and the even-numbered gate signal line set. If the on-voltage is applied to the odd-numbered gate signal line group and the off-voltage is applied to the even-numbered gate signal line group, the display state of FIG. 129 (c) is realized. If the on-voltage is applied to the even-numbered gate signal line group and the off-voltage is applied to the odd-numbered gate signal line group, the display state of FIG. 129 (a) is realized. If a turn-off voltage is applied to both the odd-numbered gate signal line set and the even-numbered gate signal line set, the display states of FIGS. 129 (b) and (d) are realized. Each state of FIGS. 129 (a), (b), (c), and (d) may be performed for a period of 4 msec or more (particularly, FIGS. 129 (b) and (d)).

  In the driving method shown in FIG. 129, the screen display state (FIGS. 129 (a) and (c)) and the black display state (black insertion, FIGS. 129 (b) and (d)) are alternately repeated. Therefore, the image display becomes intermittent display, and the moving image display performance is improved (moving image blur does not occur).

  In the embodiment of FIG. 129, in the first frame and the third frame, an image is displayed in an odd pixel row or an even pixel row, and a black screen (FIGS. 129 (b) (d)) is inserted between the two screens. It was a drive system. However, the present invention is not limited to this, and the display state of FIG. 118 may be implemented in the first frame and the third frame, and a black display may be inserted between the two frames. A timing chart in the above embodiment is shown in FIG. FIG. 130A shows the first frame, and FIG. 130B shows the second frame in the black insertion state. FIG. 130 (c) shows the third frame. Note that the fourth frame is omitted because it is the same as FIG. However, the fourth frame is not always necessary. The configuration may be 3 frames = 1 field. This is because the motion picture blur is greatly improved because the black screen is inserted in the second frame. That is, FIG. 130 (a) → (b) → (c) → (a) →..

FIG. 130 (a) displays an image for 1H in 4 horizontal scanning periods (4H) in FIG. 118 (a) (each gate signal line 17b has a Vgl voltage (ON voltage) of 1H every 4H). In the next second frame, the off voltage (Vgh) is applied to all the gate signal lines 17b, and this control is performed at a time by controlling the enable terminal as in the previous embodiment. Therefore, the state shown in Fig. 130 (b) is not limited to the implementation of one frame period, and in order to improve the moving image display, it should be maintained for a period of 4 msec or more. However, if the image is rewritten sequentially from the top of the screen (although not limited to the top) as shown in Fig. 130 (a), the image will be skipped. Game Collectively connecting the signal line 17b, also, according to the controlling the enable terminal, can be easily performed.

  In FIG. 130, each pixel row is regularly displayed, for example, turned on for 1H period in 4H period. However, each pixel row needs to have the same lighting (display) period in a unit period (for example, one frame, one field, etc.). That is, it is not necessary to regularly perform the lighting state and the non-lighting state.

  FIG. 131 shows an example of an irregular lighting state. The gate signal line 17b (1) is applied with an on-voltage to the first H, fifth H, sixth H, ninth H, thirteenth H, fourteenth H,. The off voltage is applied during other periods. Therefore, the on-voltage is not periodically applied (though it is periodic in the long term), it is random. The one frame period (unit period) plus the period during which the on-voltage is applied to each gate signal line 17b may be substantially matched with the other gate signal lines 17b. In this way, the lighting times of the respective pixel rows (the pixel rows are supposed to be lit (displayed) by applying the ON voltage to the gate signal line 17b) are substantially the same. In FIG. 131, the signal waveform applied to each gate signal line 17b is scanned 1H at a time. In this way, by scanning (applying) the basic pattern waveform by shifting the gate signal line 17b by 1H (predetermined clock or unit), the luminance of the display screen can be made uniform over the entire screen. In FIG. 131, it goes without saying that the brightness of the screen can be controlled (adjusted) by adjusting the application period of the on-voltage (Vgl).

  In the above embodiment, the same on / off voltage pattern is applied to the gate signal line 17b in each frame (unit period). However, according to the present invention, the period in which each pixel row (pixel) is lit (displayed) or not lit (not displayed) in a predetermined period is substantially equal. Therefore, in the driving method of 2 frames = 1 field, the signal waveforms of the gate signal lines 17b applied to the first frame and the second frame may be different. For example, an arbitrary pixel row may be driven such that an on-voltage is applied for a period of 10H in the first frame and an on-voltage is applied for a period of 20H in the second frame (referred to as two frames). In the unit period, an ON voltage is applied for a period of 10H + 20H). The on-voltage is applied to the other pixel rows for a period of 30H.

  This embodiment is illustrated in FIG. In FIG. 132 (a) (referred to as the first frame), the on-voltage for one horizontal scanning period (1H) is applied to the gate signal line 17b corresponding to each pixel row in a cycle of four horizontal scanning periods (4H). In FIG. 132 (b) (assumed to be the second frame), an on-voltage is applied to the gate signal line 17 corresponding to each pixel row for a period of 2H in a 4H cycle. That is, in 2 frames, an on-voltage is applied for a period of (1 + 2) H with a (4 + 4) H cycle. Even if it is driven in this way, the ON voltage is applied to each gate signal line 17b for the same period in the unit period (2 frames in FIG. 132). Therefore, each pixel row is displayed with the same luminance (assuming white raster display).

  In FIG. 130, the ON voltage is applied for a period of 1H in a 4H cycle, but the present invention is not limited to this. For example, as shown in FIG. 133, an on-voltage may be applied for a period of 1H with a period of 8H. Further, the signal waveform applied to each gate signal line 17b in each frame may be completely randomized without giving periodicity. This is because the total period in which the ON voltage is applied in a unit cycle (unit period) only needs to be the same for all the gate signal lines 17b.

However, in the above embodiment, the sum period for applying the ON voltage is made to coincide in the unit period in all the gate signal lines 17b, but this is not applied in the following cases. This is a case where a plurality of screens 50 having different luminances are provided within one screen 50 (that is, one display panel). The screen 50 is a case where the first screen 50a and the second screen 50b are configured, and the screens 50a and 50b have different luminances. Although the brightness of the two screens 50 can be varied by adjusting the program current Iw, the gate signal line 17b is scanned, and each pixel row on the first screen 50a is turned on (displayed). ) It is easy to realize a method in which the period and the lighting (display) period of each pixel row on the second screen 50b are different. For example, each pixel row on the first screen 50a applies an ON voltage to the gate signal line 17b for a period of 1H to 4H. Each pixel row on the second screen 50b applies an ON voltage to the gate signal line 17b for a period of 1H to 8H. Thus, by changing the period during which the on-voltage is applied to each screen, the brightness of the screen can be adjusted, and the gamma curve at that time can be made similar.

  In the above embodiment, the current flowing through the EL element 15 is adjusted (turned on and off) by adjusting the gate signal line 17b, thereby adjusting the luminance of the display screen 50 or improving the moving image display. there were. FIG. 134 shows another embodiment of the present invention having the above-described effects.

  The pixel 16 in FIG. 134 is arranged or configured as shown in FIG. A difference from the pixel configuration in FIG. 1 is that one terminal of the storage capacitor 19 (capacitor 19) is connected to the capacitance control line 1341. One capacitance control line 1341 is common to one pixel row. The capacity control line 1341 is connected to the capacity control common line 1343.

  In FIG. 135, the capacitor 19 has one terminal connected to the capacitance control line 1341, and the other terminal connected to the gate terminal of the TFT 11a. Now, it is assumed that the Va voltage is applied to the gate terminal (G) of the TFT 11a. Further, it is assumed that a Vdd voltage is applied to the source terminal (S) of the TFT 11a. Also, Va <Vdd. It is assumed that a Vc voltage is applied to the capacitance control line 1341.

  In this state, when the Vc voltage of the capacitance control line 1341 is changed to the + side, the Va voltage is also shifted to the + side along with this change. Since the TFT 11a is a P-channel transistor, when the gate terminal of the TFT 11a is shifted to the + side (Vdd side), the TFT 11a is in a direction in which no current flows. Therefore, when the change to the + side of the Vc voltage is larger than a certain value, the TFT 11a is in a state where no current flows completely (cut-off state). That is, by controlling the potential applied to the capacitance control line 1341, the corresponding pixel row can be brought into a black display state. Conversely, when the Vc voltage of the capacitance control line 1341 is changed to the-side, the potential of the gate terminal (G) of the TFT 11a is also shifted to the-side. Therefore, more current flows through the TFT 11a. The above matter is the case where the driving TFT 11a is composed of a P-channel transistor. When the driving TFT 11a is an N channel, the opposite is true. That is, when the potential of the capacitance control line 1341 is shifted to the + side, the N-channel driving TFT 11a allows more current to flow to the EL element 15.

  By applying the above driving method to FIG. 135, the display screen 50 can be displayed in black. That is, the black insertion described in FIG. 124 and the like can be realized.

  In FIG. 134, a capacity control common line 1343 (1343a, 1343b, 1343c, 1343d) is formed or arranged. The capacity control line 1341 in the (4N + 1) pixel row (where N is an integer greater than or equal to 0) is connected to the capacity control common line 1343a. Further, the capacitance control line 1341 of the (4N + 2) pixel row is connected to the capacitance control common line 1343b. The (4N + 3) pixel row is connected to the capacitance control common line 1343c, and the capacitance control line 1341 of the (4N + 4) pixel row is connected to the capacitance control common line 1343d.

  With the above configuration, if the voltage applied to the capacitance control common line 1343a is shifted to the + side, (4N + 1) pixel rows are not displayed (black display or low luminance display). Similarly, if the voltage applied to the capacitance control common line 1343b is shifted to the + side, the (4N + 2) pixel row is not displayed (black display or low luminance display). If the applied voltage of the capacitance control common line 1343c is shifted to the + side, the (4N + 3) pixel row is not displayed, and if the applied voltage of the capacitance control common line 1343d is shifted to the + side, (4N + 4) pixels. The line is hidden. By controlling the capacitance control common line 1343 as described above, a predetermined pixel row can be displayed in black. Accordingly, the screen brightness can be adjusted by adjusting the control timing and control cycle of the capacity control common line 1343. In addition, by setting the connection state of the capacity control line 1341 and the capacity control common line 1343, the number of connections, and the number of formed capacity control common lines 1343 to a predetermined state, a concentrated black insertion portion is provided as shown in FIG. Can do. Therefore, the moving image display can be improved.

  In FIG. 135A, the odd-numbered pixel rows are connected to the capacitance control common line 1343a, and the even-numbered pixel rows are connected to the capacitance control common line 1343b. Therefore, by alternately applying a voltage to the positive side to the capacitance control common lines 1343a and 1343b, the display screen 50 can be made into a non-display pixel row in a comb shape. In FIG. 135 (b), each of the three pixel rows is connected to a different capacitance control common line 1343. Therefore, lighting or non-lighting control can be performed in a cycle of three pixel rows.

  When the voltage applied to the capacitance control line 1341 and changed to the + side is relatively small, the current applied by the TFT 11a is returned to the original current by shifting the voltage applied to the capacitance control line 1341 to the-side again. (However, it is necessary to add a compensation voltage.) However, if the voltage shifted to the + side is larger than a predetermined value, the current flowing through the TFT 11a cannot be restored (the necessary compensation voltage increases and it becomes difficult to obtain the original current value).

  In order to perform black insertion with the configuration of FIG. 135, it is basically better not to restore the image data held in the capacitor 19 (because it is difficult to restore the original holding voltage completely). is there). In other words, the image can be displayed in black.

  For example, as shown in FIG. 136, a positive voltage is applied to the capacitance control line 1341 at the R position to make the black display 52 before image writing. That is, a + voltage is applied to the capacitance control line 1341 to make the screen 50 a black display 52. Next, after the elapse of a predetermined period, an image is written (the image writing position is the pixel writing line 51). In FIG. 136, writing is performed at a position separated by K (K1 in the case of FIG. 136 (a), K2 in the case of FIG. 136 (b)). K1 indicates the number of pixel rows. That is, the time from writing black at the R position to writing the image is the number of pixel rows × 1 horizontal scanning period. Therefore, as K increases, the black writing period increases (K1 <K2), and the image display becomes darker. The larger the K value, the darker the screen, and the smaller the K value, the brighter the screen. The brightness of the image can be adjusted by adjusting the value of K. Also, the greater the value of K, the higher the effect of improving moving image blur.

  In the above embodiment, one source driver circuit (IC) 14 and one gate driver circuit (IC) 12 display an image on one screen 50. However, the present invention is not limited to this. For example, in the embodiment of FIG. 137, the screen 50 is composed of a screen 50a and a screen 50b. A source driver circuit 14a is connected to the source signal line 18a of the screen 50a. A source driver circuit 14b is connected to the source signal line 18b of the screen 50b. Gate signal lines (17a, 17b) to the screen 50a and the screen 50b are connected to one built-in gate driver circuit 12.

  In other words, in the embodiment of FIG. 137, the gate driver circuit (IC) 12 is common to the screens 50a and 50b, and the screen 50 is divided into two and driven by the two source driver circuits (14a and 14b). Yes. The writing of the image is not limited to the downward direction (A direction) from the top of the screen 50. As shown in FIG. 137, scanning may be performed from the bottom of the screen 50 upward (B direction). Further, the screen 50a may be scanned in the A direction, and the screen 50b may be scanned in the B direction. In FIG. 137, the screen 50 is divided into two, but it goes without saying that it may be divided into three or more. Further, the source driver circuit 14a is arranged or configured to drive even-numbered source signal lines 18 of one display screen 50, and the source driver circuit 14b drives odd-numbered source signal lines 18 of the display screen 50. May be. The same applies to the gate driver circuit 12. A plurality of gate driver circuits 12 may be used to drive each screen (50a, 50b). The gate driver circuit 12a is arranged or configured to drive even-numbered gate signal lines 18 on one display screen 50, and the gate driver circuit 12b drives odd-numbered gate signal lines 18 on the display screen 50. May be. Note that a protection diode is preferably formed on the source signal line 14 and the gate signal line 12 for electrostatic protection. It goes without saying that the above matters can be applied to other embodiments of the present invention.

  The above embodiment is similar to the pixel configuration of FIG. 1, but the present invention is not limited to this. For example, a pixel configuration of a current mirror may be used as shown in FIG. The gate driver circuit 12 controls the voltage applied to the capacitor 19 using the capacitance control line 1341. Since other matters are the same as those in FIG.

  Further, as shown in FIG. 139, the pixel configuration and driving method described in FIG. 135 can be applied (adopted) to a voltage-driven pixel configuration including two transistors.

  In FIG. 139, the selection transistor 11b is configured (formed) with an N-channel transistor. Therefore, the voltage applied to the gate signal line 17 is turned on with the positive voltage (Vgh). On the other hand, the gate driver circuit 12 controls the voltage applied to the capacitor 19 using the capacitance control line 1341. When the TFT 11b is turned on, the voltage applied to the source signal line 18 is applied to the gate (G) terminal of the driving TFT 11a. The TFT 11b is turned off by applying the Vgl voltage to the gate signal line 17. Since other matters are the same as those in FIG.

  FIG. 140 shows a configuration in which the pixel configuration of FIG. 139 is connected in multiple stages. The gate signal line 17 is connected to the gate signal line 17a and the capacitance control line 1341. The voltage applied to the gate signal line 17 at the previous stage is connected to the capacitance control line 1341 of the pixel 16 at the next stage. For example, in FIG. 140, the gate signal line 17a of the pixel 16a and the capacitance control line 1341 of the pixel 16b are connected to the common gate signal line 17. Therefore, by applying the selection voltage (Vgh) to the gate signal line 17, the TFT 11b of the pixel 16a is turned on, and the Vgh voltage is also applied to the capacitance control line 1341 of the pixel 16b, and the gate (G of the TFT 11a of the pixel 16b). ) The terminal is pulled in the direction of the Vdd voltage to be turned off.

With the above operation, the video signal of the source signal line 18 is applied to the gate terminal of the pixel 16a in the pixel 16a. At the same time, the pixel 16b is in an off state (black display, low luminance display, or non-lighting state).
It becomes. Therefore, the scanning of the gate signal line 17 resets the next pixel row (OFF state (black display, low luminance display or non-lighting state)), and then the video data is written to the next pixel row.

  As described above, since each pixel 16 writes an image after resetting, there is no shortage of writing, and a good image display can be realized.

  In the configuration of FIG. 140, the pixel row at the next stage is reset. However, the present invention is not limited to this, and it is needless to say that an image may be written after resetting a pixel row separated by a plurality of pixel rows. Further, it is needless to say that the driving method of simultaneously driving a plurality of pixel rows in FIG. 140 is not limited to that in FIG. 139 and can be applied to the pixel configurations in FIGS. 138 and 135. In FIG. 139, the TFT 11b is an N-channel transistor, but may be a P-channel transistor. Even in this case, the pixel may be configured so that the driving transistor 11a of the pixel at the next stage is turned off by applying the on voltage to the gate signal line 17. Since this change can be easily made by those skilled in the art, a description thereof will be omitted. Of course, the pixel 16 in the next stage may not only display black but also display white. This is because a so-called reset state can be realized.

  An embodiment of the display device of the present invention that uses the display panel and display device of the present invention described above or implements the driving method of the present invention will be described.

  FIG. 57 is a plan view of a mobile phone as an example of an information terminal device. An antenna 571, a numeric keypad 572, and the like are attached to the housing 573. 572 and the like are display color switching keys, power on / off, and frame rate switching keys.

  Even if the key 572 is pressed once, the display color is set to the 8-color mode, and then the display color is set to the 256-color mode when the same key 572 is pressed, and the display color is set to the 4096-color mode when the key 572 is further pressed. Good. The key is a toggle switch that changes the display color mode each time it is pressed. In addition, you may provide the change key with respect to a display color separately. In this case, there are three (or more) keys 572.

  The key 572 may be a push switch, a mechanical switch such as a slide switch, or may be switched by voice recognition or the like. For example, when 4096 colors are input to the receiver by voice input, for example, “high quality display”, “256 color mode” or “low display color mode” is input to the receiver, the display screen 50 of the display panel displays. The display color is changed. This can be easily realized by adopting the current speech recognition technology.

  Further, the display color may be switched by an electrical switch or a touch panel that is selected by touching a menu displayed on the display unit 21 of the display panel. Further, it may be configured to be switched by the number of times the switch is pressed, or to be switched by rotation or direction like a click ball.

  Although 572 is a display color switching key, it may be a key for switching the frame rate. Moreover, it is good also as a key etc. which switch a moving image and a still image. A plurality of requirements such as a moving image, a still image, and a frame rate may be switched at the same time. Alternatively, the frame rate may be changed gradually (continuously) as long as the pressure is kept pressed. This case can be realized by making the resistor R of the capacitor C and the resistor R constituting the oscillator a variable resistor or an electronic volume. The capacitor can be realized by using a trimmer capacitor. Alternatively, a plurality of capacitors may be formed on the semiconductor chip, one or more capacitors may be selected, and these may be connected in parallel in a circuit.

The technical idea of switching the frame rate depending on the display color is not limited to mobile phones, but is widely applied to devices having display screens such as palmtop computers, notebook computers, desktop computers, and portable watches. be able to. Further, the present invention is not limited to a liquid crystal display device (liquid crystal display panel), and can be applied to a liquid crystal display panel, an organic EL display panel, a transistor panel, a PLZT panel, and a CRT.

  Although not shown in the cellular phone of the present invention described with reference to FIG. 57, a CCD camera is provided on the back side of the housing. Images taken with a CCD camera can be immediately displayed on the display screen 50 of the display panel. Data captured by the CCD camera can be displayed on the display screen 50. The CCD camera image data is 24 bits (16.7 million colors), 18 bits (260,000 colors), 16 bits (650,000 colors), 12 bits (4096 colors), 8 bits (256 colors) with the key 572 input. Can be switched.

  When the display data is 12 bits or more, error diffusion processing is performed for display. That is, when the image data from the CCD camera is larger than the capacity of the built-in memory, error diffusion processing or the like is performed, and the image processing is performed so that the number of display colors is less than the capacity of the built-in image memory.

  Now, it is assumed that the source driver IC 14 has a built-in RAM of one screen with 4096 colors (4 bits for each of RGB). When the image data sent from the outside of the module is 4096 colors, the image data is directly stored in the built-in image RAM of the source driver IC 14, the image data is read from the built-in image RAM, and the image is displayed on the display screen 50.

  When the image data is 260,000 colors (G: 6 bits, R, B: 5 bits, 16 bits in total), the data is temporarily stored in the operation memory of the error diffusion controller, and at the same time an error diffusion or dither processing is performed. Error diffusion or dithering is performed. By this error diffusion processing or the like, the 16-bit image data is converted to 12 bits, which is the number of bits of the built-in image RAM, and transferred to the source driver IC 14. The source driver IC 14 outputs RGB 4-bit (4096 colors) image data and displays an image on the display screen 50.

  Further, an embodiment in which the EL display panel, the EL display device, or the driving method of the present invention is employed will be described with reference to the drawings.

  FIG. 58 is a sectional view of the viewfinder in the embodiment of the present invention. However, it is schematically drawn for easy explanation. In addition, there are parts that are partially enlarged or reduced, and some parts are omitted. For example, in FIG. 58, the eyepiece cover is omitted. The above also applies to other drawings.

  The back surface of the body 573 is dark or black. This is because stray light emitted from the EL display panel (display device) 574 is diffusely reflected on the inner surface of the body 573 to prevent a decrease in display contrast. Further, a phase plate (λ / 4 plate or the like) 108, a polarizing plate 109, or the like is disposed on the light emission side of the display panel. This is also explained in FIG. 10 and FIG.

  A magnifying lens 582 is attached to the eyepiece ring 581. The observer changes the insertion position of the eyepiece ring 581 in the body 573 and adjusts so that the display image 50 on the display panel 574 is in focus.

  Further, if a positive lens 583 is disposed on the light exit side of the display panel 574 as necessary, the principal ray incident on the magnifying lens 582 can be converged. Therefore, the lens diameter of the magnifying lens 582 can be reduced, and the viewfinder can be downsized.

FIG. 59 is a perspective view of the video camera. The video camera is provided with a photographing (imaging) lens unit 592 and a video or camera body 573, and the photographing lens unit 592 and the viewfinder unit 573 are back to back. An eyepiece cover is attached to the viewfinder (see also FIG. 58) 573. An observer (user) observes the image 50 on the display panel 574 from the eyepiece cover.

  On the other hand, the EL display panel of the present invention is also used as a display monitor. The display unit 50 can freely adjust the angle at a fulcrum 591. When the display unit 50 is not used, it is stored in the storage unit 593.

  The switch 594 is a changeover or control switch that performs the following functions. A switch 594 is a display mode switching switch. The switch 594 is preferably attached to a mobile phone or the like. The display mode changeover switch 594 will be described.

  As one of the driving methods of the present invention, there is a method in which an N-fold current is supplied to the EL element 15 to light it for a period of 1 / M of 1F. The brightness can be changed digitally by changing only the 1 / M value to be lit. For example, assuming that N = 4, a current that is four times as large as the EL element 15 is passed. If the lighting period is set to 1 / M and M = 1, 2, 3, and 4 are switched, the brightness can be switched from 1 to 4 times. In addition, you may comprise so that it can change with M = 1, 1.5, 2, 3, 4, 5, 6, etc.

  The above switching operation is used for a configuration in which the display screen 50 is displayed very brightly when the power of the mobile phone is turned on, and the display brightness is reduced to save power after a predetermined time has elapsed. It can also be used as a function for setting the brightness desired by the user. For example, when outdoors, the screen is very bright. This is because the surroundings are bright outdoors and the screen cannot be seen at all. However, if the display is continued with high luminance, the EL element 15 deteriorates rapidly. For this reason, when it is very bright, it is configured to return to normal luminance in a short time. Further, in the case of displaying with high brightness, the display brightness can be increased by the user pressing the button.

  Therefore, it is preferable that the user can be switched by the button 594, can be automatically changed in the setting mode, or can be automatically switched by detecting the brightness of external light. Further, it is preferable that the display brightness is set to 50%, 60%, and 80% and can be set by the user.

  The display screen 50 is preferably a Gaussian distribution display. The Gaussian distribution display is a method in which the brightness at the center is bright and the periphery is relatively dark. Visually, if the central part is bright, it is felt bright even if the peripheral part is dark. According to the subjective evaluation, if the peripheral part keeps 70% of brightness compared to the central part, it is visually inferior. Even if the brightness is further reduced to 50% luminance, there is almost no problem. In the self-luminous display panel of the present invention, the above-described N-fold pulse driving (a method in which an N-fold current is supplied to the EL element 15 and the light is lit for 1 / M of 1F) is used from the top to the bottom of the screen. A Gaussian distribution is generated in the direction.

  Specifically, the value of M is increased at the top and bottom of the screen, and the value of M is decreased at the center. This is realized by modulating the operation speed of the shift register of the gate driver 12 or the like. The left and right brightness modulation of the screen is generated by multiplying the table data and the video data. With the above operation, when the peripheral luminance (angle of view 0.9) is 50%, the power consumption can be reduced by about 20% compared to the case of 100% luminance. When the peripheral luminance (angle of view 0.9) is 70%, the power consumption can be reduced by about 15% compared to the case of 100% luminance.

It is preferable to provide a changeover switch or the like so that the Gaussian distribution display can be turned on and off. This is because, for example, when the Gaussian display is used outdoors, the periphery of the screen cannot be seen at all. Therefore, it is preferable that the user can be switched with a button, can be automatically changed in a setting mode, or can be automatically switched by detecting the brightness of external light. Further, it is preferable that the peripheral brightness is set to 50%, 60%, 80% and so on by the user. This switching may be performed automatically by a photo sensor or may be switched by a user's switch operation.

  In a liquid crystal display panel, a fixed Gaussian distribution is generated by a backlight. Therefore, the Gaussian distribution cannot be turned on / off. The fact that the Gaussian distribution can be turned on / off is an effect peculiar to a self-luminous display device.

  Further, when the frame rate is predetermined, flicker may occur due to interference with the lighting state of an indoor fluorescent lamp or the like. That is, when the fluorescent lamp is lit at an alternating current of 60 Hz, if the EL display element 15 operates at a frame rate of 60 Hz, a slight interference occurs and the screen feels slowly blinking. There is. To avoid this, change the frame rate. The present invention adds a frame rate changing function. In addition, the N or M value can be changed in N-fold pulse driving (a method in which an N-fold current is supplied to the EL element 15 and lighted only for a period of 1 / M of 1F).

  The above functions can be realized by the switch 594. The switch 594 switches between the functions described above by holding down a plurality of times according to the menu of the display screen 50.

  Needless to say, the above items are not limited to mobile phones but can be used for televisions, monitors, and the like. Further, it is preferable to display an icon on the display screen so that the user can immediately recognize the display state. The above matters are the same for the following items.

  The EL display device and the like of this embodiment can be applied not only to a video camera but also to an electronic camera as shown in FIG. The display device is used as a monitor 50 attached to the camera body 601. In addition to the shutter 603, a switch 594 is attached to the camera body 601.

  The video camera or the like of the present invention is equipped with a touch panel and has an Internet terminal function capable of operating Web browsing, e-mail, etc. with a finger or a pen. Further, it is preferable to mount a compact flash card (with an error correction function) of 256 Mbytes or more instead of the hard disk device. By adopting only the basic function part of the Windows (registered trademark) OS, the capacity can be reduced. Since there is no HDD, there is no worry about disk crashes, and robustness can be secured. Equipped with two PC card slots. It is preferable to use a modem, ISDN, PIAFS, LAN, wireless LAN, or the like. Built-in antenna for wireless LAN. USB / RS232C interface enables connection of business peripherals such as barcode readers. In addition to a space-saving design without a keyboard, it is constructed to withstand water and dust (conforms to JIS drip-proof class 2). Improved operation for BtoBtoC users, such as using a touch panel and “one-touch keys” that can easily launch applications, and installing a handwritten E-mail function (including handwritten memo function). ing. The above functions and the like are also mounted with other display devices and information terminals of the present invention.

The above is the case where the display area of the display panel is relatively small, but the display screen 50 tends to bend when the display area is larger than 30 inches. As a countermeasure, in the present invention, an outer frame 611 is attached to the display panel as shown in FIG. 61, and the outer frame 611 is attached by a fixing member 614 so as to be suspended. The fixing member 614 is used to attach to a wall or the like.

  However, as the screen size of the display panel increases, the weight increases. Therefore, a leg mounting portion 613 is disposed on the lower side of the display panel so that the weight of the display panel can be held by the plurality of legs 612.

  The leg 612 can move left and right as shown in A, and the leg 612 can be contracted as shown in B. Therefore, the display device can be easily installed even in a narrow place.

  Note that a plastic film-metal plate composite material (hereinafter referred to as a composite material) is used for the legs 612 or the casing (also in the present invention). The composite material is obtained by strongly bonding a metal and a plastic film via a special surface treatment layer (adhesive layer). The metal plate is preferably 0.2 mm or more and 0.8 mm or less, and the plastic film laminated to the metal plate via a special surface treatment layer is preferably 15 μm or more and 100 μm or less. A special adhesion method provides strong adhesion between the plastic and the metal plate. By using this composite material, the plastic layer can be colored, dyed, and printed, and the secondary processing steps (manual application of the film and plating) on the pressed parts can be eliminated. In addition, it is suitable for deep drawing and DI molding, which was impossible in the past.

  In the television shown in FIG. 61, the surface of the screen is covered with a protective film (or a protective plate). This is for the purpose of preventing an object from hitting the surface of the display panel and damaging it. An AIR coat is formed on the surface of the protective film, and the surface is embossed to prevent external conditions (external light) from appearing on the display panel.

  A certain space is arranged by spreading beads or the like between the protective film and the display panel. Moreover, a fine convex part is formed in the back surface of a protective film, and space is hold | maintained between a display panel and a protective film with this convex part. By holding the space in this way, the impact from the protective film is suppressed from being transmitted to the display panel.

  It is also effective to place or inject an optical binder such as a liquid such as alcohol or ethylene glycol or a solid resin such as an epoxy resin between the protective film and the display panel. This is because interface reflection can be prevented and the optical binder functions as a buffer material.

  Examples of the protective film include a polycarbonate film (plate), a polypropylene film (plate), an acrylic film (plate), a polyester film (plate), and a PVA film (plate). Needless to say, other engineering resin films (ABS and the like) can be used. Moreover, what consists of inorganic materials, such as tempered glass, may be used. The same effect can be obtained by coating the surface of the display panel with an epoxy resin, a phenol resin, or an acrylic resin with a thickness of 0.5 mm or more and 2.0 mm or less instead of disposing the protective film. It is also effective to emboss the surface of these resins.

  It is also effective to coat the surface of the protective film or coating material with fluorine. This is because the dirt on the surface can be easily wiped off with a detergent or the like. Further, the protective film may be formed thick and may also be used as a front light.

The screen is not limited to 4: 3, and may be a wide display. The resolution is preferably 1280 × 768 dots or higher. DVD by making wide type
You can enjoy full-screen titles and programs such as movies and TV broadcasts in full screen. The brightness of the display panel is preferably 300 cd / m ² (candela / square meter). More preferably, the brightness of the display panel is preferably 500 cd / m ² (candela / square meter). In addition, a changeover switch is provided so that it can be displayed at a brightness (200 cd / m ² ) suitable for the Internet and normal personal computer work.

Therefore, the user can optimally set the screen brightness according to the display contents or the usage method. Only in the 500 cd / m ² more window displaying the video, and other parts are also available settings to 200 cd / m ^2. You can flexibly deal with usage such as displaying TV programs in the corner of the display and checking emails. The speaker has a tower shape and is designed to spread the sound not only in the front direction but also in the entire space.

  The TV program playback and recording functions are also improved in usability. Recording reservation from i-mode is made easy. Conventionally, it has been necessary to make a reservation after confirming the time and channel in a TV program guide such as a newspaper, but the electronic program guide can be checked and reserved in i-mode. If this is the case, you don't need to know the broadcast time. In addition, shortened playback of recorded programs is also possible. While judging the importance based on the presence or absence of telops and audio of news programs, etc., it is possible to skip the part judged unnecessary and to watch the outline of the program in a short time (about 1 to 10 minutes for a 30-minute program).

  A hard disk with a disk capacity of 40 GB or more is loaded so that TV recording can be performed. In addition to the main unit, it consists of an expansion box that combines a power supply and video input / output terminals. In addition to a personal computer and a TV, two video devices can be connected to the expansion box used to connect AV equipment such as video. In addition to the D1 terminal for the BS digital tuner, the video input also has an S terminal input, which can be selected according to the connected device. AV terminals are arranged on the front surface for convenient connection of game machines and the like.

  In addition, by setting the display screen to be 30 degrees forward bent or more and 120 degrees bent backward, it is possible to set the display screen to 90 degrees / 180/270 degrees so that it can be freely installed according to the operating environment. . For example, the browser screen can be displayed vertically by rotating 90 degrees. Moreover, a screen can be displayed toward the person sitting face-to-face by bending back 145 degrees.

  Needless to say, the above-described matters relating to the protective film, the casing, the configuration, the characteristics, the functions, and the like are also applied to other display devices or information display devices of the present invention.

  In the above embodiments, the EL elements 15 are R, G, and B, but are not limited thereto. For example, cyan, yellow, magenta, or any two colors may be used. Six colors of R, G, B, cyan, yellow, and magenta, or any four or more colors may be used. Further, it may be white monochromatic or white monochromatic light may be converted to RGB by a color filter. Moreover, it is not limited to an organic EL element, An inorganic EL element may be sufficient.

  In the embodiment of the present invention, the active matrix type display panel has been described as an example. However, the present invention is not limited to this. The source driver IC 14 or the like applies (absorbs) a current N times the predetermined current to the source signal line 18. A plurality of pixel rows are selected simultaneously. The concept that current is supplied to the EL element only during a predetermined period and current is not supplied during the other periods can be applied to a simple matrix display panel.

In addition, the EL element 15 has a large characteristic change in the early stage of lighting. For this reason, firing is likely to occur. For this measure, it is preferable to ship the product as a product after aging with white raster display for 20 hours or more and 150 hours or less after the panel is formed. In this aging, it is preferable to display at a brightness of about 2 to 10 times the predetermined display luminance.

  It goes without saying that the display panel according to the embodiment of the present invention can be effectively combined with a three-side free configuration. In particular, the three-side free configuration is effective when the pixel is manufactured using amorphous silicon technology. In addition, since a panel formed using amorphous silicon technology cannot control the process of variation in characteristics of transistor elements, it is preferable to perform N-fold pulse driving, reset driving, dummy pixel driving, and the like of the present invention. That is, the transistor and the like in the present invention are not limited to those using polysilicon technology, but may be those using amorphous silicon.

  Note that the N-fold pulse driving of the present invention (FIGS. 13, 16, 19, 20, 22, 24, 30 and the like) or the like is performed more than the display panel by forming the transistor 11 using low-temperature polysilicon technology. This is effective for a display panel in which the transistor 11 is formed by amorphous silicon technology. This is because the characteristics of adjacent transistors in the amorphous silicon transistor 11 are substantially the same. Therefore, even when driving with the added current, the driving current of each transistor is almost the target value (in particular, the N-fold pulse driving in FIGS. 22, 24, and 30 is a pixel configuration of a transistor formed of amorphous silicon). Effective).

  In the pixel configuration or the driving method described in this specification, the pixel configuration or the array configuration is not limited to the EL display panel. For example, it can be applied to a liquid crystal display panel. In that case, the EL element 15 may be replaced with a light modulation layer such as a liquid crystal layer, PLZT, or LED. For example, in the case of liquid crystal, TN (Twisted Nematic), IPS (In-Plane Switching), FLC (Ferroelectric Liquid Crystal (OCL), Optically Compensated Bend (OCB), STN (Super Quantitative Bend) Controlled Birefringence), HAN (Hybrid Aligned Nematic) mode, DSM mode (dynamic scattering mode), and the like. In particular, since DSM can be optically modulated by an applied current, matching with the present invention is good.

  The technical idea described in the embodiments of the present invention can be applied to a video camera, a projector, a stereoscopic television, a projection television, and the like. The present invention can also be applied to a viewfinder, a mobile phone monitor, a PHS, a portable information terminal and its monitor, a digital camera and its monitor.

  The present invention can also be applied to an electrophotographic system, a head mounted display, a direct view monitor display, a notebook personal computer, a video camera, and an electronic still camera. The present invention can also be applied to an automatic cash drawer monitor, public telephone, videophone, personal computer, wristwatch, and display device thereof.

  Furthermore, it goes without saying that the present invention can be applied or applied to display monitors for home appliances, pocket game devices and their monitors, backlights for display panels, or lighting devices for home use or business use. The lighting device is preferably configured so that the color temperature can be varied. In this case, the color temperature can be changed by forming RGB pixels in a stripe or dot matrix and adjusting the current flowing through them. It can also be applied to display devices such as advertisements or posters, RGB traffic lights, warning indicator lights, and the like.

The organic EL display panel is also effective as a light source for the scanner. Using an RGB dot matrix as a light source, the object is irradiated with light to read an image. Of course, it goes without saying that it may be monochromatic. Moreover, it is not limited to an active matrix, A simple matrix may be sufficient. If the color temperature can be adjusted, the image reading accuracy can be improved.

  The organic EL display device is also effective for the backlight of the liquid crystal display device. The RGB pixels of the EL display device (backlight) are formed in a stripe shape or dot matrix shape, and the color temperature can be changed by adjusting the current passed through them, and the brightness can be easily adjusted. In addition, since it is a surface light source, a Gaussian distribution that brightens the central part of the screen and darkens the peripheral part can be easily configured. It is also effective as a backlight for a field sequential type liquid crystal display panel that alternately scans R, G, and B light. Further, even when the backlight blinks, it can be used as a backlight of a liquid crystal display panel for displaying moving images by inserting black.

  The display panel, display device, and the like of the present invention exhibit distinctive effects according to their respective configurations such as high image quality, good moving image display performance, low power consumption, low cost, and high brightness.

  Note that if the present invention is used, a low power consumption information display device or the like can be configured, so that power is not consumed. Moreover, since it can be reduced in size and weight, resources are not consumed. Further, even a high-definition display panel can be sufficiently handled. Therefore, it is friendly to the global environment and space environment.

It is a pixel block diagram of the display panel of this invention. It is a pixel block diagram of the display panel of this invention. It is explanatory drawing of operation | movement of the display panel of this invention. It is explanatory drawing of operation | movement of the display panel of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a block diagram of the display apparatus of this invention. It is explanatory drawing of the manufacturing method of the display panel of this invention. It is a block diagram of the display apparatus of this invention. It is a block diagram of the display apparatus of this invention. It is sectional drawing of the display panel of this invention. It is sectional drawing of the display panel of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a block diagram of the display apparatus of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a block diagram of the display apparatus of this invention. It is a block diagram of the display apparatus of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a block diagram of the display apparatus of this invention. It is a block diagram of the display apparatus of this invention. It is a pixel block diagram of the display panel of this invention. It is a pixel block diagram of the display panel of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a pixel block diagram of the display panel of this invention. It is a block diagram of the display apparatus of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a pixel block diagram of the display panel of this invention. It is a pixel diagram of a display panel of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is a pixel block diagram of the display panel of this invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. It is explanatory drawing of the mobile telephone of this invention. It is explanatory drawing of the viewfinder of this invention. It is explanatory drawing of the video camera of this invention. It is explanatory drawing of the digital camera of this invention. It is explanatory drawing of the television (monitor) of this invention. It is a pixel block diagram of the conventional display panel. It is a functional block diagram of the driver circuit of the present invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the multistage type current mirror circuit of a voltage delivery system. It is explanatory drawing of the multistage type current mirror circuit of a current delivery system. It is explanatory drawing of the driver circuit in the other Example of this invention. It is explanatory drawing of the driver circuit in the other Example of this invention. It is explanatory drawing of the driver circuit in an Example other than this invention. It is explanatory drawing of the driver circuit in the other Example of this invention. It is explanatory drawing of the conventional driver circuit. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the control method of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the drive method of this invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the drive method of this invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is explanatory drawing of the driver circuit of this invention. It is explanatory drawing of the driver circuit of this invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is sectional drawing of the EL display apparatus of this invention. It is sectional drawing of the EL display apparatus of this invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is explanatory drawing of the source driver IC of this invention. It is a block diagram of a gate driver circuit of the present invention. FIG. 112 is a timing chart of the gate driver circuit of FIG. 111. It is a block diagram of a part of the gate driver circuit of the present invention. FIG. 114 is a timing chart of the gate driver circuit of FIG. 113. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 66 is an explanatory diagram of an EL display device according to the present invention; FIG. 66 is an explanatory diagram of an EL display device according to the present invention; FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. It is a block diagram of the EL display panel of the present invention. It is a block diagram of the EL display panel of the present invention. It is a block diagram of the EL display panel of the present invention. FIG. 46 is an explanatory diagram representing a driving method of an EL display device according to the present invention. It is a block diagram of the EL display panel of the present invention. It is a block diagram of the EL display panel of the present invention. It is a block diagram of the source driver circuit of this invention. It is explanatory drawing of the gate driver circuit of this invention. It is a block diagram of the source driver circuit of this invention. It is a block diagram of the source driver circuit of this invention. It is a block diagram of the source driver circuit of this invention. It is connection explanatory drawing of the source driver IC of this invention. It is connection explanatory drawing of the source driver IC of this invention. It is connection explanatory drawing of the source driver IC of this invention. It is a block diagram of the source driver circuit of this invention. FIG. 66 is an explanatory diagram of an EL display panel according to the present invention. FIG. 46 is an explanatory diagram of a pixel structure of an EL display panel of the present invention. It is explanatory drawing of the drive method of the display panel of this invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention. It is a block diagram of an EL display device of the present invention.

Explanation of symbols

11 TFT (Thin Film Transistor)
12 Gate driver IC (circuit)
14 Source driver IC (circuit)
15 EL (element) (light emitting element)
16 pixel 17 gate signal line 18 source signal line 19 storage capacity (additional capacitor, additional capacity)
50 Display screen 51 Write pixel (row)
52 Non-display pixels (non-display area, non-lighting area)
53 Display pixels (display area, lighting area)
61 Shift register 62 Inverter 63 Output buffer 71 Array substrate (display panel)
72 Laser irradiation range (laser spot)
73 Positioning marker 74 Glass substrate (array substrate)
81 Control IC (circuit)
82 Power IC (circuit)
83 Printed board 84 Flexible board 85 Sealing lid 86 Cathode wiring 87 Anode wiring (Vdd)
88 Data signal line 89 Gate control signal line 101 Bank (rib)
102 Interlayer insulating film 104 Contact connecting portion 105 Pixel electrode 106 Cathode electrode 107 Desiccant 108 λ / 4 plate 109 Polarizing plate 111 Thin film sealing film 281 Dummy pixel (row)
341 Output stage circuit 371 OR circuit 401 Lighting control line 471 Reverse bias line 472 Gate potential control line 561 Electronic volume circuit 562 SD (source-drain) short 571 Antenna 572 Key 573 Case 574 Display panel 581 Eyepiece ring 582 Magnifying lens 583 Convex lens 591 Support point (rotating part)
592 Shooting lens 593 Storage unit 594 Switch 601 Main body 602 Shooting unit 603 Shutter switch 611 Mounting frame 612 Leg 613 Mounting base 614 Fixing unit 631 Current source 632 Current source 633 Current source 641 Switch (ON / OFF means)
634 Current source (1 unit)
643 Internal wiring 651 Volume (current adjusting means)
681 Transistor group 691 Resistance (current limiting means, predetermined voltage generating means)
692 Decoder circuit 693 Level shifter circuit 701 Counter (counting means)
702 NOR
703 AND
704 Current output circuit 711 Raising circuit 721 D / A converter 722 Operational amplifier 731 Analog switch (ON / OFF means)
732 Inverter 761 Output pad (output signal terminal)
771 Reference current source 772 Current control circuit 781 Temperature detection circuit 782 Temperature control circuit 931 Cascade current connection line 932 Reference current signal line 941i Current input terminal 941o Current output terminal 951 Base anode line (anode voltage line)
952 Anode wiring 953 Connection terminal 961 Connection anode line 962 Common anode line 971 Contact hole 991 Base cathode line 992 Input signal line 1001 Connection resin (conductive resin, anisotropic conductive resin)
1011 Light Absorption Film 1012 Resin Bead 1013 Sealing Resin 1021 Circuit Forming Unit 1051 Gate Voltage Line 1091 Power Supply Circuit (IC)
1092 Power supply IC control signal 1093 Gate driver circuit control signal 1111 Unit gate output circuit 1341 Capacitance control line 1343 Capacitance control common line 1441 Reference voltage circuit 1443 Transistor 1444 Transistor 1451 (variable) Zener diode 1461 Wiring 1462 Buffer circuit 1463 Adjustment reference voltage output wiring 1471 Adjustment reference voltage output terminal 1481 Adjustment reference voltage input wiring 1482 Reference voltage changeover switch 1483 Adjustment reference voltage input terminal 1521 Variable magnification switch 1522 Transistor 1561 Pixel transistor formation area 1581 Lighting control driver 1582 Driver control line

Claims (10)

An EL display device having a display screen in which pixels are arranged in a matrix,
A gate driver circuit;
A source driver circuit that outputs a video signal;
The pixel includes an EL element, a driving transistor that supplies current to the EL element, a first switching transistor that applies a first voltage to a gate terminal of the driving transistor, and a driving transistor. 2. An EL display device, comprising: a second switching transistor for applying the video signal. An EL display device having a display screen in which pixels are arranged in a matrix,
A gate driver circuit;
A source driver circuit that outputs a video signal;
The pixel includes an EL element, a driving transistor that supplies current to the EL element, a first switching transistor that applies a first voltage to a gate terminal of the driving transistor, and a driving transistor. A second switch transistor for applying the video signal; and a first capacitor for holding the video signal;
The first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor is connected to the gate terminal of the driving transistor, and the second terminal of the first capacitor. The EL display device is characterized in that the terminal is held at the second voltage. The first switching transistor is turned on to supply the first voltage to the gate terminal of the driving transistor;
3. The second switching transistor is turned on after a plurality of horizontal scanning periods after applying the first voltage, and the video signal is supplied to the driving transistor. The EL display device described.   The EL display device according to claim 1, wherein the gate driver circuit includes a P-channel transistor. The pixel further includes a third switching transistor formed in a current path of the EL element,
Turning on and off the third switching transistor to control the current;
The EL display device according to claim 1, wherein a band-like non-display area and a display area can be generated on the display screen of the EL display apparatus. A second capacitor is further formed on the pixel;
The second capacitor has a first terminal and a second terminal;
The first terminal of the second capacitor is connected to the gate terminal of the driving transistor, and the second terminal of the second capacitor is connected to the gate terminal of the second switching transistor. The EL display device according to claim 1, wherein the display device is an EL display device.   The EL display device according to claim 1, further comprising detection means for detecting the brightness of external light. A gate signal line is connected to the gate driver circuit;
The gate driver circuit sequentially selects pixels of the display screen, applies the video signal,
A second pixel of the display screen that is selected by the gate driver circuit and applied with the video signal after applying the video signal to the first pixel of the display screen;
The gate signal line is connected to a gate terminal of the second switching transistor of the first pixel and a gate terminal of the first switching transistor of the second pixel. Item 3. The EL display device according to Item 1 or 2. The source driver circuit is a semiconductor IC,
The source dry circuit is mounted on a substrate on which the display screen is formed,
The EL display device according to claim 1, wherein a light shielding film is formed under the source driver circuit and on the substrate. In the display screen, first color pixels and second color pixels are arranged in the matrix,
3. The EL display device according to claim 1, wherein an area of the pixel electrode of the first color pixel is different from an area of the pixel electrode of the second color pixel. 4.

Images