JP2008146093A - El display panel and display device using the same, and method of driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device in which an EL element does not deteriorate, and which achieves a satisfactory color display. <P>SOLUTION: Electric current, which is N times as large as the electric current loaded to the EL element 15, is programmed in a capacitor 19. In order to obtain the predetermined light-emitting luminance of the EL element 15, electric current is made to flow to the EL element 15, during a period equal to 1/N of a single frame, and electric current is not loaded during other periods (1F(N-1)/N). A reverse-bias voltage is applied to the EL element 15 during a period of (N-1)/N. Thus, a faded edge line of image disappears and a proper moving picture display is realized. Because the reverse-bias voltage is applied to the EL element 15 during the period of a black display, the EL element 15 will not deteriorate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention mainly relates to an EL display panel that displays an image by self-emission, and an information display device such as a mobile phone using the EL display panel.

  Liquid crystal display panels are widely used in portable devices because they are thin and have low power consumption, so they are also used in devices such as word processors, personal computers, and televisions, as well as video camera viewfinders and monitors. Yes.

  However, since the liquid crystal display panel is not a self-luminous device, there is a problem that an image cannot be displayed unless a backlight is used. Since a predetermined thickness is required to configure the backlight, there is a problem that the thickness of the display module increases. In order to perform color display on the liquid crystal display panel, it is necessary to use a color filter. Therefore, there is a problem that the light utilization efficiency is low.

  In order to solve this problem, an EL display device according to the present invention includes a plurality of gate signal lines and a plurality of source signal lines arranged to cross each other, and the plurality of gate signal lines and the plurality of source signal lines. An active matrix EL display device comprising an image display region having pixels each having an EL element provided corresponding to the intersection of the driving transistors, and a driving transistor for supplying a current to be supplied to the EL element in the pixel; In the pixel, a first switch transistor arranged in a signal path between the driving transistor and the source signal line, and arranged in the pixel between the driving transistor and the EL element. A second switch transistor, a current output circuit for outputting a current corresponding to the video signal, and a power supply for the source signal line. And a precharge or discharge circuit for forcibly releasing or charging the first switch transistor, a first gate signal line is connected to the gate terminal of the first switch transistor, and the gate terminal of the second switch transistor Is connected to a second gate signal line, and the first switch transistor and the second switch transistor can be independently turned on / off, and the current of the current output circuit is the drive transistor. The precharge or discharge circuit outputs a voltage for setting the display in the pixel to a black level to the pixel, and the precharge or discharge circuit is configured to flow by turning on the first switch transistor. When applying a voltage to the pixel to make the display black level, and the video signal When the current corresponding to is supplied to the pixel, the second switch transistor is turned off, and the second switch transistor is turned off a plurality of times in one frame period. The display screen is formed in a strip shape and a plurality of non-display areas.

In addition, the EL display device according to the present invention corresponds to a plurality of gate signal lines and a plurality of source signal lines arranged so as to cross each other, and an intersection of the plurality of gate signal lines and the plurality of source signal lines. An active matrix EL display device having an image display region having pixels each having an EL element provided therein, a current output circuit for outputting a current corresponding to a video signal, and forcing a charge of the source signal line A precharge or discharge circuit for discharging or charging; a first gate driver circuit; and a second gate driver circuit. The pixel includes a driving transistor, and the first transistor supplies current to the EL element. A second switching transistor arranged in a signal path for supplying the driving transistor, the driving transistor, and the source signal line A first switching transistor disposed in a signal path between the first and second switching transistors, wherein the precharge or discharge circuit outputs a voltage for setting the display in the pixel to a black level to the pixel; A first gate signal line is connected to the gate terminal of the switch transistor, a second gate signal line is connected to the gate terminal of the second switch transistor, and the first gate driver circuit includes: The first switch transistor is controlled to turn on / off by controlling the first gate signal line, and the second gate driver circuit controls the second switch signal by controlling the second gate signal line. The transistor for on / off control, and applying a voltage to the pixel to make the display in the pixel black level, and to the video signal When supplying a corresponding current to the pixel, the second switching transistor is turned off, and a start pulse output to the second gate driver circuit based on video data output to the EL display device And the proportion of the image display area on the display screen is changed.

  In addition, the EL display device according to the present invention corresponds to a plurality of gate signal lines and a plurality of source signal lines arranged so as to cross each other, and an intersection of the plurality of gate signal lines and the plurality of source signal lines. An active matrix EL display device comprising an image display region having a pixel having an EL element provided therein, the driving transistor supplying a current to be supplied to the EL element in the pixel, and the driving in the pixel A first switching transistor disposed in a signal path between the driving transistor and the source signal line, and a second switching transistor disposed between the driving transistor and the EL element in the pixel. A current output circuit for outputting a current corresponding to the video signal, and forcibly discharging or discharging the charge of the source signal line. A precharge or discharge circuit for charging, a first gate signal line connected to the gate terminal of the first switch transistor, and a second gate connected to the gate terminal of the second switch transistor. A signal line is connected, and the first switch transistor and the second switch transistor can be independently controlled to be turned on / off, and the current of the current output circuit is supplied to the drive transistor; The precharge or discharge circuit is configured to flow when the switching transistor is turned on, and the precharge or discharge circuit outputs a voltage for setting the display in the pixel to a black level to the pixel, and sets the display in the pixel to a black level. When a voltage is applied to the pixel and a current corresponding to the video signal is When supplying to the element, the second switching transistor is turned off, and the current output circuit has a plurality of current mirror circuits formed on each source signal line, and selects the number of the current mirror circuits. As a result, current is output to the source signal line, and intermittent display is performed in one field or one frame period.

  In the EL display device according to the invention, the current output circuit includes a semiconductor chip whose output terminal is connected to the source signal line, and the precharge or discharge circuit is a substrate on which the image display region is formed. It is preferable to be formed.

  In the EL display device according to the present invention, each of the plurality of pixels is configured to display any one of the three primary colors R, G, and B, and the precharge or discharge circuit includes R It is preferable that the voltage can be changed so that at least one of the three primary colors G, B, and B is displayed on the pixel.

  Further, in the EL display device according to the above invention, the precharge or discharge circuit outputs a voltage for setting the display of the pixel to a black level in the first period of the horizontal scanning period, and the first circuit after the first period. In the period 2, it is preferable that the current output circuit performs a current program operation.

  Furthermore, in the EL display device according to the invention, the driving transistor is preferably a P-channel transistor.

The display panel, display device, and the like of the present invention exhibit distinctive effects according to their respective configurations such as high image quality, good moving image display performance, low power consumption, low cost, and high brightness.

  In addition, if the present invention is used, an information display device or the like with low power consumption can be configured, so that power is not consumed. Moreover, since it can be reduced in size and weight, resources are not consumed. Therefore, it is friendly to the global environment and space environment.

  In the present specification, each drawing includes parts that are omitted or enlarged or reduced for easy understanding or drawing. For example, in the cross-sectional view of the display panel in FIG. 5, the sealing film 73 and the like are illustrated to be sufficiently thick. In FIG. 6 and the like, a thin film transistor (TFT) for applying a signal to the pixel electrode is omitted. Further, in the display panel and the like of the present invention, a phase film for phase compensation is omitted, but it is desirable to add it in a timely manner. The same applies to the other drawings. Moreover, the part which attached | subjected the same number or code | symbol has the same material, function, or operation | movement.

  Note that the contents described in the drawings and the like can be combined with other embodiments and the like without particular notice. For example, a touch panel or the like may be added to the display panel of FIG. 6 to obtain an information display device as shown in FIGS. Further, a viewfinder (see FIG. 109) such as a video camera (see FIG. 74) can be configured by attaching a magnifying lens. In addition, the driving method of the present invention described with reference to FIGS. 29, 30, 40, 114, etc. can be applied to any of the display device and the display panel of the present invention. In addition, the present invention will be mainly described with respect to an active matrix display panel in which a TFT is formed in each pixel. However, the present invention is not limited to this and can be applied to a simple matrix display panel.

  As described above, the matters, contents, and specifications described in the specification and the drawings can be applied in combination with each other even if not particularly exemplified.

(Embodiment 1)
Currently, organic EL display panels configured by arranging a plurality of organic electroluminescence (EL) elements in a matrix form are attracting attention as display panels that have low power consumption and high display quality and can be made thinner. Yes.

  As shown in FIG. 2, the organic EL display panel has at least one organic EL layer composed of an electron transport layer, a light emitting layer, a hole transport layer, and the like on an array substrate 49 on which a transparent electrode as the pixel electrode 48 is formed. The layer 47 and the reflective film 46 are laminated. By applying a positive voltage to the anode (anode) of the transparent electrode (pixel electrode) 48 and a negative voltage to the cathode (cathode) of the reflective film 46 and applying a direct current therebetween, the organic EL layer 47 emits light. Thus, by using an organic compound that can be expected to have good light emission characteristics for the organic EL layer, the EL display panel can withstand practical use.

The cathode electrode, the anode electrode, or the reflective film may be configured by forming an optical interference film made of a dielectric multilayer film on the ITO electrode. The dielectric multilayer film is a multilayer film (dielectric mirror) in which a low refractive index dielectric film and a high refractive index dielectric film are alternately formed. This dielectric multilayer film has a function (filter effect) for improving the color tone of light emitted from the organic EL structure.

  A large current flows through the wirings 51 and 63 that supply current to the anode or the cathode. For example, when the screen size of the EL display device is 40 inches, a current of about 100 A flows. Therefore, the resistance values of these wirings must be made sufficiently low. In response to this problem, in the present invention, first, a wiring such as an anode is formed as a thin film. And the thickness of the conductor is thickly formed in this thin film wiring by the electrolytic plating technique. Further, as necessary, the wiring itself or a metal wiring made of copper thin is added to the wiring.

  In addition, in order to supply a large current to the anode or cathode wiring, a high voltage and small current power wiring is used from the current supply means to the vicinity of the anode wiring and the like, and a low voltage and high voltage using a DCDC converter or the like. The power is converted into current and supplied.

  For the reflective film 46, it is preferable to use a material having a small work function such as aluminum, magnesium, indium, copper, or an alloy thereof, particularly an Al-Li alloy. The transparent electrode (pixel electrode) 48 can be made of a conductive material having a high work function such as ITO (tin-doped indium oxide) or gold. In addition, when gold is used as an electrode material, the electrode is in a translucent state. ITO may be other materials such as IZO. The same applies to the pixel electrode.

  Note that when a thin film is deposited on the pixel electrode 48 or the like, an organic EL film may be formed in an argon atmosphere. Further, by forming a carbon film with a thickness of 20 nm or more and 50 nm or less on ITO as the pixel electrode 48, the stability of the interface is improved, and the light emission luminance and the light emission efficiency are also improved.

(Embodiment 2)
Hereinafter, in order to facilitate understanding of the EL display panel structure of the present invention, a method for manufacturing the organic EL display panel of the present invention will be described first.

  In order to improve heat dissipation, the array substrate 49 may be formed of sapphire glass. Alternatively, a thin film or a thick film having good thermal conductivity may be formed. For example, the use of a substrate on which a diamond thin film is formed is exemplified. Of course, a quartz glass substrate or a soda glass substrate may be used. In addition, a ceramic substrate such as alumina or a metal plate made of copper or the like may be used, or an insulating film coated with a metal film by vapor deposition or coating may be used. When the pixel electrode is of a reflective type, light is emitted from the surface direction of the substrate as the substrate material. Therefore, a transparent or translucent material such as glass, quartz or resin, or a non-transparent material such as stainless steel may be used. it can. This configuration is illustrated in FIG. In FIG. 5, the cathode electrode is formed of a transparent electrode 72 such as ITO.

  In the embodiment of the present invention, the cathode or the like is formed of a metal film. However, the present invention is not limited to this, and may be formed of a transparent film such as ITO or IZO. Thus, a transparent EL display panel can be configured by making both the anode and cathode electrodes of the EL element 15 transparent. That is, by increasing the transmittance to about 80% without using a metal film, it is possible to achieve a configuration in which the other side of the display panel can be almost seen through while displaying characters and pictures.

The array substrate 49 may be a plastic substrate. Plastic substrates are difficult to break and are lightweight, making them ideal as display panel substrates for mobile phones. The plastic substrate is preferably used as a laminated substrate by attaching an auxiliary substrate to one surface of a base substrate serving as a core material with an adhesive. Of course, these substrates are not limited to plates,
A film having a thickness of 0.05 mm or more and 0.3 mm or less may be used.

  As a material for the base substrate, an alicyclic polyolefin resin is preferably used. An example of such an alicyclic polyolefin resin is ARTON (single plate having a thickness of 200 μm) manufactured by Nippon Synthetic Rubber. From polyester resin, polyethylene resin or polyethersulfone resin, etc., on which one side of the base substrate is formed with a hard coat layer with heat resistance, solvent resistance or moisture permeability function, and a gas barrier layer with air permeability resistance function An auxiliary substrate (or film or membrane) is placed.

  Thus, when the array substrate 49 is made of plastic, the array substrate 49 is composed of the base substrate and the two auxiliary substrates. Therefore, the hard coat layer and the gas barrier are also formed on the other surface of the base substrate in the same manner as described above. An auxiliary substrate (or film or film) made of a polyethersulfone resin or the like on which a layer is formed is disposed. Note that the base substrate and the auxiliary substrate are attached to each other with an adhesive or a pressure-sensitive adhesive to form a laminated substrate.

  As the adhesive, it is preferable to use a UV (ultraviolet) curable acrylic resin, and it is preferable to use an acrylic resin having a fluorine group. In addition, an epoxy adhesive or pressure-sensitive adhesive may be used. The refractive index of the adhesive or pressure-sensitive adhesive is preferably 1.47 or more and 1.54 or less. In addition, it is preferable that the difference in refractive index with respect to the refractive index of the array substrate 49 is 0.03 or less. In particular, the adhesive is preferably added with a light diffusion material such as titanium oxide as described above to function as a light scattering layer.

  When bonding each auxiliary substrate to the base substrate, the angle formed by the optical slow axes of each auxiliary substrate is 45 degrees or more and 120 degrees or less, more preferably 80 degrees or more and 100 degrees or less (approximately 90 degrees). It is good to do. By setting it within this range, the retardation generated in the auxiliary substrate and the polyethersulfone resin as the auxiliary substrate can be completely canceled in the laminated substrate. Therefore, the organic EL display panel plastic substrate can be handled as an isotropic substrate having no phase difference.

  With this configuration, versatility is significantly increased as compared with a film substrate or a film laminated substrate having a phase difference. That is, it becomes possible to convert linearly polarized light into elliptically polarized light as designed by combining with a retardation film. If there is a phase difference in the array substrate 49 or the like, an error from the design value occurs due to this phase difference.

The hard coat layer in the auxiliary substrate can use an epoxy resin, a urethane resin, an acrylic resin, or the like as a material, and also serves as a first undercoat layer of a transparent conductive film having a stripe electrode or a pixel electrode. As the gas barrier layer, SiO ₂
Inorganic materials such as SiOx or organic materials such as polyvinyl alcohol and polyimide can be used. As an adhesive, an adhesive, etc., an epoxy adhesive or a polyester adhesive can be used in addition to the acrylic described above. In addition, although the thickness of an adhesive layer shall be 100 micrometers or less, in order to smooth the unevenness | corrugation of surfaces, such as a board | substrate, it is preferable to set it as 10 micrometers or more.

  Moreover, it is preferable to use a substrate having a thickness of 40 μm or more and 400 μm or less as the auxiliary substrate and the auxiliary substrate constituting the array substrate 49. In addition, by setting the thickness of each auxiliary substrate to 120 μm or less, unevenness or phase difference at the time of melt extrusion called a die line of polyethersulfone resin can be suppressed low, and the thickness is preferably 50 μm or more and 80 μm or less. And

Next, on this laminated substrate, SiOx is formed as an auxiliary undercoat layer of the transparent conductive film,
A transparent conductive film made of ITO to be a pixel electrode is formed by a sputtering technique. The transparent conductive film of the plastic substrate for an organic EL display panel manufactured as described above can realize a sheet resistance value of 25Ω / □ and a transmittance of 80% as its film characteristics.

  When the thickness of the base substrate is as thin as 50 μm to 100 μm, the organic EL display panel plastic substrate is curled by heat treatment in the manufacturing process of the organic EL display panel. In addition, cracks occur in the ITO that constitutes the striped electrode and the subsequent conveyance becomes impossible. Also, good results cannot be obtained in connection of circuit components. However, when the thickness of the base substrate is 200 μm or more and 500 μm or less with a single plate, the substrate is not deformed and has excellent smoothness, good transportability, and stable transparent conductive film characteristics. Also, connection of circuit components can be carried out without any problem. Furthermore, since it has moderate softness | flexibility and planarity, it is thought that it is good to make thickness into 250 micrometers or more and 450 micrometers or less.

  When an organic material such as the aforementioned plastic substrate is used as the array substrate 49, it is preferable to form a thin film made of an inorganic material as a barrier layer on the surface in contact with the liquid crystal layer. This barrier layer made of an inorganic material is preferably formed of the same material as the AIR coat. The sealing lid 41 can also be manufactured by the same technique or configuration as the array substrate 49.

Further, when the barrier layer is formed on the pixel electrode or the stripe electrode, it is preferable to use a low dielectric constant material in order to reduce the loss of the voltage applied to the light modulation layer as much as possible. For example, an amorphous carbon film (relative dielectric constant: 2.0 to 2.5) to which fluorine is added is exemplified. Other examples include the LKD series (LKD-T200 series (relative permittivity 2.5 to 2.7), LKD-T400 series (relative permittivity 2.0 to 2.2)) manufactured and sold by JSR. The The LKD series is a spin coating type based on MSQ (methy-silsesquioxane) and has a low dielectric constant of 2.0 to 2.7, which is preferable. In addition, organic materials such as polyimide, urethane, and acrylic, and inorganic materials such as SiNx and SiO ₂ may be used. There is no problem even if these barrier layer materials are used for the auxiliary substrate.

  By using the array substrate 49 or the sealing lid 41 formed of plastic, there is an advantage that it can be pressed, in addition to the advantages that it is not broken and can be reduced in weight. In other words, a substrate having an arbitrary shape can be produced by pressing or cutting (see FIG. 3). Further, it can be processed into an arbitrary shape and thickness by melting or chemical treatment. For example, a circular shape, a spherical shape (curved surface or the like), or a conical shape is exemplified. In addition, by pressing, at the same time as the manufacture of the substrate, the uneven portion 252 can be formed on one substrate surface, and the scattering surface can be formed or embossed.

  It is also easy to form a backlight or a cover substrate positioning pin into a hole in the array substrate 49 formed by pressing plastic. Further, an electric circuit such as a capacitor or a resistor formed by thick film technology or thin film technology may be formed in the array substrate 49 and the sealing lid 41. Further, a concave portion (not shown) is formed in the sealing lid 41, a convex portion 251 is formed on the array substrate 49, and the concave portion and the convex portion are formed so as to be fitted with each other. The array substrate 49 may be integrated so as to be integrated.

When a glass substrate is used, a bank used for depositing an EL element on the periphery of the pixel 16 is formed. The bank is formed in a convex shape with a thickness of 2 to 3 μm using a resin material. The bank (convex portion) 251 made of this resin can be produced simultaneously with the formation of the sealing lid 41 or the array substrate 49 by press working (see FIG. 3). This is a great effect generated by forming the sealing lid 41 and the array substrate 49 from resin. In this way, the manufacturing time can be shortened by forming the resin portion simultaneously with the substrate, so that the cost can be reduced. Also,
At the time of manufacturing the array substrate 49 or the like, the convex portions 251 are formed in a dot shape in the display region portion. The convex portion 251 is formed between adjacent pixels, thereby holding a predetermined space between the sealing lid 41 and the array substrate 49.

  In the above embodiment, the convex portion 251 that functions as a bank is formed. However, the present invention is not limited to this. For example, the pixel portion may be dug down (concave portion) by press working or the like. In addition to the formation of the concavo-convex portions 252 and the convex portions 251, a method of forming a concavo-convex portion by first forming a flat substrate and then pressing by reheating is included.

  Alternatively, a mosaic color filter may be formed by directly coloring the sealing lid 41 and the array substrate 49. The substrate is coated with a dye or pigment using a technique such as inkjet printing. After infiltration, drying may be performed at a high temperature, and the surface may be coated with a resin such as a UV resin, or an inorganic material such as silicon oxide or nitrogen oxide. Further, the color filter may be formed by a gravure printing technique, an offset printing technique, a semiconductor pattern forming technique in which a film is applied and developed with a spinner. In addition to the color filter, a black matrix (BM) having a complementary color relationship of black or dark color or light to be modulated may be directly formed by coloring using a similar technique. Further, a recess may be formed on the substrate surface so as to correspond to the pixel, and a color filter, BM, or TFT may be embedded in the recess. In particular, it is preferable to coat the surface with an acrylic resin. This configuration also has an advantage that the pixel electrode surface and the like are smoothed.

  Alternatively, the pixel electrode or the cathode electrode may be configured directly by conducting the resin on the substrate surface with a conductive polymer or the like. Furthermore, a configuration in which a large hole is formed in the substrate and an electronic component such as a capacitor is inserted into the hole is also exemplified. Thereby, the advantage that a board | substrate can be comprised thinly is exhibited.

  Moreover, you may form a pattern freely by cutting the surface of a board | substrate. Alternatively, the sealing lid 41 and the peripheral portion of the array substrate 49 may be melted. In the case of an organic EL display panel, the periphery of the substrate may be melted and sealed in order to prevent moisture from entering from the outside.

  As described above, by forming the substrate with a resin, it is easy to make a hole in the substrate. Further, the substrate shape can be freely configured by press working or the like.

  Further, in order to make the sealing lid 41 and the array substrate 49 usable as a multilayer circuit board or a double-sided substrate, a hole is formed in the sealing lid 41 and the array substrate 49, and a conductive resin or the like is filled in the hole, It is also possible to electrically connect the front and the back.

  The sealing lid 41 and the array substrate 49 itself may be a multilayer wiring board. For example, a conductive pin or the like can be inserted in place of the conductive resin, a terminal of an electronic component such as a capacitor can be inserted into the formed hole, or a circuit wiring, a capacitor, a coil, or a resistor is formed in the substrate. May be. Multi-layering is configured by bonding thin substrates, and at this time, one or more of the substrates (films) to be bonded may be colored.

  In addition, dyes and pigments can be added to the substrate material to color the substrate itself and to form a filter. Further, the serial number can be formed simultaneously with the production of the substrate. Further, by coloring only the part other than the display area, it is possible to prevent malfunctions by irradiating light on the mounted IC chip.

Also, half of the display area of the substrate can be colored in a different color. This may be achieved by applying resin plate processing techniques (injection processing, compression processing, etc.). In addition, by using the same processing technique, half of the display area can be made to have a different EL layer thickness. In addition, the display portion and the circuit portion can be formed at the same time. It is also easy to change the substrate thickness between the display area and the driver loading area.

  Further, microlenses can be formed on the sealing lid 41 or the array substrate 49 so as to correspond to the pixels or to correspond to the display area. Further, a diffraction grating may be formed by processing the sealing lid 41 and the array substrate 49. Further, by forming unevenness sufficiently finer than the pixel size, the viewing angle can be improved or the viewing angle can be made dependent. It is to be noted that such arbitrary-shaped processing and fine processing technology can be realized by a stamper technology for forming a microlens developed by OMRON Corporation.

  Striped electrodes (not shown) are formed on the sealing lid 41 and the array substrate 49. In addition, an antireflection film (AIR coat) is formed on the surface where the substrate comes into contact with air, and when other constituent materials such as a polarizing plate (polarizing film) are affixed, it is reflected on the surface of the constituent material. A prevention film (AIR coat) is formed. Further, when a polarizing plate or the like is not attached to the sealing lid 41 and the array substrate 49, an antireflection film (AIR coat) is directly formed on the sealing lid 41 and the array substrate 49.

  Although the above embodiment has been described mainly with respect to the sealing lid 41 and the array substrate 49 being formed of plastic, the present invention is not limited to this. For example, even if the sealing lid 41 and the array substrate 49 are a glass substrate or a metal substrate, the concavo-convex portions 252 and the convex portions 251 can be formed or configured by pressing, cutting, or the like. Moreover, it is not limited to a substrate. For example, a film or a sheet may be used.

  In addition, it is effective to form a thin film made of a fluororesin in order to prevent or suppress the adhesion of dust to the surface of the polarizing plate. In addition, a conductor film such as a thin film having a hydrophilic group, a conductive polymer film, or a metal film may be applied or deposited for preventing static electricity.

  In addition, the polarizing plate (polarizing film) disposed or formed on the light incident surface or the light emitting surface of the display panel 82 is not limited to linearly polarized light, and may be elliptically polarized light. Alternatively, a plurality of polarizing plates may be bonded together, or a polarizing plate and a retardation plate may be combined or bonded.

  As the main material constituting the polarizing film, a TAC film (triacetyl cellulose film) is optimal. This is because the TAC film has excellent optical properties, surface smoothness and processability. As for the production of the TAC film, it is optimal to produce it by a solution casting film forming technique.

The AIR coat is exemplified by a structure formed of a dielectric single layer film or a multilayer film.
In addition, a resin having a low refractive index of 1.35 to 1.45 may be applied. For example, a fluorine-type acrylic resin etc. are illustrated and a thing with a refractive index of 1.37 or more and 1.42 or less is especially good.

  The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide wavelength band of visible light, and this is called multi-coat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band, and this is called a V coat. Multi-coat and V-coat are used properly according to the use of the display panel. The AIR coat is not limited to two or more layers, and may be a single layer.

In the case of multi-coating, aluminum oxide (Al ₂ O ₃ ) has an optical film thickness of nd = λ / 4, zirconium (ZrO ₂ ) has nd1 = λ / 2, and magnesium fluoride (MgF ₂ ) has nd1 = λ / 4. It is formed by stacking. Usually, the thin film is formed as λ = 520 nm or a value in the vicinity thereof.

In the case of V coat, silicon monoxide (SiO) has an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF ₂ ) nd1 = λ / 4, or yttrium oxide (Y ₂ O ₃ ) and magnesium fluoride. (MgF ₂ ) is formed by stacking nd1 = λ / 4. Since SiO has an absorption band on the blue side, when modulating blue light, it is better to use Y ₂ O ₃ in view of the stability of the substance. It may also be used SiO ₂ thin film. Of course, a low refractive index resin or the like may be used for the AIR coating. For example, an acrylic resin such as fluorine is exemplified. These are preferably ultraviolet curable types.

  In order to prevent the display panel from being charged with static electricity, a hydrophilic resin is applied to the surface of a light guide plate such as a cover substrate or the display panel 82, or the substrate material such as the panel is made hydrophilic. Is preferably made of a good material. In addition, in order to prevent surface reflection, the surface of the polarizing plate 54 may be embossed.

  In each pixel, a plurality of switching elements or thin film transistors (TFTs) as current control elements are formed. The TFTs to be formed may be the same type of TFT, or may be different types of TFTs, such as P-channel type and N-channel type TFTs. Preferably, both the switching thin film transistor and the driving thin film transistor are used. Those of the same polarity are desirable. The structure of the TFT is not limited to that of a planar type TFT, and may be a staggered type or an inverted staggered type, or may have a impurity region (source, drain) formed using a self-alignment method. A non-self-alignment method may be used.

  The EL element 15 of the present invention has an EL structure in which ITO serving as a hole injection electrode (pixel electrode), one or more organic layers, and an electron injection electrode are sequentially stacked on an array substrate, The array substrate is provided with TFTs.

  In order to manufacture the EL device of the present invention, first, an array of TFTs is formed in a desired shape on a substrate. Then, ITO, which is a transparent electrode (pixel electrode) on the smoothing film, is formed and patterned by sputtering. Thereafter, an organic EL layer, an electron injection electrode, and the like are stacked.

  A normal polycrystalline silicon TFT may be used as the TFT. The TFT is provided at the end of each pixel of the EL structure, and has a size of about 10 to 30 μm. The size of the pixel at this time is about 20 μm × 20 μm to 300 μm × 300 μm.

A TFT wiring electrode is provided on the array substrate. The wiring electrode has low resistance,
In addition, the hole injection electrode is electrically connected to keep the resistance value low. Generally, the wiring electrode is made of Al, Al, transition metal (except for Ti), Ti or titanium nitride (TiN). However, in the present invention, the material is not limited to this material. The total thickness of the hole injection electrode serving as the foundation of the EL structure and the wiring electrode of the TFT is not particularly limited, but is usually about 100 to 1000 nm.

An insulating layer is provided between the wiring electrode of the TFT 11 and the organic layer of the EL structure. The insulating layer is formed by sputtering or vacuum deposition of an inorganic material such as silicon oxide such as SiO ₂ or silicon nitride, a silicon oxide layer formed by SOG (spin-on-glass), photoresist, polyimide, acrylic Any coating material may be used as long as it has insulating properties, such as a coating film made of a resin-based material such as a resin. Among them, polyimide is preferable. The insulating layer also serves as a corrosion / water resistant film that protects the wiring electrode from moisture and corrosion.

  There may be two or more emission peaks of the EL structure. For example, the green and blue light emitting portions in the EL element of the present invention can be obtained by a combination of a blue-green light emitting EL structure and a green transmission layer or a blue transmission layer. The red light-emitting portion can be obtained by an EL structure that emits blue-green light and a fluorescence conversion layer that converts blue-green light emitted from the EL structure to a wavelength close to red.

  Next, the EL structure constituting the EL element 15 of the present invention will be described. The EL structure of the present invention includes an electron injection electrode that is a transparent electrode, one or more organic layers, and a hole injection electrode. Each of the organic layers has at least one hole transport layer and a light emitting layer. For example, the organic layer sequentially includes an electron injection transport layer, a light emitting layer, a hole transport layer, and a hole injection layer. Note that the hole transport layer may be omitted. The organic layer of the EL structure of the present invention can have various configurations, and the electron injection / transport layer is omitted, or is integrated with the light emitting layer, or the hole injection transport layer and the light emitting layer are mixed. May be.

As a material for the hole injection electrode, since it has a structure for extracting light emitted from the hole injection electrode side, ITO (tin-doped indium oxide), IZO (zinc-doped indium oxide), ZnO, SnO ₂ , In ₂ O _3, etc. Among them, ITO and IZO are particularly preferable. The thickness of the hole injection electrode only needs to have a certain thickness or more that can sufficiently inject holes, and is preferably about 10 to 500 nm. In addition, the material for the hole injection electrode needs to have a low driving voltage in order to improve the reliability of the element, but a preferable example is ITO of 10 to 30Ω / □ (film thickness 50 to 300 nm). It is done. In actual use, the film thickness and optical constant of the electrode may be set so that the interference effect due to reflection at the hole injection electrode interface such as ITO sufficiently satisfies the light extraction efficiency and color purity. The hole injection electrode can be formed by vapor deposition or the like, but is preferably formed by sputtering. The sputtering gas is not particularly limited, and an inert gas such as Ar, He, Ne, Kr, or Xe, or a mixed gas thereof may be used.

  The electron injection electrode is made of a material using a metal, a compound or an alloy having a low work function formed by sputtering or the like, preferably by vapor deposition. For example, K, Li, Na, Mg, La, Ce, Ca, Sr, Ba, Al, Ag, In, Sn, Zn, Zr and other metal elements alone, or two components containing them to improve stability It is preferable to use a three-component alloy system. Examples of alloy systems include Ag · Mg (Ag: 1 to 20 at%), Al·Li (Li: 0.3 to 14 at%), In · Mg (Mg: 50 to 80 at%), Al · Ca (Ca: 5 to 20 at%) and the like are preferable. The thickness of the electron injection electrode thin film may be a certain thickness that can sufficiently inject electrons, and may be 0.1 nm or more, preferably 1 nm or more. Moreover, although there is no restriction | limiting in particular in the upper limit, Usually, a film thickness should just be about 100-500 nm.

  The hole injection layer has a function of facilitating injection of holes from the hole injection electrode, and the hole transport layer has a function of transporting holes and a function of blocking electrons. Also called transport layer.

  The electron injecting and transporting layer is provided when the electron injecting and transporting function of the compound used for the light emitting layer is not so high, and prevents the function of facilitating the injection of electrons from the electron injecting electrode, the function of transporting electrons and the holes. It has a function.

These hole injection layer, hole transport layer, and electron injection transport layer increase and seal the holes and electrons injected into the light emitting layer, optimize the recombination region, and improve the luminous efficiency. is there. Note that the electron injecting and transporting layer may be provided separately for the layer having an injection function and the layer having a transport function.

  The thickness of the light emitting layer, the combined thickness of the hole injecting layer and the hole transporting layer, and the thickness of the electron injecting and transporting layer are not particularly limited and vary depending on the forming method, but are usually about 5 to 100 nm. Is preferred.

  The thickness of the hole injection layer, the hole transport layer, and the thickness of the electron injection / transport layer depends on the design of the recombination / light emitting region, but if it is about the same as the thickness of the light emitting layer or about 1/10 to 10 times Good. The thicknesses of the hole injection layer, the hole transport layer, and the thickness in the case of separating the electron injection layer and the electron transport layer are preferably 1 nm or more for the injection layer and 20 nm or more for the transport layer. At this time, the upper limit of the thickness of the injection layer and the transport layer is usually about 100 nm for the injection layer and about 100 nm for the transport layer. Such a film thickness is the same when two injection transport layers are provided.

  In addition, by controlling the film thickness while considering the carrier mobility and carrier density (determined by the ionization potential and electron affinity) of the combined light-emitting layer, electron injection transport layer, and hole injection transport layer, the recombination region and light emission region Can be designed freely, and it is possible to design the emission color, control the emission luminance and emission spectrum by the interference effect of both electrodes, and control the spatial distribution of emission.

  The light emitting layer of the EL element 15 of the present invention contains a fluorescent material which is a compound having a light emitting function. Examples of the fluorescent substance include metal complex dyes such as tris (8-quinolinolato) aluminum (Alq3) as disclosed in Japanese Patent Laid-Open No. 63-264692, and Japanese Patent Laid-Open No. 6-11069 (phenyl). Anthracene derivatives), JP-A-6-114456 (tetraarylethene derivatives), JP-A-6-1000085, JP-A-2-247278, and the like are listed.

  The EL element 15 that emits blue light may use “DMPhen (Triphenylamine)” having an emission wavelength of about 400 nm as the material of the light emitting layer. At this time, for the purpose of increasing the light emission efficiency, it is preferable to employ a material in which the band gap is the same as that of the light emitting layer for the electron injection layer (Bathocupline) and the hole injection layer (m-MTDATXA). This is because when DMPhen having a large band gap of 3.4 eV is used in the light emitting layer, electrons stay in the electron injection layer and holes stay in the hole injection layer, so that recombination of electrons and holes in the light emitting layer occurs. It is hard to happen. The problem that a light emitting material having an amine group such as DMPhen is unstable in structure and difficult to extend the life can be solved by transferring energy excited in DMPhen to a dopant and emitting light from the dopant.

Luminous efficiency can be improved by using a phosphorescent material as the EL material.
The fluorescent material has an external quantum efficiency of about 2-3%. The fluorescent light emitting material has an internal quantum efficiency (efficiency at which the energy by excitation is changed to light) is 25%, whereas the phosphorescent light emitting material reaches nearly 100%, so that the external quantum efficiency is high.

  Further, CBP is preferably used as a host material for the light-emitting layer of the EL element. Here, red (R), green (G), and blue (B) phosphorescent materials are doped. All doped materials contain Ir. It is preferable to use Btp2Ir (acac) for the R material, (ppy) 2Ir (acac) for the G material, and FIrpic for the B material.

Examples of the hole injection layer / hole transport layer include, for example, JP-A 63-295695, JP-A 2-191694, JP-A 3-792 and JP-A-5-234681. Japanese Laid-Open Patent Publication No. 5-239455, Japanese Laid-Open Patent Publication No. 5-299174, Japanese Laid-Open Patent Publication No. 7-12622
Various organic compounds described in JP-A-5, JP-A-7-126226, JP-A-8-1000017, EP0650955A1, and the like can be used.

  In addition, it is preferable to use a vacuum evaporation method for forming these hole injecting and transporting layer, light emitting layer and electron injecting and transporting layer because a homogeneous thin film can be formed.

(Embodiment 3)
Hereinafter, the manufacturing method and structure of the EL display panel of the present invention will be described in more detail. As described above, first, the TFT 11 for driving the pixels is formed on the array substrate 49. One pixel is composed of 4 or 5 TFTs. Further, the pixel is current-programmed, and the programmed current is supplied to the EL element 15. Normally, the current programmed value is held in the capacitor 19 as a voltage value. The pixel configuration such as the combination of the TFTs 11 will be described later. Next, a pixel electrode 48 as a hole injection electrode is formed on the TFT 11. The pixel electrode 48 is patterned by photolithography. A light-shielding film is formed or disposed in the lower layer or the upper layer of the TFT 11 in order to prevent image quality deterioration due to a photoconductor phenomenon (hereinafter referred to as a photocon) that occurs when light enters the TFT 11.

  In order to form a TFT on a plastic substrate, the surface on which the organic semiconductor is formed may be processed to form an electronic thin film using pentacene molecules composed of carbon and hydrogen. This thin film has a size 20 to 100 times that of conventional crystal grains and has sufficient semiconductor properties suitable for electronic device manufacturing.

  Pentacene molecules tend to adhere to surface impurities when grown on a silicon substrate. This makes the growth irregular and results in crystal grains that are too small to produce a high quality device. In order to grow the crystal grains larger, it is preferable to apply a single layer “molecular buffer” of molecules called cyclohexene on a silicon substrate. This layer covers "sticky sites" on the silicon, creating a clean surface and growing pentacene molecules to very large grains. By applying and using such a new thin film of pentacene molecules with large crystal grains at a low temperature, flexible transistors can be mass-produced.

  Alternatively, a metal thin film serving as a gate may be formed on a substrate in an island shape, and an amorphous silicon film may be deposited or applied thereon, and then heated to form a semiconductor film. The semiconductor film is crystallized well in the island-shaped portion. Therefore, mobility becomes good.

If oxygen plasma or O ₂ asher is used at the time of cleaning, the smoothing film 71 around the pixel electrode 48 is also ashed simultaneously, and the periphery of the pixel electrode 48 is removed. In order to solve this problem, in the present invention, as shown in FIG. 4, an edge protection film 81 made of acrylic resin is formed around the pixel electrode 48. Examples of the constituent material of the edge protective film 81 include the same materials as organic materials such as an acrylic resin and a polyimide resin that constitute the smoothing film 71, and other inorganic materials such as SiO ₂ and SiNx, Al ₂ O ₃ Etc. are also exemplified.

  The edge protection film 81 is formed so as to fill the space between the pixel electrodes 48 after the patterning of the pixel electrodes 48. Of course, the edge protection film 81 may be formed to a height of 2 μm or more and 4 μm or less to serve as a bank of a metal mask (a spacer that prevents the metal mask from being in direct contact with the pixel electrode 48) when the organic EL material is separately applied. Needless to say.

As the vacuum deposition apparatus, an apparatus obtained by modifying a commercially available high vacuum deposition apparatus (manufactured by Nippon Vacuum Technology Co., Ltd., EBV-6DA type) is used. The main exhaust system is a turbo molecular pump (TC 1500, manufactured by Osaka Vacuum Co., Ltd.) with an exhaust speed of 1500 liters / min. The ultimate vacuum is about 1 × 10e ⁻⁶ Torr (Pa) or less, It is performed in the range of 3 × 10e ⁻⁶ Torr (Pa). All vapor deposition may be performed by connecting a DC power source (manufactured by Kikusui Electronics Co., Ltd., PAK10-70A) to a resistance heating vapor deposition boat made of tungsten.

  A carbon film of 20 to 50 nm is formed on the array substrate arranged in the vacuum layer in this way. Next, 4- (N, N-bis (p-methylphenyl) amino) -α-phenylstilbene is formed to a thickness of about 5 nm at a deposition rate of 0.3 nm / s as a hole injection layer.

  As a hole transport layer, N, N′-bis (4′-diphenylamino-4-biphenylyl) -N, N′-diphenylbenzidine (manufactured by Hodogaya Chemical Co., Ltd.) and 4-N, N-diphenylamino-α -Phenylstilbene is co-evaporated at a deposition rate of 0.3 nm / s and 0.01 nm / s, respectively, to form a film thickness of about 80 nm.

  As the light-emitting layer (electron transport layer), tris (8-quinolinolato) aluminum (manufactured by Dojin Chemical Co., Ltd.) is formed to a film thickness of about 40 nm at a deposition rate of 0.3 nm / s.

  Next, as an electron injection electrode, only Li at a low temperature from an Al-Li alloy (manufactured by High Purity Chemical Co., Ltd., Al / Li weight ratio 99/1) is deposited at a film thickness of about 1 nm at a deposition rate of about 0.1 nm / s. Then, the temperature of the Al-Li alloy is further raised, and from the state where Li is exhausted, only Al is formed at a deposition rate of about 1.5 nm / s to a film thickness of about 100 nm, and a stacked electron An injection electrode was obtained.

  The organic thin film EL device thus prepared leaks the inside of the vapor deposition tank with dry nitrogen, and then, in a dry nitrogen atmosphere, the sealing lid 41 made of Corning 7059 glass is used as the sealing agent 45 (trade name, manufactured by Anelva Corporation). : Super back seal 953-7000) to obtain a display panel. A desiccant 55 is disposed in the space between the sealing lid 41 and the array substrate 49. This is because the organic EL film is sensitive to humidity, so that moisture that permeates the sealant 45 is absorbed by the desiccant 55 to prevent the organic EL layer 47 from deteriorating.

In order to suppress the penetration of moisture from the sealing agent 45, it is a good measure to lengthen the path from the outside. For this reason, in the display panel of the present invention, fine concave portions 43 and convex portions 44 are formed in the peripheral portion of the display area. The convex portions 44 formed on the peripheral portion of the array substrate 49 are formed at least double. The distance between the protrusions (projection pitch) is preferably 100 μm or more and 500 μm or less, and the height of the protrusions is preferably 30 μm or more and 300 μm or less. This convex portion is formed by a stamper technique. For this stamper technology, the method used by Omron as a microlens forming method and the method used by Matsushita Electric as a microlens forming method with a CD pickup lens are applied.

  On the other hand, a recess 43 is also formed in the sealing lid 41. The formation pitch of the recesses 43 is the same as the formation pitch of the projections 44. In this way, by making the formation pitch the same, the convex portion 44 fits exactly into the concave portion 43, and no positional deviation occurs between the sealing lid 41 and the array substrate 49 during the manufacture of the display panel. A sealing agent 45 is disposed between the concave portion 43 and the convex portion 44. The sealing agent 45 adheres the sealing lid 41 and the array substrate 49 and prevents moisture from entering from the outside.

As the sealant 45, it is preferable to use a UV (ultraviolet) curable resin made of an acrylic resin, and it is preferable to use an acrylic resin having a fluorine group. In addition, an epoxy adhesive or pressure-sensitive adhesive may be used. The refractive index of the adhesive or pressure-sensitive adhesive is 1.
47 or more and 1.54 or less are preferably used. In particular, as the sealing adhesive, fine powder of titanium oxide, fine powder of silicon oxide or the like is added at a ratio of 65% to 95% by weight, and the average particle diameter of the fine powder is 20 μm to 100 μm. It is preferable. This is because the effect of suppressing the entry of humidity from the outside increases as the weight ratio of the fine powder increases. However, if the amount is too large, bubbles or the like are likely to enter, and on the contrary, the space becomes larger and the sealing effect is lowered.

  The weight of the desiccant is desirably 0.04 g or more and 0.2 g or less, particularly 0.06 g or more and 0.15 g or less per 10 mm of the seal length. This is because when the amount of the desiccant is too small, the moisture prevention effect is reduced and the organic EL layer is immediately deteriorated. On the other hand, if the amount is too large, the desiccant becomes an obstacle when sealing, and good sealing cannot be performed.

  Although it is the structure sealed using the glass sealing lid 41 in FIG. 2, the sealing using a film may be sufficient as FIG. For example, as the sealing film, it is exemplified that a film of an electrolytic capacitor on which DLC (diamond-like carbon) is deposited is used. Since this film has extremely poor moisture permeability (moisture resistance), it can be used as the sealing film 73. Moreover, the structure which vapor-deposits a DLC film directly on the surface of the transparent electrode 72 may be sufficient. The thickness of the thin film is calculated by n · d (where n is the refractive index of the thin film, and when a plurality of thin films are stacked, the refractive indexes thereof are combined (calculating n · d of each thin film). When the plurality of thin films are laminated, their refractive indexes are calculated together.) Is preferably equal to or less than the emission main wavelength λ of the EL element 15. By satisfying this condition, the light extraction efficiency from the EL element 15 becomes twice or more as compared with the case of sealing with a glass substrate. Further, an alloy or a mixture or a laminate of aluminum and silver may be formed.

  Half of the light generated from the organic EL layer 47 is reflected by the reflective film 46 and is transmitted through the array substrate 49 and emitted. However, since the reflective film 46 reflects external light, reflection occurs, and the display contrast is lowered. For this measure, a λ / 4 plate 50 and a polarizing plate 54 are arranged on the array substrate 49. When the pixel is a reflective electrode, the light generated from the organic EL layer 47 is emitted upward. Therefore, the λ / 4 plate 50 and the polarizing plate 54 must be disposed on the light emitting side. The reflective pixel is obtained by forming the pixel electrode 48 from aluminum, chromium, silver or the like. Further, by providing the surface of the pixel electrode 48 with projections (or projections and depressions), the interface with the organic EL layer 47 is widened, the emission area is increased, and the emission efficiency is improved.

  One or a plurality of phase films (phase plate, phase rotation means, phase difference plate, phase difference film) are disposed between the array substrate 49 and the polarizing plate (polarizing film) 54. Polycarbonate is preferably used as the phase film. This phase film generates a phase difference between incident light and outgoing light, and contributes to efficient light modulation.

  In addition, as the phase film, an organic resin plate or an organic resin film such as a polyester resin, a PVA resin, a polysulfone resin, a vinyl chloride resin, a ZEONEX resin, an acrylic resin, or a polystyrene resin may be used. In addition, crystals such as quartz may be used. The phase difference of one phase plate is preferably 50 nm to 350 nm, more preferably 80 nm to 220 nm in a uniaxial direction.

  As shown in FIG. 5, a circularly polarizing plate 74 (circularly polarizing film) in which a phase film and a polarizing plate are integrated may be used.

The λ / 4 plate (phase film) 50 is preferably colored with a dye or a pigment to have a function as a color filter. In particular, since the organic EL layer has poor red (R) purity, the colored λ / 4 plate 50 cuts a certain wavelength range to adjust the color temperature. The color filter is generally provided with a pigment dispersion type resin as a dyeing filter, and the pigment absorbs light in a specific wavelength band and transmits light in a wavelength band not absorbed.

  As described above, a part or the whole of the phase film may be colored, or a part or the whole may have a diffusion function. Further, the surface may be embossed or an antireflection film may be formed to prevent reflection. In addition, it is preferable to form a light-shielding film or a light absorption film at a location that is not effective or unhindered for image display so as to increase the black level of the display image or to exhibit a contrast enhancement effect by preventing halation. Further, by forming irregularities on the surface of the phase film, microlenses may be formed in a kamaboko shape or a matrix shape. The microlenses are arranged so as to correspond to one pixel electrode or three primary color pixels, respectively.

  As described above, since the phase difference can be generated by rolling or photopolymerization when forming the color filter, the color filter may have the function of the phase film. In addition, the phase difference may be given by photopolymerizing the smoothing film 71 of FIG. If comprised in this way, it will become unnecessary to comprise or arrange | position a phase film outside a board | substrate, the structure of a display panel will also become simple and cost reduction can be expected. The above matters can be applied to the polarizing plate 54.

  The polarizing plate 54 is exemplified by a resin film obtained by adding iodine or the like to polyvinyl alcohol (PVA) resin. The polarizing plates of the pair of polarization separation means perform polarization separation by absorbing a polarized light component in a direction different from a specific polarization axis direction in incident light, so that light use efficiency is relatively poor. Therefore, a reflective polarizer that performs polarization separation by reflecting a polarized component (reflective polarizer) in a direction different from a specific polarization axis direction of incident light may be used. If comprised in this way, the utilization efficiency of light will increase with a reflective polarizer, and a brighter display will be attained rather than the above-mentioned example using a polarizing plate.

  In addition to such polarizing plates and reflective polarizers, the polarization separation means of the present invention is a combination of a cholesteric liquid crystal layer and a (1/4) λ plate, and reflective polarization using the Brewster angle. It is also possible to use a polarization beam splitter (PBS), etc.

  Although not shown in FIG. 2, the surface of the polarizing plate 54 is provided with an AIR coat.

  Although the TFT is connected to the pixel electrode 48, the present invention is not limited to this. In the active matrix, as a switching element, in addition to a thin film transistor (TFT), a diode system (TFD), a varistor, a thyristor, a ring diode, a photodiode, a phototransistor, an FET, a MOS transistor, a PLZT element, and the like are possible. That is, any of those constituting the switching element and the driving element can be used.

  In addition, it is preferable that the TFT adopts an LDD (lightly doped drain) structure. Note that TFT means all elements that perform transistor operations such as switching, such as FETs. Further, the structure of the EL film, the panel structure, and the like can be applied to a simple matrix display panel. In this specification, an organic EL element (OEL, PEL, PLED, OLED) is described as an example of the EL element, but the present invention is not limited to this, and the present invention is also applicable to an inorganic EL element.

There are two active matrix methods used for organic EL display panels: (1) a specific pixel can be selected and necessary display information can be given, and (2) current can flow through the EL element over one frame period. The condition must be met.

  In order to satisfy these two conditions, in the conventional organic EL element configuration shown in FIG. 115, the first TFT 11a is a switching thin film transistor for selecting a pixel, and the second TFT 11b is for supplying current to the EL element 15. Driving thin film transistor.

  Here, compared with the active matrix system used for the liquid crystal, the switching TFT 11a is necessary for the liquid crystal, but the driving TFT 11b is necessary for lighting the EL element 15. This is because in the case of liquid crystal, the on state can be maintained by applying a voltage, but in the case of the EL element 15, the lighting state of the pixel 16 cannot be maintained unless a current is continuously supplied.

  Therefore, in order to keep the current flowing in the organic EL display panel, the driving TFT 11b must be kept on. First, when both the scanning line and the data line are turned on, charges are accumulated in the capacitor 19 through the switching TFT 11a. Since the capacitor 19 continues to apply a voltage to the gate of the driving TFT 11b, the current continues to flow from the current supply line 20 even when the switching TFT 11a is turned off, and the pixel 16 can be turned on for one frame period.

  When displaying gradation using this configuration, it is necessary to apply a voltage corresponding to the gradation as the gate voltage of the driving TFT 11b. Therefore, the variation in the on-current of the driving TFT 11b appears in the display as it is.

  The on-current of a transistor is extremely uniform if it is a single crystal transistor, but in a low-temperature polycrystalline transistor formed by low-temperature polysilicon technology with a formation temperature of 450 degrees or less that can be formed on an inexpensive glass substrate. Since the threshold value varies in a range of ± 0.2 V to 0.5 V, the on-current flowing through the driving TFT 11b varies correspondingly, and display unevenness occurs. These irregularities are caused not only by variations in the threshold voltage but also by the mobility of the TFT and the thickness of the gate insulating film. The characteristics also change due to the deterioration of the TFT 11.

  Therefore, in the method of displaying gradation in an analog manner, it is necessary to strictly control the device characteristics in order to obtain a uniform display. In the current low-temperature polycrystalline polysilicon TFT, this variation is suppressed within a predetermined range. I can not meet the specifications.

  In order to solve this problem, there are four transistors in one pixel, and a method of obtaining a uniform current by compensating for variations in threshold voltage with a capacitor, or a constant current circuit for each pixel to make the current uniform A method for achieving this can be considered.

  However, in these methods, since the programmed current is made through the EL element 15, the transistor that controls the drive current becomes a source follower to the switching transistor connected to the power supply line when the current path changes, and the drive margin Becomes narrower. Therefore, there is a problem that the drive voltage becomes high.

  In addition, it is necessary to use a switching transistor connected to a power source in a low impedance region, and there is a problem that this operation range is affected by fluctuations in characteristics of the EL element 15. In addition, when the kink current occurs in the voltage-current characteristics in the saturation region, or when the threshold voltage of the transistor varies, there is a problem that the stored current value varies.

  In the EL element structure of the present invention, the TFT 11 that controls the current flowing through the EL element 15 does not have a source follower configuration and the influence of the kink current is minimized even if the transistor has a kink current. In this configuration, the variation of the stored current value can be reduced.

  Specifically, as shown in FIG. 6A, the EL element structure of the present invention is formed by a plurality of TFTs 11 and EL elements 15 each having at least four unit pixels. Note that the pixel electrode is configured to overlap the source signal line. That is, an insulating film or a smoothing film made of an acrylic material is formed on the source signal line 18 for insulation, and a pixel electrode is formed on the insulating film. The configuration in which the pixel electrode is overlaid on the source signal line 18 in this way is called a high aperture (HA) structure.

  By making the first gate signal line (first scanning line) 17a active (ON voltage applied), the first TFT (or switching element) 11a and the third TFT (or switching element) 11c are passed through. The second TFT 11b activates the first gate signal line 17a (applies an ON voltage) so that a current value to be passed through the EL element 15 is passed and the gate and drain of the first TFT 11a are short-circuited. The gate voltage (or drain voltage) of the first TFT 11a is stored so that the current value flows through the capacitor 19 connected between the gate and source of the first TFT 11a.

  Note that the capacitor 19 that is the source-gate capacitance of the first TFT 11a is preferably set to have a capacitance of 0.2 pF or more. As another configuration, there is an example in which the capacitor 19 is separately formed. That is, this is a configuration in which a storage capacitor is formed from the capacitor electrode layer, the gate insulating film, and the gate metal. From the standpoint of preventing luminance reduction due to leakage of the M3 transistor 11c and stabilizing the display operation, it is preferable to form a separate capacitor in this way. The size of the capacitor 19 is preferably 0.2 pF or more and 2 pF or less, and more preferably 0.4 pF or more and 1.2 pF or less.

  The capacitor 19 is preferably formed in a non-display area between adjacent pixels. Generally, when creating a full-color organic EL layer, since the organic EL layer is formed by mask vapor deposition using a metal mask, there is a risk that the position of the organic EL layer is shifted and the organic EL layers of the respective colors overlap. There is. Therefore, the non-display area between adjacent pixels of each color must be separated by 10 μm or more, and this part does not contribute to light emission. Therefore, forming the capacitor 19 in this region is an effective means for improving the aperture ratio.

  Next, the first gate signal line 17a is inactive (OFF voltage is applied), the second gate signal line 17b is active, and the current flow path is connected to the first TFT 11a and the EL element 15. 4 is switched to a path including the TFT 11 d and the EL element 15, and the stored current is supplied to the EL element 15.

  This circuit has four TFTs 11 in one pixel, the gate of the first transistor M1 is connected to the source of the second transistor M2, and the gates of the second transistor M2 and the third transistor M3. Are connected to the first gate signal line 17a, the drain of the second transistor M2 is connected to the source of the third transistor M3 and the source of the fourth transistor M4, and the drain of the third transistor M3 is connected to the source signal line 18. It is connected. The gate of the fourth transistor M4 is connected to the second gate signal line 17b, and the drain of the fourth transistor M4 is connected to the anode electrode of the EL element 15.

In FIG. 6, all TFTs are configured by P-channel. P channel is somewhat
Although mobility is lower than that of an N-channel TFT, it is preferable because it has a high breakdown voltage and is unlikely to deteriorate. However, the present invention is not limited to the EL element configuration configured by the P channel. You may comprise only N channel (refer FIG.70, FIG.71, FIG.75 etc.), and you may comprise using both N channel and P channel.

  The third and fourth transistors are preferably configured with the same polarity and configured with an N channel, and the first and second transistors are preferably configured with a P channel. In general, P-channel transistors have features such as higher reliability and less kink current compared to N-channel transistors. For EL elements that obtain the desired light emission intensity by controlling the current. If the first TFT 11a is a P channel, the effect is increased.

(Embodiment 4)
Hereinafter, the EL element configuration of the present invention will be described with reference to FIG. The EL device configuration of the present invention is controlled by two timings. The first timing is a timing for storing a necessary current value. When the TFT 11b and the TFT 11c are turned on at this timing, an equivalent circuit is shown in FIG. Here, a predetermined current I1 is written from the signal line, the TFT 11a is connected to the gate and the drain, and the current I1 flows through the TFT 11a and the TFT 11c. Therefore, the voltage between the gate and the source of the TFT 11a becomes V1 so that the current I1 flows.

  The second timing is a timing at which the TFT 11b and the TFT 11c are closed and the TFT 11d is opened, and the equivalent circuit at that time is shown in FIG. 7B. In this case, since the TFT 11a of M1 always operates in the saturation region, the current I1 becomes constant, and the voltage V1 between the source and gate of the TFT 11a remains held.

  The gate of the TFT 11b and the gate of the TFT 11c are connected to the same gate signal line 17a. However, the gate of the TFT 11b and the gate of the TFT 11c may be connected to different gate signal lines 17b (so that SA1 and SA2 can be individually controlled). That is, there are three gate signal lines for one pixel (the configuration in FIG. 6 is two). By individually controlling the ON / OFF timing of the gate of the TFT 11a and the ON / OFF timing of the gate of the TFT 11c, the current value variation of the EL element 15 due to the variation of the TFT 11 can be further reduced.

  When the first gate signal line 17a and the second gate signal line 17b are made common and the third and fourth transistors have different conductivity types (N channel and P channel), the driving circuit is simplified, and the pixel The aperture ratio can be improved. With this configuration, the write path from the signal line is turned off as the operation timing of the present invention. That is, when a predetermined current is stored, if there is a branch in the current flow path, an accurate current value is not stored in the source-gate capacitance (capacitor) of M1. The third transistor M3 and the fourth transistor M4 have different conductivity types, and by controlling the threshold values of each other, the M4 can be turned on after the M3 is always turned off at the switching timing of the scanning lines. However, in this case, attention must be paid to the process because it is necessary to accurately control each other's threshold values.

Although the circuit described above can be realized with at least four transistors, the TFT 11e (M5) is configured as shown in FIG. 6B to control the timing more accurately or to reduce the mirror effect as will be described later. The operation principle is the same even if the total number of transistors is 4 or more by cascade connection. As described above, by adding the TFT 11e, the current programmed through the third transistor M3 can be supplied to the EL element 15 with higher accuracy.

  In the configuration of FIG. 6, it is more preferable that the current value Ids in the saturation region of the first TFT 11a satisfies the following formula. In the following expression, the value of λ satisfies the condition of 0.01 or more and 0.06 or less between adjacent pixels.

Ids = k * (Vgs−Vth) ² (1 + Vds * λ)
In the present invention, the operating range of the TFT 11a is limited to the saturation region, but generally the transistor characteristics in the saturation region deviate from the ideal characteristics and are affected by the source-drain voltage (mirror effect).

Consider a case where a threshold value shift of ΔVt occurs in each TFT 11a in an adjacent pixel. In this case, the stored current values are the same. If the threshold shift is ΔL, approximately ΔV × λ corresponds to a shift in the current value of the EL element 15 due to a change in the threshold of the TFT 11a. Therefore, in order to suppress the current deviation to x (%) or less, λ must be 0.01 × x / y or less, where y (V) is the threshold shift allowable amount between adjacent pixels. I understand. This tolerance varies depending on the brightness of the application. In luminance region of the luminance up to ^{100cd / m 2 ~1000cd / m 2} , human if the amount of variation is 2% or more recognizes boundaries varied. Therefore, it is necessary that the variation amount of the luminance (current amount) is within 2%. When the luminance is higher than 100 cd / cm ² , the luminance change amount of adjacent pixels is 2% or more. When the EL display element of the present invention is used as a display for a portable terminal, the required luminance is about 100 cd / m ² . Actually, when the pixel configuration of FIG. 6 was prototyped and the fluctuation of the threshold was measured, it was found that the maximum value of the fluctuation of the threshold was 0.3 V in the TFT 11a of the adjacent pixel. Therefore, λ must be 0.06 or less in order to keep the luminance variation within 2%. However, since humans cannot recognize the change, it is not necessary to make it 0.01 or less. Further, in order to achieve this variation in threshold value, it is necessary to make the transistor size sufficiently large, which is unrealistic.

  Further, it is preferable that the current value Ids in the saturation region of the first TFT 11a satisfies the following formula. Note that the variation of λ is 1% or more and 5% or less between adjacent pixels.

Ids = k * (Vgs−Vth) ² (1 + Vds * λ)
Even if there is no change in threshold between adjacent pixels, if there is a change in λ in the above equation, the value of the current flowing through the EL element will change. In order to suppress the fluctuation within ± 2%, the fluctuation of λ must be suppressed to ± 5%. However, since humans cannot recognize changes, it is not necessary to make it 1% or less. In order to achieve 1% or less, the transistor size needs to be considerably increased, which is unrealistic.

  Further, according to experiments, array trial manufacture, and examination, it is preferable that the channel length of the first TFT 11a is 10 μm or more and 200 μm or less, and further 15 μm or more and 150 μm or less. This is considered to be because when the channel length L is increased, the electric field is relaxed by increasing the grain boundaries contained in the channel, and the kink effect is suppressed to a low level.

  Further, the TFT 11 constituting the pixel is formed of a polysilicon TFT formed by a laser recrystallization method (laser annealing), and the channel direction in all transistors is the same direction as the laser irradiation direction. Is preferred.

An object of the present invention is to propose a circuit configuration in which variations in transistor characteristics do not affect display. For this purpose, four or more transistors are required. When determining circuit constants based on these transistor characteristics, it is difficult to obtain appropriate circuit constants if the characteristics of the four transistors are not aligned. When the channel direction is horizontal and vertical with respect to the major axis direction of laser irradiation, the threshold value and mobility of transistor characteristics are different. In both cases, the degree of variation is the same. Since the mobility and the average value of the threshold values are different between the horizontal direction and the vertical direction, it is desirable that the channel directions of all the transistors constituting the pixel are the same.

  Further, when the capacitance value of the capacitor 19 is Cs (pF) and the off-current value of the second TFT 11b is Ioff (pA), it is preferable that the following equation is satisfied.

3 <Cs / Ioff <24
More preferably, it is preferable to satisfy the following formula.

6 <Cs / Ioff <18
By setting the off-state current of the TFT 11b to 5 pA or less, it is possible to suppress the change in the current value flowing through the EL element to 2% or less. This is because when the leakage current increases, the electric charge stored between the gate and the source (both ends of the capacitor) cannot be held for one field in the voltage non-writing state. Therefore, if the storage capacity of the capacitor 19 is large, the allowable amount of off-current is also large. By satisfying the above equation, the fluctuation of the current value between adjacent pixels can be suppressed to 2% or less.

  In addition, it is preferable that the transistor constituting the active matrix is a p-ch polysilicon thin film transistor and the TFT 11b has a multi-gate structure having a dual gate structure or more. Since the TFT 11b functions as a switch between the source and the drain of the TFT 11a, a characteristic having a high ON / OFF ratio is required as much as possible. In order to satisfy this requirement, a high ON / OFF ratio characteristic can be realized by making the gate structure of the TFT 11b a multi-gate structure.

The transistors constituting the active matrix are formed of polysilicon thin film transistors, and it is preferable that the (channel width W) * (channel length L) of each transistor be 54 μm ² or less. There is a correlation between (channel width W) * (channel length L) and variations in transistor characteristics. The cause of variations in transistor characteristics is often caused by variations in energy due to laser irradiation, and in order to absorb this, the laser irradiation pitch (generally a few tens of μm) is increased as much as possible in the channel. It is desirable to have a structure that includes it. Therefore, by setting the (channel width W) * (channel length L) of each transistor to 54 μm ² or less, a thin film transistor with uniform characteristics can be obtained without variations due to laser irradiation. If the transistor size becomes too small, characteristic variations due to area occur. Therefore, the (channel width W) * (channel length L) of each transistor is 9 μm ² or more, and further, 16 μm ² or more and 45 μm ² or less. It is preferable to do.

  Further, it is preferable that the mobility variation of the first TFT 11a in adjacent unit pixels is 20% or less. This is because the charging capability of the switching transistor is deteriorated due to insufficient mobility, and the capacity between the gate and the source of the first transistor M1 cannot be charged before a necessary current value is passed in time. Therefore, by suppressing the variation in movement to within 20%, it is possible to reduce the luminance variation between pixels below the recognition limit.

  As described above, FIG. 6 is described as a pixel configuration, but these can also be applied to the configurations illustrated in FIGS. 8 and 9. Hereinafter, the pixel configuration in FIG. 8 and the like will be described.

  When setting the current to flow to the EL element 15, the signal current to flow to the conversion TFT 11a is set to Iw, and as a result, the gate-source voltage generated in the conversion TFT 11a is set to Vgs. At the time of writing, since the gate and drain of the conversion TFT 11a are short-circuited by the TFT 11d, the conversion TFT 11a operates in the saturation region. Therefore, the signal current Iw is given by the following equation.

(Equation 1) Iw = μ1 · Cox1 · W1 / L1 / 2 (Vgs−Vth1) ²
Here, Cox is a gate capacitance per unit area, and is given by Cox = ε0 · εr / d. Vth is the TFT threshold, μ is the carrier mobility, W is the channel width, L is the channel length, ε0 is the vacuum mobility, εr is the relative dielectric constant of the gate insulating film, and d is the thickness of the gate insulating film. is there.

  Assuming that the current flowing through the EL element 15 is Idd, the current level of Idd is controlled by the driving TFT 11 b connected in series with the EL element 15. In the present invention, since the voltage between the gate and the source coincides with Vgs in the equation (1), the following equation is established if it is assumed that the driving TFT 11b operates in the saturation region.

(Equation 2) Idrv = μ 2 · Cox 2 · W 2 / L 2/2 (Vgs−Vth 2) ²
The conditions for an insulated gate field effect thin film transistor (TFT) to operate in the saturation region are generally given by the following equation, where Vds is the drain-source voltage.

(Equation 3) | Vds |> | Vgs−Vth |
Here, since the conversion TFT 11a and the driving TFT 11b are formed close to the inside of a small pixel, they are generally μ1 = μ2 and Cox1 = Cox2, and it is considered that Vth1 = Vth2 unless particularly devised. Then, at this time, the following formula is easily derived from the formula (1) and the formula (2).

(Formula 4) Idrv / Iw = (W2 / L2) / (W1 / L1)
The point to be noted here is that in the equations (1) and (2), the values of μ, Cox, and Vth themselves usually vary from pixel to pixel, from product to product, or from production lot to production lot. Since the equation (4) does not include these parameters, the value of Idrv / Iw does not depend on these variations. If W1 = W2 and L1 = L2 are designed, Idrv / Iw = 1, that is, Iw and Idrv have the same value, and the drive current Idd flowing through the EL element 15 is accurate regardless of variations in TFT characteristics. Since it becomes the same as the signal current Iw, the light emission luminance of the EL element 15 can be accurately controlled as a result.

  As described above, since the threshold value Vth1 of the conversion TFT 11a and the threshold value Vth2 of the driving TFT 11b are basically the same, when a signal voltage having a cut-off level is applied to the gate at a common potential in both TFTs, Both the conversion TFT 11a and the driving TFT 11b should be non-conductive. However, in practice, Vth2 may be lower than Vth1 due to factors such as parameter variations within the pixel. At this time, since a sub-threshold level leakage current flows through the driving TFT 11b, the EL element 15 emits slight light emission. This slight light emission reduces the contrast of the screen and impairs display characteristics.

  In the present invention, in particular, the threshold voltage Vth2 of the driving TFT 11b is set not to be lower than the threshold voltage Vth1 of the corresponding conversion TFT 11a in the pixel. For example, the gate length L2 of the driving TFT 11b is made longer than the gate length L1 of the conversion TFT 11a so that Vth2 does not become lower than Vth1 even if the process parameters of these thin film transistors fluctuate. Leakage can be suppressed. The above matters also apply to the relationship between the conversion TFT 11a and the TFT 11d in FIG.

  As shown in FIG. 8, the pixel circuit is controlled by controlling the first scanning line scanA (SA) in addition to the driving TFT 11b for controlling the driving current flowing in the light emitting element including the conversion TFT 11a and the EL element 15 through which the signal current flows. Of the conversion TFT 11a, the switching TFT 11d for short-circuiting between the gate and the drain of the conversion TFT 11a during the writing period by the control of the second scanning line scanB (SB). It comprises a capacitor 19 for holding the gate-source voltage even after the writing is completed, an EL element 15 as a light emitting element, and the like. As described above, since the gate signal line is two pixels, the configuration, function, operation, and the like of the entire specification of the present invention based on FIG. 6 described above can be applied.

  Although the TFT 11c in FIG. 8 is composed of an N-channel MOS (NMOS) and the other transistors are composed of a P-channel MOS (PMOS), this is an example, and this is not necessarily the case. One terminal of the capacitor 19 is connected to the gate of the conversion TFT 11a and the other terminal is connected to Vdd (power supply potential). However, the capacitor 19 is not limited to Vdd, and may be any constant potential. The cathode (cathode) of the EL element 15 is connected to the ground potential. Therefore, it goes without saying that the above items also apply to FIG.

  The configuration of FIG. 8 includes data including a scanning line driving circuit that sequentially selects the scanning lines scanA and scanB, and a current source CS that generates a signal current Iw having a current level corresponding to luminance information and sequentially supplies the signal current Iw to the data line data. A line driving circuit; and a plurality of pixels including current-driven EL elements 15 that are arranged at intersections of the scanning lines scanA and scanB and the data lines data and emit light upon receiving a driving current. .

  As a feature, the pixel configuration shown in FIG. 8 includes a receiving unit (specifically, a capturing TFT 11c) that captures a signal current Iw from the data line data when the scanning line scanA is selected. A conversion unit that once converts the current level of the captured signal current Iw into a voltage level and holds it, and a driving current having a current level corresponding to the held voltage level, corresponding to the light-emitting element OLED (EL, OEL, PEL and PLED).

  The conversion unit includes a conversion TFT 11a having a gate, a source, a drain, and a channel, and a capacitor 19 connected to the gate. The conversion TFT 11a and the signal current Iw taken in by the receiving unit are passed through the channel to generate a converted voltage level at the gate, and the voltage level generated in the capacitor 19 is held.

  The converter includes a switching TFT 11d inserted between the drain and gate of the conversion TFT 11a. The switching TFT 11d becomes conductive when the current level of the signal current Iw is converted to a voltage level, and the drain and gate of the conversion TFT 11a are electrically connected to generate a voltage level based on the source at the gate of the conversion TFT 11a. Close. The switching TFT 11d is cut off when the voltage level is held in the capacitor 19, and the gate of the conversion TFT 11a and the capacitor 19 connected thereto are separated from the drain of the conversion TFT 11a.

  The driving unit includes a driving TFT 11b having a gate, a drain, a source, and a channel. The driving TFT 11b receives the voltage level held in the capacitor 19 at the gate, and a driving current having a current level corresponding to the voltage level flows to the EL element 15 through the channel. The gate of the conversion TFT 11a and the gate of the driving TFT 11b are directly connected to form a current mirror circuit so that the current level of the signal current Iw and the current level of the driving current are in a proportional relationship.

  The driving TFT 11b operates in a saturation region, and a driving current corresponding to the difference between the voltage level applied to its gate and the threshold voltage is supplied to the EL element 15.

  The driving TFT 11b is set so that its threshold voltage does not become lower than the threshold voltage of the corresponding conversion TFT 11a in the pixel. Specifically, the driving TFT 11b is set so that its gate length is not shorter than the gate length of the conversion TFT 11a. Alternatively, the driving TFT 11b may be set so that the gate insulating film thereof is not thinner than the gate insulating film of the corresponding conversion TFT 11a in the pixel.

  Further, the driving TFT 11b may be set so that the threshold voltage does not become lower than the threshold voltage of the corresponding conversion TFT 11a in the pixel by adjusting the concentration of impurities injected into the channel. If the threshold voltages of the conversion TFT 11a and the driving TFT 11b are set to be the same, when the signal voltage of the cut-off level is applied to the gates of both of the commonly connected thin film transistors, the conversion TFT 11a and the driving TFT 11b Should both be off. However, in reality, there are slight variations in process parameters within the pixel, and the threshold voltage of the driving TFT 11b may be lower than the threshold voltage of the conversion TFT 11a.

  At this time, since the weak current of the sub-threshold level flows to the driving TFT 11b even with a signal voltage equal to or lower than the cut-off level, the EL element 15 emits light slightly and the contrast of the screen appears. Therefore, the gate length of the driving TFT 11b is made longer than the gate length of the conversion TFT 11a. Thereby, even if the process parameter of the thin film transistor varies within the pixel, the threshold voltage of the driving TFT 11b does not become lower than the threshold voltage of the conversion TFT 11a.

  In the short channel effect region A where the gate length L is relatively short, the TFT threshold Vth increases as the gate length L increases. On the other hand, in the suppression region B where the gate length L is relatively large, regardless of the gate length L, the threshold value Vth of the TFT is substantially constant. Using this characteristic, the gate length of the driving TFT 11b is made longer than the gate length of the conversion TFT 11a. For example, when the gate length of the conversion TFT 11a is 7 μm, the gate length of the drive TFT 11b is set to about 10 μm.

  The gate length of the conversion TFT 11a may belong to the short channel effect region A, while the gate length of the drive TFT 11b may belong to the suppression region B. Thereby, the short channel effect in the driving TFT 11b can be suppressed, and the threshold voltage reduction due to the process parameter variation can be suppressed. As described above, the sub-threshold level leakage current flowing through the driving TFT 11b can be suppressed, so that the light emission of the EL element 15 can be suppressed and the contrast can be improved.

  A method for driving the pixel circuit shown in FIG. 8 will be briefly described. First, at the time of writing, the first scanning line scanA and the second scanning line scanB are selected. By connecting the current source CS to the data line data in a state where both scanning lines are selected, the signal current Iw corresponding to the luminance information flows through the conversion TFT 11a. The current source CS is a variable current source that is controlled according to luminance information. At this time, since the gate and the drain of the conversion TFT 11a are electrically short-circuited by the switching TFT 11d, Expression (3) is established, and the conversion TFT 11a operates in the saturation region. Therefore, a voltage Vgs given by the equation (1) is generated between the gate and the source.

Next, the first scanning line scanA and the second scanning line scanB are brought into a non-selected state. More specifically, first, the second scanning line scanB is set to a low level to turn off the switching TFT 11d.
State. As a result, the voltage Vgs is held by the capacitor 19. Next, the pixel circuit and the data line data are electrically disconnected by setting the first scanning line scanA to a high level to be in the off state, and thereafter, the pixel line and the data line data are electrically disconnected from each other. Can write. Here, the data output as the current level of the signal current by the current source CS is valid at the time when the second scanning line scanB is not selected, but after that any level (for example, writing of the next pixel) Data).

  The driving TFT 11b has a gate and a source connected in common with the conversion TFT 11a, and is formed close to the inside of a small pixel. Therefore, if the driving TFT 11b operates in the saturation region, the driving TFT 11b The flowing current is given by the equation (2), that is, the driving current Idd flowing through the EL element 15. In order to operate the driving TFT 11b in the saturation region, a sufficient power supply potential may be applied to the Vdd voltage so that the formula (3) is satisfied even when the voltage drop in the EL element 15 is taken into consideration.

  As in FIG. 6B and the like, TFTs 11e and 11f may be added as shown in FIG. 9 for the purpose of increasing the impedance and the like, thereby realizing better current driving. . Since other matters have been described with reference to FIG.

A DC voltage was applied to the EL display device described in FIGS. 6 and 8 and so on, and the device was continuously driven at a constant current density of 10 mA / cm ² . In the EL structure, 7.0V,
Light emission of 200 cd / cm ² in green (emission maximum wavelength λmax = 460 nm) was confirmed.
In the blue light emitting part, the luminance is 100 cd / cm ² and the color coordinates are x = 0.129 and y = 0.105.
In the green light emitting part, the luminance is 200 cd / cm ² and the color coordinates are x = 0.340, y = 0.62.
5. In the red light emitting part, the luminance is 100 cd / cm ² and the color coordinates are x = 0.649, y = 0.3.
38 luminescent colors were obtained.

(Embodiment 5)
Hereinafter, a display device, a display module, an information display device, a driving circuit, a driving method, and the like using FIGS. 6, 8, and 9 will be described.

In full-color organic EL display panels, improvement of the aperture ratio is an important development issue.
This is because increasing the aperture ratio increases the light utilization efficiency, leading to higher brightness and longer life. In order to increase the aperture ratio, the area of the TFT that blocks light from the organic EL layer may be reduced. A low-temperature polycrystalline Si-TFT has a performance 10 to 100 times that of amorphous silicon, and further has a high current supply capability, so that the size of the TFT can be very small. Therefore, in the organic EL display panel, it is preferable that the pixel transistor and the peripheral drive circuit are manufactured by a low temperature polysilicon technique. Of course, it may be formed by amorphous silicon technology, but the pixel aperture ratio becomes considerably small.

  By forming a driving circuit such as the gate driver 12 or the source driver 14 on the array substrate 49, it is possible to reduce a resistance that is particularly problematic in a current-driven organic EL display panel. That is, the connection resistance of TCP is eliminated, and the lead-out line from the electrode is shortened by 2 to 3 mm as compared with the case of TCP connection, and the wiring resistance is reduced. Furthermore, there is an advantage that the process for TCP connection is eliminated and the material cost is reduced.

(Embodiment 6)
Next, the EL display panel or EL display device of the present invention will be described. FIG. 10 is an explanatory diagram focusing on the circuit of the EL display device. Pixels 16 are arranged or formed in a matrix. Each pixel 16 is connected to a source driver 14 that outputs a current for current programming of each pixel. A current mirror circuit corresponding to the number of bits of the video signal is formed at the output stage of the source driver 14. For example, in the case of 64 gradations, 63 current mirror circuits are formed for each source signal line, and a desired current can be applied to the source signal line 18 by selecting the number of these current mirror circuits. It is configured. Note that the minimum output current of one current mirror circuit is preferably 10 nA to 50 nA, particularly 15 nA to 35 nA. This is to ensure the accuracy of the transistors constituting the current mirror circuit in the source driver 14.

  A precharge or discharge circuit for forcibly releasing or charging the source signal line 18 is incorporated. The voltage (current) output value of this circuit is preferably configured so that it can be set independently for R, G, and B because the threshold values of the EL elements 15 are different for RGB.

  As described above, it goes without saying that the pixel configuration, array configuration, panel configuration, and the like described so far are applied to the configuration, method, and apparatus described later.

It is known that an organic EL element has a large temperature dependency characteristic (temperature characteristic).
In order to adjust the light emission luminance change due to the temperature characteristics, a non-linear element such as a thermistor or a posistor that changes the output current is added to the current mirror circuit, and the temperature characteristics change is adjusted by the thermistor as an analog reference. Create a current. In this case, since it is uniquely determined by the EL material to be selected, there is often no need for a microcomputer or the like for software control. That is, it may be fixed to a certain shift amount or the like by a liquid crystal material. What is important is that the temperature characteristics differ depending on the luminescent color material, and it is necessary to perform optimum temperature characteristics compensation for each luminescent color.

  Alternatively, temperature compensation may be performed by a microcomputer. The temperature of the EL display panel is measured with a temperature sensor, and is changed by a microcomputer (not shown) or the like according to the measured temperature. Further, the reference current or the like may be automatically switched by microcomputer control or the like at the time of switching, or control may be performed so that a specific menu can be displayed. Moreover, it may be configured to be switched by using a mouse or the like, or by switching the display screen of the EL display device to a touch panel and displaying a menu and pressing a specific portion.

  In the present invention, the source driver 14 is formed of a semiconductor silicon chip, and is connected to the terminal of the source signal line 18 of the array substrate 49 by a glass-on-chip (COG) technique. For wiring of signal lines such as the source signal line 18, metal wiring such as chromium, aluminum, and silver is used. This is because a low resistance wiring with a narrow wiring width can be obtained. Since the process can be simplified when the pixel is of a reflective type, the metal wiring is preferably formed simultaneously with the reflective film by using a material constituting the reflective film of the pixel.

  The present invention is not limited to the COG technology, and the above-described source driver 14 and the like may be mounted on the chip-on-film (COF) technology and connected to the signal line of the display panel. Further, the source driver 14 may have a three-chip configuration by separately manufacturing the power supply IC 102.

A TCF tape may be used. A film for TCF tape can be thermocompression bonded without using an adhesive to a polyimide film and a copper (Cu) foil. In addition to the film for TCP tape, in addition to this, a method of casting a melted polyimide on a Cu foil and a method of casting Cu on a metal film formed by sputtering on a polyimide film by plating or vapor deposition There is. Any of these methods may be used, but a method using a TCP tape for attaching Cu to a polyimide film without using an adhesive is most preferable. For the lead pitch of 30 μm or less, a Cu-laminated laminate without using an adhesive is used. Among the methods for forming a Cu-clad laminate without using an adhesive, a method of forming a Cu layer by plating or vapor deposition is suitable for thinning the Cu layer, which is advantageous for miniaturization of the lead pitch.

  On the other hand, the gate driver 12 is formed by the same process as the TFT of the pixel by a low temperature polysilicon technology. This is because the internal structure is easier and the operating frequency is lower than that of the source driver 14. Therefore, it can be formed easily even by low-temperature polysilicon technology, and a narrow frame can be realized. Of course, the gate driver 12 may be formed of a silicon chip and mounted on the array substrate 49 using COG technology or the like. In addition, switching elements such as pixel TFTs, gate drivers, and the like may be formed by high-temperature polysilicon technology or may be formed by an organic material (organic TFT).

  The gate driver 12 includes a shift register 22a for the gate signal line 17a and a shift register 22b for the gate signal line 17b. Each shift register 22 is controlled by positive and negative phase clock signals (CLKxP, CLKxN) and a start pulse (STx). In addition, it is preferable to add an enable (ENABL) signal for controlling the output and non-output of the gate signal line and an up / down (UPDWM) signal for reversing the shift direction up and down. In addition, it is preferable to provide an output terminal for confirming that the start pulse is shifted to the shift register and output. Note that the shift timing of the shift register is controlled by a signal from a control IC (not shown). A level shift circuit for performing level shift of external data and an inspection circuit are incorporated.

  Since the buffer capacity of the shift register 22 is small, the gate signal line 17 cannot be driven directly. Therefore, at least two or more inverter circuits 23 are formed between the output of the shift register 22 and the output gate 24 that drives the gate signal line 17.

  The same applies to the case where the source driver 14 is formed directly on the array substrate 49 by polysilicon technology such as low-temperature polysilicon, and between the gate of an analog switch such as a transfer gate that drives the source signal line and the shift register 22 of the source driver. A plurality of inverter circuits 23 are formed. The following items (the output of the shift register and the output stage that drives the signal line (related to the inverter circuit arranged between the output stages such as the output gate or transfer gate)) are common to the source driver and the gate driver circuit. 10, for example, the output of the source driver 14 is shown as being directly connected to the source signal line 18, but in reality, a multistage inverter circuit 23 is connected to the output of the shift register 22 of the source driver. The output of the inverter circuit is connected to the gate of an analog switch such as a transfer gate.

  The inverter circuit 23 includes a P-channel MOS transistor and an N-channel MOS transistor. As described above, the inverter circuit 23 is connected in multiple stages to the output terminal of the shift register 22 of the gate driver 12, and its final output is connected to the output gate 24. Note that the inverter circuit 23 may be composed of only the P channel. However, in this case, it may be configured as a simple gate circuit instead of an inverter circuit.

  An inverter close to a cyst register, where the channel width of the P-channel or N-channel TFT constituting each inverter circuit 23 is W and the channel length is L (in the case of a double gate or more, the width or channel length of the constituting channel is added). Is 1 and the order of the inverter near the display side is N (Nth stage).

If the number of connected stages of the inverter circuit 23 is large, characteristic differences of the connected inverter circuits 23 are multiplexed (stacked), and a difference occurs in transmission time from the shift register 22 to the output gate 24 (delay time variation). For example, in an extreme case, the output gate 24 in FIG.
Although a is turned on after 1.0 μsec (starting after the pulse is output from the shift register) (the output voltage is switched), the output gate 24 b is 1.5 μsec later (the pulse is output from the shift register). From the beginning) (the output voltage is switched).

  Therefore, the number of inverter circuits 23 formed between the shift register 22 and the output gate 24 should be small, but the gate width W of the TFT channel constituting the output gate 24 should be very large. Further, since the gate drive capability of the output stage of the cyst register 22 is small, it is impossible to drive the output gate 24 directly by a gate circuit (such as a NAND circuit) constituting the shift register. Therefore, it is necessary to connect the inverters in multiple stages. For example, the size of W4 / L4 (channel width of P channel / channel length of P channel) of the inverter circuit 23d in FIG. 10 and the size of W3 / L3 of the inverter circuit 23c. If the ratio is large, the delay time becomes long, and the characteristics of the inverter also vary greatly.

  FIG. 11 shows the relationship between delay time variation (dotted line) and delay time ratio (solid line). The horizontal axis is indicated by (Wn-1 / Ln-1) / (Wn / Ln). For example, in FIG. 10, if the channel length L of the inverter circuit 23d and the inverter circuit 23c is the same and 2W3 = W4, (W3 / L3) / (W4 / L4) = 0.5. In the graph of FIG. 11, the delay time ratio is 1 when (Wn−1 / Ln−1) / (Wn / Ln) = 0.5, and the time variation is 1 as well as the delay.

  FIG. 11 shows that as (Wn−1 / Ln−1) / (Wn / Ln) increases, the number of connection stages of the inverter circuit 23 increases and the delay time variation also increases. Further, it is shown that the delay time from the inverter circuit 23 to the inverter circuit 23 at the next stage becomes longer as (Wn−1 / Ln−1) / (Wn / Ln) becomes smaller. From this graph, it can be seen that it is advantageous in design that the delay time ratio and the delay time variation are within two. Therefore, what is necessary is just to satisfy the conditions of following Formula.

0.25 ≦ (Wn−1 / Ln−1) / (Wn / Ln) ≦ 0.75
The P channel W / L ratio (Wp / Lp) and the N channel W / L ratio (Ws / Ls) of each inverter circuit 23 must satisfy the following relationship.

0.4 ≦ (Ws / Ls) / (Wp / Lp) ≦ 0.8
Furthermore, the number n of stages of the inverter circuit 23 formed between the output terminal of the shift register and the output gate (or transfer gate) satisfies the following equation, and therefore, the variation in delay time is small and good.

3 ≦ n ≦ 8
Mobility μ also has challenges. When the mobility μn of the N-channel transistor is small, the sizes of the TG and the inverter are increased, and the power consumption and the like are increased. In addition, the driver formation area increases and the panel size also increases. On the other hand, if the mobility μn is large, the characteristics of the transistor are likely to be deteriorated. Therefore, the mobility μn is preferably in the following range.

50 ≦ μn ≦ 150
The slew rate of the clock signal in the shift register 22 is set to 500 V / μsec or less. This is because when the slew rate is high, the N-channel transistor is severely deteriorated.

In FIG. 10, the inverter circuit 23 is connected in multiple stages to the output of the shift register, but a NAND circuit may be used. This is because an inverter can also be configured with a NAND circuit. That is, the number of connection stages of the inverter circuit 23 may be considered as the number of gate connection stages. Also in this case, the relationship such as the W / L ratio described so far is applied. In addition, the items described with reference to FIGS. 10 and 11 also apply to FIGS. 46, 47, 49, and the like.

  Further, in FIG. 10 and the like, when the switching transistor of the pixel is a P channel, the output from the final stage inverter is the on voltage Vgl applied to the gate signal line 17 and the off voltage Vgh applied to the gate signal line 17. . Conversely, when the pixel switching transistor is N-channel, the output from the final stage inverter is applied with the off voltage Vgh applied to the gate signal line 17 and the on voltage Vgl applied to the gate signal line 17.

  In the above embodiment, the gate driver is manufactured at the same time as the pixel 16 using high-temperature polysilicon or low-temperature polysilicon technology. However, the present invention is not limited to this. For example, as shown in FIG. 12, a source driver 14 and a gate driver 12 made of a semiconductor chip may be separately stacked on the display panel 82.

  When the display panel 82 is used for an information display device such as a mobile phone, the source driver 14 and the gate driver 12 are preferably mounted on one side of the display panel as shown in FIG. The configuration in which the driver IC is mounted on the display area is referred to as a three-side free configuration (structure), where the gate driver 12 is mounted on the X side of the display area and the source driver 14 is mounted on the Y side). This is because it is easy to design the center line of the display screen 21 to be the center of the display device, and it is easy to mount the driver IC. Note that the gate driver circuit may be manufactured as a three-side free configuration using high-temperature polysilicon or low-temperature polysilicon technology (that is, at least one of the source driver 14 and the gate driver 12 in FIG. 12 is polysilicon). Directly formed on the array substrate 49 by a technique).

  The three-side free configuration is not only a configuration in which an IC is directly stacked or formed on the array substrate 49, but also a film (TCP, TAB technology, etc.) with the source driver 14 and the gate driver 12 attached to one side of the array substrate 49. Also includes a configuration attached to (or almost one side). In other words, this means all configurations, arrangements, or the like in which no IC is mounted or attached on two sides.

  As shown in FIG. 12, when the gate driver 12 is disposed beside the source driver 14, the gate signal line 17 needs to be formed up to the display screen 21 along the C side (see FIG. 13 and the like).

  Note that the pitch of the gate signal lines 17 formed on the C side is 5 μm or more and 12 μm or less. This is because if it is less than 5 μm, noise will be applied to the adjacent gate signal line due to the influence of parasitic capacitance. According to the experiment, the influence of the parasitic capacitance is remarkably generated at 7 μm or less, and when it is less than 5 μm, image noise such as a beat is generated on the display screen. In particular, the occurrence of noise differs between the left and right sides of the screen, and it is difficult to reduce image noise such as a beat. On the other hand, if the reduction exceeds 12 μm, the frame width D of the display panel becomes too large to be practical.

  In order to reduce the image noise described above, a grant pattern (a conductive pattern whose voltage is fixed to a constant voltage or set to a stable potential as a whole) is disposed in the lower layer or upper layer of the portion where the gate signal line 17 is formed. Can be reduced. Further, a separately provided shield plate (shield foil (conductive pattern fixed to a constant voltage or set to a stable potential as a whole)) may be disposed on the gate signal line 17.

The gate signal line 17 on the C side in FIG. 13 may be formed of an ITO electrode. However, in order to reduce the resistance, it is preferable that the ITO and the metal thin film are laminated or formed of a metal film. When laminating with ITO, a titanium film is formed on ITO, and an aluminum or aluminum / molybdenum alloy thin film is formed thereon. Alternatively, a chromium film is formed on ITO. In the case of a metal film, it is formed of an aluminum thin film or a chromium thin film. The above matters are the same in other embodiments of the present invention.

  In FIG. 14, the source driver 14 and the gate driver 12 are integrated into one chip (one-chip driver IC 14a). If one chip is used, only one IC chip needs to be mounted on the display panel 82. Therefore, the mounting cost can be reduced. Various voltages used in the one-chip driver IC 14a can be generated simultaneously.

  The source driver 14, the gate driver 12, and the one-chip driver IC 14a are made of a semiconductor wafer such as silicon and mounted on the display panel 82. However, the present invention is not limited to this, and the low-temperature polysilicon technology and the high-temperature polysilicon technology are used. May be formed directly on the display panel 82.

  In FIG. 15, the gate drivers 12a and 12b are mounted (or formed) on both ends of the source driver 14, but the present invention is not limited to this. For example, as shown in FIG. 12, one gate driver 12 may be arranged on one side adjacent to the source driver 14. In FIG. 15 and the like, a portion indicated by a thick solid line indicates a portion where the gate signal lines 17 are formed in parallel. Therefore, the gate signal lines 17 corresponding to the number of scanning signal lines are formed in parallel in the portion b (lower screen), and one gate signal line 17 is formed in the portion a (upper screen).

  As shown in FIG. 15, when two gate drivers 12a and 12b are used, the number of gate signal lines 17a formed in parallel with the side C in FIG. 15 becomes 1/2 of the number of scanning lines (on the left and right sides of the screen). This is because half the number of gate signal lines can be arranged). Therefore, the frame has a feature that it is uniform on the left and right of the screen.

The present invention is also characterized by the scanning direction of the gate signal line 17 and the screen division. For example,
In FIG. 15, the gate driver 12a is connected to the gate signal line 17b at the top of the screen. The gate driver 12b is connected to the gate signal line 17a at the bottom of the screen. The scanning direction of the gate signal line 17 is also from the top to the bottom of the screen as indicated by the arrow A. The source signal line 18 is common to the upper part of the screen and the lower part of the screen.

  In FIG. 16, the gate driver 12a is connected differently from the adjacent gate signal line 17 at the top of the screen. The gate driver 12a is connected to the odd-numbered gate signal line 17b. The gate driver 12b is connected to the even-numbered gate signal line 17a. The scanning direction of the gate signal line is the direction from the top to the bottom of the screen (arrow A). The gate signal line 17a is from the bottom to the top of the screen (arrow B). In this way, by connecting the gate signal line 17 to the gate driver 12 and by setting the scanning method of the gate signal line to a predetermined direction, the display screen 21 is not inclined in luminance and flicker is also generated. Can be suppressed. The source signal line 18 is common to the upper part of the screen and the lower part of the screen. However, it goes without saying that it may be divided at the top and bottom of the screen. The above matters also apply to other embodiments.

In FIG. 14, which is made into one chip, the gate driver 12a is connected to the gate signal line 17b at the top of the screen. The gate driver 12b is connected to the gate signal line 17a at the bottom of the screen. As indicated by the arrow A, the scanning direction of the gate signal line 17b is from the top to the bottom of the screen. As indicated by an arrow B, the scanning direction of the gate signal line 17a is from the bottom to the top of the screen. The source signal line 18 is common to the upper part of the screen and the lower part of the screen. In this way, by connecting the gate signal line 17 to the gate driver 12 and by setting the scanning method of the gate signal line to a predetermined direction, the display screen 21 is not inclined in luminance and flicker is also generated. Can be suppressed.

The one-chip driver IC 14a is made of a semiconductor wafer such as silicon,
Although it is mounted on the display panel 82, the present invention is not limited to this. The display panel 82 may be directly formed on the display panel 82 by a low-temperature polysilicon technique or a high-temperature polysilicon technique. In addition, a driver IC that drives the upper part of the screen may be arranged on the upper side of the display screen, and a driver IC that drives the lower part of the screen may be arranged on the lower side of the display screen (that is, the mounted IC has two chips). The above matters also apply to other embodiments of the present invention.

  In FIGS. 14 and 15, the screen is expressed as being divided at the center, but the present invention is not limited to this. For example, in the case of FIG. 15, the display screen 21a may be reduced and the display screen 21b may be increased. This display screen 21a is used as a partial display area (see FIG. 17), and mainly displays time and date and is used in the low power consumption mode. 14 and 15, the display screen 21a is displayed by the gate signal line 17b, and the display screen 21b is displayed by the gate signal line 17a.

  Further, in FIG. 17 and the like, as shown in FIG. 18, the display screen 21a may have a three-side free configuration, and the display screen 21b may have a configuration in which the conventional source driver 14 and the gate driver 12 are arranged on separate sides. . That is, the gate signal line 17a and the source signal line 18a are output from the one-chip driver IC 14a.

  Further, as shown in FIG. 19, the display screen 21 may be divided into two screens 21a and 21b, and the source driver 14 and the gate driver 12 corresponding to each screen may be arranged. In FIG. 19, since the writing time of the video signal output from each source driver 14 is doubled compared to the other embodiments, the signal can be sufficiently written to the pixel. In addition, as shown in FIG. 20, the display screen 21 may be one, and the source drivers 14 may be arranged one by one above and below the screen. This can be similarly applied to the gate driver 12.

  In the embodiment described above, the gate signal lines 17 are formed in parallel and wired up to the pixel region. However, the present invention is not limited to this. As shown in FIG. Needless to say, the wiring may be arranged parallel to the side.

  In FIG. 17, FIG. 18, FIG. 19, etc., changing the frame rate (the driving frequency or the number of screen rewrites per unit time (one second)) on the display screens 21a and 21b is also an effective means for reducing power consumption. It is. Further, changing the number of display colors or the display colors on the display screens 21a and 21b is also effective for reducing power consumption.

  In the configuration illustrated in FIG. 6, the cathode of the EL element 15 is connected to the Vs1 potential. However, there is a problem that the driving voltage of the organic EL constituting each color is different. For example, when a current of 0.01 A is applied per unit square centimeter, the terminal voltage of the EL element is 5 V in blue (B), but 9 V in green (G) and red (R). That is, the terminal voltage differs between B, G, and R. Therefore, the source / drain voltages (SD voltage) of the TFTs 11c and 11d held by B, G and R are different, and the off-leak current between the source-drain voltages (SD voltage) of the transistors is different for each color. When off-leakage current is generated and the off-leakage characteristic is different for each color, flickering occurs when the color balance is shifted, and the gamma characteristic is shifted in correlation with the emission color.

In order to cope with this problem, in the present invention, as shown in FIG. 22, the potential of one cathode electrode of at least R, G, and B colors is made different from the potential of the cathode electrode of the other color. Yes. Specifically, in FIG. 22, B is a cathode electrode 53a, and G and R are cathode electrodes 53b.

  The cathode electrode 53a is formed using a metal mask technique in which organic EL of each color is separately applied. The metal mask is used because organic EL is weak to water and cannot be etched. Using a metal mask (not shown), a cathode electrode 53a is deposited and simultaneously connected to the contact hole 52a. The contact hole 52a can be electrically connected to the B cathode wiring 51a.

  Similarly, the cathode electrode 53b is formed using a metal mask technique in which organic ELs of different colors are separately applied. Using a metal mask (not shown), a cathode electrode 53b is deposited and simultaneously connected to the contact hole 52b. The contact hole 52b can be electrically connected to the RG cathode wiring 51b. Note that the aluminum film thickness of the cathode electrode is preferably 70 nm to 200 nm.

  With the above configuration, different voltages can be applied to the cathode electrodes 53a and 53b. Therefore, even if the Vdd voltage in FIG. 6 is common to each color, the voltage applied to at least one color EL element of RGB is set. Can be changed. In FIG. 22, the same cathode electrode 53b is used for RG, but the present invention is not limited to this, and different cathode electrodes may be used for R and G.

  With the configuration described above, it is possible to prevent the occurrence of an off-leakage current between the source-drain voltage (SD voltage) of the transistor and the kink phenomenon in each color. Therefore, no flicker occurs, and a good image display can be realized without a gamma characteristic being shifted in correlation with the emission color.

  Further, Vs1 in FIG. 6 is set as the cathode voltage, and the cathode voltage is made different for each color. However, the present invention is not limited to this, and the anode voltage Vdd may be made different for each color. For example, the V pixel voltage of the R pixel may be 8V, G may be 6V, and B may be 10V. These anode voltage and cathode voltage are preferably configured to be adjustable within a range of ± 1V.

  Even when the panel size is about 2 inches, a current of nearly 100 mA is output from the anode connected to the Vdd voltage. Therefore, it is essential to reduce the resistance of the anode wiring (current supply line) 20. In order to deal with this problem, in the present invention, as shown in FIG. 18, the anode wiring 63 is supplied from the upper side and the lower side of the display area (both ends feeding). By supplying power at both ends as described above, the occurrence of a luminance gradient at the top and bottom of the screen is eliminated.

  In order to increase the light emission luminance, the pixel electrode 48 is preferably roughened. This configuration is shown in FIG. First, fine irregularities are formed at a location where the pixel electrode 48 is to be formed using a stamper technique. When the pixel is a reflection type, the pixel electrode 48 is formed by forming a metal thin film of about 200 nm of aluminum by sputtering. A convex portion is provided at a location where the pixel electrode 48 is in contact with the organic EL, and the surface is roughened. In the case of a simple matrix display panel, the image electrode 48 is a striped electrode. Moreover, a convex part is not limited only to convex shape, A concave shape may be sufficient. Moreover, you may form a concave and a convex simultaneously.

The size of the protrusion is about 4 μm in diameter, and the average distance between adjacent points is 10 μm, 20 μm
40 μm, and the unit area density of the protrusions is 1000 to 1200 pieces / mm ² , respectively.
When the luminance was measured at 100 to 120 pieces / mm ² and 600 to 800 pieces / mm ² , it was found that the emission luminance increased as the unit area density of the protrusions increased. Therefore, it was found that by changing the unit area density of the protrusions on the pixel electrode 48, the light emission luminance can be adjusted by changing the surface state of the pixel electrode. According to the examination, the unit area density of the protrusions is 100 / mm ^2.
A favorable result was able to be obtained by setting it above 800 pieces / mm < ² > or more.

  Organic EL is a self-luminous element. When light emitted by this light emission enters a TFT as a switching element, a photoconductor phenomenon (photoconversion) occurs. “Photocon” refers to a phenomenon in which leakage (off leakage) increases when a switching element such as a TFT is turned off by photoexcitation.

  In order to deal with this problem, in the present invention, as shown in FIG. 24, a light shielding film 91 is formed below the gate driver 12 (or the source driver 14 in some cases) and below the pixel TFT 11. The light shielding film 91 is formed of a metal thin film such as chromium, and the film thickness is 50 nm or more and 150 nm or less. This is because if the film thickness is thin, the light-shielding effect is poor, and if it is thick, unevenness is generated, making it difficult to pattern the upper TFT 11.

  A smoothing film 71a made of an inorganic material having a thickness of 20 nm to 100 nm is formed on the light shielding film 91. Alternatively, one electrode of the capacitor 19 may be formed using the layer of the light shielding film 91. In this case, it is preferable to make the smoothing film 71a as thin as possible and increase the capacitance value of the capacitor. Alternatively, the light shielding film 91 may be formed of aluminum, a silicon oxide film may be formed on the surface of the light shielding film 91 using an anodic oxidation technique, and the silicon oxide film may be used as a dielectric film of the capacitor 19. A pixel electrode having an HA structure is formed on the smoothing film 71b.

  The gate driver 12 and the like should suppress light from not only the back surface but also the front surface. This is because it malfunctions due to the influence of the photocon. Therefore, in the present invention, when the cathode electrode is a metal film, the cathode electrode is also formed on the surface of the gate driver 12 or the like, and this electrode is used as a light shielding film.

  However, if a cathode electrode is formed on the gate driver 12, a malfunction of the driver due to an electric field from the cathode electrode or an electrical contact between the cathode electrode and the driver circuit may occur. In order to cope with this problem, in the present invention, at least one layer, preferably a plurality of layers of organic EL films are formed on the gate driver 12 and the like simultaneously with the formation of the organic EL film on the pixel electrode. Since the organic EL film is basically an insulator, by forming the organic EL film on the gate driver, the cathode and the gate driver are isolated, and the above-described problems can be solved.

  On the other hand, when the cathode electrode is a transparent electrode, that is, in the case of a light extraction structure in which the pixel electrode is a reflection type and the common electrode is a transparent electrode (ITO, IZO, etc.), the sheet resistance value of the transparent electrode becomes a problem. . This is because the transparent electrode has a high resistance, but it is necessary to pass a current at a high current density to the cathode of the organic EL. Therefore, when the cathode electrode is formed of a single layer of ITO film, it becomes heated due to heat generation, or an extreme luminance gradient occurs on the display screen.

In order to cope with this problem, a low resistance wiring 92 made of a metal thin film is formed on the surface of the cathode electrode. The low resistance wiring 92 has the same configuration as the black matrix (BM) of the liquid crystal display panel (chrome or aluminum material with a thickness of 50 nm to 200 nm) and the same position (between the pixel electrodes, above the gate driver 12, etc.) It is. However, the function of the organic EL is completely different because it is not necessary to form a BM. The low resistance wiring 92 is not limited to the surface of the transparent electrode 72 but may be formed on the back surface (surface in contact with the organic EL film). Further, as the metal film formed in a BM shape, an alloy such as Mg · Ag, Mg · Li, Al·Li, or a laminated structure such as aluminum, magnesium, indium, copper, or an alloy of each may be used. In order to prevent corrosion and the like, an ITO or IZO film is further laminated on the BM, and an inorganic thin film such as SiNx or SiO ₂ or an organic thin film such as polyimide is formed.

  In the pixel shown in FIG. 8, the driving TFT 11b and the conversion TFT 11a have a current mirror relationship, and their characteristics (threshold value Vt, S value, mobility μ, etc.) must match. In addition, it goes without saying that the characteristics of the TFTs are preferably the same in the pixel of FIG.

  The semiconductor film constituting the TFT 11 of the pixel 16 is generally formed by laser annealing in the low temperature polysilicon technology. Variations in the laser annealing conditions result in variations in TFT 11 characteristics. However, if the characteristics of the TFTs 11 in one pixel 16 match, the current programming method shown in FIGS. 6 and 8 can be driven so that a predetermined current flows through the EL element 15. This is an advantage not found in voltage programming.

  In response to this problem, in the present invention, as shown in FIG. 25, a laser irradiation spot 230 at the time of annealing is irradiated in parallel with the source signal line 18. Further, the laser irradiation spot 230 is moved so as to coincide with one pixel column. Of course, the present invention is not limited to one pixel column, and for example, the laser beam of RGB in FIG. 25 may be irradiated in units of one pixel 16 (in this case, it is a three pixel column). In particular, the pixels are made of three pixels of RGB and have a square shape. Accordingly, each of the R, G, and B pixels has a vertically long pixel shape. Therefore, the arrangement of the TFTs 11 formed in the pixel 16 is arranged in the vertical direction as shown in FIG. 25 (conversion TFT 11a, driving TFT 11b). Therefore, by making the laser irradiation spot 230 vertically long and annealing, it is possible to prevent variation in characteristics of the TFT 11 within one pixel.

  In general, the length of the laser irradiation spot 230 is a fixed value such as 10 inches. Since the laser irradiation spot 230 is moved, it is necessary to arrange the panel so that one laser irradiation spot 230 can be moved within the movable range (that is, the laser irradiation spot at the center of the display screen 21 of the panel). 230 do not overlap).

  In the configuration of FIG. 26, three panels are formed so as to be arranged vertically within the range of the length of the laser irradiation spot 230. The annealing apparatus that irradiates the laser irradiation spot 230 recognizes the positioning markers 242a and 242b of the glass substrate 241 and moves the laser irradiation spot 230. The positioning marker 242 is recognized by a pattern recognition device. An annealing device (not shown) recognizes the positioning marker 242 and determines the position of the pixel column. Then, annealing is sequentially performed by irradiating the laser irradiation spot 230 so as to overlap the pixel row position.

  As shown in FIG. 6, the gate signal line 17a becomes conductive during the row selection period (here, since the TFT 11 in FIG. 6 is a P-channel transistor, it becomes conductive at a low level), and the gate signal line 17b is in the non-selection period. It becomes a conductive state.

  When the state of the source signal line is the gradation 0 display state, when the current value for gradation 1 is applied and the row selection period is operated for 75 μsec, the source signal is shown as indicated by the solid line a in FIG. When the parasitic capacitance of the line 18 increases, the current value output to the EL element 15 decreases.

The dotted line b in FIG. 27 is a case where the current value for gradation 1 is 10 times that of the solid line a, and the decrease rate of the current value output to the EL element 15 with respect to the increase in the parasitic capacitance of the source signal line 18. Becomes smaller. Since a variation of about 10% cannot be observed as a luminance difference for the human eye with respect to a predetermined current value, if a decrease of about 10% is recognized, the allowable source capacitance is 2 pF or less for the solid line a and 25 pF for the dotted line b. It becomes as follows.

  The time t required to change the current value of the source signal line 18 is t = C · V / I, where C is the size of the stray capacitance, V is the voltage of the source signal line, and I is the current flowing through the source signal line. Therefore, the fact that the current value can be increased by 10 times indicates that the time required for the current value change can be shortened to nearly 1/10, or that the current value can be changed to a predetermined current value even when the source capacitance becomes 10 times. Therefore, in order to write a predetermined current value within a short horizontal scanning period, it is effective to increase the current value.

When the input current is increased 10 times, the output current is also increased 10 times, and in order to obtain a predetermined luminance so that the luminance of the EL element becomes 10 times, the conduction period of the switching TFT 11d in FIG. The predetermined brightness is displayed by setting the period to 1/10. That is, in order to sufficiently charge and discharge the parasitic capacitance of the source signal line 18 and to program a predetermined current value to the conversion TFT 11a of the pixel 16, it is necessary to output a relatively large current from the source driver 14. There is. However, when such a large current flows through the source signal line 18, this current value is programmed in the pixel, and a large current flows through the EL element 15 with respect to a predetermined current. For example, if programming is performed with 10 times the current, naturally 10 times the current flows through the EL element 15, and the EL element 15 emits light with 10 times the luminance. That is, in order to obtain a predetermined light emission luminance, the time required to flow through the EL element 15 may be reduced to 1/10. By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained.

  It should be noted that although the current value of 10 times is written in the pixel conversion TFT 11a (more precisely, the terminal voltage of the capacitor 19 is set) and the on-time of the EL element 15 is reduced to 1/10, this is an example. . In some cases, a 10 times larger current value may be written into the pixel conversion TFT 11a, and the on-time of the EL element 15 may be reduced to 1/5. On the other hand, there may be a case where 10 times the current value is written to the pixel conversion TFT 11a and the on-time of the EL element 15 is doubled. The present invention is characterized in that the pixel write current is set to a value other than a predetermined value and the current flowing through the EL element 15 is driven intermittently. In this specification, for ease of explanation, it is assumed that a current value of N times is written in the TFT 11 of the pixel and the ON time of the EL element 15 is 1 / N times. However, the present invention is not limited to this, and it goes without saying that a current value of N1 times may be written to the TFT 11 of the pixel, and the ON time of the EL element 15 may be 1 / N2 times (different from N1 and N2).

  For ease of explanation, it is assumed that 1F is set to 1 / N on the basis of 1F (one field or one frame). However, there is a time during which one pixel row is selected and the current value is programmed (usually one horizontal scanning period (1H)), and an error occurs depending on the scanning state. This is only a matter of convenience for the purpose, and is not limited to this.

  The organic (inorganic) EL display device also has a problem in that the display method is basically different from a display that displays an image as a set of line displays with an electron gun, such as a CRT. That is, in the EL display device, the current (voltage) written to the pixel is held for a period of 1F (1 field or 1 frame). For this reason, when a moving image is displayed, there is a problem that the outline blur of the display image occurs.

In the present invention, a current is passed through the EL element 15 only during the period of 1F / N, and no current is passed during the other period (1F (N-1) / N). Consider the case where this driving method is implemented and one point on the screen is observed. In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is a temporal display (intermittent display) state. When the moving image data display is viewed in this intermittent display state, the outline of the image is not blurred and a good display state can be realized. That is, a moving image display close to a CRT can be realized. Although intermittent display is realized, the main clock of the circuit is not different from the conventional one. Therefore, the power consumption of the circuit does not increase.

  In the case of a liquid crystal display panel, image data (voltage) for light modulation is held in the liquid crystal layer, and it is necessary to rewrite the data applied to the liquid crystal layer when performing black insertion display. Therefore, the operation clock of the source driver 14 must be increased and image data must be applied to the source signal line 18 alternately with the black display data, so that black insertion display (intermittent display such as black display) is to be realized. It is necessary to raise the main clock of the circuit. In addition, an image memory for performing time axis expansion is also required.

  However, in the pixel configuration of the EL display panel of the present invention, as shown in FIGS. 6, 47, 52 to 56, 59 to 63, 71, 74, 75, and 95, the image data is The current is held by the capacitor 19 and a current corresponding to the terminal voltage of the capacitor 19 is passed through the EL element 15. Therefore, the image data is not held in the light modulation layer like the liquid crystal display panel.

  In the present invention, the current flowing through the EL element 15 is controlled only by turning on or off the switching TFT 11d or the TFT 11e. That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is held in the capacitor 19 as it is. Therefore, if the switching element is turned on at the next timing and a current flows through the EL element 15, the flowing current is the same as the previously flowing current value. In the present invention, it is not necessary to increase the main clock of the circuit even when black insertion display (intermittent display such as black display) is realized. In addition, since it is not necessary to perform time axis expansion, an image memory is also unnecessary. In addition, the organic EL element 15 has a short response time from application of current to light emission and a high-speed response. Therefore, it is suitable for moving image display, and further, intermittent display can solve the problem of moving image display, which is a problem of conventional data holding type display panels (liquid crystal display panel, EL panel, etc.).

  As shown in FIG. 28, the gate signal line 17b has a conventional conduction period of 1F (when the current program time is 0, the normal program time is 1H, and the number of pixel rows of the EL display device is at least 100 or more. 1F, the error is 1% or less), and if N = 10, according to FIG. 27, even if the source capacitance is about 20 pF from gradation 0 to gradation 1, which takes the longest time to change, 75 μm It can change in about seconds. This indicates that an EL display device of about 2 type can be driven at a frame frequency of 60 Hz.

  Further, when the source capacity is increased in a large display device, the source current may be increased 10 times or more. In general, when the source current value is increased N times, the conduction period of the gate signal line 17b (TFT 11d) may be set to 1 F / N. Accordingly, the present invention can be applied to a television, a monitor display device, and the like.

  Hereinafter, it will be described in more detail with reference to the drawings. First, the parasitic capacitance 404 in FIG. 6 is generated by the coupling capacitance between the source signal lines, the buffer output capacitance of the source driver 14, the cross capacitance between the gate signal line 17 and the source signal line 18, and the like. This parasitic capacitance 404 is usually 10 pF or more. In the case of voltage driving, a voltage is applied from the source driver 14 to the source signal line 18 with a low impedance, so that there is no problem in driving even if the parasitic capacitance 404 is somewhat large.

However, in the current drive, it is necessary to program the capacitor 19 of the pixel with a minute current of 5 nA or less, particularly in the case of black level image display. Therefore, when the parasitic capacitance 404 is generated with a magnitude greater than or equal to a predetermined value, the time for programming to one pixel row (usually within 1H, but is not limited to within 1H since two pixel rows may be written simultaneously). The parasitic capacitance cannot be charged or discharged inside. If charging / discharging is not possible in the 1H period, writing into the pixel is insufficient and the resolution is not at all.

  In the pixel configuration of FIG. 6, as shown in FIG. 7A, the program current I <b> 1 flows through the source signal line 18 during current programming. V1 of the capacitor 19 is set (programmed) so that the current I1 flows through the conversion TFT 11a and the current through which the program current I1 flows is maintained. At this time, the switching TFT 11d is in an open state (off state).

  Next, the TFT 11 operates as shown in FIG. That is, the off voltage Vgh is applied to the gate signal line 17a, and the conversion TFT 11a and the take-in TFT 11c are turned off. On the other hand, the on voltage Vgl is applied to the gate signal line 17b, and the switching TFT 11d is turned on.

  Now, assuming that the program current I1 is N times the current (predetermined value) that flows originally, the current flowing through the EL element 15 in FIG. 7B is also I1. Therefore, the EL element 15 emits light with a brightness N times the predetermined value.

  Therefore, if the switching TFT 11d is turned on only for a period of 1 / N of the time for which the switching TFT 11d is originally turned on (about 1F) and the other period (N-1) / N is turned off, the average brightness of the entire 1F becomes a predetermined brightness. Become. This display state approximates that the CRT is scanning the screen with an electron gun. The difference is that the range in which the image is displayed is 1 / N of the entire screen (the whole screen is 1) is lit (in CRT, the lit range is one pixel row (strictly Is one pixel)).

  In the present invention, the 1 / N image display area moves from the top to the bottom of the display screen 21 as shown in FIG. In the present invention, current flows through the EL element 15 only during the 1F / N period, and no current flows during the other period (1F · (N−1) / N). Therefore, although the image is intermittently displayed, the image is retained by the afterimage to the human eye, so that the entire screen appears to be displayed uniformly.

  In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is a temporal display (intermittent display) state. In a liquid crystal display panel (an EL display panel other than the present invention), since data is held in pixels for a period of 1F, even if image data changes in the case of moving image display, the change cannot be followed. The video was blurred (outline of the image). However, since the image is intermittently displayed in the present invention, the outline of the image is not blurred and a good display state can be realized. That is, a moving image display close to a CRT can be realized.

  Further, in the EL display device, since the black display is completely unlit, there is no contrast reduction as in the case where the liquid crystal display panel is intermittently displayed. Further, as shown in FIG. 7, intermittent display can be realized simply by turning on and off the switching TFT 11d. This is because the image data is stored in the capacitor 19. That is, the image data is held in each pixel 16 during the period of 1F. Whether or not a current corresponding to the held image data is supplied to the EL element 15 is realized by controlling the switching TFT 11d.

Accordingly, there is no change in the number of TFTs 11 constituting one pixel in the case where the intermittent display is realized or not. That is, the parasitic capacitance 40 of the source signal line 18 is maintained without changing the pixel configuration.
The effect of 4 is removed, and a good current program is realized. In addition, a moving image display close to a CRT is realized.

  In addition, since the operation clock of the gate driver 12 is sufficiently slower than the operation clock of the source driver 14, the main clock of the circuit is not increased. Further, it is easy to change the value of N.

  As shown in FIG. 30, the image display direction (image writing direction) is downward from the top of the screen in the first field (FIG. 30A), and upward from the bottom of the screen in the second field. It is good also as (FIG.30 (b)). That is, FIG. 30 (a) and FIG. 30 (b) may be repeated alternately.

  Further, as shown in FIG. 31, in the first field, the screen is directed downward from the top (FIG. 31A), and once the entire screen is displayed in black (non-display area) 312 (FIG. 31B). )), In the next second field, the bottom of the screen may be set upward (FIG. 31C), and the entire screen may be temporarily displayed in black (non-display area) 312 (FIG. 31D). That is, what is necessary is just to repeat the state of Fig.31 (a) from FIG.31 (d) alternately.

  In FIG. 30, FIG. 31, etc., the screen writing method is from the top to the bottom or from the bottom to the top, but the present invention is not limited to this. The above matters are the same in other embodiments of the present invention.

  In FIG. 31A, the image display area 311 is set to 1 / N, and the non-display area 312 is set to (N-1) / N (however, this is an ideal state. This is different because there is a punch through due to the SG capacitance of the TFT 11a). That is, this is a case where the image display area 311 is single. The image display area 311 moves downward from the top of the screen as shown by the arrow (FIG. 29 (a1) → FIG. 29 (a2) → FIG. 29 (a3) → FIG. 29 (a1) →). However, the movement of the image display area 311 is not limited to the downward movement from the top of the screen, and may be the upward movement from the bottom of the screen. The first frame (first field) is scanned (operated) so that it moves downward from the top of the screen, and the second frame (second field) moves upward from the bottom of the screen. Needless to say, it is good. Further, scanning (operation) may be performed from the right to the left of the screen or from the left to the right of the screen.

  FIG. 28 shows operation timing waveforms. As described above, one screen is displayed in the period of 1F, and the current is programmed in the period of 1H. FIG. 28 (a) shows the timing waveform of the gate signal line 17a in FIGS. 6 (a) and 6 (b). FIG. 28B shows a timing waveform of the gate signal line 17b. Basically, when the gate signal line 17b becomes the ON voltage Vgl, the switching TFT 11d is turned on (period is 1 F / N), and the EL element 15 has a peak current N times the predetermined current I1, and the EL The element 15 emits light with a luminance (N · B) N times the predetermined luminance B. During the period of 1F ((N−1) / N), the switching TFT 11d is turned off. The control of the gate signal line can be easily realized by controlling the two shift registers (22a, 22b) in the gate driver 12, as shown in FIG. This is because the shift register 22a may hold (scan) the control data of the gate signal line 17a, and the shift register 22b may hold (scan) the control data of the gate signal line 17b.

FIG. 32 shows the waveform of the gate signal line 17b. If FIG. 32A is the voltage waveform of the gate signal line 17b of the first pixel row, FIG. 32B shows the voltage waveform of the gate signal line 17b of the second pixel row adjacent to the first pixel row. Show. Similarly, FIG. 32C shows the voltage waveform of the gate signal line 17b of the next third pixel row, and FIG. 32D shows the voltage waveform of the gate signal line 17b of the fourth pixel row.

  As described above, the waveform of the gate signal line 17b is made the same in each pixel row, and the application is performed by shifting at an interval of 1H. By scanning in this manner, it is possible to shift the pixel rows that are sequentially lit while prescribing the time during which the EL element 15 is lit to 1 F / N, so that the waveform of the gate signal line 17b in each pixel row can be changed. It is easy to make them identical and shift. This is because it is only necessary to control ST1 and ST2 which are data applied to the shift registers 22a and 22b in FIG. For example, if the ON voltage Vgl is output to the gate signal line 17b when the input ST2 is L level, and the OFF voltage Vgh is output to the gate signal line 17b when the input ST2 is H level, the gate signal line 17b is output. ST2 to be applied to is input at the L level for the period of 1F / N and is set to the H level for the other periods. The input ST2 is simply shifted by the clock CLK2 synchronized with 1H.

Similarly, the waveform of the gate signal line 17a shown in FIG.
This is because ST1 that is input data of the shift register 22a in FIG. For example, if the ON voltage Vgl is output to the gate signal line 17a when the input ST1 is L level, and the OFF voltage Vgh is output to the gate signal line 17a when the input ST1 is H level, the gate signal line 17a is output. ST1 to be applied to is input at the L level for the period of 1H, and is set to the H level for the other periods. This input ST1 is simply shifted by the clock CLK1 synchronized with 1H.

  FIG. 29B shows an example in which the image display area 311 is set to 1 / (2N), and the two image display areas 311a and 311b are moved downward from the top of the screen as indicated by arrows (FIG. 29B1). ) → FIG. 29 (b2) → FIG. 29 (b3) → FIG. 29 (b1) →). However, the movement of the image display areas 311a and 311b is not limited to moving from the top to the bottom of the screen, and may be moved from the bottom to the top of the screen. The first frame (first field) is scanned (operated) so that it moves downward from the top of the screen, and the second frame (second field) moves upward from the bottom of the screen. Needless to say, it is good. Further, scanning (operation) may be performed from the right to the left of the screen or from the left to the right of the screen.

  Further, FIG. 29C shows an example in which the image display area 311 is set to 1 / (3N), and the three image display areas 311a, 311b, and 311c are moved downward from the top of the screen as indicated by arrows ( FIG. 29 (c1) → FIG. 29 (c2) → FIG. 29 (c3) → FIG. 29 (c1) →).

  As shown in FIGS. 29B and 29C, the more the image display area 311 is divided, the more the frame rate of the entire image display (the number of times the screen is written per second, for example, the frame rate 60 is 1 Rewriting the screen 60 times per second). If the frame rate is lowered, the operation clock of the circuit can be lowered accordingly, so that power consumption can be reduced. That is, the light emission period of the EL element 15 is shortened, the apparent instantaneous luminance is increased, and the image display area 311 and the non-display area 312 are repeated at high speed, and flicker is reduced. Therefore, the frame rate can be reduced.

  By driving as described above, the number of times of lighting in one frame (one field) can be increased and flicker can be reduced. When the EL element is turned on, the frequency component is increased by increasing the number of times of lighting, so that it is difficult to be observed by human eyes. For example, when the lighting period per time is set to 1/7 and lighting is performed seven times in one frame, display without flicker can be realized even at a frame frequency of 30 Hz.

By controlling on / off of the switching TFT 11d, the luminance of the image can be adjusted (variable). For example, in the case of FIG. 29A (when there is one image display region 311), the brightness of the display screen 21 is changed by changing the area of the non-display region 312 (from FIG. 33A1). 33 (a2) is darker and FIG. 33 (a3) is darker than FIG. 33 (a2)).

  Similarly, in the case of FIG. 29B (when there are two image display areas 311), FIG. 33B2 is darker than FIG. 33B1, and FIG. 33B3 is shown in FIG. 33B2. However, the display brightness of the display screen 21 becomes darker. The same applies to the case of FIG. 29 (c) (when there are three image display areas 311, that is, 3 or more) (FIG. 33 (c2) is darker than FIG. 33 (c1) and FIG. 33 (c2). FIG. 33 (c3) is darker).

  In FIG. 29, the image display area 311 is scanned on the display screen 21, but the present invention is not limited to this. As shown in FIGS. 33 (c1) and (c2), one frame (one field) is shown. The entire screen may be the non-display area 312 for the eyes, and the entire screen may be the image display area 311 for the next two frames (two fields). That is, the entire screen is alternately switched between the image display state and the non-lighting state. However, the image display time and the non-lighting time are not limited to the same time. For example, the image display time may be 1F / 4, and the non-lighting time may be 3F / 4. Thus, the display brightness of the image can be changed (adjusted) by changing the ratio between the image display time and the non-lighting time.

  In any case, as shown in FIG. 34, by changing the value of N, the display brightness B of the image can be changed linearly. Further, the brightness of the image can be easily changed by simply controlling the value of N.

  FIG. 35 is a block diagram of a circuit for adjusting (controlling) display luminance according to the present invention. The frame memory (field memory) 354 stores video data input from the outside. The CPU 353 performs calculation using the accumulated video data. The calculation uses at least one of the maximum luminance, optimum luminance, average luminance, and luminance distribution of the video data. In addition, the maximum luminance, optimum luminance, average luminance, luminance distribution, and change rate of each frame of continuous video data are also considered.

  The calculated result is stored in the luminance memory 352. The luminance memory 352 is data obtained by correcting the brightness of an image. For example, on a bright screen such as a beach, the average luminance of the image is corrected to be bright, and when there is a relatively dark portion in the image data, the image data is converted to image data that is darker than the actual value. On the night screen or the like, since the image is entirely dark, a relatively bright part is corrected more brightly.

  The counter circuit 351 is a circuit that counts how much the N value in FIG. The N value is changed in real time in the waveform of the gate signal line 17b. Since the N value is time, it can be easily changed by counting with a counter, and the brightness of the image can be changed.

  The switching circuit 355 is a circuit for switching a voltage Vgl for turning on the TFT 11 of the pixel 16 and a voltage Vgh for turning it off (when the pixel TFT 11 is in the P channel and vice versa in the N channel). That is, based on the output of the counter circuit 351, the period of 1F / N shown in FIG. Therefore, the brightness of the display screen 21 can be easily changed in real time.

The display brightness is controlled in real time according to the video signal data. By controlling in this way, the dynamic range of the brightness expression can be expanded substantially three times or more. Further, the EL display device is completely black (non-lighted) when no current is passed through the EL element, so that no black floating occurs in the image display. That is, the contrast is also increased. In particular, in the case of current programming, since the current value programmed in the pixel is as small as 10 nA in black display, the parasitic capacitance 404 cannot be charged and discharged sufficiently, and it is difficult to realize complete black display. Further, power is supplied to the source signal line 18 by a pulse applied to the gate signal line 17 (punch-through voltage), and black floating occurs.

  The present invention forcibly turns off the switching TFT 11d and stops supplying current to the EL element 15. Therefore, the EL element 15 is completely turned off. Therefore, good contrast can be realized.

  In FIG. 35, the brightness of the image is changed in real time based on the video data of the video signal. However, the present invention is not limited to this. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume, this change is detected and the counter value of the counter circuit 351 is changed to change the brightness (or contrast or dynamics) of the display screen 21. Range) may be changed. Alternatively, brightness such as outside light may be detected by a photo sensor, and the brightness of the display screen 21 may be automatically changed based on the detected data. Further, it may be configured to change manually or automatically depending on the contents and data of the image to be displayed.

  In any case, as described above with reference to FIGS. 28 and 35, the present invention may be performed by controlling the gate signal line 17 or changing the current (voltage) applied to the source signal line 18. However, both may be combined.

  As shown in FIG. 36, the time when the gate signal line 17b is turned on during the 1F / N period is 1F (not limited to 1F but may be a unit period) as shown in FIG. Good. This is because a predetermined average luminance is obtained by turning on the EL element 15 for a predetermined period of the unit time. However, immediately after the program period (1H) of FIG. 36A, the gate signal line 17b is set to the ON voltage Vgl so that the EL element 15 emits light is less affected by the retention characteristic of the capacitor 19 of FIG. It will be good. Further, in the period of 1F / N, the position may be changed as indicated by symbols A and B and arrows in FIG. If the timing of data applied to ST in FIG. 10 (when it is set to L level in 1F) can be adjusted or varied, this change can be easily realized.

  In addition, as illustrated in FIG. 37, the period (1F / N) in which the gate signal line 17b is set to the on voltage Vgl may be divided into a plurality (divided number K). In other words, the period of 1F / (K · N) is performed K times during the period of turning on voltage Vgl. With this control, the image display state is as shown in FIG. 29B (K = 2) and FIG. 29C (K = 3). In this way, by dividing the image portion (image display area 311) to be lit into a plurality of portions, the occurrence of flicker can be suppressed and an image display with a low frame rate can be realized. Further, it is preferable that the number of divisions of the image is variable. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume, this change is detected and the value of K is changed manually. Or you may comprise so that it may change automatically.

  In this way, if it is configured to be able to adjust or vary the timing of data to be applied to ST in FIG. 10 (when it becomes L level at 1F), the value of K (the number of divisions of the image display area 311). It is also easy to change the value.

In FIG. 37, the period (1F / N) in which the gate signal line 17b is set to the on voltage Vgl is divided into a plurality (division number K), and the period in which the on voltage Vgl is set is 1F / (K · N). However, the present invention is not limited to this. The 1F / (K · N) period may be implemented L (L ≠ K) times. That is, in the present invention, the display screen 21 is displayed by controlling the period (time) flowing through the EL element 15, and therefore the period of 1F / (K · N) is performed L (L ≠ K) times. This is included in the technical idea of the present invention. Further, the luminance of the display screen 21 can be changed digitally by changing the value of L. For example, when L = 2 and L = 3, the luminance (contrast) changes by 50%. These controls can also be easily realized with the circuit configurations of FIG. 10, FIG. 35, FIG. 46, FIG.

  Further, when the image display region 311 is divided, the period during which the gate signal line 17b is set to the on voltage Vgl is not limited to the same period. For example, as shown in FIG. 38, the period during which the ON voltage Vgl is set may be a plurality of periods such as t1 and t2.

  Although FIG. 28 illustrates that adjacent pixel rows are sequentially lit (displayed), the present invention is not limited to this. As shown in FIG. 39, interlace scanning may be performed. In the interlaced scanning, an image is written in an odd-numbered pixel row in the first field (FIG. 39 (a) write pixel row 391), and an image is written in an even-numbered pixel row in the next second field (FIG. 39 (b) write pixel). Line 391) An image display method. The pixel row not to be written holds the image data of the previous field (holding pixel row 392). In this way, flicker can be reduced by performing interlaced scanning with an EL display device.

  With the driving method of FIG. 39, the gate signal lines 17b of all (or a plurality of) even pixel rows can be shared, and the gate signal lines 17b of all (or a plurality of) odd pixel rows can be shared. Therefore, the number of gate signal lines 17 can be greatly reduced. Further, when the entire screen is displayed alternately between the image display area 311 and the non-display area 312, all the gate signal lines 17 b can be shared. These configurations are particularly effective in a three-side free configuration as shown in FIG.

  In the interlace scanning, an image is written in an odd-numbered pixel row in the first field and an image is written in an even-numbered pixel row in the next second field. However, the present invention is not limited to this. For example, in the first field, an image may be written every two pixel rows by skipping two pixel rows, and an image may be written every two pixel rows not written in the first field in the next second field. Further, every three pixel rows or four pixel rows may be used. In the first field, an image may be written every two pixel rows from the second row of the screen (see FIG. 40A), and in the next second field, an image may be written every two pixel rows from the first row (see FIG. (See FIG. 40 (b)). Further, as shown in FIG. 40, the pixel row to be written or the pixel row to be written may be controlled to be the non-display area 312. Further, an image may be written from the top to the bottom of the screen in the first field, and an image may be written from the bottom to the top of the screen in the second field. These are all included in the concept of interlaced scanning.

  Interlaced scanning can also be easily realized by implementing the method described with reference to FIGS. This is because the pixel row corresponding to the non-display area 312 that is not lit is only required to turn off the switching TFT 11d shown in FIG.

  Naturally, as shown in FIG. 41, the non-display area 312 and interlaced scanning can be combined. In FIG. 41A, the scanning region 501 including the writing pixel row 391 and the holding pixel row 392 is sequentially shifted. In FIG. 41A, an image is written from the first line. Similarly in FIG. 41B, the scanning region 501 including the writing pixel row 391 and the holding pixel row 392 is sequentially shifted. In FIG. 41B, an image is written from the second line.

  The above embodiment has mainly described the configuration of the pixel 16 of FIG. However, the present invention is not limited to this. For example, it can be realized by the pixel 16 of FIGS.

  In the pixel configuration of FIG. 8, the current value applied to the source signal line 18 is programmed in the capacitor 19 by applying the ON voltage Vgl to the gate signal line 17 a. As shown in FIG. 42, the data corresponding to the video signal is applied to the source signal line 18 from the power source switching means 403 in the source driver 14. When the current mirror efficiency is 1, the programmed current flows to the driving TFT 11 b and this current is applied to the EL element 15. This relationship (timing waveform etc.) can be diverted from the matters shown in FIG. However, when current programming is performed, it may be necessary to individually control the on / off timing of the capture TFT 11c and the switching TFT 11d. In this case, the gate terminal for turning on and off the take-in TFT 11c and the switching TFT 11d must be another gate signal line 17.

  In order to implement the display method such as FIG. 29, it is necessary to cut off the current flowing through the EL element 15. For this purpose, a TFT 11e is added as shown in FIG. A current is applied to the EL element 15 by setting the gate terminal of the TFT 11e to the on voltage Vgl, and a current to the EL element 15 is blocked by setting the gate terminal of the TFT 11e to the off voltage Vgh (non-lighting state).

  Therefore, the image display described in FIG. 29 and the like can be realized by applying the signal waveforms of the gate signal lines 17a and 17b described in FIG.

  In the image display area 311 and the non-display area 312, as shown in FIG. 43, the odd pixel row and the even pixel row may be switched for each frame (field). If the odd pixel rows are displayed in FIG. 43A and the even pixel rows are not displayed, the odd pixel rows are not displayed in the next frame (field) (see FIG. 43B), and the even pixel rows are displayed. Is displayed.

  Thus, if the non-display area and the display area are displayed repeatedly for each pixel row, the occurrence of flicker is greatly suppressed.

  In FIG. 43, a non-display pixel row and a display pixel row are set for each pixel row. However, the present invention is not limited to this. A non-display pixel row and a display are displayed for every two pixel rows or more. It may be a pixel row.

  For example, if there are two rows, if the first pixel row and the second pixel row are display pixel rows and the third pixel row and the fourth pixel row are non-display pixel rows in the first field (frame), 5 The pixel row and the sixth pixel row are display pixel rows. In the next second field (frame), if the first and second pixel rows are non-display pixel rows, and the third and fourth pixel rows are display pixel rows, the fifth and sixth pixel rows The eyes are non-display pixel rows. In the next third field (frame), as in the first field, the first and second pixel rows are display pixel rows, and the third and fourth pixel rows are non-display pixel rows. The fifth and sixth pixel rows are display pixel rows.

  In this specification, the terms “field” and “frame” are used synonymously or separated. In general, in NTSC interlaced driving, one frame is composed of two fields. However, in progressive driving, one frame is one field. Thus, although the field and the frame are properly used in the world of the video signal, the image displayed on the display panel in the present invention can be applied to either progressive or interlace. Therefore, it is expressed that either is acceptable. Conceptually, it is a unit of time for completing a series of screens in both fields and frames.

  The display method of FIG. 44 is also effective. For ease of explanation, FIG. 44 (a) shows the first field (first frame), FIG. 44 (b) shows the second field (second frame), and FIG. 44 (c) shows the third field (first frame). (3 frames) and FIG. 44 (d) are the fourth field (fourth frame).

  In the first field (frame), the first pixel row and the second pixel row are non-display pixel rows, the third pixel row and the fourth pixel row are display pixel rows, the fifth pixel row and the sixth pixel row are display pixels. And In the second field (frame), odd pixel rows are display pixel rows, and even pixel rows are non-display pixel rows. In the third field (frame), the first pixel row and the second pixel row are display pixel rows, and the third pixel row and the fourth pixel row are non-display pixel rows. In the fourth field (frame), odd pixel rows are non-display pixel rows and even pixel rows are display pixel rows. Thereafter, the display is repeated sequentially from the display state of the first field (first frame).

  In the driving method of FIG. 44, one field is composed of four fields (frames). In this way, by performing image display in a plurality of fields (a plurality of frames), occurrence of flicker is often suppressed as compared with FIG.

  In the embodiment of FIG. 44, in the first field (frame), the second pixel row is set as a non-display pixel row, and in the second field (frame), the first pixel row is set as a non-display pixel row. It is not limited. In the first field (frame), four pixel rows are set as non-display pixel rows, in the second field (frame), two pixel rows are set as non-display pixel rows, and in the third field (frame), one pixel is set. In the fourth field (frame), the fourth pixel row is a non-display pixel row, and in the fifth field (frame), the second pixel row is a non-display pixel row, and the sixth field. In (frame), the non-display pixel rows may be set for each pixel row.

  The driving method of the present invention can easily realize display effects (such as animation effects). FIG. 45 shows a display method in which the display area appears in order of FIG. 45 (a) → FIG. 45 (b) → FIG. 45 (c) → FIG. 45 (d). An animation effect can be realized by slowly scrolling the non-display area 312. These controls can be easily realized with the circuit configurations of FIG. 10, FIG. 46, FIG. This does not write a black display state as an image and easily realizes an animation effect by controlling the gate signal line 17b and the like.

  A display panel that holds data for one field (one frame) in a pixel such as a liquid crystal display panel has a problem in that motion blur occurs. However, since a CRT or the like is only displayed momentarily by an electron gun, there is no problem of moving image blur.

  An effective means for solving this problem is black insertion. The present invention can easily realize a black insertion method close to a CRT that displays a moving image.

  FIG. 48 shows that the letter F moves from the top to the bottom of the screen. As shown in FIG. 48, a non-display state (FIGS. 48 (b), (d), (f)) is inserted between image displays (FIGS. 48 (a), (c), (e)). Yes. Therefore, the image is displayed in a flying manner. As a result, no moving image blur occurs and a good moving image display can be realized.

In this way, the circuit configuration of FIG. 46 may be employed to make the entire screen a non-display area. The difference from FIG. 10 is that an ENBL terminal 601 is provided. The ENBL terminal 601 is connected to one terminal of the OR circuit 602 in which the gate signal line 17 is formed. By setting the ENBL terminal to the L level, the Vgh level is output to all the gate signal lines 17b, the switching TFT 11d or 11e for supplying current to the EL element 15 is turned off, and the entire screen is connected to the non-display area 312. Become. When the ENBL terminal is at H level, normal operation is performed.

  In FIG. 10, FIG. 46, FIG. 47, and FIG. 49, it has been described that data input to the ST terminal is sequentially shifted by a clock (serial operation), but the present invention is not limited to this. For example, it may be a parallel input that determines the ON / OFF state of each gate signal line at once (a configuration in which ON / OFF logic of all the gate signal lines is output and determined at a time for the number of controllers or gate signal lines 17. Such).

  The embodiment of FIG. 48 is a moving image display, but it is also easy to implement an animation effect such as flashing for each of R, G, and B (see FIG. 50). 50A, FIG. 50A is an image of red display 311R, FIG. 50C is an image of green display 311G, and FIG. 50E is an image of blue display 311B. A non-display state (FIGS. 50B, 50D, 50F) is inserted between the images in FIGS. 50A, 50C, and 50E. If this operation is performed slowly from FIG. 50 (a) to FIG. 50 (f), the images of R, G and B can be displayed as if they are flashing.

  Also, as shown in FIG. 51, it is easy to implement an animation effect such as flashing for each different image. 51, FIG. 51A shows the first image 311a, FIG. 51C shows the second image 311b, and FIG. 51E shows the third image 311c. A non-display state (FIGS. 51 (b), (d), and (f)) is inserted between the images of FIGS. 51 (a), (c), and (e). If the operations from FIG. 51A to FIG. 51F are performed slowly, the first, second, and third images can be displayed as if they are flashing.

  In the above embodiment, a current N times as large as a predetermined value of the source signal line 18 is conceptually passed, and a current N times as long as 1 / N is passed through the EL element 15 to obtain a desired luminance. It is a method (configuration). This method (configuration) solved the problem of insufficient writing due to the presence of the parasitic capacitance 404.

(Embodiment 7)
The configuration of FIG. 52 is a method for solving the problem of insufficient writing due to the presence of the parasitic capacitance 404 by forming a driving TFT 11an having a driving capability of N-1 times that of the driving TFT 11a.

  The difference between FIG. 52 and FIG. 6A is that, in addition to the driving TFT 11a, N-1 times driving TF · BR> S11an-1 and switching TFT 11f are added. The difference between FIG. 6 and FIG. 52 will be mainly described. The reason why the driving TFT 11an-1 is selected is that the driving TFT 11an-1 and the driving TFT 11a are configured to be N times as long as the currents of the driving TFT 11an-1 and the driving TFT 11a are added. That is, the channel width W2 of the driving TFT 11an-1 is set to N-1 times the channel width W1 of the driving TFT 11a. For example, if N = 10 and the channel width W1 of the driving TFT 11a is 1, the channel width W2 of the driving TFT 11an-1 is nine times. Therefore, theoretically, if the driving TFT 11a allows a current of 1 to flow, the driving TFT 11an-1 has a capability of flowing a current 9 times as large.

  In FIG. 52, the driving current of the driving TFT 11an-1 is set to N-1. In the configuration of FIG. 52, when the N-fold current is supplied to the source signal line 18, the driving current is supplied to the EL element 15. This is because a current that is one time that of the TFT 11a is added. In the configuration of FIG. 53, since the current of the driving TFT 11b that passes current to the EL element 15 does not flow to the source signal line 18, the driving current of the TFT 11n needs to be increased N times.

  For ease of explanation, if the driving TFT 11a passes a current I1, and the driving TFT 11an-1 passes a current In-1, I1 + In-1 = Iw (in this case, Iw is an EL element). 15), which is N times the current I1 to be passed through.

  In the current program period, the gate signal line 17a is applied to the ON voltage Vgl, and the driving TFT 11b, the switching TFT 11f, and the capturing TFT 11c are turned on. Further, the off voltage Vgh is applied to the gate signal line 17b, and the switching TFT 11d is turned off. Therefore, a voltage corresponding to the program current Iw is programmed in the capacitor 19. That is, a current of I1 + In−1 = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15) flows through the source signal line 18.

  Next, in a period in which a current flows through the EL element 15, the off voltage Vgh is applied to the gate signal line 17a, and the driving TFT 11b, the switching TFT 11f, and the take-in TFT 11c are turned off. Therefore, the source signal line 18 and the pixel 16 are separated. Further, the on voltage Vgl is applied to the gate signal line 17b, and the switching TFT 11d is turned on. Therefore, a current I1 corresponding to 1 / N of the program current Iw flows through the EL element 15.

  By driving as described above, the source signal line 18 can be supplied with a current N times as large as a desired value (current flowing through the EL element). Therefore, the influence of the parasitic capacitance 404 is excluded, and the current program can be sufficiently performed on the capacitor 19. On the other hand, a desired value of current can be applied to the EL element 15.

  In FIG. 52, it is assumed that the driving TFT 11an-1 having N-1 current capability is formed in one pixel, but the present invention is not limited to this. As shown in FIG. 54, a plurality of TFTs (TFT 11n1 to TFT 11n6 in FIG. 54) may be manufactured. The operation is the same as in FIG.

  Further, the configuration of FIG. 52 can also be developed in the current mirror system shown in FIG. As shown in FIG. 53, a TFT 11n having N times driving capability may be formed. However, in the current mirror configuration, the switching TFT 11f is not necessary.

  In FIG. 53, the ratio of the channel width W2 of the TFT 11n to the channel width W1 of the driving TFT 11b is N: 1. For ease of explanation, if the driving TFT 11b passes a current I1, and the TFT 11n passes an In current, then In = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15). ).

  During the current program period, the ON voltage Vgl is applied to the gate signal line 17a, and the capturing TFT 11c and the switching TFT 11d are turned on. Therefore, a voltage corresponding to the program current Iw is programmed in the capacitor 19. That is, a current of In = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15) flows through the source signal line 18. Note that it is preferable to control the on / off state of the take-in TFT 11c and the switching TFT 11d with a slight shift in timing. In this case, the gate signal line for controlling the take-in TFT 11c and the gate signal line for controlling the switching TFT 11d are required to be separately controlled.

Next, in a period in which a current flows through the EL element 15, the off voltage Vgh is applied to the gate signal line 17a, and the take-in TFT 11c and the switching 11d are turned off. Therefore, the source signal line 18 and the pixel 16 are disconnected, and the current I corresponding to 1 / N of the program current Iw.
1 flows to the EL element 15.

  By driving as described above, the source signal line 18 can be supplied with a current N times as large as a desired value (current flowing through the EL element). Therefore, the influence of the parasitic capacitance 404 is excluded, and the current program can be sufficiently performed on the capacitor 19. On the other hand, a desired value of current can be applied to the EL element 15.

  As described with reference to FIG. 42, the gate signal line 17b and the TFT 11e are provided in order to control the current to flow through the EL element 15 for non-image display as shown in FIG. 14 or for the 1 / N period. Therefore, in the configuration of FIG. 53, the problem of insufficient writing due to the parasitic capacitance 404 is eliminated at all by flowing N times more current and driving the current flowing through the EL element 15 in a 1 / N period. Further, black insertion display can be easily realized, and good moving image display can be realized.

  Further, the configuration of FIG. 53 is very effective. For example, if N = 10 is to be realized with the configuration of FIG. 6 alone, it is necessary to apply a pulsed current 10 times higher than the desired value to the EL element 15. In this case, since the terminal voltage of the EL element 15 becomes high, it is necessary to design the Vdd voltage high, and the EL element 15 may be deteriorated.

  However, in the configuration of FIG. 53, if the channel width W2 of the TFT 11n is 5 times that of the driving TFT 11b and programmed with a current that is twice as high, 5 × 2 = 10 is obtained. This can be realized by applying only a half period. Therefore, there is no problem that the EL element 15 deteriorates, and it is not necessary to increase the Vdd voltage almost.

  On the other hand, if N = 10 is to be realized only by the TFT 11n, the channel width W2 of the TFT 11n needs to be 10 times that of the driving TFT 11b in the configuration of FIG. When the magnification is 10 times, the formation area of the TFT 11n occupies most of the area of the pixel. Therefore, the pixel aperture ratio becomes extremely small or cannot be realized. However, in the configuration of FIG. 53, it is only necessary to make the channel width W2 of the TFT 11n five times that of the driving TFT 11b, so that a sufficient pixel aperture ratio can be realized.

  There are many ways to achieve N = 10. For example, the channel width W2 of the TFT 11n is twice that of the driving TFT 11b, and a current five times higher is applied to the EL element 15 for a period of 1/5, or the channel width W2 of the TFT 11n is four times that of the driving TFT 11b. For example, a method in which a current five times higher is applied to the EL element 15 for a period of 1 / 2.5. That is, the multiplication may be set to 10 in consideration of the design of the TFT 11n (channel width W2), the current flowing through the EL element 15 and the period thereof. Thus, the value of N can be designed freely.

  In FIG. 53, the TFT 11n having the current capability of N is formed in one pixel, but the present invention is not limited to this. As shown in FIG. 55, a plurality of TFTs (TFT11n1 to TFT11n5 in FIG. 55) may be manufactured. The operation is the same as in FIG.

  There are many ways of realizing N = 10 in the configuration of FIG. The channel width W2 of the driving TFT 11an-1 is four times that of the driving TFT 11a, and a current twice higher is applied to the EL element 15 for a period of half, or the channel width W2 of the driving TFT 11an-1 is set to the driving TFT 11a. For example, a method of applying a current 5 times higher to the EL element 15 for a period of 1/5. That is, the multiplication may be set to 10 in consideration of the design of the driving TFT 11an-1 (channel width W2), the current passed through the EL element 15 and the period thereof. Thus, the value of N can be designed freely.

  It is obvious that the items described above can be applied to FIGS. 52, 54, and 56 to 58. That is, according to the present invention, a driving TFT having a large channel width is formed in each pixel, and the current for driving the source signal line 18 is increased. In addition, as described with reference to FIG. 29 and the like, the current or current flowing in the EL element 15 is increased and the current flowing in the EL element 15 is set to a predetermined period.

  Further, the display described with reference to FIGS. 14 and 29 can be realized by controlling on / off of the switching TFT 11d or TFT 11e. With this display, the moving image display can be improved and the brightness can be adjusted. Therefore, in the present invention, a current that is N times or proportional to N is applied to the EL element 15, but the present invention is not limited to this. A configuration in which a current that is a predetermined one or less is supplied to the EL element 15 may be employed. This is because even in this case, the moving image display can be improved and the brightness can be easily adjusted.

  6 and 52 are the same, but when the switching TFT 11d is turned on, the characteristic variation due to the kink phenomenon of the driving TFT 11a can be suppressed by increasing the resistance value. This has been described with reference to the configuration of FIG. By disposing the TFT 11e of FIG. 6B and applying a Vbb voltage (Vgl <Vbb <Vgh) to the gate terminal of the TFT 11e, variation in the current flowing through the driving TFT 11a is reduced.

  6 and 52, it is preferable to apply the Vbb voltage to the gate signal line 17b to turn on the switching TFT 11d. In other words, the switching TFT 11d is applied with the off voltage Vgh in the off state and applied with the Vbb voltage in the on state.

  This control is easy if the circuit is configured as shown in FIG. If the off-state voltages Vgh and Vbb are used as power supplies, the output stage inverter of the shift register 22b can apply the off-voltage Vgh to the gate signal line 17b in the off state and the Vbb voltage to the gate signal line 17b in the on state. It is.

  Similarly to FIG. 6B, as shown in FIG. 56, a TFT 11e to which a Vbb voltage is applied may be separately formed or arranged. The same applies to the current mirror configuration. For example, as shown in FIGS. 59 and 60, the switching TFT 11f for applying the Vbb voltage may be separately formed or arranged. The same applies to the pixel configuration of FIG.

  In FIG. 62, by separating the driving TFT 11a into the TFT 11a1 and the TFT 11a2 and connecting the gate terminals in cascade, the kink phenomenon can be suppressed and the characteristic variation can also be suppressed. The same applies to the driving TFT 11a in FIG. 6, the driving TFT 11b in FIG. 8, the driving TFT 11a in FIG. 52, the driving TFT 11b in FIG. 53, and the like (preferably employed as the configuration of the driving TFT).

  54 and 55, the TFT 11n is divided into a plurality of parts. As another configuration, the gate signal line 17c determines whether or not the TFT 11n1 and the TFT 11n2 divided as shown in FIG. It may be controlled by the potential (Vgh or Vhl) applied to. When the TFT 11f2 is turned off, the current flowing through the source signal line 18 is ½ that when the TFT 11n1 and TFT 11n2 are operating. These controls may be determined from the viewpoint of image display data of the display panel and power consumption.

The difference between FIG. 56 and FIG. 57 is that the gate terminal of the switching TFT 11f is connected to the gate signal line 1.
This is a point connected to 7c. That is, the on / off state of the switching TFT 11f is not affected by the potential state of the gate signal line 17a, and unique control can be realized. When the switching TFT 11f is constantly in the OFF state, the TFT 11n is disconnected from the pixel, and the pixel configuration in FIG. 6A is obtained. If the gate signal line 17c and the gate signal line 17a are logically shorted and used, the configuration shown in FIG. 56 is obtained.

  The problem of FIG. 56 here is that if a characteristic deviation such as the threshold value Vt of the TFT 11n and the driving TFT 11a occurs for each pixel, the current flowing in the EL element 15 varies for each pixel. When variation occurs in the current, a feeling of roughness appears in the displayed image even in a uniform display such as a white raster. In this respect, this problem does not occur in the configuration of FIG.

  Therefore, when the screen size of the display panel is small and the influence of the parasitic capacitance 404 is small, the switching TFT 11f is constantly used in the off state. Further, when the screen size of the display panel is large and the influence of the parasitic capacitance 404 cannot be eliminated only by the operation of the driving TFT 11a, the gate signal line 17c is short-circuited with the logic of the gate signal line 17a to realize the pixel configuration of FIG. Then, it is good to drive.

  FIG. 49 shows a circuit block for driving the pixel configuration of FIG. A shift register 22c for driving the gate signal line 17c is formed, and the gate signal line 17c is driven. When driving with the pixel configuration of FIG. 6, the control is performed so that the data of ST3 is constantly set to L and the Vgh off-voltage is continuously output to the gate signal line 17c. When used in the configuration of FIG. 57, the data input states (timing, logic, etc.) of the shift registers 22c and 22a may be the same.

  The configuration of FIG. 57 can also be realized by the configuration of a current mirror. FIG. 58 shows the pixel configuration. As shown in FIG. 58, whether or not the divided driving TFTs 11a and 11n are operated for improving the driving current may be controlled by the potential (Vgh or Vhl) applied to the gate signal line 17c. When the switching TFT 11f is turned off, only the driving TFT 11a is operated by the current flowing through the source signal line 18.

Therefore, like the pixel configuration of FIG. 57, the screen size of the display panel is small,
When the influence of the parasitic capacitance 404 is small, the switching TFT 11f is constantly used in the off state. When the screen size of the display panel is large and the influence of the parasitic capacitance 404 cannot be eliminated only by the operation of the driving TFT 11a, the gate signal line 17c is short-circuited with the logic of the gate signal line 17a, and the driving current is increased to drive. As described above, the circuit block of FIG. 49 can also be applied to the pixel configuration of FIG.

  In the configuration of FIG. 49, a shift register 22c for controlling the gate signal line 17c is newly formed and operated. However, it is not limited to this configuration. Since only the Vgl or Vgh voltage is applied to the gate terminal of the switching TFT 11f, the control logic of the gate signal line 17c is easy. When the TFT 11n is not operated, the off voltage Vgh may be applied to the gate terminals of all the switching TFTs 11f in the display screen 21. When the TFT 11n is operated, the potential of the gate signal line 17a may be applied to the gate signal line 17c. Therefore, it is not necessary to separately use the shift register 22c as shown in FIG. That is, the data of the shift register 22a may be output to the gate signal line 17c as it is, or a gate circuit may be added so that the potentials of all the gate signal lines 17c become the off voltage Vgh.

(Embodiment 8)
The driving method of the present invention will be described below. By multiplying the current flowing through the source signal line 18 by N, the influence of the parasitic capacitance 404 is eliminated, and a good image display with resolution can be realized. FIG. 64 is an explanatory diagram of another embodiment for increasing the current flowing through the source signal line. Here, for ease of explanation, as an example, N = 10 will be described (the current flowing through the source signal line is multiplied by 10).

  As shown in FIG. 64, an ON voltage Vgl is applied to the gate signal line 17a of the M pixel row (for ease of explanation, M = N / 2 = 10/2 = 5). The current writing state is set. At the same time, a current 10 times the predetermined current originally applied to the write pixel row 871a is applied to the source signal line 18. Here, the reason why the current is 10 times the predetermined current to be applied is to apply twice the current to the 5 pixel rows so that 5 × 2 = 10. Therefore, the writing pixel row 871a is displayed with double the luminance. In this way, since the display is performed with twice the luminance, the half area is set as the non-display area 312 by the driving method of FIG. When the non-display area 312 includes the writing pixel row 871b, current data different from the original display data is written, and the writing pixel row 871b is not displayed. If the above operations are shifted line by line, complete image display can be realized.

  FIG. 65 shows another embodiment. An ON voltage Vgl is applied to the gate signal line 17a of the M pixel row (M = 10 for ease of explanation), and the M pixel row is set in a current writing state. At the same time, a current 10 times the predetermined current originally applied to the write pixel row 871a is applied to the source signal line 18. The reason why the current is set to 10 times the predetermined current to be applied is to apply 10 times the current to 10 pixel rows so that 10 × 1 = 10. Therefore, the writing pixel row 871a is displayed with 1 × luminance. If the non-display area 312 is a writing pixel row 871b by the driving method of FIG. 29A, current data different from the original display data is written and the writing pixel row 871b is not displayed. If the above operations are shifted line by line, complete image display can be realized.

  This is a matter common to current programming methods such as FIGS. 6, 8, 42, 52, 53, and 54, but there is a problem that black display is difficult in the current programming method. For example, even if the white peak current flowing through the EL element 15 is 2 μA, the first gradation in the 64 gradation display is 2 μA / 64≈30 nA. It is difficult to charge and discharge the parasitic capacitance 404 such as the source signal line 18 in the 1H period with this minute current. Although the pixels 16 are formed or arranged in a matrix, only one pixel is shown in the drawing for easy explanation.

  In order to cope with this problem, in the present invention, a voltage source 401 for writing a black level voltage (current) to the source signal line 18 is formed or arranged. Specifically, the voltage source 401 is configured so that a DCDC converter generates a predetermined voltage and this voltage can be applied by the power source switching means 403 constituted by an analog switch or the like.

  A specific example of a signal waveform applied to the source signal line 18 is shown in FIG. In the first t2 period of the 1H period in which current programming is performed, a voltage Vb for turning off or substantially displaying black is applied to the source signal line 18 of the driving TFT 11b (the conversion TFT 11a in FIG. 6 and the like). This voltage is generated by the voltage source 401 and applied to the source signal line 18 by the power source switching means 403. Since the acquisition TFT 11c and the switching TFT 11d are on during the program period, the voltage Vb applied to the source signal line 18 becomes the terminal voltage of the capacitor 19, that is, the gate terminal voltage of the driving TFT 11b. Therefore, the first pixel in the 1H period is displayed in black (non-lighting state).

Originally, when the displayed image is black, the terminal voltage of the capacitor 19 is maintained as it is. When the actually displayed image is white display, the white display voltage Vw (which should be expressed as Iw in the case of current programming) is applied after the Vb voltage is applied, and this voltage (current) is applied to the capacitor. 19 and the 1H period ends. Here, for ease of explanation, the white display voltage Vw (current Iw) is applied because the actually displayed image is white display. However, as a matter of course, in the case of a natural image, the voltage held in the capacitor 19 is a voltage (current) between Vb and Vw.

  As shown in FIG. 66, by applying a signal to the source signal line 18 and driving the gate signal lines 17a and 17b, a good black display can be realized, and an image display such as FIG. 29 can be implemented.

  In the pixel configuration of FIG. 6, a good black display can be realized by applying the signal waveform of FIG. In the first t2 period of the 1H period in which the current program is performed, the voltage Vb for turning off or substantially displaying black is applied to the source signal line 18 of the conversion TFT 11a. This voltage is generated by the voltage source 401 and applied to the source signal line 18 by the power source switching means 403.

  Since the driving TFT 11b and the capturing TFT 11c are on during the program period, the voltage Vb applied to the source signal line 18 becomes the terminal voltage of the capacitor 19, that is, the gate terminal voltage of the conversion TFT 11a. Therefore, the first pixel in the 1H period is displayed in black (non-lighting state).

  As described above, when the displayed image is black, the terminal voltage of the capacitor 19 is held as it is. When the actually displayed image is white display, the white display voltage Vw (which should be expressed as Iw in the case of current programming) is applied after the Vb voltage is applied, and this voltage (current) is applied to the capacitor. 19 and the 1H period ends.

  The voltage source 401 (precharge circuit) illustrated in FIG. 42 or the like may be directly formed on the array substrate 49 by a low temperature polysilicon technique or the like. Since the EL element 15 has different element configurations and materials for R, G, and B, the voltage (current) that generates light is often different (rising voltage (current)). In order to cope with this characteristic, it is preferable that the precharge voltage can be set individually for R, G, and B, and that at least one of the three primary colors can be changed.

  The precharge time t2 for applying the Vb voltage needs to be 1 μsec or longer. The precharge time t2 for applying the Vb voltage is preferably 1% to 10% of 1H, and more preferably 2% to 8% of 1H.

  Further, it is preferable that the voltage to be precharged can be changed depending on the contents (brightness, definition, etc.) of the display screen 21. For example, when the user presses the adjustment switch or turns the adjustment volume, this change is detected and the value of the precharge voltage (current) is changed. You may comprise so that it may change automatically with the content and data of the image to display.

  42 and 64 to 66 have been described by exemplifying the current programming type pixel configuration as shown in FIG. 6, but the present invention is not limited to this. For example, the pixel configuration of the voltage programming method shown in FIGS. 67 and 68 is also effective. This is because the driving circuit and the signal processing circuit are simplified and a good black display can be realized by adopting a method in which voltages are simultaneously applied to a plurality of pixel rows.

As described above, the present invention can be applied to various pixel configurations. FIG. 69 shows an embodiment in which the P channel of the TFT 11 in FIG. Also in FIG. 69, the switching TFT 11d can be turned on / off by controlling the gate signal line 17, and it is needless to say that the image display of FIG. Also, the drive waveforms in FIGS. 28 and 35 are the same or similar, and thus description thereof is omitted. In FIG. 6, it is also effective to use only the driving TFT 11b and the capturing TFT 11c as N-channel TFTs. This is because the penetration voltage to the capacitor 19 is reduced and the holding characteristics of the capacitor are also improved.

  FIG. 69 shows a configuration including only the current source 402. That is, the voltage source 401 that performs precharging is not provided. However, when the parasitic capacitance 404 is relatively small or the 1H period is sufficiently long, black display can be sufficiently achieved without the voltage source 401. In addition, as described with reference to FIG. 29 and the like, in the case where the complete non-display area 312 is implemented, the voltage source 401 is almost unnecessary. If necessary, it may be configured as shown in FIG.

  FIG. 71 shows an embodiment in which the P channel of the TFT 11 in FIG. Also in FIG. 71, the TFT 11e and the like can be turned on and off by controlling the gate signal line 17, so that the image display of FIG. Also, the drive waveforms in FIGS. 28 and 35 are the same or similar, and thus description thereof is omitted.

  As described above, a satisfactory black display can be realized by applying the Vb voltage (Ib current) with the voltage source 401.

  When N = 10 or more and a high current pulse is applied to the EL element 15, the EL terminal voltage also increases. The EL element 15 has different rise voltages and gamma curves for R, G, and B. In particular, since the gamma curve of B is gentle, the terminal voltage of the EL element 15 tends to increase. When the terminal voltage is adjusted to the EL element 15 of a color (R, G, B color) having a high rising voltage and a gentle gamma curve, the power consumption increases.

  One method for solving this is a system in which the cathode shown in FIG. 22 is separated by R, G, and B. Note that R, G, and B need not have different cathode potentials. In particular, only one color cathode whose gamma curve is separated from the other colors may be separated. As another method, a configuration of separating the Vdd power supply voltage as shown in FIG. 72 is also effective. That is, the R color Vdd power supply is VddR, the G color Vdd power supply is VddG, and the B color Vdd power supply is VddB. By separating in this way, each of RGB can be adjusted by a separate power source, and even if the terminal voltages of the RGB EL elements 15 are different, the increase in power consumption is small.

  Note that R, G, and B do not need to have different Vdd potentials. In particular, only Vdd of only one color whose gamma curve is separated from other colors may be separated. Further, as shown in FIG. 73, the configuration of FIG. 22 may be combined. That is, R, G, and B, which are separated by R, G, and B, have different cathode potentials (R pixel is VsR, G pixel is VsG, and B pixel is VsB). In particular, only the cathode potential of only one color whose gamma curve is separated from the other colors may be separated. Further, the Vdd power supply voltage is separated. In this configuration, the R-color Vdd power supply is set to VddR, the G-color Vdd power supply is set to VddG, and the B-color Vdd power supply is set to VddB. Also in this case, it is not necessary to set different Vdd potentials for R, G, and B. In particular, only Vdd of only one color whose gamma curve is separated from other colors may be separated.

  72 and 73, the pixel 16 has the configuration shown in FIG. 6, but the present invention is not limited to this, and FIGS. 8, 9, 47, 52 to 56, 59 to 63, and FIG. Needless to say, the configuration of FIG. 67, FIGS. 69 to 71, FIG. 74, FIG.

  The problem of the present invention is that the current applied to the EL element 15 is instantaneous, but is N times larger than the conventional one. If the current is large, the life of the EL element may be reduced. In order to solve this problem, it is effective to apply a reverse bias voltage Vm to the EL element 15.

  Hereinafter, a method for applying the reverse bias voltage Vm will be described. In order to apply the reverse bias voltage Vm, it is necessary to individually control the gate terminals of the driving TFT 11b and the capturing TFT 11c in the configuration of FIG. That is, it is necessary to individually turn on and off the driving TFT 11b and the capturing TFT 11c. This control method will be described with reference to FIG.

  First, as shown in FIG. 76A, the take-in TFT 11c is turned on, and the switching TFT 11d is turned on (see also FIG. 6). Then, the reverse bias voltage Vm is applied to the a terminal of the EL element 15. The reverse bias voltage Vm is a voltage within a range of 5V to 15V, which is lower than the cathode voltage Vs.

  When the EL element 15 is lit, a voltage higher than 5V and less than 15V is applied to the terminal a with respect to the cathode voltage Vs. That is, the reverse bias voltage Vm is ideally applied with a voltage having the same absolute value and the opposite polarity to the voltage applied when the EL element 15 is lit. Actually, since it is difficult to apply a voltage having the same absolute value and the opposite polarity, a voltage two to three times the opposite polarity is applied. As described above, the EL element 15 hardly deteriorates by applying the reverse bias voltage Vm.

  Next, as shown in FIG. 76B, the switching TFT 11d is turned off and the driving TFT 11b is turned on. Then, the black display voltage Vb is written into the capacitor 19. This operation is illustrated in FIG. Next, as shown in FIG. 76C, the on / off state of the TFT 11 is the same as that in FIG. 76B, and the image display voltage (current) from the current source 402 is written into the capacitor 19. This operation is also described with reference to FIG. Finally, as shown in FIG. 76 (d), the driving TFT 11b and the capturing TFT 11c are turned off, the switching TFT 11d is turned on, and a current is supplied to the EL element 15 to light it.

  The above operation is shown in FIG. The reverse bias voltage Vm is applied to the source signal line 18 at the time t1 of the 1H period, the black display voltage Vb is applied during the next t2 period, and the image data Vw (Iw) is applied during the t3 period. Other operations are described with reference to FIG. 76 and are described with reference to FIGS. 28 and 29 such as a driving method, and thus the description thereof is omitted.

  In the configuration of FIG. 76, a reverse current flows through the EL element 15 when the current of the source signal line 18 is taken into the pixel 16. Therefore, when the EL element 15 is an organic electroluminescent element, it is possible to delay the electrochemical deterioration due to the oxidation-reduction reaction of organic molecules, as in the case where a reverse voltage is applied.

  FIG. 78 shows an energy diagram of a three-layer organic light-emitting device comprising an anode / hole transport layer / light-emitting layer / electron transport layer / cathode. The behavior of positive and negative carriers during light emission is shown in FIG. Electrons are injected from the cathode (cathode) into the electron transport layer, and holes are also injected from the anode (anode) into the hole transport layer. The injected electrons and holes move to the counter electrode by the applied electric field. At that time, carriers are trapped in the organic layer, or carriers are accumulated due to a difference in energy level at the interface of the light emitting layer.

When space charge is accumulated in the organic layer, the molecule is oxidized or reduced, and the generated radical anion molecule or radical cation molecule is unstable. It is known to cause an increase in voltage (Applied Physics
Letters, Vol.69, No.15, P.2160-2162, 1996). In order to prevent this, the device structure is changed as an example, and a reverse voltage is applied.

  In FIG. 78 (b), since a reverse current is applied, injected electrons and holes are drawn out to the cathode and the anode, respectively. Thereby, it becomes possible to extend the lifetime by eliminating the formation of space charge in the organic layer and suppressing the electrochemical degradation of the molecules.

  In FIG. 78, the description has been made on the three-layer type element. However, in the multilayer type element of four layers or more and the element of two layers or less, the electrochemistry of the organic film is caused by electrons and holes injected from the electrodes. It is the same that mechanical degradation occurs. Therefore, the lifetime can be extended by this embodiment regardless of the number of layers. Even in an element in which a plurality of materials are mixed in one layer, the electrochemical deterioration of molecules occurs in the same manner, which is effective.

  As described above, the feature of the present invention is that even if the pixel has a function of preventing deterioration of organic molecules and a function of flowing a bias current for preventing waveform rounding caused by stray capacitance parasitic on the source signal line, The display is possible without increasing the number of necessary transistors. That is, it is not necessary to increase the number of transistors for flowing a reverse current, which leads to an advantage that the aperture ratio of each pixel of the display device does not need to be reduced.

  FIG. 79 explains the application effect of the reverse bias voltage Vm. FIG. 79 shows the light emission luminance of the EL element 15 and the terminal voltage of the EL element when driven with a predetermined current. In FIG. 79, the dotted line b indicates the terminal voltage of the EL element 15 when the reverse bias voltage Vm is applied to the EL element 15. An alternate long and short dash line c indicates a terminal voltage of the EL element 15 when the reverse bias voltage Vm is not applied to the EL element 15. The solid line a indicates the emission luminance ratio (ratio when the initial luminance is 1) of the EL element 15 when the reverse bias voltage Vm is applied to the EL element 15 (solid line a).

  In FIG. 79, specifically, the EL element emits R light and is driven with a current density of 100 A / square meter. Sample B is continuously applying a current of 100 A / square meter for a time t. Although the terminal voltage increased at the lighting time of 1500 hours, the luminance dropped rapidly, and after about 2500 hours, only about 15% of the luminance was obtained with respect to the initial luminance.

  Sample A was pulse-driven at 30 Hz, applied a current density of 200 A / square meter at half time t2, and applied a reverse bias voltage of -14 V at half time t1 (that is, average per unit time). The emission brightness is the same for samples A and B). In sample A, the terminal voltage of the EL element 15 hardly changed as indicated by the dotted line b, and the lighting time when the luminance was 50% was 4000 hours.

  Thus, even if the reverse bias voltage Vm is applied, the terminal voltage of the EL element 15 does not increase, and the reduction rate of the light emission luminance is small. Therefore, long-life driving of the EL element 15 can be realized.

  FIG. 80 shows changes in the reverse bias voltage Vm and the terminal voltage of the EL element 15. This terminal voltage is when a rated current is applied to the EL element 15. FIG. 80 shows the case where the current flowing through the EL element 15 is a current density of 100 A / square meter, but the tendency of FIG. 80 is almost the same as the case where the current density is 50 to 100 A / square meter. Therefore, it is estimated that it can be applied in a wide range of current densities.

The vertical axis represents the ratio of the terminal voltage after 2500 hours to the terminal voltage of the initial EL element 15. For example, the terminal voltage when a current density of 100 A / square meter is applied at an elapsed time of 0 hours is 8 V, and the terminal voltage when a current density of 100 A / square meter is applied is 10 V at an elapsed time of 2500 hours. Then, the terminal voltage ratio is 10/8 = 1.25.

  The horizontal axis represents the ratio of the rated terminal voltage V0 to the product of the reverse bias voltage Vm and the time t1 when the reverse bias voltage is applied in one cycle. For example, if the time when the reverse bias voltage Vm is applied is ½ at 60 Hz, t1 = 0.5. In addition, if the terminal voltage (rated terminal voltage) when the current density of 100 A / square meter is applied at an elapsed time of 0 hour is 8 V and the reverse bias voltage Vm is 8 V, | reverse bias voltage × t 1 | / (Rated terminal voltage × t2) = | −8V × 0.5 | / (8V × 0.5) = 1.0.

  According to FIG. 80, when | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.0 or more, the terminal voltage ratio does not change (it does not change from the initial rated terminal voltage), and the reverse bias voltage Vm The effect of application is well demonstrated. However, since the terminal voltage ratio tends to increase when | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 or more, the reverse bias voltage is 1.0 or more, preferably 1.75 or less. The magnitude of the bias voltage Vm and the application time ratio (ratio between t1 and t2) may be determined.

  However, when bias driving is performed, it is necessary to alternately apply the reverse bias voltage Vm and the rated current. As shown in FIG. 79, when the average luminance per unit time of samples A and B is made equal, it is necessary to flow a higher current instantaneously when the reverse bias voltage Vm is applied than when the reverse bias voltage Vm is not applied. is there. Therefore, when the reverse bias voltage Vm is applied (sample A in FIG. 79), the terminal voltage of the EL element 15 must also be increased.

  However, in FIG. 80, the rated terminal voltage V0 is a terminal voltage satisfying the average luminance (that is, a terminal voltage for lighting the EL element 15) even in a driving method in which a reverse bias voltage is applied (in the specific example of this specification). Therefore, it is a terminal voltage when a current having a current density of 200 A / square meter is applied (however, since it is ½ duty, the average luminance in one cycle is the luminance at a current density of 200 A / square meter).

  In addition, although the above matter assumes the case where the EL element 15 is white raster display (when the maximum current is applied to the EL element of the entire screen), when displaying an image of the EL display device, It is a natural image and performs gradation display. Therefore, the white peak current of the EL element 15 (current flowing at maximum white display. In the specific example of the present specification, the average current density of 100 A / square meter) does not always flow.

  In general, when video display is performed, the current (current flowing) applied to each EL element 15 is white peak current (current flowing at the rated terminal voltage. According to a specific example of the present specification, a current density of 100 A / In the embodiment of FIG. 80, when displaying an image, the value on the horizontal axis needs to be increased by 0.2 times. Therefore, the magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or the ratio between t1 and t2) so that | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 0.2 or more. ) Should be determined. Preferably, the magnitude of the reverse bias voltage Vm and the application time ratio t1 are such that | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 × 0.2 = 0.35 or less. It is good to decide.

That is, since the value of 1.0 on the horizontal axis (| reverse bias voltage × t1 | / (rated terminal voltage × t2)) in FIG. 80 needs to be 0.2, an image is displayed on the display panel (this (Normally, the white raster will not be displayed at all times.) When the reverse bias voltage × t1 | / (rated terminal voltage × t2) is larger than 0.2, The reverse bias voltage Vm is applied for a predetermined time t1. Further, even if the value of | reverse bias voltage × t1 | / (rated terminal voltage × t2) increases, the terminal voltage ratio does not increase so much as shown in FIG. Therefore, considering that white raster display is performed, the upper limit value may be set so that the value of | reverse bias voltage × t1 | / (rated terminal voltage × t2) satisfies 1.75 or less.

(Embodiment 9)
Hereinafter, the reverse bias system of the present invention will be described with reference to the drawings. The present invention is basically applied with the reverse bias voltage Vm (current) during a period when no current flows through the EL element 15, but the present invention is not limited to this. For example, the reverse bias voltage Vm may be forcibly applied while a current is flowing through the EL element 15. In this case, as a result, no current flows through the EL element 15, and the non-lighting state (black display state) will occur. The present invention will be described mainly with respect to the application of the reverse bias voltage Vm in the pixel configuration of the current program, but is not limited to this. For example, if the TFT 11e is turned off in FIG. 68 and the reverse bias voltage Vm is applied to the anode of the EL element 15 as in FIG. 81, the reverse bias voltage Vm described below can be obtained even in the pixel configuration of the voltage programming method. Application can be easily realized. Therefore, the effects described in FIG. 80 and the like can be exhibited.

  FIG. 81 is an explanatory diagram of the reverse bias voltage application type driving method of the present invention. In FIG. 81, a switching TFT 11g for applying a reverse bias voltage Vm is arranged or formed in the pixel configuration of FIG. The gate terminal of the switching TFT 11g is connected to the control gate signal line 17d. The reverse bias voltage Vm is applied to the anode of the EL element 15 by turning on the switching TFT 11g.

  First, as shown in FIG. 1 (a1), when the ON voltage Vgl is applied to the gate signal line 17a, the driving TFT 11b and the capturing TFT 11c are turned ON. Then, as shown in FIG. 1A2, the program current Iw flows from the source driver 14 to the take-in TFT 11c and the like, and the capacitor 19 is current-programmed. Although not limited to N times, here, for ease of explanation, it is assumed that a current of N times is programmed and a current Id is allowed to flow through the EL element 15 for a period of 1 F / N.

  Next, as shown in FIG. 1B1, an off voltage Vgh is applied to the gate signal line 17b, and the driving TFT 11b and the capturing TFT 11c are turned off. When the on-voltage Vgl is applied to the gate signal line 17b at the same time (but not simultaneously), the switching TFT 11d is turned on. Then, as shown in FIG. 1 (c2), the power source Vdd flows the current programmed current Id through the conversion TFT 11a to the EL element 15, and the EL element 15 emits light as shown in FIG. 1 (c1). To do. If the program conversion efficiency is 100%, the light emission luminance is about N times as high.

  The light emission period is 1 F / N. During the remaining period (1F (N−1) / N), the switching TFT 11d is in an OFF state, and the EL element 15 is not lit (black display). Since no current flows through the EL element 15 at the time of non-lighting, complete black display can be realized. Further, since the white peak current is large during light emission, the light emission luminance is also high. Therefore, with the driving method of the present invention, a very high contrast display can be realized.

When black display is realized and used in the case where 1 time of current flows through the EL element 15 (conventional driving method) in all of the 1F period, the black display current needs to be programmed in the capacitor 19. However, in the current driving method, the current value at the time of black display is small, so that there is a problem that black floating occurs due to large influence of parasitic capacitance and insufficient resolution. In addition, it is also affected by the penetration voltage from the gate signal line 17. Due to these problems, the EL element 15 is slightly turned on even in the black display portion, and the contrast becomes very poor.

  In the system of the present invention, since no current flows completely through the EL element 15 during the period of (1F (N−1) / N), complete black display can be realized. In other words, black float does not occur. Therefore, high contrast display can be realized without performing the precharge for black display described in FIG.

  Needless to say, the method illustrated in FIG. 81 may be added to the method illustrated in FIG. Further, the realization of high contrast display is similarly effective in the pixel configuration of the voltage program as shown in FIG. That is, by performing 1F / N pulse driving, no current flows through the EL element 15 during the period of (1F (N−1) / N), and high contrast display can be realized.

  As shown in FIG. 1D1, an on-voltage is applied to the gate signal line 17d to turn on the switching TFT 11g. At this time, the switching TFT 11d is turned off. By turning on the switching TFT 11g, the anode of the EL element 15 (depending on the pixel configuration, the reverse bias voltage Vm may be applied to the cathode of the EL element 15. The reverse bias voltage Vm is a positive voltage. The reverse bias voltage Vm (reverse bias current Im flows) can be expressed as the EL element 15. Since the EL element 15 can be regarded as a capacitor in terms of circuit, a current flows in an alternating manner by applying the reverse bias voltage Vm. Also, the accumulated charge is discharged). The application time t1 is configured to satisfy the state of FIG. 80 (FIG. 1 (d2)).

  The period in which the reverse bias voltage Vm is applied is preferably a period in which the current Id does not flow through the EL element 15. This is not impossible, but if the current Id is flowing, the reverse bias voltage Vm is short-circuited.

  In FIG. 1 (d1), the period for applying the reverse bias voltage Vm is one of 1F. However, the period is not limited to this, and is not limited to this. The reverse bias voltage Vm may be applied to the EL element 15 in three or more times).

  This control can be easily performed because the on / off voltage may be applied to the gate signal line 17d at an arbitrary timing during the period in which the off voltage is applied to the gate signal line 17b. Then, the sum of these ON times may be set to the time t1 described in FIG.

  In addition, the period 1F (1-1 / N) in which no current flows through the EL element 15 may be divided into a plurality of periods. By dividing into a plurality, the occurrence of flicker is suppressed. When the period 1F (1-1 / N) is divided into a plurality of periods, the reverse bias voltage Vm may be applied during that period. However, it is not necessary to apply the reverse bias voltage Vm to all of the divided periods 1F (1-1 / N).

  As shown in FIG. 79, a driving method in which no reverse bias voltage is applied and no current flows through the EL element 15 will be corrected (or supplemented) based on the contents described with reference to FIG. The time t1 described in FIG. 80 is the time when the reverse bias voltage Vm is applied. The time t2 is a time during which a current is applied to the EL element 15.

Note that the reverse bias voltage Vm does not have to be a fixed value (Vm = −8 V) in terms of DC. That is, the reverse bias voltage Vm may be a sawtooth waveform signal or a pulse-like waveform signal. Moreover, the signal waveform of a sine wave may be sufficient. In this case, the reverse bias voltage is an integrated waveform or an effective value. Also, although the application time t1 is unclear, the integration of the Vm voltage, the effective value may be a rectangular waveform, and the time when the rectangular waveform is applied may be t1.

  For example, assume that the waveform of the reverse bias voltage is the voltage waveform (triangular wave) illustrated in FIG. 82A, the maximum amplitude value is 16 V, and the application time is t1 = 100 μsec. In this case, as shown in FIG. 82B, this is equivalent to a voltage waveform having a maximum amplitude value of 8 V and an application time of t1 = 100 μsec. Further, as shown in FIG. 82 (c), the processing may be performed on the assumption that the maximum amplitude value is 16V and the application time is equivalent to a voltage waveform of t1 = 50 μsec. The above matters also apply to the positive voltage applied to the EL element 15.

  The same applies to the current Id flowing through the EL element 15. That is, the current (voltage) that flows through the EL element 15 may be a sine waveform instead of a direct current. In this case, too, if converted to a direct current effective value and converted to the rectangular wave application period t2. Good.

  The period during which the reverse bias voltage Vm is applied may be any period other than the period during which the ON voltage is applied to the gate signal line 17a (normally, 1H period: program period), as shown in FIG. 83 (a).

  Further, since the reverse bias voltage Vm may be applied during the period when the current Id is not applied to the EL element 15, as shown in FIG. 83B, the period during which the ON voltage is applied to the gate signal line 17a (programming) The reverse bias voltage Vm may be applied in a period including the period (FIG. 83B shows a period in which the current Id is applied to the EL element 15 (an ON voltage is applied to the gate signal line 17b). The reverse bias voltage Vm is applied in addition to the period of time).

  The matters relating to the application time, the application method, the application timing, etc., of the reverse bias voltage Vm described with reference to FIGS. 1 and 83 are also applied to other embodiments.

  As described above, in the present invention, the non-lighting period (non-display area) 312 is provided in the 1F period. By providing this non-lighting period, the moving image display performance is improved, and the EL element 15 is provided in the non-lighting period. A reverse bias voltage Vm can be applied. Therefore, the EL element 15 does not deteriorate and the terminal voltage does not increase, so that the power supply voltage Vdd can be set low.

  FIG. 83 shows a configuration in which the reverse bias voltage Vm is applied immediately before the EL element 15. However, as shown in FIG. 84, the reverse bias voltage Vm is applied to the EL element 15 via the switching TFT 11d as shown in FIG. A configuration in which the bias voltage Vm (current −Im) is applied is also exemplified.

  By applying an on voltage to the gate signal line 17d, the switching TFT 11g is turned on, and the reverse bias voltage Vm is applied. At the same time, the reverse bias voltage Vm can be applied to the EL element 15 by turning on the switching TFT 11d. With the configuration of FIG. 84, the application of the reverse bias voltage Vm can be controlled by both the switching TFTs 11g and 11d, so that the control becomes easy and the flexibility is improved.

  A turn-on voltage is applied to the gate signal line 17 when the corresponding pixel is selected. The off voltage is applied during the non-selection period. Accordingly, the off-voltage can be used as the reverse bias voltage because the off-voltage is applied to the gate signal line in most of the 1F period.

The off voltage is normally a potential lower than the cathode voltage in order to completely turn off the TFT (of course, the opposite is true when the TFT is a P-channel). In particular, when the TFT is amorphous silicon, the off-voltage is usually set to be quite low.

  In the configuration of FIG. 85, the driving TFT 11b and the capturing TFT 11c connected to the gate signal line 17a are N-channel TFTs. Therefore, the driving TFT 11b and the take-in TFT 11c are turned on at the off voltage Vgh and turned off at the on voltage Vgl. During most of the period of 1F, the ON voltage Vgl is applied to the gate signal line 17b. This ON voltage Vgl is set as a reverse bias voltage Vm (Vgl = Vm).

  The switching TFT 11g is also controlled by the voltage applied to the gate signal line 17d, as in the previous embodiment. Note that, since the voltage applied to the gate signal line 17d controls on / off of the switching TFT 11g, the voltage to be applied is not limited to Vgh and Vgl, and other arbitrary voltages are used. Can be used.

  When the switching TFT 11g is turned on, the ON voltage Vgl applied to the gate signal line 17a is applied to the EL element 15. Therefore, the reverse bias voltage Vm can be applied to the EL element 15. The configuration of FIG. 85 does not require a signal line for supplying the reverse bias voltage Vm as shown in FIG. 84, so that the pixel aperture ratio can be improved. In FIG. 85, a voltage applied to the gate signal line 17b may be applied to the EL element 15 (the switching TFT 11d needs to be configured such as an N channel).

  85 shows a configuration in which the voltage of the gate signal line 17 is a reverse bias voltage. FIG. 86 shows a configuration in which the voltage applied to the source signal line 18 is a reverse bias voltage of the EL element 15. When the reverse bias voltage Vm is applied to the source signal line 18 at the timing when the switching TFT 11 g is turned on, the reverse bias voltage Vm can be applied to the EL element 15 through the source signal line 18. The timing and the like have been described with reference to FIG.

  When the time for applying the reverse bias voltage Vm is longer than the period in which the current is applied to the EL element 15, the voltage charged in the EL element 15 is discharged as shown in FIG. It is also effective to short-circuit between the anode terminal and the cathode terminal of the EL element 15. By short-circuiting in this way, holes accumulated in the hole transport layer of the EL element 15 are extracted, and electrons accumulated in the electron transport layer are also extracted, so that deterioration of the EL element can be suppressed. . Incidentally, it goes without saying that the matters relating to the application time, application method, application timing, etc. of the reverse bias voltage Vm described in FIG. 83, FIG.

  In FIG. 87, each TFT is configured by the P channel, but in FIG. 88, the configuration of FIG. 87 is changed to the N channel. 88, when the switching TFT 11g is turned on, the anode terminal and the cathode terminal of the EL element 15 are short-circuited, and the Vdd voltage is applied to both terminals. During this period, holes accumulated in the hole transport layer of the EL element 15 are extracted, and electrons accumulated in the electron transport layer are also extracted, so that deterioration of the EL element can be suppressed. As in FIG. 87, it goes without saying that the matters relating to the application time, application method, application timing, etc. of the reverse bias voltage Vm described in FIG. 83, FIG.

  Further, the reverse bias voltage Vm can be applied to the EL element 15 by changing the control direction in which the current flows. FIG. 89 is a configuration diagram thereof. In FIG. 89, reference numeral 402 denotes a constant current source.

In FIG. 89, when the switching TFT 11g is on, the switching T
A current in the same direction as the constant current source 402 flows through the FT 11 g, and a forward voltage is applied to the EL element 15. On the other hand, when the switching TFT 11g is off, the EL element 15 and the constant current source 402 form a loop, so the direction of the current flowing through the EL element 15 is reversed. That is, by arranging or forming the constant current source 402, the reverse bias voltage Vm can be easily applied to the EL element 15 under the control of the switching TFT 11g. The timing of the gate signal line 17 at this time is shown in FIG. The on-voltage is applied to the gate signal line 17d during a period other than the period when the gate signal line 17a is selected. In this way, holes accumulated in the hole transport layer of the EL element 15 are extracted, and electrons accumulated in the electron transport layer are also extracted, thereby suppressing deterioration due to oxidation of the hole transport material and reduction of the electron transport material. become able to.

  FIG. 91 shows a configuration in which the switching TFT 11g is an N channel, the switching TFT 11g is turned off when the switching TFT 11d is turned on, and the switching TFT 11g is turned on when the switching TFT 11d is turned off. . When the switching TFT 11d is on, the EL element 15 is lit, and when the switching TFT 11g is on, the reverse bias voltage Vm is applied to the EL element 15.

  It is effective to set the reverse bias voltage Vm to a voltage lower than the cathode voltage Vk. However, if a reverse bias voltage Vm is separately generated, a generation circuit is required. For this problem, a flying capacitor is formed in FIG. The flying capacitor 1001 may be disposed (formed) for each pixel, or one circuit may be disposed (formed) on the panel.

  The flying capacitor 1001 is operated by controlling the gate signal lines 17e and 17f. The gate signal line 17e and the gate signal line 17f are operated in opposite phases.

  First, an on voltage is applied to the gate signal line 17e, the TFTs 11i and 11j are turned on, and a Vdd voltage is applied to the capacitor 19b. At this time, a turn-off voltage is applied to the gate signal line 17f, and after charging the capacitor 19b, the TFTs 11h and 11k are turned off.

  Next, an off voltage is applied to the gate signal line 17e to turn off the TFTs 11i and 11j, and an on voltage is applied to the gate signal line 17f to turn on the TFTs 11h and 11k. Then, the Vdd voltage charged in the capacitor 19 b has an opposite phase, and the −Vdd voltage is applied to the EL element 15.

  With the configuration described above, an antiphase Vm voltage (Vm = −Vdd) can be generated. Therefore, the supply wiring for the Vm voltage is not necessary.

  The above embodiment has been described mainly by exemplifying the current programming type pixel configuration described in FIG. 6, but the present invention is not limited to this, and the current mirror pixel configuration shown in FIG. Needless to say, the bias voltage Vm can be applied. The operation is omitted because the configuration described in FIG. 81 can be applied as it is. Further, as shown in FIG. 94, it goes without saying that a reverse bias voltage can be applied even in a pixel configuration of voltage programming. The same applies to FIG. 68 and the like. Therefore, a configuration or a system in which a reverse bias voltage is applied to the EL element 15 at the time of non-lighting can be applied even with a voltage programmed pixel configuration.

In FIG. 71, the number of TFTs 11 constituting the pixel is five. However, in FIG. 6A, there are four. Therefore, the configuration of FIG. 6A has an advantage that the aperture ratio can be increased and the rate of occurrence of pixel defects is small because the number of TFTs 11 constituting the pixel 16 is smaller by one.

  FIG. 74 also shows a current programming pixel configuration. A current program can be performed by applying an ON voltage to the gate signal line 17a. Further, a programmed current can be supplied to the EL element 15 by applying an off voltage to the gate signal line 17b and applying an on voltage to the gate signal line 17b.

  In the configuration of FIG. 74 as well, by applying an on voltage or an off voltage to the gate signal line 17c, the current flowing through the EL element 15 can be controlled, and the driving method or display state illustrated in FIG. 29 and the like can be realized.

  Although the TFT 11e is added in FIG. 74, it goes without saying that the image display of FIG. 29 and the like can also be realized by deleting the TFT 11e, operating the gate signal line 17b, and controlling the on / off state of the switching TFT 11d. Yes.

  FIG. 95 also shows a current programming pixel configuration. A current program can be performed by applying an ON voltage to the gate signal line 17a. Further, a programmed current can be supplied to the EL element 15 by applying an off voltage to the gate signal line 17b and applying an on voltage to the gate signal line 17b.

  Also in the configuration of FIG. 95, the on / off state of the switching TFT 11d can be realized by applying an on voltage or an off voltage to the gate signal line 17c, so that the current flowing through the EL element 15 can be controlled. Therefore, the driving method or display state illustrated in FIG. 29 and the like can be realized.

  FIG. 61 shows an example of the pixel configuration of the voltage program. In the present invention, a predetermined light emission luminance is obtained by controlling the application time of a current flowing in an EL element in a predetermined time of one field or one frame (1F, of course, 2F or more can be considered as one segment). Is the method. That is, this is a method of obtaining a predetermined luminance by making the current passed through the EL element higher than a predetermined luminance and shortening the ON time for the luminance higher than the predetermined luminance.

  FIG. 68 also shows a pixel configuration by a voltage program. In FIG. 68, 19a is a threshold detection capacitor (capacitor), and 19b is an input signal voltage holding capacitor (capacitor).

  In step 1 (section 1), since all the TFTs 11a to 11e are turned on and the driving transistors are once turned on, a current value shift occurs due to variations in threshold values.

  In step 2 (section 2), the current value of the driving TFT 11a becomes 0 by turning off the TFT 11c and TFT 11e while keeping the TFT 11b and TFT 11d on, so that the threshold value of the driving TFT 11a becomes the threshold value. It is detected by the detection capacitor 19a.

In step 3 (section 3), the TFT 11b and TFT 11d are turned off and the TFT 11c and TFT 11e are turned on to hold the input signal voltage of the data signal line in the input signal voltage holding capacitor 19b and at the same time the driving A signal voltage obtained by adding a threshold to the input signal voltage is applied to the gate of the TFT 11a for driving the EL element 15 to emit light. Since the driving TFT 11a operates in the saturation region, a current proportional to the square of the voltage value obtained by subtracting the threshold value from the gate voltage flows, but the threshold value is already applied to the gate voltage by the threshold detection capacitor 19a. As a result, the threshold value is canceled as a result. Therefore, even if the threshold value of the driving TFT 11a varies, a constant current value always flows to the EL element 15 as shown in the simulation result.

  In step 4 (section 4), when the pixel 16 enters the non-selection period, the TFT 11b and the TFT 11d are turned off, the TFT 11e is kept on, and the TFT 11c is turned off, and is held in the input signal voltage holding capacitor 19b. Since the input signal voltage and the threshold voltage held by the threshold detection capacitor 19a are applied to the gate of the driving TFT 11a, a current flows through the EL element 15 and the light continues to be emitted.

  As described above, in order to detect the threshold value of the driving transistor more accurately, the period of the first step is set to 2 μsec or more and 10 μsec or less, and the period of the second step is set to 2 μsec or more and 10 μsec or less. is necessary. This is to ensure sufficient writing or operation time. However, if it is too long, the original voltage programming time is shortened and stability is lost.

  Therefore, the voltage programming method of FIG. 61 is also effective for implementing the driving method or display device of the present invention. In FIG. 61, the switching TFT 11d can be turned on and off by controlling the gate signal line 17b. Therefore, the current flowing through the EL element 15 can be made intermittent. Also in FIG. 68, the TFT 11e can be on / off controlled by controlling the gate signal line 17c. Therefore, the display states shown in FIGS. 29 and 33 can be realized.

  In addition, the driving method of lighting for a period of 1 / N by controlling the on / off state of the TFT 11e by multiplying the current flowing through the EL element 15 by N (not limited to N times or 1 / N). It is clear that can be realized. That is, the present invention is not limited to the pixel configuration of the current program of FIG. 6, and the driving method of the present invention can be realized even with the pixel configuration of the voltage program such as FIG. 68. Therefore, the matters described in this specification can be applied to the pixel configuration or device described or illustrated in this specification.

  Similarly, FIGS. 67 and 75 also show the pixel configuration of the voltage program. 67 and 75, the TFT 11e can be turned on and off by controlling the gate signal line 17b. Therefore, the current flowing through the EL element 15 can be made intermittent. Therefore, the display states shown in FIGS. 29 and 33 can be realized. Therefore, an animation effect can be easily realized. Various image displays can be realized. Other items or operations are the same as or similar to those in FIG. Needless to say, the above items can also be applied to the reverse bias voltage Vm application method described with reference to FIGS.

  As a problem of the method of applying N times the pulse voltage, there is a problem that the current flowing through the EL element 15 increases and the EL element 15 is likely to deteriorate. Further, when N = 10 or more, there is a problem that the terminal voltage of the EL element 15 required when a current flows becomes high and power efficiency is deteriorated. However, this problem occurs when the current flowing through the EL element is large as in white display. A solution to this problem will be described with reference to FIG. 96A, taking the pixel configuration of FIG. 6 as an example.

  As shown in FIG. 96A, when the current Idd to the EL element 15 is flowing, the Vdd voltage (power supply voltage) is the source-drain voltage Vsd of the driving TFT 11a and the terminal voltage Vd of the EL element 15. Divided pressure. At this time, if the Idd current is large, the Vd voltage also increases.

  When the Vdd voltage is sufficiently high, a current (Idd) equal to the current Iw programmed in the driving TFT 11 a flows in the EL element 15. Therefore, as shown by the solid line in FIG. 97, the currents Iw and Idd are equal or substantially linear (proportional). The linear relationship means that a penetration occurs in the capacitor 19 due to a signal applied to the gate signal line 17 and the like, and Idd = Iw is not established.

  In the present invention, the Vdd voltage is used at such a low voltage that Idd and Iw cannot maintain a linear (proportional) relationship. That is, the necessary relationship is Vsd + Vd> Vdd. Furthermore, it is preferable that Vd> Vdd.

  For example, as an example, assume that N = 10 and the Iw current necessary for maximum white display is 2 μA. In this state, if the Idd current is 2 μA, Vd = 14V in the G color EL element, and the Vdd voltage at this time is set to 14V or less. Alternatively, at this time, if Vsd = 7V, Vd + Vsd = 14V + 7V = 21V <Vdd = 21V.

  When driven in this state, the relationship between the currents Idd and Iw is as shown by the dotted line in FIG. 97, and in the maximum white display, the relationship between Iw and Idd is not a linear relationship (nonlinear relationship, range A in FIG. 97). ). However, the linear relationship (range B in FIG. 97) is maintained in black display or gray display (region where display luminance is relatively low).

  In the region A, the current flowing through the EL element 15 is limited, and a large current that deteriorates the EL element 15 does not flow. Further, when the Iw current is increased in the area A, the change rate is small but the Idd current increases, so that gradation display can be realized. However, since it is non-linear in the area A, gamma conversion is necessary. For example, if the image display is 64 gradation display, the input image data 64 gradation data is converted into a table, converted into 128 gradations or 256 gradations, and applied to the source driver 14.

  In the region A, the Vsd voltage of the driving TFT 11a and the Vd voltage of the EL element 15 are divided, and the terminal voltage Va of the EL element 15 is determined. At this time, as a matter to be noted, the EL element 15 is formed uniformly by vapor deposition (or formed by application by an ink jet technique or the like), so that it is formed uniformly. Therefore, the EL terminal voltage Va becomes a uniform value within the surface of the display screen 21. Therefore, the characteristics of the driving TFT 11a vary and are corrected by the terminal voltage Va of the EL element 15. As a result, by reducing the Vdd voltage as in the present invention, variations in characteristics of the driving TFT 11a can be absorbed, and low power consumption can be realized by reducing the Vdd voltage. Even when N is large, a high voltage is not applied to the EL element 15.

  The EL element 15 can be formed not only by a vapor deposition technique and an ink jet technique, but also by a stamp technique in which an inked stamp is applied to paper and printed.

  First, a portion to be a stamp is formed. A groove pattern having the same shape as the light emitting region of the organic EL element is formed on the Si substrate by a semiconductor process, and a material for doping the organic EL material is filled in the groove to obtain a stamp. On the other hand, an organic EL material to be an electrode or a light emitting layer is formed on the glass substrate on which the organic EL element is formed.

  Next, the stamp and the glass substrate to which the material for the organic EL element is attached are exactly overlapped. While maintaining this state, heat treatment is performed at + 100 ° C. to + 200 ° C. for about 10 minutes. By doing so, the doping material embedded in the stamp groove evaporates and diffuses into the light emitting layer of the organic EL element. After that, a stamp in which a doping material corresponding to the color is embedded is sequentially applied to the organic EL element, and RGB is separately applied. By using this stamp technology, an EL element 15 having a rectangular pattern of 10 μm or a pattern having a line width of 10 μm can be easily formed.

  In addition, a current is applied to the EL element 15 at 1 / N of the period of 1F, the applied current is higher than a predetermined luminance, and a luminance higher than the predetermined is obtained by shortening the ON time to obtain the predetermined luminance. It was supposed to be. However, the present invention is a method of setting the average brightness within a certain period to a predetermined value. Therefore, it is not limited to 1F (1 field or 1 frame). For example, the display state of FIG. 33 (c1) continues for 2F, the display state of FIG. 33 (c2) continues for 3F, or the states of FIG. 33 (c1) and FIG. 33 (c2) are alternately repeated. Also good. Finally, it may be driven so as to obtain a desired average luminance at 5F.

  Therefore, the technical idea of the present invention is to generate an ON state and an OFF state of the EL element 15 within a certain period, and alternately repeat the ON state and the OFF state. It is a method to obtain. Control is realized by controlling the on / off voltage of the gate signal line 17.

  Although a current N times the predetermined current is supplied to the source signal line 18 and a current N times the predetermined current is supplied to the EL element 15 for 1 / N period, this cannot be realized in practice. This is because the signal pulse applied to the gate signal line 17 actually penetrates the capacitor 19 and a desired voltage value (current value) cannot be set in the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set for the capacitor 19. For example, even if it is driven to set a current value 10 times, only about 5 times the current is set in the capacitor 19. Even if N = 10, the current that actually flows through the EL element 15 is the same as in the case of N = 5. Therefore, the present invention is a method of setting a current value N times and driving so that a current proportional to or corresponding to N times flows to the EL element 15 (however, the driving method described in FIG. 97 is also implemented). Limited is difficult). Alternatively, it is a driving method in which a current larger than a desired value is applied to the EL element 15 in a pulse shape.

  In FIG. 29 and the like, the non-display area 312 does not need to be completely in a non-lighted state. There is no problem in practical use even if weak light emission or light image display is present. That is, it should be interpreted that the display luminance is lower than that of the image display area 311. In addition, the non-display area 312 includes a case where only one or two colors of the R, G, and B image displays are in a non-display state.

  In each pixel configuration (for example, FIG. 61, FIG. 70A, FIG. 95), even if the gate terminal of the switching TFT 11d is configured to be able to directly apply an on / off voltage, Intermittent operation is possible. Further, even if the gate terminal of the TFT 11e in FIG. 60, the conversion TFT 11a in FIG. 8, and the gate terminal of the driving TFT 11b in FIG. 9 can be directly applied with an on / off voltage, the current flowing through the EL element 15 is intermittently operated. Can be made. That is, the display state shown in FIG. 29 can be implemented by controlling the gate terminal of the TFT that applies current to the EL element 15.

(Embodiment 10)
In addition, as in the display method of FIG. 43, a display method that switches between odd-numbered pixel rows and even-numbered pixel rows (or every plurality of pixel rows) for each predetermined field (frame) can be applied to a stereoscopic image display apparatus or method. . Hereinafter, the stereoscopic display device of the present invention will be described with reference to FIGS.

First, in the display method of the present invention, the image display area 311 and the non-display area 312 are basically configured in pixel row units (pixel row direction). Therefore, when displaying as in FIG. 43, it is necessary to convert the vertical and horizontal directions, but this conversion is easy. This is because the rows and columns of the image data stored in the memory may be switched. If the vertical and horizontal directions are converted, the display state shown in FIG. 98 (a1) is obtained. That is, the scanning direction of the display panel is the arrow direction indicated by A, but the image is on the screen on the screen and the screen is below the screen as shown in FIG. 98 (a1). Therefore, it appears to the user of the display panel as if scanning from the top to the bottom of the screen.

The display screen 21 of the display panel displays the image of the right eye on the odd pixel columns (rows) from the left,
The left-eye image is displayed in the even-numbered pixel column (row). The image display is synchronized with observation glasses 852 that are synchronized with the display panel. The observation glasses 852 include two liquid crystal panels that function as shutters 851.

  In the first field (first frame), as shown in FIG. 98 (a1), the odd-numbered pixel columns from the left (actually odd-numbered pixel rows) become the image display area 311 and the even-numbered pixel columns from the left (actually) The even-numbered pixel row) is the non-display area 312. In synchronization with the display state of FIG. 98 (a1), the left eye shutter 851L of the observation glasses 852 is closed, and the right eye shutter 851R of the observation glasses 852 is opened. Therefore, the observer sees the image of FIG. 98 (a1) with only the right eye.

  In the second field (second frame) next to the first field (first frame), as shown in FIG. 98 (a2), even-numbered pixel columns (actually even-numbered pixel rows) from the left are image display areas 311. Thus, an odd-numbered pixel column from the left (actually an odd-numbered pixel row) becomes the non-display area 312. In synchronization with the display state of FIG. 98 (a2), the right eye shutter 851R of the observation glasses 852 is closed and the left eye shutter 851L of the observation glasses 852 is opened. Therefore, the observer sees the image of FIG. 98 (a2) with only the left eye.

  By repeating the above operations alternately, stereoscopic image display can be realized by making the eyeglass-type shutter 851 used by the observer and the image display state appear alternately and synchronously.

  In order to realize stereoscopic image display without using the shutter 851, a prism 861 may be disposed on the light emission side of the display panel as shown in FIG. The A part of the prism 861 is arranged so as to correspond to the image display area 311 at a certain display timing, and the B part of the prism 861 is arranged so as to correspond to the non-display area 312 at the above display timing. In this manner, by arranging the prism 861, it is possible to make an image of an odd-numbered pixel row enter the right eye of the viewer and an image of an even-numbered pixel row enter the left eye of the viewer. Note that an optical coupling material 862 such as ethylene glycol is disposed between the prism 861 and the display panel and optically coupled.

  In FIG. 98, the switching means 852 is glasses, but is not limited to this. Any light source can be used as long as it can control light incident on the right eye and light incident on the left eye of the observer. For example, a goggle type is exemplified. Further, an example in which the switching unit 852 and the display panel are integrated (head mounted display) is exemplified. The shutter 851 is not limited to the liquid crystal display panel, and may be a mechanical one such as a camera shutter or a rotary filter. In addition, examples incorporating a polygon mirror, a shutter using PLZT, a shutter using electroluminescence, and the like are also exemplified.

As described above, stereoscopic display can be realized by using the display method of FIG. 43 for the display image of one display panel. The apparatus or method of FIGS. 98 and 99 displays different images for each of a plurality of pixel rows (columns) or for each of odd-numbered pixel rows (columns) and even-numbered pixel rows (columns). It is not limited only to stereoscopic display. For example, it may be used for the purpose of simply displaying two images superimposed. In addition, using the EL display device of the present invention,
Needless to say, it is particularly effective to implement the driving method of the present invention.

  In addition, although the element which drives each pixel was TFT11, it is not limited to this. For example, the pixel 16 can be configured by a combination of a thin film diode (TFD), and the current flowing through the EL element 15 can be intermittently operated by operating one terminal voltage level of the diode. The same applies to switching elements such as varistors and thyristors.

  For example, if the driving TFT in the conversion TFT 11a of FIG. 6 is taken as an example, an N-channel or P-channel bipolar transistor may be used as shown in FIG. Further, as shown in FIG. 100B, an N-channel or P-channel MOS transistor may be used. Further, a phototransistor or a photodiode may be used as shown in FIG. 100C, and a thyristor element or the like may be used as shown in FIG. This means that the present invention can also be applied to switching elements constituting other pixels.

  The TFT element can be used for either the P channel or the N channel. Further, the position of the EL element 15 is not limited to the position as shown in FIG. For example, FIG. 96A shows a connection state between the conversion TFT 11a and the EL element 15 shown in FIG. An example of this modification is the configuration shown in FIG. Further, the configuration of FIGS. 96C and 96D in which the driving TFT is an N channel is also exemplified. These matters apply not only to the conversion TFT 11a but also to switching elements constituting other pixels.

  The switching element such as TFT is preferably formed of a low-temperature polycrystalline Si-TFT, but may be an amorphous silicon TFT. In particular, when the current flowing through the EL element 15 is 1 μA or less, it is sufficient in terms of characteristics to be formed by amorphous silicon technology. In addition, a gate driver circuit, a source driver circuit, and the like may be formed using elements using amorphous silicon technology.

  Further, the configuration of the gate driver 12 shown in FIGS. 10, 46, 47, and 49 is not limited to this (in FIG. 10 and the like, the ST signal is sequentially shifted in synchronization with the clock (serial processing). For example, it may be a parallel input that determines the on / off state of each gate signal line at once (the on / off logic of all the gate signal lines is equal to the number of controllers or gate signal lines 17 at a time. Output configuration, etc.).

FIG. 101 is a configuration diagram of an organic EL module. A control IC 101 and a power supply IC 102 are mounted on the printed circuit board 103. The printed circuit board 103 and the array substrate 49 are electrically connected by a flexible substrate 104. The power supply voltage, current, control signal, and video data are supplied to the source driver 14 and the gate driver 12 of the array substrate 49 through the flexible substrate 104.

  At this time, the problem is the control signal of the gate driver 12. It is necessary to apply a control signal having an amplitude of at least 5V to the gate driver 2. However, since the power supply voltage of the control IC 101 is 2.5V or 3.3V, the control signal cannot be directly applied from the control IC 101 to the gate driver 12.

In response to this problem, the present invention applies a control signal for the gate driver 12 from the power supply IC 102 driven at a high voltage. Since the power supply IC 102 also generates the operating voltage of the gate driver 12, it is a matter of course that a control signal having an optimum amplitude can be generated for the gate driver 12.

  In FIG. 102, the control signal of the gate driver 12 is generated by the control IC 101, the level is once shifted by the source driver 14, and then applied to the gate driver 12. Since the drive voltage of the source driver 14 is 5 to 8 V, the 3.3 V amplitude control signal output from the control IC 101 can be converted to 5 V amplitude that the gate driver 12 can receive.

  77 and 103 are explanatory views of the display module device of the present invention. FIG. 103 shows a configuration in which a built-in display memory 151 is provided in the source driver 14. The built-in display memory has a capacity of 8 color display (1 bit for each color), 256 color display (RG is 3 bits, B is 2 bits), and 4096 color display (RGB is 4 bits each). When the 8-color, 256-color, or 4096-color display is performed and a still image is displayed, the driver controller disposed in the source driver 14 reads the image data in the built-in display memory 151, so that ultra-low power consumption can be realized. . Of course, the built-in display memory 151 may be a multi-color display memory having 260,000 colors or more. Also, the image data in the built-in display memory 151 may be used for moving images.

  The image data in the built-in display memory 151 may be stored after the error diffusion process or the dither process. By performing error diffusion processing, dither processing, etc., 260,000 color display data can be converted into 4096 colors, and the capacity of the built-in display memory 151 can be reduced. Error diffusion processing and the like can be performed by the error diffusion controller 141.

  In FIG. 103 and the like, 14 is described as a source driver, but not only a driver, but also a power supply IC 102, a buffer circuit 154 (including a circuit such as a shift register), a data conversion circuit, a latch circuit, a command decoder, and a shift circuit. The address conversion circuit and various functions or circuits for processing the input from the built-in display memory 151 and outputting the voltage or current to the source signal line are configured. These matters are the same in other embodiments of the present invention.

  Needless to say, the configuration described with reference to FIG. 103 and the like can also be applied to the three-side free configuration described with reference to FIGS. 12 to 16, FIG. 18, FIG. 20, FIG.

  The frame rate is related to the power consumption of the panel module. That is, if the frame rate is increased, the power consumption increases almost in proportion. For mobile phones and the like, it is necessary to reduce power consumption from the standpoint of extending the standby time. On the other hand, in order to increase the display color (increase the number of gradations), the drive frequency of the source driver 14 and the like must be increased. However, it is difficult to increase power consumption due to power consumption problems.

  In general, in an information display device such as a mobile phone, lower power consumption is given priority over the number of display colors. The power consumption increases because the operating frequency of the circuit that increases the number of display colors increases or the change in the voltage (current) waveform applied to the EL element increases. Therefore, the number of display colors cannot be increased too much. In response to this problem, the present invention displays an image by performing error diffusion processing or dither processing on the image data.

Although not shown in the cellular phone of the present invention described with reference to FIG. 104, a CCD camera is provided on the back side of the housing. Images and data captured by the CCD camera can be immediately displayed on the display screen 21 of the display panel. The image data of the CCD camera is 24 bits (16.7 million colors), 18 bits (260,000 colors), 16 bits (650,000 colors), 12 bits (4096 colors), 8 bits (
256 colors) can be switched by key input.

  When the display data is 12 bits or more, error diffusion processing is performed for display. That is, when the image data from the CCD camera is greater than or equal to the capacity of the built-in display memory 151, error diffusion processing or the like is performed, and image processing is performed so that the number of display colors is less than or equal to the capacity of the built-in display memory 151.

  Now, the source driver 14 will be described assuming that it has a built-in display memory 151 of 4096 colors (4 bits for each of RGB) and one screen. When the image data sent from the outside of the module is 4096 colors, it is directly stored in the built-in display memory 151 of the source driver 14, the image data is read from the built-in display memory 151, and the image is displayed on the display screen 21.

  When the image data is 260,000 colors (G: 6 bits, R, B: 5 bits each, 16 bits in total, as shown in FIGS. 77 and 103, it is temporarily stored in the arithmetic memory 152 of the error diffusion controller 141, At the same time, error diffusion or dither processing is performed in the arithmetic circuit 153. By this error diffusion processing or the like, 16-bit image data is converted into 12 bits which is the number of bits of the built-in display memory 151 and transferred to the source driver 14. The source driver 14 outputs RGB 4-bit (4096 colors) image data and displays the image on the display screen 21.

  In the configuration of FIG. 77 and the like, the error diffusion processing or dither processing method may be changed for each field or frame by using the vertical synchronization signal VD (changing the processing method by the vertical synchronization signal VD). For example, in the dither processing, the Bayer type is used in the first frame, and the halftone type is used in the next second frame. In this way, by changing and switching the dither processing for each frame, an effect of making the dot unevenness associated with the error diffusion processing less noticeable is exhibited.

  Further, processing coefficients such as error diffusion processing may be changed between the first frame and the second frame. Various processes such as error diffusion processing in the first frame, dither processing in the second frame, and error diffusion processing in the third frame may be combined. Further, a processing method may be selected in which a random number generation circuit is provided and processing is performed for each frame with a random value.

  If information such as the frame rate is described in the transmitted format, the frame rate can be automatically changed by decoding or detecting the described data. It is preferable to describe whether the transmitted image is a moving image or a still image, and in particular, in the case of a moving image, it is preferable to describe the number of frames per second of the moving image. Further, it is preferable to describe the model number of the mobile phone in the transmission packet. In this specification, it is described as a transmission packet. However, it is not necessary to be a packet. If the information (number of display colors, frame rate, etc.) described in FIG. Either is acceptable.

  FIG. 106 shows a transmission format sent to the mobile phone of the present invention. Transmission includes both data to be received and data to be transmitted. That is, the cellular phone may transmit the voice from the receiver or the image taken by the CCD camera attached to the cellular phone to another cellular phone or the like. Therefore, matters related to the transmission format described in FIG. 105 and the like apply to both transmission and reception.

  In the mobile phone of the present invention, data is digitized and transmitted in a packet format. As described in FIG. 106, a frame includes a flag part (F), an address part (A), a control part (C), an information part (I), and a frame check sequence (FCS). As shown in FIG. 107, the control unit (C) has three formats: information transfer (I frame), monitoring (S frame), and unnumbered system (U frame).

  First, the information transfer format is a control field format used when transferring information (data), and the information transfer format is the only format having a data field except for a part of the non-numbered format. A frame in this format is called an information frame (I frame).

  The monitoring format is a format used for performing a data link monitoring control function, that is, information frame reception confirmation, information frame retransmission request, and the like. A frame in this format is called a monitoring frame (S frame).

  The unnumbered format is a control field format used to perform other data ring control functions. A frame in this format is called an unnumbered frame (U frame).

  The terminal and the network manage information frames to be transmitted and received using a transmission sequence number N (S) and a reception sequence number N (R). Both N (S) and N (R) are composed of 3 bits, and 8 are used as a circulation number from 0 to 7, and the next to 7 has a modulus structure of 0. Therefore, the modulus in this case is 8, and the number of frames that can be continuously transmitted without receiving a response frame is 7.

  In the data area, 8-bit data indicating the color number data and 8-bit data indicating the frame rate are described. Examples of these are shown in FIGS. 105 (a) and 105 (b). In addition, it is preferable to describe the distinction between still images and moving images in the number of display colors. Also, it is desirable to describe the model name of the mobile phone, the contents of image data to be transmitted / received (natural images such as people, menu screens), etc. in the packet of FIG. When the model receiving the data decodes the data and recognizes it as its own (corresponding model number) data, the display color, the frame rate, etc. are automatically changed according to the described contents. Moreover, you may comprise so that the described content may be displayed on the display screen 21 of a display apparatus. The user may manually change to an optimal display state by looking at the description content (display color, recommended frame rate) on the display screen 21 and operating keys.

  As an example, in FIG. 105 (b), the numerical value 3 is described with an example of a frame rate of 80 Hz, but is not limited to this, and indicates a certain range such as 40 to 60 Hz. Also good. In addition, the mobile phone model may be described in the data area. This is because the performance varies depending on the model and the frame rate needs to be changed. It is also preferable to describe information such as whether the image is a comic or advertisement (CM). Further, information such as a viewing fee and a packet length may be described in the packet. This is because the user can determine whether to receive the information after confirming the viewing fee. In addition, it is preferable that data indicating whether or not the image data has been subjected to error diffusion processing is also described.

  Information such as the image processing method (types such as error diffusion processing and dither processing, types of weighting functions and their data, gamma coefficients, etc.) and model number may be described in the transmitted format. In addition, if information such as whether the image data is data taken by a CCD, JPEG data, resolution, MPEG data, or BITMAP data is described, the data is decoded or detected based on this, It becomes possible to change automatically received mobile phones to the optimum state.

  Of course, it is preferable to describe whether the transmitted image is a moving image or a still image, and in particular, in the case of a moving image, it is preferable to describe the number of frames per second of the moving image. It is also preferable to describe information such as the number of playback frames recommended per second at the receiving terminal.

  The above matters are the same even when the transmission packet is transmission. Further, although described in this specification as a transmission packet, it need not be a packet. In other words, any data may be used as long as information described in FIG.

  It is preferable to add a function to the error diffusion processing controller 141 to perform inverse error diffusion processing on the data sent after being subjected to error processing, return to the original data, and then perform error diffusion processing again. The presence / absence of error diffusion processing is placed in the packet data of FIG. Also, data necessary for inverse error diffusion processing such as error diffusion (including dithering) processing method and format is also stored.

  The reverse error diffusion process is performed because the correction of the gamma curve can be realized in the process of the error diffusion process. There are cases where the gamma curve of the EL display device or the like that has received the data and the transmitted gamma curve are not adapted, or the transmitted data is image data that has already undergone processing such as error diffusion. In order to cope with this situation, reverse error diffusion processing is performed and converted to original data so as not to be affected by gamma curve correction. Thereafter, error diffusion processing is performed by the received EL display device, etc., and error diffusion processing is performed so as to obtain an optimal gamma curve for the reception display panel and to achieve an optimal error diffusion processing.

  If it is desired to switch the frame rate depending on the display color, a user button may be arranged on a device such as a cellular phone so that the display color can be switched using the button.

  FIG. 104 is a plan view of a mobile phone as an example of an information terminal device. An antenna 191, a numeric keypad 192, and the like are attached to the housing 193. Reference numeral 194 denotes a display color switching key or a power on / off / frame rate switching key.

  FIG. 108 shows an internal circuit block of a mobile phone or the like. The circuit mainly includes blocks such as an up-converter 205 and a down-converter 204, a demultiplexer 201, and an LO buffer 203.

  If the key 194 is pressed once, the display color is set to the 8-color mode, and if the same key 194 is pressed, the display color is set to the 256 color mode, and if the same key 194 is pressed further, the display color is set to the 4096 color mode. But you can. The key is a toggle switch that changes the display color mode each time it is pressed. In addition, you may provide the change key with respect to a display color separately. In this case, there are three (or more) keys 194.

  The key 194 may be a push switch, a mechanical switch such as a slide switch, or may be switched by voice recognition or the like. For example, voice input of 4096 colors to the receiver, for example, “high quality display”, “256 color mode” or “low display color mode” is input to the receiver and displayed on the display screen 21 of the display panel. Configure the color to change. This can be easily realized by adopting the current speech recognition technology.

  The display color may be switched by an electrically switched switch or a touch panel that is selected by touching a menu displayed on the display screen 21 of the display panel. Further, it may be configured to be switched by the number of times the switch is pressed, or to be switched by rotation or direction like a click ball.

Although 194 is a display color switching key, it may be a key for switching a frame rate. Moreover, it is good also as a key etc. which switch a moving image and a still image. A plurality of requirements such as a moving image, a still image, and a frame rate may be switched at the same time. Alternatively, the frame rate may be changed gradually (continuously) as long as the pressure is kept pressed. This case can be realized by making the resistor R of the capacitor C and the resistor R constituting the oscillator a variable resistor or an electronic volume. The capacitor can be realized by using a trimmer capacitor. Alternatively, a plurality of capacitors may be formed on the semiconductor chip, one or more capacitors may be selected, and these may be connected in parallel in a circuit.

  The technical idea of switching the frame rate depending on the display color is not limited to mobile phones, but can be widely applied to devices having display screens such as palmtop computers, laptop computers, desktop computers, and portable watches. it can. Further, the present invention is not limited to a liquid crystal display device, and can be applied to a liquid crystal display panel, an organic EL display panel, a TFT panel, a PLZT panel, and a CRT.

(Embodiment 11)
Further, an embodiment in which the EL display panel, the EL display device, or the driving method of the present invention is employed will be described with reference to the drawings.

  FIG. 109 is a cross-sectional view of the viewfinder in the embodiment of the present invention. However, it is schematically drawn for easy explanation. In addition, there are places that are partially enlarged or reduced or omitted. For example, the eyepiece cover is omitted in FIG. The above also applies to other drawings.

  The back surface of the body 451 is dark or black. This is because stray light emitted from the display panel 82 is diffusely reflected on the inner surface of the body 451 to prevent a decrease in display contrast. A λ / 4 plate 50 (phase plate or the like), a polarizing plate 54, or the like is disposed on the light emission side of the display panel. This is also illustrated in FIG.

  A magnifying lens 453 is attached to the eyepiece ring 452. The observer changes the insertion position of the eyepiece ring 452 in the body 451 and adjusts it so that the display image on the display panel is in focus. Further, if the positive lens 454 is disposed on the light exit side of the display panel as necessary, the principal ray incident on the magnifying lens 453 can be converged. Therefore, the lens diameter of the magnifying lens 453 can be reduced, and the viewfinder can be downsized.

  FIG. 110 is a perspective view of the video camera. The video camera includes a photographing lens 461 and a video camera body 462, and the photographing lens 461 and the viewfinder 466 are back to back. Further, an eyepiece cover 464 is attached to the viewfinder 466 (see also FIG. 109). An observer (user) observes an image on the display panel from the eyepiece cover 464 portion.

  On the other hand, the EL display panel of the present invention is also used as the display screen 21. The display screen 21 can freely adjust the angle at a fulcrum 468. When the display screen 21 is not used, it is stored in the storage unit 463.

  In FIG. 110, reference numeral 465 denotes a display mode switch. When the display mode changeover switch 465 is pressed, the circuit of FIG. 35 operates and the items described in FIG. 35 are performed.

The EL display device of this embodiment can be applied not only to a video camera but also to an electronic camera as shown in FIG. The display panel 82 is used as a monitor attached to the digital camera body 472. In addition to the shutter 471, a display mode changeover switch 465 is attached to the digital camera body 472.

  It is also preferable to have an “automatic screen adjustment” function that automatically adjusts the clock phase and screen position (horizontal / vertical) and an “auto gain control function” that automatically adjusts the black level and contrast. If the black level contrast is adjusted to an appropriate value, the optimum gradation display can be realized for each of the RGB colors. Furthermore, it is preferable to install a function for suppressing bleeding that occurs when the VGA mode or the like is reduced or enlarged. In addition, it is preferable to install a “power save mode” in which the backlight is automatically turned off when not used for a certain period of time. The above matters are the same in other embodiments of the present invention.

  The above is a case where the display area of the display panel 82 is relatively small, but the display screen 21 is easily bent when the display area is larger than 30 inches. As a countermeasure, in the present invention, as shown in FIG. 112, an outer frame 481 is attached to the display panel 82, and the outer frame 481 is attached by a fixing member 482 so that it can be suspended. As shown in FIG. 113, the fixing member 482 is attached to a wall 491 or the like using a fixing member 482 such as a screw.

  However, as the screen size of the display panel 82 increases, the weight increases. Therefore, a leg attachment portion 484 is disposed below the display panel 82 so that the weight of the display panel 82 can be held by the plurality of legs 483.

  As shown in FIG. 112, the leg 483 can move left and right as shown in A, and the leg 483 can be contracted as shown in B. Therefore, the display device can be easily installed even in a narrow place.

  Note that a plastic film-metal plate composite material (hereinafter referred to as a composite material) is used for the legs 483 or the casing (also in the present invention). The composite material is obtained by strongly bonding a metal and a plastic film via a special surface treatment layer (adhesive layer). The metal plate is preferably 0.2 mm or more and 0.8 mm or less, and the plastic film bonded to the metal plate via a special surface treatment layer is preferably 15 μm or more and 100 μm or less. A special adhesion method provides a strong adhesion between the plastic and the metal plate. By using this composite material, it is possible to color, dye and print on the plastic layer, and it is possible to eliminate the secondary processing step (manual application of film, plating) on the press part. In addition, it is suitable for deep drawing and DI molding, which was impossible in the past.

  112, the screen surface is covered with a protective film (which may be a protective plate) 493. This is for the purpose of preventing an object from hitting the display screen 21 of the display panel 82 and damaging it. An AIR coat is formed on the surface of the protective film 493, and the surface is embossed to prevent external conditions (external light) from appearing on the liquid crystal display screen 21.

By spreading beads between the protective film 493 and the display panel 82,
A certain space is arranged. Further, a minute convex portion is formed on the back surface of the protective film 493, and a space is held between the display panel 82 and the protective film 493 by the convex portion. Thus, holding the space prevents the impact from the protective film 493 from being transmitted to the display panel 82.

  It is also effective to place or inject an optical binder such as a liquid such as alcohol or ethylene glycol or a solid resin such as an epoxy resin between the protective film 493 and the display panel 82. This is because interface reflection can be prevented and the optical binder functions as a buffer material.

  Examples of the protective film 493 include a polycarbonate film (plate), a polypropylene film (plate), an acrylic film (plate), a polyester film (plate), a PVA film (plate), and the like. In addition, an engineering resin film (ABS or the like) can also be used. Moreover, what consists of inorganic materials, such as tempered glass, may be used. The same effect can be obtained by coating the surface of the display panel 82 with an epoxy resin, phenol resin, or acrylic resin in a thickness of 0.5 mm or more and 2.0 mm or less instead of disposing the protective film 493. It is also effective to emboss the surface of these resins.

  It is also effective to coat the surface of the protective film 493 or the coating material with fluorine. This is because the dirt on the surface can be easily wiped off with a detergent or the like. Further, the protective film may be formed thick and may also be used as a front light.

The screen is not limited to 4: 3, and may be a wide display.
The resolution is preferably 1280 × 768 dots or higher. By adopting the wide type, it is possible to enjoy full-screen titles and programs such as DVD movies and TV broadcasts in a wide display. The brightness of the display panel 82 is 300 cd / m ² (candela / square meter),
Furthermore, it is preferably 500 cd / m ² (candela / square meter). In addition, a changeover switch is provided so that it can be displayed at a brightness (200 cd / m ² ) suitable for the Internet and normal personal computer work.

In this way, the user can obtain an optimal screen brightness depending on the display contents or the usage method. Further only to 500 cd / m ² window displaying the video, other portions are also possible setting that 200 cd / m ^2. You can flexibly handle the usage of displaying TV programs in the corner of the display and checking emails. The speaker has a tower shape and is designed to spread the sound not only in the front direction but also in the entire space.

  The usability of TV program playback and recording functions has also improved. For example, recording reservation from i-mode can be easily performed. Conventionally, it has been necessary to make a reservation after confirming the time and channel in a TV program guide such as a newspaper, but the electronic program guide can be checked and reserved in i-mode. If this is the case, you don't need to know the broadcast time. In addition, the recorded program can be shortened. While judging the importance based on the presence / absence of telops and audio in news programs, etc., it is possible to skip the part judged unnecessary and to watch the outline of the program in a short time (about 1 to 10 minutes for a 30-minute program).

  In addition, a hard disk with a disk capacity of 40 GB or more is loaded so that television recording can be performed. In addition to the main unit, it is composed of an expansion box that combines a power supply and video input / output terminals. In addition to a personal computer and a TV, two systems of video equipment can be connected to an expansion box used to connect AV equipment such as video. Video input is provided with S terminal input in addition to D1 terminal for BS digital tuner, and can be selected according to the connected equipment. In addition, AV terminals are arranged on the front surface for convenient connection with a game machine or the like.

  Needless to say, the above-described matters relating to the protective film 493, the casing, the configuration, the characteristics, the functions, and the like are also applied to other display devices or information display devices of the present invention.

As already described, TFT 11d in FIG. 52, TFT 11e in FIG. 53, TFT 11d in FIG. 54, TFT 11b in FIG. 55, TFT 11d in FIG. 56, TFT 11d in FIG. 57, TFT 11e in FIG. 58, TFT 11e in FIG. By controlling the on / off state of the TFT 11d in FIG. 62, the TFT 11d in FIG. 63, the TFT 11e in FIG. 67, the TFT 11e in FIG. 75, etc., FIGS. 29, 33, 39, 41, 43, 44, 45,
Needless to say, the driving method or the display method or apparatus described in FIGS. 48, 50, 51, 98, etc. can be implemented.

  In addition, the driving TFT 11b, the capturing TFT 11c, the switching TFT 11d, and the like shown in FIG. 6 are preferably formed of an N channel. This is because the penetration voltage to the capacitor 19 is reduced.

  In addition, since the EL element has a large characteristic change in the early stage of lighting, burning and the like are likely to occur. For this measure, it is preferable to ship the product as a product after aging with white raster display for 20 hours or more and 150 hours or less after the panel is formed. In this aging, it is preferable to display at a brightness of about 2 to 10 times the predetermined display luminance.

  The drive (display) method and the drive circuit have been described with reference to FIGS. 10, 29 to 33, 35, 40, 43, 46, 47, 49, 81, 83 to 94, and the like. However, a semiconductor chip made of gallium arsenide, silicon, germanium or the like that realizes these technical ideas is also within the scope of the present invention. A display device, an information display device, or the like can be realized by mounting these semiconductor chips on a display panel.

  Further, by connecting the terminal for applying the Vbb voltage in FIG. 6B, FIG. 9, FIG. 56, FIG. 59, FIG. 60, FIG. 62 and the like to the gate driver 12b as described in FIG. Image display can be realized.

  In addition, matters relating to the power supply voltage Vdd described with reference to FIGS. 96 and 100 are also applied to all pixel configurations, display panels, information display devices, and driving methods in this specification. 2 to 5, 12 to 24, 77, 81, 83 to 94, 99, 101 to 103, 105, 108 to 112, etc. Needless to say, the present invention is applied to all pixel configurations, driver arrangements, display panels, information display devices, or driving methods.

  The method or configuration for applying a reverse bias voltage to the EL element 15 described with reference to FIGS. 76, 78, 81, 83 to 94, etc. is also shown in FIGS. 6, 8, 29, 42, 46, Needless to say, the present invention is applied to the pixel configuration or the array configuration shown in FIGS. 47, 52 to 56, 59 to 63, 67, 69 to 75, and 95. Further, it is not necessary to explain that these configurations can realize FIGS. 28 to 31, 33 to 40, 43 to 45, 48, 50, 51, and 75. Needless to say, the combination with the three-side free configuration of FIGS. 12 to 21 is also effective. In particular, the three-side free configuration is effective when the pixel is manufactured using amorphous silicon technology. In addition, in a panel formed by amorphous silicon technology, it is not possible to control the process of variation in characteristics of TFT elements, and therefore it is preferable to implement current driving according to the present invention.

  Furthermore, using these techniques, FIGS. 2 to 5, 12 to 24, 77, 81, 83 to 94, 99, 101 to 103, 105, and 108 to 112 are used. Needless to say, the present invention can be applied to a display panel, an information display device, or a driving method.

  The pixel configuration described in FIGS. 1 and 80 to 94, or the pixel configuration or array configuration in the driving method is not limited to the EL display panel. For example, it can be applied to a liquid crystal display panel. In that case, the EL element 15 may be replaced with a light modulation layer such as a liquid crystal layer, PLZT, or LED. Further, the switching element is not limited to the TFT. Needless to say, the present invention is applied to all pixel configurations, driver arrangements, display panels, information display devices, and driving methods in this specification.

  6, 8, 17 to 21, 29, 42, 46, 47, 52 to 56, 59 to 63, 67 to 75, 81, 83 to 95. The pixel configuration or array configuration is not limited to the EL display panel. For example, it can be applied to a liquid crystal display panel. In that case, the EL element 15 may be replaced with a light modulation layer such as a liquid crystal layer, PLZT, or LED. Further, the switching element is not limited to the TFT as described with reference to FIG.

  Also, the configuration, apparatus, and system of FIGS. 3, 12, 15, 17, 17 to 21, 77, 104 to 106, and 109 to 112 are limited to those using an EL display panel. It is not a thing. For example, the present invention can be applied to a display using a PDP display panel, a PLZT display panel, a liquid crystal display panel, or the like.

  The methods of FIGS. 25 and 26 are not limited to the method of manufacturing an EL display panel. For example, the present invention can be applied to a liquid crystal display panel manufacturing method. 12 to 21 is not limited to the EL display panel, and it goes without saying that the present invention can also be applied to an LED display panel, a liquid crystal display panel, and the like. The same applies to the display methods of FIGS. 28 to 31, 33 to 40, 43 to 45, 48, 50, 51, and 75.

  As described above, the technical idea described in the embodiments of the present invention can be applied to a video camera, a projector, a stereoscopic television, a projection television, and the like. The present invention can also be applied to a viewfinder, a mobile phone monitor, a PHS, a portable information terminal and its monitor, a digital camera and its monitor. The present invention can also be applied to an electrophotographic system, a head mounted display, a direct view monitor display, a notebook personal computer, a video camera, and an electronic still camera. The present invention can also be applied to an automatic cash drawer monitor, public telephone, videophone, personal computer, wristwatch, and display device thereof. Furthermore, it goes without saying that the present invention can be applied or applied to a display monitor for home appliances, a pocket game device and its monitor, a backlight for a display panel, or a lighting device for home use or business use. It can also be applied to display devices such as advertisements or posters, RGB traffic lights, warning indicator lights, and the like.

Explanatory drawing of the drive method of the display panel of this invention Sectional view of the display device of the present invention Sectional view of the display panel of the present invention Sectional view of the display device of the present invention Sectional view of the display device of the present invention Circuit diagram of display panel of the present invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Circuit diagram of display device of the present invention Explanatory drawing of the display apparatus of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display apparatus of this invention Explanatory drawing of the display apparatus of this invention Sectional view of the display device of the present invention Explanatory drawing of the manufacturing method of the display panel of this invention Explanatory drawing of the manufacturing method of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Circuit block diagram of display panel of the present invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Circuit block diagram of display panel of the present invention Circuit block diagram of display panel of the present invention Explanatory drawing of the drive method of the display panel of this invention Circuit block diagram of display panel of the present invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the display apparatus of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the drive method of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the display panel of this invention Explanatory drawing of the information display apparatus of this invention Explanatory drawing of the information display apparatus of this invention Explanatory drawing of the display panel of this invention Configuration diagram of display device of the present invention Configuration diagram of display device of the present invention Explanatory drawing of the display apparatus of this invention The top view of the information display device of the present invention Explanatory drawing of the data transmission method of the display apparatus of this invention Explanatory drawing of the data transmission method of the display apparatus of this invention Explanatory drawing of the data transmission method of the display apparatus of this invention Explanatory drawing of the information display apparatus of this invention Sectional view of the viewfinder of the present invention The perspective view of the video camera of the present invention The perspective view of the electronic camera of this invention Illustration of the television of the present invention Illustration of the television of the present invention Explanatory drawing of the drive method of the display panel of this invention Circuit diagram of conventional display panel

Explanation of symbols

11 TFT
12 Gate driver 14 Source driver 14a 1 chip driver IC
DESCRIPTION OF SYMBOLS 15 EL element 16 Pixel 17 Gate signal line 18 Source signal line 19 Capacitor 20 Current supply line 21 Display screen 22 Shift register 23 Inverter circuit 24 Output gate 41 Sealing lid 43 Concave part 44 Convex part 45 Sealant 46 Reflective film 47 Organic EL layer 48 pixel electrode 49 array substrate 50 λ / 4 plate 51 cathode wiring 52 contact hole 53 cathode electrode 54 polarizing plate 55 desiccant 61, 62 connection terminal 63 anode wiring 71 smoothing film 72 transparent electrode 73 sealing film 74 circular polarizing plate 81 Edge protective film 82 Display panel 91 Light shielding film 92 Low resistance wiring 101 Control IC
102 Power IC
DESCRIPTION OF SYMBOLS 103 Printed circuit board 104 Flexible board 105 Data signal 141 Error diffusion controller 151 Built-in display memory 152 Operation memory 153 Operation circuit 154 Buffer circuit 191 Antenna 192 Numeric keypad 193 Case 194 Key 201 Deplexer 202 LNA
203 LO buffer 204 Down converter 205 Up converter 206 PA Pre-driver 207 PA
230 Laser irradiation spot 241 Glass substrate 242 Positioning marker 251 Convex part 252 Concave part 311 Image display area 312 Non-display area 351 Counter circuit 352 Luminance memory 353 CPU
354 frame memory (field memory)
355 Switching circuit 391 Write pixel row 392 Holding pixel row 401 Voltage source 402 Current source 403 Power source switching means 404 Parasitic capacitance 451 Body 452 Eyepiece ring 453 Magnifying lens 454 Positive lens 461 Shooting lens 462 Video camera body 463 Storage unit 464 Eyepiece cover 465 Display Mode switch 466 Viewfinder 467 Lid 468 Support point 471 Shutter 472 Digital camera body 481 Outer frame 482 Fixing member 483 Leg 484 Leg mounting part 491 Wall 492 Fixing bracket 493 Protective film (protective plate)
501 Scanning area 601 ENBL terminal 602 OR circuit 851 Shutter 852 Observation glasses (switching means)
861 Prism 862 Optical coupling material 871 Write pixel row 1001 Flying capacitor

Claims (7)

A plurality of gate signal lines and a plurality of source signal lines arranged so as to intersect with each other; and a pixel having an EL element provided corresponding to an intersection of the plurality of gate signal lines and the plurality of source signal lines. An active matrix EL display device having an image display area,
In the pixel, a driving transistor that supplies a current to be supplied to the EL element;
A first switching transistor disposed in a signal path between the driving transistor and the source signal line in the pixel;
A second switching transistor disposed between the driving transistor and the EL element in the pixel;
A current output circuit that outputs a current corresponding to the video signal;
A precharge or discharge circuit for forcibly discharging or charging the source signal line charge,
A first gate signal line is connected to the gate terminal of the first switch transistor, a second gate signal line is connected to the gate terminal of the second switch transistor, and the first switch signal The transistor and the second switch transistor are configured to be independently on / off-controllable,
The current of the current output circuit is configured to flow by turning on the first switching transistor to the driving transistor,
The precharge or discharge circuit outputs to the pixel a voltage for setting the display in the pixel to a black level,
When applying to the pixel a voltage that makes the display in the pixel black level, and when supplying a current corresponding to the video signal to the pixel, the second switch transistor is turned off,
An EL display device, wherein the second switch transistor is turned off a plurality of times in one frame period to generate a plurality of non-display areas in a strip shape on the display screen of the EL display device. A plurality of gate signal lines and a plurality of source signal lines arranged so as to intersect with each other; and a pixel having an EL element provided corresponding to an intersection of the plurality of gate signal lines and the plurality of source signal lines. An active matrix EL display device having an image display area,
A current output circuit that outputs a current corresponding to the video signal;
A precharge or discharge circuit that forcibly releases or charges the source signal line;
A first gate driver circuit;
A second gate driver circuit;
The pixel includes a driving transistor, a second switching transistor arranged in a signal path through which the first transistor supplies current to the EL element, the driving transistor, and the source signal line. And a first switching transistor disposed in the signal path of
The precharge or discharge circuit outputs to the pixel a voltage for setting the display in the pixel to a black level,
A first gate signal line is connected to the gate terminal of the first switch transistor, a second gate signal line is connected to the gate terminal of the second switch transistor,
The first gate driver circuit controls on / off of the first switching transistor by controlling the first gate signal line,
The second gate driver circuit controls on / off of the second switching transistor by controlling the second gate signal line,
When applying to the pixel a voltage that makes the display in the pixel black level, and when supplying a current corresponding to the video signal to the pixel, the second switch transistor is turned off,
An EL display device characterized in that, based on video data output to the EL display device, a start pulse output to the second gate driver circuit is controlled to change a ratio occupied by an image display area of the display screen. . A plurality of gate signal lines and a plurality of source signal lines arranged so as to intersect with each other; and a pixel having an EL element provided corresponding to an intersection of the plurality of gate signal lines and the plurality of source signal lines. An active matrix EL display device having an image display area,
In the pixel, a driving transistor that supplies a current to be supplied to the EL element;
A first switching transistor disposed in a signal path between the driving transistor and the source signal line in the pixel;
A second switching transistor disposed between the driving transistor and the EL element in the pixel;
A current output circuit that outputs a current corresponding to the video signal;
A precharge or discharge circuit for forcibly discharging or charging the source signal line charge,
A first gate signal line is connected to the gate terminal of the first switch transistor, a second gate signal line is connected to the gate terminal of the second switch transistor, and the first switch signal The transistor and the second switch transistor are configured so as to be controlled on and off independently,
The current of the current output circuit is configured to flow by turning on the first switching transistor to the driving transistor,
The precharge or discharge circuit outputs to the pixel a voltage for setting the display in the pixel to a black level,
When applying to the pixel a voltage that makes the display in the pixel black level, and when supplying a current corresponding to the video signal to the pixel, the second switch transistor is turned off,
In the current output circuit, a plurality of current mirror circuits are formed in each source signal line, and by selecting the number of the current mirror circuits, a current is output to the source signal line,
An EL display device characterized by being intermittently displayed in one field or one frame period. The current output circuit includes a semiconductor chip whose output terminal is connected to the source signal line,
3. The EL display device according to claim 1, wherein the precharge or discharge circuit is formed on a substrate on which the image display area is formed.   Each of the plurality of pixels is configured to display any one of the three primary colors R, G, and B, and the precharge or discharge circuit includes at least one of the three primary colors R, G, and B. 3. The EL display device according to claim 1, wherein a voltage can be changed to display a color on the pixel. The precharge or discharge circuit outputs a voltage for setting a pixel display to a black level in a first period of a horizontal scanning period,
The EL display device according to claim 1, wherein the current output circuit performs a current program operation in a second period after the first period.
3. The EL display device according to claim 2, wherein the driving transistor is a P-channel transistor.

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