JP2007034225A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute an accurate circuit operation in a pixel circuit. <P>SOLUTION: With respect to two or more vertical scanner parts (a write scanner 14 and a drive scanner 15) disposed on one side of a pixel array, buffer parts (or buffer parts 25 and 35 and level conversion parts 24 and 34) of respective vertical scanner parts are collectively disposed in a position near a pixel array part 20, whereby line lengths from scan pulse output ends of respective vertical scanner parts to the pixel array are approximately equalized. Alternatively they are disposed side by side in a vertical direction per vertical scanner circuit component corresponding to one scan line, whereby differences in line length are eliminated. Reduction or elimination of the differences in line length reduces delay time differences of scan pulses from respective vertical scanner parts in such a degree that the delay time differences don't influence the circuit operation, or eliminates the delay time differences. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention is a display device in which pixel circuits formed at a portion where a signal line and a plurality of types of scanning lines intersect are arranged in a matrix. For example, an organic electroluminescence element (organic EL element) is used as a light emitting element. The present invention relates to the display device used.

JP 2003-255856 A JP 2003-271095 A

As can be seen in Patent Documents 1 and 2, image display apparatuses using organic EL elements as pixels have been developed. Since the organic EL element is a self-luminous element, it has advantages such as higher image visibility than a liquid crystal display, no need for a backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough (so-called current control type).
In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor: TFT) provided in the pixel circuit.

FIG. 11 is a block diagram of an active matrix organic EL display device.
This display device includes a pixel array unit 100 in which pixel circuits G each having an organic EL element as a light emitting element are arranged in m rows and n columns in a matrix form as shown as pixel circuits G11... Gmn. Have.
In the pixel array unit 100, signal lines DTL are provided for the first to n-th columns, and in this case, four types of scanning lines are respectively provided from the first row to the m-th row. It is arranged with respect to. Each pixel circuit G11... Gnm is disposed at a portion where the signal line and the four types of scanning lines intersect.

Each of the n signal lines DTL is driven by the horizontal selector 101. Specifically, a signal corresponding to luminance information is applied to each signal line by the horizontal selector 101, and the signal is supplied to each pixel circuit G in the row selected by the scanning line.
The four types of scanning lines include a scanning line WSL driven by the write scanner 104, a scanning line DSL driven by the drive scanner 105, a scanning line AZL1 driven by a first AZ (Auto Zero) scanner, and a second AZ scanner. There is a scanning line AZL2 to be performed.
These four types of scanning lines are arranged in each row, and each pixel circuit G performs a predetermined operation in accordance with scanning pulses given by the four scanning lines.

When the pixel circuit G in a certain row is driven by the four types of scanning lines, a signal potential is applied to each signal line by the horizontal selector 101, so that each pixel circuit G in that row corresponds to the signal potential. A light emission operation with high brightness is performed.
Four types of scanning lines sequentially select each row, thereby displaying one screen (one frame) of video.

In the case of the configuration as shown in FIG. 11, the write scanner 104 and the drive scanner 105 are arranged on the right side of the pixel array unit 100. In this case, the drive scanner 105 is located in the pixel array unit 100 rather than the write scanner 104. Distant position.
The scanning line WSL from the light scanner 104 is extended in the row direction in the pixel array unit 100 from the output end P1 of the write scanner 104 as a base point, and the pixel circuits G (G11, G21) in the leftmost column of the pixel array unit 100 ... Gm1).
The scanning line DSL from the drive scanner 105 is extended in the row direction in the pixel array unit 100 from the output end P3 of the drive scanner 105 as a base point, and the pixel circuits G (G11, G11, L) in the leftmost column of the pixel array unit 100 G21... Gm1).

Here, in FIG. 11, the positions P2 and P4 on the right end side of the pixel array unit 100 are the pixel input end of the scanning line WSL and the pixel input end of the scanning line DSL, respectively, but the output end P1 of the scanning line WSL and the pixel input As a difference between the distance of the end P2 and the distance between the output end P3 of the scanning line DSL and the pixel input end P4, a difference in wiring length occurs between the scanning lines DSL and WSL.
That is, the distance until the scanning pulse output from the drive scanner 105 reaches the pixel array unit 100 is longer than the distance until the scanning pulse output from the write scanner 104 reaches the pixel array unit 100.

  FIG. 12 shows an internal configuration of the scanning line write scanner 104 and the drive scanner 105 for the scanning lines WSL and DSL in one row. FIG. 12 shows the arrangement order of circuits formed on the side of the pixel array section 20.

The write scanner 104 includes a shift register unit 121, a clock supply unit 122, a logic unit 123, a level conversion unit 124, and a buffer unit 125.
The drive scanner 105 includes a shift register unit 131, a clock supply unit 132, a logic unit 133, a level conversion unit 134, and a buffer unit 135.
In the shift register units 121 and 131, the clock supply units 122 and 132, and the logic units 123 and 133, for example, a voltage VH of + 10V and a power supply line of a voltage VL1 as, for example, 0V (ground potential) are arranged, and + 10V to 0V Operates at the operating power supply voltage.
The level converters 124 and 134 and the buffer units 125 and 135 are provided with a power line of a voltage VH of, for example, + 10V and a voltage VL2 of, for example, -5V, and operate with an operating power supply voltage of + 10V to -5V.
A clock CK having a predetermined frequency is supplied to the clock supply units 122 and 132 through a clock line.

In the write scanner 104, the pulse output from the shift register unit 121 is supplied to the processing of the logic unit 123, thereby generating a scan pulse waveform. The clock supply unit 122 supplies the clock CK to the shift register 121.
The pulse waveform generated by the logic unit 123 is level-converted by the level conversion unit 124 into a pulse of + 10V to −5V as a level suitable for operation control in the pixel circuit G. The pulse is waveform-shaped by the buffer unit 125 and output to the scanning line WSL as a scanning pulse by the write scanner 104.

In the drive scanner 105, the pulse output from the shift register unit 131 is supplied to the processing of the logic unit 133, thereby generating a scan pulse waveform. The clock supply unit 132 supplies the clock CK to the shift register 131.
The pulse waveform generated by the logic unit 133 is level-converted by the level conversion unit 134 to a pulse of +10 V to −5 V as a level suitable for operation control in the pixel circuit G. The pulse is waveform-shaped by the buffer unit 135 and output to the scanning line DSL as a scanning pulse by the drive scanner 105.

In such a configuration, the output terminal P 1 of the write scanner 104 is an output terminal of the buffer unit 125, and the output terminal P 3 of the drive scanner 105 is an output terminal of the buffer unit 135.
The difference in wiring length is the distance between the output terminals P1 and P3 of the buffer units 125 and 135, as shown in the figure, and is, for example, about 1000 μm.

As described above, if there is a difference in wiring length between the light scanner 104 and the drive scanner 105 until the pixel array unit 100 is reached, the scanning pulse of the scanning line DSL and the scanning pulse of the scanning line WSL are caused by the difference in wiring length. As a result, a difference in pulse delay occurs when viewed from the pixel array unit 100.
For example, when a pulse as shown in FIG. 13A is output from the output terminal P1 of the light scanner 104, the waveform becomes dull at the pixel input terminal P2 due to the wiring resistance and wiring capacity between P1 and P2. ) Delay occurs.
On the other hand, when a pulse as shown in FIG. 13C is output from the output terminal P3 of the drive scanner 105, the pixel input terminal P4 is affected by the wiring resistance between P3 and P4 and the wiring capacitance as shown in FIG. Thus, a delay occurs. Then, as can be seen by comparing FIGS. 13B and 13D, the delay amount of the pulse from the drive scanner 105 becomes larger due to the difference in wiring length, that is, the difference in wiring resistance and wiring capacitance.
When viewed from each pixel circuit G, the pulse from the scanning line DSL and the pulse from the scanning line WSL are given with the difference in the delay amount.

  Here, in each pixel circuit G, each transistor in the pixel circuit is turned on / off by each pulse of the scanning lines DSL, WSL, AZL1, and AZL2, and a necessary operation is performed. When the light emission drive operation is controlled so that a certain operation period is set by the phase difference of the pulse, the difference in the delay amount affects the operation period, and an accurate pixel circuit operation cannot be executed. There is.

  Therefore, the present invention reduces the difference in the scanning pulse delay amount of each vertical scanner unit when a plurality of vertical scanner units are arranged on one side of the pixel array as in the above-described light scanner 104 and drive scanner 105. Alternatively, the object is to eliminate the pixel circuit so that the operation of the pixel circuit is correctly executed.

The display device according to the present invention includes a pixel array in which pixel circuits are arranged in a matrix, and a column direction on the pixel array in order to apply a signal defining emission luminance to each of the pixel circuits arranged in a matrix. A plurality of types of scanning lines arranged in a row direction on the pixel array to control the operation of the pixel circuits arranged in a matrix, and the signal lines. And a plurality of vertical scanner units for driving each of the plurality of types of scanning lines as a vertical scanner unit including a signal line driving unit, a scanning pulse generation circuit unit, and an output buffer circuit unit. Among the plurality of vertical scanner units, for two or more vertical scanner units arranged on the same side of the pixel array, the output buffer circuit unit in each vertical scanner unit is connected to the pixel array. They are arranged together at the closest position.
Each of the vertical scanner units is provided with a level conversion circuit unit for level-converting the scan pulse from the scan pulse generation circuit unit and supplying the level to the output buffer circuit unit. Among them, for two or more vertical scanner units arranged on the same side of the pixel array, the output buffer circuit unit and the level conversion circuit unit in each vertical scanner unit are positioned closest to the pixel array. Are arranged together.

  In addition, the display device of the present invention includes a pixel array in which pixel circuits are arranged in a matrix, and a column on the pixel array for applying a signal defining emission luminance to each of the pixel circuits arranged in a matrix. Signal lines arranged in a direction, a plurality of types of scanning lines arranged in a row direction on the pixel array to control the operation of the pixel circuits arranged in a matrix, and the signal lines. A signal line driving unit for driving, and a plurality of vertical scanner units for driving each of the plurality of types of scanning lines. Of the plurality of vertical scanner units, two or more vertical scanner units arranged on the same side of the pixel array are arranged in the vertical direction for each vertical scanner circuit component corresponding to one scanning line. Are arranged side by side.

In such a display device of the present invention, for two or more vertical scanner units (for example, a write scanner and a drive scanner) arranged on the same side of the pixel array, the output buffer circuit unit of each vertical scanner unit collects pixels. By being arranged at a position close to the array, the scanning line wiring length from the scanning pulse output end of each vertical scanner section to the pixel array becomes substantially equal. That is, the difference in wiring length from the output end of each vertical scanner unit to the pixel array can be significantly reduced.
The same applies to the case where the output buffer circuit unit and the level conversion circuit unit of each vertical scanner unit are collectively arranged near the pixel array.
Further, by arranging the vertical scanner circuit constituent portions corresponding to one scanning line so as to be arranged in the vertical direction, the difference in the wiring length can be eliminated.
By reducing or eliminating the difference in wiring length, it is possible to reduce the delay time difference between the scanning pulses from the vertical scanner units to the extent that the circuit operation is not affected, or to eliminate the delay time difference.

  According to the present invention, for each scanning pulse output from two or more vertical scanner units arranged on the same side of the pixel array, the difference in the wiring length of the scanning lines from each vertical scanner unit to the pixel array is reduced. Alternatively, the delay time difference due to the difference in wiring length can be reduced or eliminated. Therefore, the scanning pulse output from each vertical scanner unit is supplied to each pixel circuit without a delay time difference (or small enough not to affect the circuit operation). There is an effect that an appropriate circuit operation based on the scanning pulse can be realized.

In addition, when the output buffer circuit and level conversion circuit of the vertical scanner are placed together at a position close to the pixel array, the wiring of the power line can be easily routed and the circuit layout design is simplified. it can.
In addition, when the vertical scanner circuit components corresponding to one scanning line are arranged so as to be arranged in the vertical direction, it is easy to reduce the number of power lines and clock lines arranged in the vertical direction and to route the wiring. .

Hereinafter, examples of display devices using organic EL elements will be described as first to fourth embodiments of the display device of the present invention.

[First Embodiment]

FIG. 1 shows a configuration of a display device according to an embodiment. As will be described later, this display device includes a pixel circuit 10 having a compensation function for fluctuations in threshold voltage of the drive transistor and variations in mobility.
As shown in FIG. 1, the display device of this example includes a pixel array unit 20 in which pixel circuits 10 are arranged in a matrix of m rows × n columns, a horizontal selector 11, a drive scanner 15, a write scanner 14, and a first AZ scanner. 12. A second AZ scanner 11 is provided.
Further, signal lines DTL1, DTL2,..., Which are selected by the horizontal selector 11 and supply video signals corresponding to luminance information as input signals to the pixel circuit 10, are arranged in the column direction with respect to the pixel array unit 20. The signal lines DTL1, DTL2,... Are arranged for n columns of the pixel circuits 10 arranged in a matrix in the pixel array unit 20.

Further, the scanning lines WSL1, WSL2,..., The scanning lines DSL1, DSL2,..., The scanning lines AZL1-1, AZL1-2, and the scanning lines AZL2-1, AZL2 in the row direction with respect to the pixel array unit 20. -2 ... are arranged. Each of these scanning lines is arranged for m rows of the pixel circuits 10 arranged in a matrix in the pixel array unit 20.
The scanning lines WSL (WSL1, WSL2,...) Are selectively driven by the write scanner 14.
The scanning lines DSL (DSL1, DSL2,...) Are selectively driven by the drive scanner 15.
The scanning lines AZL1 (AZL1-1, AZL1-2,...) Are selectively driven by the first AZ scanner 12.
The scanning lines AZL2 (AZL2-1, AZL2-2,...) Are selectively driven by the second AZ scanner 13.
The drive scanner 15, the write scanner 14, the first AZ scanner 12, and the second AZ scanner 13 give a selection pulse to each scanning line at a predetermined timing set based on the input start pulse sp and clock ck, respectively.

FIG. 2 shows the configuration of the pixel circuit 10. In FIG. 2, only one pixel circuit 10 arranged at a portion where the signal line DTL and the scanning lines WSL, DSL, AZL1, and AZL2 intersect is shown for simplification.
The pixel circuit 10 includes an organic EL element 1 that is a light emitting element, one holding capacitor C1, a sampling transistor T1, a drive transistor T5, a switching transistor T3, a first detection transistor T2, and a second detection transistor T4. It consists of five thin film transistors (TFTs). The sampling transistor T1, the drive transistor T5, the first detection transistor T2, and the second detection transistor T4 are n-channel TFTs, and the switching transistor T3 is a p-channel TFT.

The storage capacitor C1 has one terminal connected to the source of the drive transistor T5 and the other terminal connected to the gate of the drive transistor T5. In the figure, the source node of the drive transistor T5 is shown as point B, and the gate node of the drive transistor T5 is shown as point A. Therefore, the storage capacitor C1 is connected between the points A and B.
The light emitting element of the pixel circuit 10 is, for example, the organic EL element 1 having a diode structure, and includes an anode and a cathode. The anode of the organic EL element 1 is connected to the source (point B) of the drive transistor T5, and the cathode is connected to a predetermined cathode potential Vcat.

The source of the first detection transistor T2 is connected to the first fixed potential Vss1, the drain thereof is connected to the gate (point A) of the drive transistor T5, and the gate thereof is connected to the scanning line AZL1.
The source of the second detection transistor T4 is connected to the second fixed potential Vss2, the drain is connected to the source (point B) of the drive transistor T5, and the gate is connected to the scanning line AZL2.
The sampling transistor T1 has one end connected to the signal line DTL, the other end connected to the gate (point A) of the drive transistor T5, and the gate connected to the scanning line WSL.
The switching transistor T3 has a drain connected to the power supply potential Vcc, a source connected to the drain of the drive transistor T5, and a gate connected to the scanning line DSL.

The sampling transistor T1 operates when selected by the scanning pulse WS given from the write scanner 14 by the scanning line WSL, samples the input signal Vsig from the signal line DTL, and holds it in the holding capacitor C1.
The drive transistor T5 drives the organic EL element 1 by current according to the signal potential held in the holding capacitor C1.
The switching transistor T3 conducts when it is selected by the scanning pulse DS supplied from the drive scanner 15 by the scanning line DSL, and supplies a current from the power supply potential Vcc to the drive transistor T5.
The first detection transistor T2 is selected and turned on at a predetermined timing by a scanning pulse AZ1 provided from the first AZ scanner 12 by the scanning line AZL1.
The second detection transistor T4 is selected and turned on at a predetermined timing by the scanning pulse AZ2 given from the second AZ scanner 13 by the scanning line AZL2.

The threshold voltage Vth of the drive transistor T5 is detected prior to the current drive of the organic EL element 1 by the operation of the first and second detection transistors T2 and T4, and the detected threshold voltage is used to cancel the influence in advance. An operation (threshold detection operation) held in the holding capacitor C1 is executed.
Further, during the period in which the sampling transistor T1 and the switching transistor T3 are both conductive, a correction operation for the variation in mobility of the drive transistor T5 is performed.

The fixed potential Vss2 is set lower than the level obtained by subtracting the threshold voltage Vth of the drive transistor T5 from the fixed potential Vss1. That is, Vss2 <Vss1-Vth.
The fixed potential Vss2 is set smaller than the sum of the threshold voltage Vel of the organic EL element 1 and the cathode potential Vcat (Vss2 <Vthel + Vcat).

The operation of the pixel circuit 10 will be described with reference to FIG.
FIG. 3 shows a timing chart of the scanning pulses DS, WS, AZ1, and AZ2 given by the scanning lines DSL, WSL, AZL1, and AZL2. As can be seen from the above configuration, this is the ON / OFF timing of the switching transistor T3, the sampling transistor T1, the detection transistor T2, and the detection transistor T4, respectively.
FIG. 3 also shows fluctuations in the point A potential and the point B potential.

  Time tm0 to tm8 in the timing chart of FIG. 3 is one cycle in which the organic EL element 1 which is a light emitting element is driven to emit light, for example, one frame period of image display. One frame period is composed of a non-light emission period and a light emission period of the organic EL element 1, and for example, the time point tm0 is the end timing of the previous one frame and the start timing of the current one frame.

In the period up to the time point tm0 in FIG. 3, that is, the period immediately before the end of the previous frame, the scanning line pulses DS, WS, AZ1, and AZ2 are at the low level. Therefore, the p-channel switching transistor T3 is in the on state, while the sampling transistor T1 and the detection transistors T2 and T4 are in the off state.
At this time, the drive transistor T5 causes a drive current to flow according to the potential held in the holding capacitor C1, thereby causing the organic EL element 1 to emit light. At this time, the source potential (point B potential) of the drive transistor T5 is held at a predetermined operating point.
Since the source of the drive transistor T5 is connected to the power source Vcc and is always set to operate in the saturation region, the drive transistor T5 functions as a constant current source, and the current Ids flowing through the organic EL element 1 is the drive transistor. According to the gate-source voltage Vgs of T5,
Ids = (1/2) · μ · (W / L) · Cox · (Vgs−Vth) ² (Equation 1)
It becomes. Where Ids is the current flowing between the drain and source of a transistor operating in the saturation region, μ is the mobility, W is the channel width, L is the channel length, Cox is the gate capacitance, and Vth is the threshold voltage of the drive transistor T5. Yes.

One frame period starts from time tm0. At this time, the scanning pulse DS rises to a high level. As a result, the switching transistor T3 is turned off, the current supply to the organic EL element 1 is stopped, and a non-emission period is entered.
At time tm1, the scanning pulse AZ2 rises to a high level. As a result, the detection transistor T4 is turned on, and the potential at the point B is lowered to the fixed potential Vss2.
Further, at time tm2, the scanning pulse AZ1 rises to a high level. As a result, the detection transistor T2 is turned on, and the potential at the point A is lowered to the fixed potential Vss1.

Since the fixed potential Vss2 is set lower than the level obtained by subtracting the threshold voltage Vth of the drive transistor T5 from the fixed potential Vss1 as described above, the drive transistor T5 maintains the on state.
Further, the voltage values of the fixed potentials Vss1 and Vss2 are set so that the voltage Vel (= point B potential) applied to the organic EL element 1 is smaller than the sum of the threshold voltage Vthel and the cathode voltage Vcat of the organic EL element 1. Therefore, no current flows through the organic EL element 1, and therefore the non-light emitting state is maintained.

Thereafter, the scanning pulse AZ2 is lowered to a low level, and the detection transistor T4 is turned off. Then, the scanning pulse DS is lowered at a time tm3, and the switching transistor T3 is turned on.
At this time, the potential at the point B increases due to the drain current flowing through the drive transistor T5, and the gate-source voltage Vgs of the drive transistor T5 takes the threshold voltage Vth after a lapse of a certain time. At this time, the voltage Vel applied to the organic EL element 1 is Vs = Vss1−Vth ≦ Vcat + Vthel.
At this time, the potential difference Vth (that is, the threshold voltage of the drive transistor T5) appearing between the points A and B is held in the holding capacitor C1.
As described above, as the threshold detection operation, the detection transistors T2 and T4 are selected and operated at appropriate timings by the scanning pulses AZ1 and AZ2, respectively, so that the threshold voltage Vth of the drive transistor T5 is detected, and this is detected as the storage capacitor C1. Hold on.
This is an operation for correcting the threshold fluctuation of the drive transistor T5.
At time tm4, the scanning pulse DS is set to the high level, the switching transistor T3 is turned off, and the threshold detection period (Vth correction period) ends. Thereafter, the scanning pulse AZ1 is also set to the low level, and the detection transistor T2 is turned off.

At time tm5, the scanning pulse WS is set to the high level, the sampling transistor T1 is turned on, and the signal voltage Vsig from the signal line DTL is written into the storage capacitor C1. As a result, the gate voltage of the drive transistor T5 is set to the signal voltage Vsig from the signal line DTL.
At this time, the gate-source voltage Vgs of the drive transistor T5 is determined by the holding capacitor C1, the parasitic capacitance Cel of the organic EL element 1, and the parasitic capacitance C2 of the drive transistor T5 as shown in Equation 2.
Vgs = (Cel / (Cel + C1 + C2)). (Vsig−Vss1) + Vth
... (Formula 2)
However, since the parasitic capacitance Cel is larger than the capacitances C1 and C2, the gate-source voltage Vgs of the drive transistor T5 is approximately Vsig + Vth.

At the time tm6 when the writing of the signal voltage Vsig from the signal line DTL is completed, the scan pulse DS is set to the low level while the scan pulse WS is maintained at the high level, and the switching transistor T3 is turned on.
Thereafter, the scanning pulse WS is set to the low level at the time tm7, but the period in which the switching transistor T3 and the sampling transistor T1 are both conducted by the scanning pulses DS and WS is the mobility correction period of the drive transistor T5.
At this time, the B point potential increases according to the mobility of the drive transistor T5. That is, the source potential of the drive transistor T5 has a large amount of increase in the source potential during the mobility correction period if the mobility is large, and the amount of increase in the source potential is small if the mobility is small. This results in an operation of adjusting the potential difference between point A and point B in the light emission period according to the mobility.

At time tm7, the scanning pulse WS is set to the low level, and the light emission period is started.
As apparent from Equation 1 above, in the saturation region, the drain current Ids of the drive transistor T5 is controlled by the gate-source voltage Vgs, but the gate-source voltage Vgs ( = Vsig + Vth) is constant, the drive transistor T5 operates as a constant current source for flowing a constant current to the organic EL element 1.
As a result, the potential at point B rises to a voltage at which current flows through the organic EL element 1, and the organic EL element 1 emits light. That is, the light emission period with the luminance corresponding to the signal voltage Vsig in the current frame is started.

As described above, the pixel circuit 10 performs an operation for light emission of the organic EL element 1 in one frame period. As described above, threshold detection (Vth correction period from time points tm3 to tm4) and mobility correction (time points tm6 to tm6). tm7) is performed.
The threshold voltage of the drive transistor T5 is held in the storage capacitor C1 during the non-light emission period in each frame period, and the gate-source voltage Vgs = Vsig + Vth in the light emission period is set. Regardless of variations in the threshold voltage Vth of the drive transistor T5 in each pixel circuit 10, a current corresponding to the signal potential Vsig can be applied to the organic EL element 1. That is, high image quality can be maintained without causing uneven brightness on the screen even if the threshold voltage Vth changes with time or varies.
In addition, since the drain current varies depending on the mobility of the drive transistor T5, the image quality deteriorates due to variations in the mobility of the drive transistor T5 for each pixel circuit 10, but the mobility correction in the non-light emitting period causes the drive transistor T5 to The source potential is obtained according to the magnitude of the mobility, and as a result, the gate-source potential is adjusted so as to absorb the mobility variation of the drive transistor T5 of each pixel circuit 10. Therefore, the image quality due to the mobility variation is improved. The decline is also eliminated.

By the way, in the display device of this example, the mobility correction is performed during the period in which the scanning pulses WS and DS overlap as described above. That is, the mobility correction period is controlled by the phase difference between the two types of scanning pulses DS and WS. Therefore, the timing of each scanning pulse WS, DS is important.
As shown in FIGS. 1 and 2, the write scanner 14 that generates the scanning pulse WS and the drive scanner 15 that generates the scanning pulse DS are arranged on the right side of the pixel array unit 20. If the various circuit systems constituting the write scanner 14 and the drive scanner 15 are simply arranged, the result is as shown in FIG. 12 described above, and the scanning line DSL from the drive scanner 15 and the scanning line WSL from the write scanner 14 have wiring lengths. The difference will occur.
As described with reference to FIGS. 11 and 13, if a difference in delay time occurs between the scan pulse WS and the scan pulse DS due to the difference in wiring length, accurate operation control in the pixel circuit 10 may not be performed. is there.

That is, in the operation described with reference to FIG. 3, the period length as the mobility correction period varies depending on the delay time difference between the scan pulse WS and the scan pulse DS.
The mobility correction period is adjusted, for example, in units of 100 nsec as a period length within a range of 500 to 2000 nsec, and is set to an appropriate period length.
Temporarily, the circuit units of the drive scanner 15 and the write scanner 14 are arranged as shown in FIG. 12, and the difference in wiring length between the scanning line DSL from the drive scanner 15 and the scanning line WSL from the write scanner 14 is shown in FIG. It is assumed that the width is 1000 μm and the width of each wiring is 5 μm. When the wiring sheet resistance value is 2.2Ω, the ON resistance value is 50 kΩ, and the wiring capacitance is 500 fF, the delay time difference between the scanning pulses DS and WS is about 25 nsec.
That is, an appropriate period length is set in units of 100 nsec as the mobility correction period, but about a quarter of the time is affected by the pulse delay. As a result, an appropriate mobility correction operation may not be realized.

Therefore, in this example, the difference between the wiring lengths of the scanning lines WSL and DSL is reduced, and the delay time difference between the scanning pulses WS and DS is reduced.
Hereinafter, the configuration of the write scanner 14 and the drive scanner 15 for reducing the delay time difference will be described.

FIG. 4 shows the internal configuration of the write scanner 14 and the drive scanner 15 arranged on the right side of the pixel array unit 20 in the order of arrangement of each circuit.
The write scanner 14 includes a shift register unit 21, a clock supply unit 22, a logic unit 23, a level conversion unit 24, and a buffer unit 25. The shift register unit 21, the clock supply unit 22, and the logic unit 23 are the scan pulse generation circuit portion of the write scanner 14, and the pulses generated by the scan pulse generation circuit portion are passed through the level conversion unit 24 and the buffer unit 25. It is set as the structure which outputs.
The drive scanner 15 includes a shift register unit 31, a clock supply unit 32, a logic unit 33, a level conversion unit 34, and a buffer unit 35. The shift register unit 31, the clock supply unit 32, and the logic unit 33 are the scan pulse generation circuit portion of the drive scanner 15, and the pulses generated by the scan pulse generation circuit portion are passed through the level conversion unit 34 and the buffer unit 35. It is set as the structure which outputs.

The shift register units 21 and 31, the clock supply units 22 and 32, and the logic units 23 and 33 are provided with a voltage VH of, for example, + 10V and a power supply line of voltage VL1 of, for example, 0V (ground potential), and + 10V to 0V. Operates at the operating power supply voltage.
The level converters 24 and 34 and the buffer units 25 and 35 are provided with a power line of a voltage VH of + 10V and a voltage VL2 of -5V, for example, and operate with an operating power supply voltage of + 10V to -5V.
A clock CK having a predetermined frequency is supplied to the clock supply units 22 and 32 through a clock line.

In the write scanner 14, the pulse output from the shift register unit 21 is used for the processing of the logic unit 23, thereby generating a waveform corresponding to the scanning pulse WS. The clock supply unit 22 supplies the clock CK to the shift register 21.
The pulse waveform generated by the logic unit 23 is level-converted by the level conversion unit 24 into a pulse of +10 V to −5 V as a level suitable for operation control in the pixel circuit 10. Then, the pulse is waveform-shaped by the buffer unit 25 and output to the scanning line WSL as the scanning pulse WS by the write scanner 14.

In the drive scanner 15, a pulse corresponding to the scanning pulse DS is generated by using the pulse output from the shift register unit 31 for processing of the logic unit 33. The clock supply unit 32 supplies the clock CK to the shift register 31.
The pulse waveform generated by the logic unit 33 is level-converted by the level conversion unit 34 into a pulse of +10 V to −5 V as a level suitable for operation control in the pixel circuit 10. The pulse is shaped by the buffer unit 35 and output to the scanning line DSL as a scanning pulse DS by the drive scanner 15.

  As can be seen from FIG. 4, in the drive scanner 15, the circuit portions as the buffer unit 35 and the level conversion unit 34 are separated from the scan pulse generation circuit portion by the logic unit 33, the clock supply unit 32, and the shift register unit 31. The buffer unit 35 and the level conversion unit 34 are arranged at positions closer to the pixel array unit 20 than the write scanner 14. As a result, the buffer unit 35, the level conversion unit 34, the buffer unit 25, and the level conversion unit 24 are arranged in order from the side closer to the pixel array unit 20.

  Since the output terminal P1 of the write scanner 14 is an output terminal of the buffer unit 25 and the output terminal P3 of the drive scanner 15 is an output terminal of the buffer unit 35, each part of the write scanner 14 and the drive scanner 15 is thus constructed. Is arranged, the difference between the wiring lengths, that is, the distance between the output ends P1 and P3 of the buffer units 25 and 35 can be set to about 200 to 300 μm, for example. That is, it becomes the length of the part necessary for the circuit arrangement of the buffer unit 35 and the level conversion unit 34, and the difference in the wiring length is smaller than that in the conventional configuration as shown in FIG. It can be shortened to about 1/5.

That is, in this example, for the write scanner 14 and the drive scanner 15 arranged on the same side of the pixel array unit 20, the buffer unit 35 and the level conversion unit 34 of the drive scanner 15, the buffer unit 25 of the write scanner 14, The level conversion unit 24 is arranged at the position closest to the pixel array unit 20.
As a result, the difference in wiring length between the scanning line WSL from the write scanner 14 and the scanning line DSL from the drive scanner 15 is reduced. By reducing the difference in wiring length, the difference in delay time of the scan pulses DS and WS due to the influence of the difference in wiring resistance and wiring capacitance is also reduced.
As a result, the mobility correction period determined by the phase difference between the scanning pulses WS and DS is almost appropriately controlled, and the operation of the pixel circuit 10 is accurately performed.

  The power scanner 14 and the drive scanner 15 are provided with power lines for voltages VH, VL1, and VL2, but the buffer unit 35, the level converting unit 34, the buffer unit 25, and the level converting unit 24 are arranged at a combined position. As a result, there is an advantage that the power supply lines of the voltages VL2 and VL1 can be easily routed.

In FIG. 4, the buffer unit 35 and the level conversion unit 34 of the drive scanner 15 are arranged closer to the pixel array unit 20 than the buffer unit 25 and the level conversion unit 24 of the write scanner 14. It may be. That is, the buffer unit 25, the level conversion unit 24, the buffer unit 35, and the level conversion unit 34 may be arranged in order from the side closer to the pixel array unit 20.
Further, the logic unit 23, the clock supply unit 22, and the shift register unit 21 of the write scanner 14 are arranged on the side farther from the pixel array unit 20 than the logic unit 33, the clock supply unit 32, and the shift register unit 31 of the drive scanner 15. An example is also conceivable.

[Second Embodiment]

A second embodiment will be described with reference to FIG. The overall configuration and operation of the display device are the same as those described with reference to FIGS.
In the second embodiment, as can be seen from FIG. 5, the buffer unit 35 of the drive scanner 15, the buffer unit 25 of the write scanner 14, and the level conversion unit 34 of the drive scanner 15 in order from the pixel array unit 20. In this state, the level converter 24 of the write scanner 14 is arranged.

  Since the output terminal P1 of the write scanner 14 is an output terminal of the buffer unit 25 and the output terminal P3 of the drive scanner 15 is an output terminal of the buffer unit 35, the write scanner 14 and the drive scanner as shown in FIG. When the 15 portions are arranged, the difference in wiring length, that is, the distance between the output ends P1 and P3 of the buffer portions 25 and 35 can be set to about 100 to 150 μm, for example. That is, the length of the portion necessary for the circuit arrangement of the buffer unit 35 is reduced, and the difference in the wiring length is reduced to about 1/10 compared to the conventional configuration as shown in FIG. Can be shortened.

That is, in this example, for the write scanner 14 and the drive scanner 15 arranged on the same side of the pixel array unit 20, the buffer unit 35 of the drive scanner 15 and the buffer unit 25 of the write scanner 14 include the pixel array unit. By arranging them together at a position closest to 20, the difference in wiring length between the scanning line WSL from the write scanner 14 and the scanning line DSL from the drive scanner 15 is made larger than that in the first embodiment. Further reduction. Since the difference in the wiring length is further reduced, the difference in the delay time of the scan pulses DS and WS due to the influence of the difference in the wiring resistance and the wiring capacitance becomes a shorter time. The determined mobility correction period is further appropriately controlled, and the operation of the pixel circuit 10 is accurately performed.
Further, since the level converters 34 and 24 are also arranged after the buffers 35 and 25, there is also an advantage that the power lines of the voltages VL2 and VL1 can be easily routed in this case.

Note that the buffer unit 25 of the write scanner 14, the buffer unit 35 of the drive scanner 15, the level conversion unit 34 of the drive scanner 15, and the level conversion unit 24 of the write scanner 14 may be arranged in this order from the pixel array unit 20. Good.
Alternatively, the buffer unit 35 of the drive scanner 15, the buffer unit 25 of the write scanner 14, the level conversion unit 24 of the write scanner 14, and the level conversion unit 34 of the drive scanner 15 may be arranged in order from the pixel array unit 20. Good.
Alternatively, the buffer unit 25 of the write scanner 14, the buffer unit 35 of the drive scanner 15, the level conversion unit 24 of the write scanner 14, and the level conversion unit 34 of the drive scanner 15 may be arranged in order from the pixel array unit 20. Good.

Further, the logic unit 23, the clock supply unit 22, and the shift register unit 21 of the write scanner 14 are arranged on the side farther from the pixel array unit 20 than the logic unit 33, the clock supply unit 32, and the shift register unit 31 of the drive scanner 15. An example is also conceivable.

[Third Embodiment]

As a third embodiment, an example in which the level converter 34 is not provided in the write scanner 14 and the drive scanner 15 will be given.
Since this is a case where the pixel circuit 10 is a low-voltage drive type circuit, first, the configuration and operation of the pixel circuit 10 will be described with reference to FIGS.
The overall configuration of the display device is such that a write scanner 14 and a drive scanner 15 are arranged on the side of the pixel array 20 in which the pixel circuits 10 are arranged in a matrix, and an AZ scanner is arranged on the other side. One is arranged.

  This pixel circuit 10 includes an organic EL element 1 as a light emitting element, two holding capacitors Cc and Cs, five p-channels as a sampling transistor T11, a drive transistor T15, a switching transistor T13, and detection transistors T12 and T14. It consists of a thin film transistor (TFT).

The sampling transistor T11 has one end connected to the signal line DTL and the other end connected to the connection point of the holding capacitors Cc and Cs. A scanning pulse WS from the write scanner 14 is supplied to the gate of the sampling transistor T11.
Switching transistor T13 has its drain connected to power supply potential Vcc and its source connected to the source of drive transistor T5. A scanning line pulse DS from the drive scanner 15 is supplied to the gate of the switching transistor T13.
One end of the detection transistor T12 is connected to the source of the drive transistor T15, and the other end is connected to the connection point of the holding capacitors Cc and Cs.
The detection transistor T14 has one end connected to the gate of the drive transistor T15 and the other end connected to the fixed potential Vini.
A scanning pulse AZ from the AZ scanner is supplied to each gate of the detection transistors T12 and T14.
The storage capacitor Cs has one end connected to the power supply voltage Vcc line and the other end connected to the storage capacitor Cc.
The storage capacitor Cc has one end connected to the gate of the drive transistor T15 and the other end connected to the storage capacitor Cs.
The organic EL element 1 which is a light emitting element has an anode connected to the drain of the drive transistor T5 and a cathode connected to a predetermined cathode potential Vcat.
The source node of the drive transistor T15 is shown as point C, and the gate node is shown as point D.
In this pixel circuit, for example, Vcc = 4.8V and Vcat = −7.6V are set.

The operation of the pixel circuit of FIG. 6 will be described with reference to FIG.
FIG. 6 shows a timing chart of the scanning pulses WS, AZ, and DS. This is the on / off timing of the sampling transistor T11, the detection transistors T12 and T14, and the switching transistor T13, respectively.
FIG. 6 also shows fluctuations in the point C potential and the point D potential.
Further, the time points tm10 to tm15 are one cycle in which the organic EL element 1 as a light emitting element is driven to emit light, for example, one frame period of image display. One frame period is composed of a non-light emission period and a light emission period of the organic EL element 1, and for example, a time point tm10 is an end timing of the previous one frame and a start timing of the current one frame.

At time tm10, the scanning pulse AZ is set to the low level, and the detection transistors T12 and T14 are turned on. At this time, the scanning pulse DS continues to be at a low level from the previous frame, and the switching transistor T13 remains on.
When the detection transistors T12 and T14 are turned on, the point D becomes the fixed potential Vini, and the point C potential becomes the power supply voltage Vcc.
At time tm11, the scanning pulse DS becomes high level, and the switching transistor T13 is turned off. At this timing, a Vth correction period for detecting the threshold voltage of the drive transistor T15 is started. That is, the potential at point C drops to Vini + threshold voltage Vth, and the threshold voltage Vth of the drive transistor T15 is held in the holding capacitor Cc.
At time tm12, the scanning pulse AZ is set to the high level, the detection transistors T12 and T14 are turned off, and the threshold voltage Vth correction period ends.
Thereafter, at time tm13, the scanning pulse WS is set to the low level, the sampling transistor T11 is turned on, and the signal voltage Vsig from the signal line DTL is charged in the storage capacitor Cs.
At time tm14, the scanning pulse DS is set to the low level and the switching transistor T13 is turned on, whereby a current flows through the organic EL element 1, and light emission with luminance corresponding to the signal voltage Vsig is started.

When such a low voltage driving pixel circuit 10 is used, it is not necessary to level-convert and output the scanning pulses WS and DS in the write scanner 14 and the drive scanner 15, which are shown in the first and second embodiments. There is no need to provide the level conversion units 24 and 34.
Accordingly, the configuration of the write scanner 14 and the drive scanner 15 in this example is shown in FIG. 8, and the write scanner 14 includes a shift register unit 21, a clock supply unit 22, a logic unit 23, and a buffer unit 25. 1 includes a shift register unit 31, a clock supply unit 32, a logic unit 33, and a buffer unit 35.
In the third embodiment, as can be seen from FIG. 8, the buffer unit 35 of the drive scanner 15 and the buffer unit 25 of the write scanner 14 are arranged in order from the pixel array unit 20 in order. Yes.

Since the output terminal P1 of the write scanner 14 is an output terminal of the buffer unit 25 and the output terminal P3 of the drive scanner 15 is an output terminal of the buffer unit 35, the write scanner 14 and the drive scanner as shown in FIG. When the 15 portions are arranged, the difference in wiring length, that is, the distance between the output ends P1 and P3 of the buffer portions 25 and 35 can be set to about 100 to 150 μm, for example. That is, the length of the portion necessary for the circuit arrangement of the buffer unit 35 is reduced, and the difference in the wiring length is reduced to about 1/10 compared to the conventional configuration as shown in FIG. The difference between the delay times of the scanning pulses DS and WS can be reduced.
In the operation example of FIG. 7, mobility correction is not performed, and a certain operation period is not determined by the phase difference between the scan pulses WS and DS. However, it is not preferable as the pixel operation that the timing deviation due to the delay time difference occurs in the scanning pulses WS and DS. On the other hand, in this example, the difference between the delay times of the scan pulses WS and DS due to the circuit arrangement is minimized, so that the scan pulse timing is accurate and an appropriate pixel circuit operation is executed.

Note that the buffer unit 25 of the write scanner 14 and the buffer unit 35 of the drive scanner 15 may be arranged in order from the side closer to the pixel array unit 20.
Further, the logic unit 23, the clock supply unit 22, and the shift register unit 21 of the write scanner 14 are arranged on the side farther from the pixel array unit 20 than the logic unit 33, the clock supply unit 32, and the shift register unit 31 of the drive scanner 15. An example is also conceivable.

[Fourth Embodiment]

A fourth embodiment will be described with reference to FIGS.
FIG. 9 shows an arrangement image of the write scanner 14 and the drive scanner 15 arranged on the right side of the pixel array unit 20.
The write scanners 14-1, 14-2,..., 14-m are circuit components as the write scanner 14 corresponding to the scanning lines WSL1, WSL2,.
Drive scanners 15-1, 15-2,..., 15-m are circuit components as drive scanners 15 corresponding to the respective scanning lines DSL1, DSL2,.
In other words, in this example, the write scanner 14 and the drive scanner 15 are arranged in the vertical direction for each circuit component corresponding to one scanning line.

The configuration of the drive scanner 15-1 and the write scanner 14-1 is shown in FIG. The same applies to the drive scanner 15-2 and the write scanner 14-2 and later.
As illustrated in FIG. 10, the drive scanner 15-1 includes a shift register unit 31, a clock supply unit 32, a logic unit 33, a level conversion unit 34, and a buffer unit 35.
The write scanner 14-1 includes a shift register unit 21, a clock supply unit 22, a logic unit 23, a level conversion unit 24, and a buffer unit 25.
This configuration is an example having the level conversion units 24 and 34, and when the low voltage drive pixel circuit 10 is employed as in the third embodiment, the level conversion units 24 and 34 are not necessary. .

The output terminal P1 of the write scanner 14-1 is the output terminal of the buffer unit 25, and the output terminal P3 of the drive scanner 15-1 is the output terminal of the buffer unit 35. As can be seen from FIG. The output terminals P1 and P3 of the units 25 and 35 are equidistant when viewed from the pixel array unit 20, that is, the scanning line WSL1 from the write scanner 14-1 and the scanning line DSL1 from the drive scanner 15-1 There is no difference in wiring length. Accordingly, there is no difference between the delay times of the scan pulses DS and WS.
As a result, the operation of the pixel circuit 10 is most accurately performed such that the mobility correction period determined by the phase difference between the scanning pulses WS and DS is appropriately controlled.

The power scanners 15-1 to 14-m and the drive scanners 15-1 to 15-m are provided with power lines VH, VL1, and VL2, respectively. Since the unit 34, the buffer unit 25, and the level conversion unit 24 are gathered in the vicinity of the pixel array unit 20, the power supply lines for the voltages VL2 and VL1 can be easily routed.
Further, the light scanners 14-1... 14-m and the drive scanners 15-1... 15-m are arranged in the vertical direction, so that the number of power supply lines arranged in the vertical direction is reduced, and wiring is routed. It becomes easier. Further, only one clock CK wiring is required in the vertical direction for the clock generators 32 and 22, which also facilitates the wiring layout.

Although the first to fourth embodiments have been described above, various modifications can be considered as the present invention.
In the embodiment, the write scanner 14 and the drive scanner 15 are given as an example of a plurality of vertical scanner units arranged on the same side of the pixel array unit 20, but the left side of the pixel array unit 20 in FIGS. The circuit arrangement configuration described above may be applied to the two first AZ scanners 12 and the second AZ scanner 13 shown in FIG. That is, the buffer unit, or the buffer unit and the level conversion unit are collectively arranged close to the pixel array unit 20.
For example, in the operation example of FIG. 2, the correction period of the threshold voltage Vth is controlled at the falling edge and the rising edge of the scanning pulse DS in the period in which the scanning pulse AZ1 is at the high level and the scanning pulse AZ2 is at the low level. Consider an operation example in which the threshold voltage Vth correction period is started by lowering the scan pulse AZ2 while the switching transistor T3 is turned on by the scan pulse DS, and the threshold voltage Vth correction period is ended by lowering the scan pulse AZ1. It is done. Then, the threshold voltage Vth correction period is defined by the phase difference between the scanning pulses AZ1 and AZ2. In this case, the scanning pulses AZ1 and AZ2 are caused by the difference in the wiring length reaching the pixel array unit 20 for the scanning lines AZL1 and AZL2. The delay time difference affects the operation of the pixel circuit 10.
Therefore, it is effective to reduce the delay time difference between the scanning pulses AZ1 and AZ2 by arranging the buffer unit or the buffer unit and the level converting unit together so as to be close to the pixel array unit 20.
In addition, it is naturally possible to arrange the first AZ scanner 12 and the second AZ scanner 13 so as to be arranged in the vertical direction for each circuit component corresponding to one scanning line as in the example of FIG.

  In the above example, two vertical scanner units (for example, the drive scanner 15 and the write scanner 14) are arranged on one side of the pixel array unit 20, but three or more are arranged on one side of the pixel array unit 20. When the vertical scanner section is provided, the output buffer circuits of each vertical scanner section are collectively arranged at a position close to the pixel array so as to reduce the difference in the wiring length of each vertical section, or the wiring length of the vertical scanner section is reduced. In order to eliminate the difference, it is also conceivable that the circuit components corresponding to one scanning line are arranged in the vertical direction.

1 is a block diagram of a display device according to an embodiment of the present invention. It is a circuit diagram of a pixel circuit of a display device of an embodiment. FIG. 11 is an explanatory diagram of the operation of the pixel circuit of the embodiment. It is a block diagram of composition of a write scanner and a drive scanner of a 1st embodiment. It is a block diagram of the structure of the write scanner and drive scanner of 2nd Embodiment. FIG. 6 is a circuit diagram of a pixel circuit according to a third embodiment. It is explanatory drawing of operation | movement of the pixel circuit of 3rd Embodiment. It is a block diagram of the structure of the write scanner and drive scanner of 3rd Embodiment. It is explanatory drawing of arrangement | positioning of the write scanner and drive scanner of 4th Embodiment. It is a block diagram of the structure of the write scanner and drive scanner of 4th Embodiment. It is explanatory drawing of a structure of an organic electroluminescence display. It is a block diagram of the structure of the conventional write scanner and drive scanner. It is explanatory drawing of the delay difference of a scanning pulse.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Organic EL element, 10 pixel circuit, 11 horizontal selector, 12 1st AZ scanner, 13 2nd AZ scanner, 14 write scanner, 15 drive scanner, 21, 31 shift register part, 22, 32 clock supply part, 23, 33 logic part , 24, 34 level conversion unit, 25, 35 buffer unit, C1 storage capacitor, T1 sampling transistor, T2, T4 detection transistor, T3 switching transistor, T5 drive transistor

Claims (3)

A pixel array in which pixel circuits are arranged in a matrix;
In order to apply a signal that defines light emission luminance to each of the pixel circuits arranged in a matrix, signal lines arranged in the column direction on the pixel array;
In order to control the operation of each of the pixel circuits arranged in a matrix, a plurality of types of scanning lines arranged in the row direction on the pixel array;
A signal line driver for driving the signal line;
As a vertical scanner unit comprising a scan pulse generation circuit unit and an output buffer circuit unit, a plurality of vertical scanner units for driving each of the plurality of types of scanning lines,
With
Among two or more vertical scanner units, for two or more vertical scanner units arranged on the same side of the pixel array, the output buffer circuit unit in each vertical scanner unit is the most in the pixel array. A display device characterized by being arranged together in a close position. Each vertical scanner section is provided with a level conversion circuit section for level-converting the scanning pulse from the scanning pulse generation circuit section and supplying the level to the output buffer circuit section.
Among the plurality of vertical scanner units, for two or more vertical scanner units arranged on the same side of the pixel array, the output buffer circuit unit and the level conversion circuit unit in each vertical scanner unit are The display device according to claim 1, wherein the display devices are collectively arranged at a position closest to the pixel array. A pixel array in which pixel circuits are arranged in a matrix;
In order to apply a signal that defines light emission luminance to each of the pixel circuits arranged in a matrix, signal lines arranged in the column direction on the pixel array;
In order to control the operation of each of the pixel circuits arranged in a matrix, a plurality of types of scanning lines arranged in the row direction on the pixel array;
A signal line driver for driving the signal line;
A plurality of vertical scanner units for driving each of the plurality of types of scanning lines;
With
Among the plurality of vertical scanner units, for two or more vertical scanner units disposed on the same side of the pixel array,
A display device, wherein vertical scanning circuit components corresponding to one scanning line are arranged in a vertical direction.

Images