JP2008216614A - Display and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably write input signal voltage and correct shift while preventing luminance degradation due to the voltage drop between the gate and source of the drive transistor caused by coupling when turning off the writing transistor. <P>SOLUTION: On the basis of the size of both the transistors P11, N11 of the P-channel MOS transistor P11 and the N-channel MOS transistor N11 when almost the same current flows in them in the last stage buffer 431 in the output circuit 43 of a write scanning circuit, the size of the P channel MOS transistor P11 is made larger than the reference size and the size of the N-channel MOS transistor N11 is made smaller. The output pulse B used as the write pulse WS can quickly rises and falls gradually. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device and an electronic apparatus, and more particularly, to a planar (flat panel type) display device in which pixels including electro-optic elements are arranged in a matrix (matrix shape), and an electronic apparatus having the display device.

  In recent years, in the field of display devices that perform image display, a flat display device in which pixels (pixel circuits) including light emitting elements are arranged in a matrix, for example, as a light emitting element of a pixel, according to a current value flowing through the device. So-called current-driven electro-optic elements whose emission brightness changes, for example, organic EL display devices using organic EL (Electro Luminescence) elements utilizing the phenomenon of light emission when an electric field is applied to an organic thin film have been developed and commercialized. It is being advanced.

  The organic EL display device has the following features. That is, since the organic EL element can be driven with an applied voltage of 10 V or less, it has low power consumption and is a self-luminous element. Therefore, for each pixel including the liquid crystal cell, the liquid crystal cell emits light from the light source (backlight). Compared to a liquid crystal display device that displays an image by controlling the light intensity, the image is highly visible, and the liquid crystal display device does not require an illumination member such as a backlight. Is easy. Furthermore, since the response speed of the organic EL element is as high as about several μsec, an afterimage at the time of displaying a moving image does not occur.

  In the organic EL display device, as in the liquid crystal display device, a simple (passive) matrix method and an active matrix method can be adopted as the driving method. However, although a simple matrix display device has a simple structure, there is a problem that it is difficult to realize a large and high-definition display device. Therefore, in recent years, the current flowing through the electro-optical element is controlled by an active element provided in the same pixel circuit as the electro-optical element, for example, an insulated gate field effect transistor (generally, a TFT (Thin Film Transistor)). Active matrix display devices have been actively developed.

  By the way, it is generally known that the IV characteristic (current-voltage characteristic) of the organic EL element is deteriorated with time (so-called deterioration with time). In a pixel circuit using an N-channel TFT as a transistor for driving an organic EL element with current (hereinafter referred to as “driving transistor”), the organic EL element is connected to the source side of the driving transistor. When the IV characteristic of the organic EL element deteriorates with time, the gate-source voltage Vgs of the driving transistor changes, and as a result, the emission luminance of the organic EL element also changes.

  This will be described more specifically. The source potential of the drive transistor is determined by the operating point of the drive transistor and the organic EL element. When the IV characteristic of the organic EL element deteriorates, the operating point of the driving transistor and the organic EL element fluctuates. Therefore, even if the same voltage is applied to the gate of the driving transistor, the source potential of the driving transistor is Change. As a result, since the source-gate voltage Vgs of the drive transistor changes, the value of the current flowing through the drive transistor changes. As a result, since the value of the current flowing through the organic EL element also changes, the light emission luminance of the organic EL element changes.

  In addition, in a pixel circuit using a polysilicon TFT, in addition to the deterioration over time of the IV characteristics of the organic EL element, the threshold voltage Vth of the driving transistor and the mobility μ of the semiconductor thin film constituting the channel of the driving transistor are changed over time. The threshold voltage Vth and the mobility μ vary from pixel to pixel due to variations in manufacturing processes (individual transistor characteristics vary).

  If the threshold voltage Vth and mobility μ of the driving transistor differ from pixel to pixel, the current value flowing through the driving transistor varies from pixel to pixel. Therefore, even if the same voltage is applied to the gate of the driving transistor, the organic EL element The light emission luminance varies among pixels, and as a result, the uniformity of the screen is lost.

  Therefore, even if the IV characteristic of the organic EL element deteriorates with time, or the threshold voltage Vth or mobility μ of the driving transistor changes with time, the light emission luminance of the organic EL element is not affected by those effects. In order to keep constant, the compensation function for the characteristic variation of the organic EL element, the correction for the variation of the threshold voltage Vth of the driving transistor (hereinafter referred to as “threshold correction”), the mobility μ of the driving transistor Each pixel circuit is provided with a correction function for correction of fluctuations (hereinafter referred to as “mobility correction”) (see, for example, Patent Document 1).

JP 2006-133542 A

  In the prior art described in Patent Document 1, each pixel circuit is provided with a compensation function for a characteristic variation of the organic EL element and a correction function for a variation in threshold voltage Vth and mobility μ of the drive transistor, so that Even if the IV characteristics deteriorate over time or the threshold voltage Vth and mobility μ of the driving transistor change over time, the light emission luminance of the organic EL element can be kept constant without being affected by them. However, on the other hand, the number of elements constituting the pixel circuit is large, which hinders miniaturization of the pixel size.

  On the other hand, in order to reduce the number of elements and the number of wirings constituting the pixel circuit, for example, the power supply potential supplied to the drive transistor of the pixel circuit can be switched, and the organic EL element is switched by switching the power supply potential. It is conceivable to adopt a method of omitting the transistor for controlling the light emission period / non-light emission period by providing the drive transistor with the function of controlling the light emission period / non-light emission period.

  By adopting such a method, the minimum number of elements, specifically, a write transistor that samples the input signal voltage and writes it in the pixel, and a storage capacitor that holds the input signal voltage written by this write transistor, A pixel circuit can be configured with a driving transistor that drives the electro-optic element based on the input signal voltage held in the holding capacitor.

  As described above, in the case of adopting a configuration in which the number of elements constituting the pixel circuit is reduced by using the drive transistor as a transistor for controlling the light emission period / non-light emission period of the organic EL element, the input signal voltage is written by the write transistor. At the same time, the mobility correction is performed. Incidentally, in the related art described in Patent Document 1, mobility correction is performed after the writing period of the input signal voltage is over.

  As described above, if the mobility correction is performed at the same time as the input signal voltage is written, the mobility correction is performed in a state where the input signal voltage is not sufficiently written. As a result, unevenness occurs and the image quality deteriorates (details will be described later).

  Further, when the response speed of the fall of the write pulse for driving the write transistor is fast (when the write pulse falls sharply), the gate of the drive transistor is coupled by coupling when the write transistor is turned off as shown in FIG. Since the potential is drastically lowered and the gate-source voltage Vgs of the driving transistor is lowered (shrinks) along with this, there is a problem that the luminance is lowered by the amount that the gate-source voltage Vgs is lowered.

  Therefore, the present invention stably performs input signal voltage writing and mobility correction, and prevents a decrease in luminance due to a decrease in gate-source voltage of the driving transistor due to coupling when the writing transistor is off. An object of the present invention is to provide a display device capable of stably writing an input signal voltage and an electronic apparatus having the display device.

  To achieve the above object, the present invention provides an electro-optic element, a write transistor that samples and writes an input signal voltage, a storage capacitor that holds the input signal voltage written by the write transistor, and the storage capacitor. A pixel array unit in which pixels including a driving transistor for driving the electro-optic element based on the held input signal voltage are arranged in a matrix and connected in series between a first power source and a second power source A scanning circuit having a final stage buffer including a P-channel transistor and an N-channel transistor, and selectively scanning each pixel of the pixel array unit in a row unit by applying a write pulse output through the final stage buffer to the write transistor; A display device comprising: the P-channel transistor and the N channel. The size of the P channel transistor is set larger than the reference size of the P channel transistor when the size of the P channel transistor and the size of the N channel transistor when a current of the same level flows through the transistor is used as a reference, The size of the N-channel transistor is set smaller than a reference size of the N-channel transistor.

  In the display device having the above-described configuration and the electronic device using the display device, the size of the P-channel transistor constituting the final stage buffer is set to be larger than the reference size, so that writing is determined by the size of the P-channel transistor. The response speed when the pulse transitions to the active state can be increased compared to the case of the reference size. As a result, writing of the input signal voltage by the writing pulse can be performed earlier than in the case of the reference size, that is, the mobility correction can be performed in a state where the input signal voltage is sufficiently written. Writing and mobility correction can be performed stably.

  In addition, since the size of the N-channel transistor constituting the final stage buffer is set smaller than the reference size, the response speed when the write pulse transits to the inactive state, which is determined by the size of the N-channel transistor, is used as a reference. Can be slower than size. Accordingly, a decrease in the gate potential of the drive transistor due to coupling when the write transistor is turned off can be suppressed, so that a decrease in the gate-source voltage of the drive transistor can be suppressed.

  According to the present invention, the writing of the input signal voltage and the mobility correction can be performed stably, so that variations in mobility correction among pixels can be eliminated and the image quality can be improved. In addition, since it is possible to suppress a decrease in the gate-source voltage of the driving transistor due to coupling when the writing transistor is turned off, the input signal can be prevented while preventing a decrease in luminance due to the decrease in the gate-source voltage. Voltage writing can be performed stably.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a system configuration diagram showing an outline of the configuration of an active matrix display device according to an embodiment of the present invention. Here, as an example, a case of an active matrix type organic EL display device using a current-driven electro-optical element whose emission luminance changes according to a current value flowing through the device, for example, an organic EL element as a pixel light-emitting element is taken as an example. Will be described.

  As shown in FIG. 1, the organic EL display device 10 according to this embodiment includes a pixel array unit 30 in which pixels (PXLC) 20 are two-dimensionally arranged in a matrix (matrix shape), and the pixel array unit 30. A driving unit that is arranged in the periphery and drives each pixel 20, for example, a writing scanning circuit 40, a power supply scanning circuit 50, and a horizontal driving circuit 60 is configured.

  The pixel array unit 30 is provided with scanning lines 31-1 to 31-m and power supply lines 32-1 to 32-m for each pixel row with respect to a pixel array of m rows and n columns. The signal lines 33-1 to 33-n are wired.

  The pixel array unit 30 is usually formed on a transparent insulating substrate such as a glass substrate, and has a flat (flat) panel structure. Each pixel 20 of the pixel array unit 30 can be formed using an amorphous silicon TFT (Thin Film Transistor) or a low-temperature polysilicon TFT. When the low-temperature polysilicon TFT is used, the scanning circuit 40, the power supply scanning circuit 50, and the horizontal driving circuit 60 can also be mounted on the display panel (substrate) 70 that forms the pixel array section 30.

  The writing scanning circuit 40 is configured by a shift register or the like, and sequentially supplies scanning signals WS1 to WSm to the scanning lines 31-1 to 31-m when writing video signals to the respective pixels 20 of the pixel array unit 30. 20 is scanned sequentially (line-sequential scanning) in units of rows.

  The power supply scanning circuit 50 is constituted by a shift register or the like, and is synchronized with the line sequential scanning by the write scanning circuit 40 and switches between a first potential Vccp and a second potential Vini lower than the first potential Vccp. DS1 to DSm are supplied to the power supply lines 32-1 to 32-m.

  The horizontal drive circuit 60 appropriately selects one of the signal voltage Vsig and the offset voltage Vofs of the video signal according to the luminance information supplied from a signal supply source (not shown), and the signal lines 33-1 to 33-33. For example, data is written all at once to each pixel 20 of the pixel array unit 30 via n. That is, the horizontal drive circuit 60 employs a line-sequential writing drive mode in which the input signal voltage Vsig is written all at once in a row (line) unit.

  Here, the offset voltage Vofs is a reference voltage (for example, equivalent to a black level) of a signal voltage of a video signal (hereinafter sometimes referred to as “input signal voltage” or simply “signal voltage”) Vsig. is there. The second potential Vini is a potential sufficiently lower than the offset voltage Vofs.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating a specific configuration example of the pixel (pixel circuit) 20. As shown in FIG. 2, the pixel 20 includes a current-driven electro-optical element, for example, an organic EL element 21, whose light emission luminance changes according to a current value flowing through the device, and the organic EL element 21 includes In addition, the driving transistor 22, the writing transistor 23, the storage capacitor 24, and the auxiliary capacitor 25 are provided.

  Here, N-channel TFTs are used as the drive transistor 22 and the write transistor 23. However, the combination of the conductivity types of the driving transistor 22 and the writing transistor 23 here is only an example, and is not limited to these combinations.

  The organic EL element 21 has a cathode electrode connected to a common power supply line 34 that is wired in common to all the pixels 20. The drive transistor 22 has a source electrode connected to the anode electrode of the organic EL element 21 and a drain electrode connected to the power supply line 32 (32-1 to 32-m).

  The writing transistor 23 has a gate electrode connected to the scanning line 31 (31-1 to 31-m), and one electrode (source electrode / drain electrode) connected to the signal line 33 (33-1 to 33-n). The other electrode (drain electrode / source electrode) is connected to the gate electrode of the drive transistor 22. The storage capacitor 24 has one end connected to the gate electrode of the drive transistor 22 and the other end connected to the source electrode of the drive transistor 22 (the anode electrode of the organic EL element 21).

  The auxiliary capacitor 25 has one end connected to the source electrode of the drive transistor 22 and the other end connected to the cathode electrode (common power supply line 34) of the organic EL element 21. The auxiliary capacitor 25 is connected in parallel to the organic EL element 21 to compensate for the capacity shortage of the organic EL element 21. Accordingly, the auxiliary capacitor 25 is not an essential component, and the auxiliary capacitor 25 can be omitted when the capacity of the organic EL element 21 is sufficient.

  In the pixel 20 having such a configuration, the writing transistor 23 becomes conductive in response to the scanning signal WS applied to the gate electrode from the writing scanning circuit 40 through the scanning line 31, and thereby from the horizontal driving circuit 60 through the signal line 33. The video signal input signal voltage Vsig or offset voltage Vofs corresponding to the supplied luminance information is sampled and written into the pixel 20. The written input signal voltage Vsig or offset voltage Vofs is held in the holding capacitor 24.

  When the potential DS of the power supply line 32 (32-1 to 32-m) is at the first potential Vccp, the driving transistor 22 is supplied with current from the power supply line 32 and is held in the storage capacitor 24. By supplying the organic EL element 21 with a drive current having a current value corresponding to the voltage value of the input signal voltage Vsig, the organic EL element 21 is driven by current.

(Pixel structure)
FIG. 3 shows an example of a cross-sectional structure of the pixel 20. As shown in FIG. 3, in the pixel 20, an insulating film 202 and a window insulating film 203 are formed on a glass substrate 201 on which pixel circuits such as a driving transistor 22 and a writing transistor 23 are formed, and a concave portion of the window insulating film 203 is formed. The organic EL element 21 is provided in 203A.

  The organic EL element 21 includes an anode electrode 204 made of metal or the like formed on the bottom of the recess 203A of the window insulating film 203, and an organic layer (electron transport layer, light emitting layer, hole transport) formed on the anode electrode 204. Layer / hole injection layer) 205 and a cathode electrode 206 made of a transparent conductive film or the like formed on the organic layer 205 in common for all pixels.

  In the organic EL element 21, the organic layer 208 is formed by sequentially depositing a hole transport layer / hole injection layer 2051, a light emitting layer 2052, an electron transport layer 2053 and an electron injection layer (not shown) on the anode electrode 204. It is formed. Then, current flows from the drive transistor 22 to the organic layer 205 through the anode electrode 204 under current drive by the drive transistor 22 in FIG. 2, whereby electrons and holes are recombined in the light emitting layer 2052 in the organic layer 205. It is designed to emit light.

  As shown in FIG. 3, after the organic EL elements 21 are formed on the glass substrate 201 on which the pixel circuit is formed via the insulating film 202 and the window insulating film 203 in units of pixels, the organic EL element 21 is interposed via the passivation film 207. The sealing substrate 208 is bonded by the adhesive 209, and the organic EL element 21 is sealed by the sealing substrate 208, whereby the display panel 70 is formed.

(Threshold correction function)
Here, the power supply scanning circuit 50 supplies power while the horizontal drive circuit 60 supplies the offset voltage Vofs to the signal lines 33 (33-1 to 33-n) after the writing transistor 23 is turned on. The potential DS of the line 32 is switched between the first potential Vccp and the second potential Vini. By switching the potential DS of the power supply line 32, a voltage corresponding to the threshold voltage Vth of the drive transistor 22 is held in the holding capacitor 24.

  The voltage corresponding to the threshold voltage Vth of the driving transistor 22 is held in the holding capacitor 24 for the following reason. Due to variations in the manufacturing process of the drive transistor 22 and changes over time, transistor characteristics such as the threshold voltage Vth and mobility μ of the drive transistor 22 vary for each pixel. Due to this variation in transistor characteristics, even if the same gate potential is applied to the drive transistor 22, the drain-source current (drive current) Ids varies from pixel to pixel, resulting in variations in light emission luminance. In order to cancel (correct) the influence of the variation in threshold voltage Vth for each pixel, a voltage corresponding to the threshold voltage Vth is held in the holding capacitor 24.

  The threshold voltage Vth of the driving transistor 22 is corrected as follows. That is, by holding the threshold voltage Vth in the storage capacitor 24 in advance, the threshold voltage Vth of the drive transistor 22 is stored in the storage capacitor 24 when the drive transistor 22 is driven by the input signal voltage Vsig. The threshold voltage Vth is corrected by offsetting the voltage corresponding to Vth, in other words.

  This is the threshold correction function. With this threshold correction function, even if the threshold voltage Vth varies or changes with time for each pixel, the light emission luminance of the organic EL element 21 can be kept constant without being influenced by the threshold voltage Vth. The principle of threshold correction will be described in detail later.

(Mobility correction function)
The pixel 20 shown in FIG. 2 has a mobility correction function in addition to the threshold correction function described above. That is, the scanning signal WS (WS1 to WS1) output from the writing scanning circuit 40 during the period in which the horizontal driving circuit 60 supplies the signal voltage Vsig of the video signal to the signal lines 33 (33-1 to 33-n). When the input signal voltage Vsig is held in the storage capacitor 24 in a period in which the write transistor 23 is turned on in response to (WSm), that is, in the mobility correction period, the drain-source current Ids of the drive transistor 22 corresponds to the mobility μ. Mobility correction is performed to cancel the dependency. The specific principle and operation of this mobility correction will be described later.

(Bootstrap function)
The pixel 20 shown in FIG. 2 further has a bootstrap function. That is, the horizontal drive circuit 60 cancels the supply of the scanning signals WS (WS1 to WSm) to the scanning lines 31 (31-1 to 31-m) at the stage where the input signal voltage Vsig is held in the holding capacitor 24, and the writing is performed. The transistor 23 is turned off to electrically disconnect the gate of the drive transistor 22 from the signal line 33 (33-1 to 33-n). Thereby, since the gate potential Vg of the drive transistor 22 varies in conjunction with the source potential Vs, the gate-source voltage Vgs of the drive transistor 22 can be kept constant.

  That is, even if the IV characteristic of the organic EL element 21 changes with time and the source potential Vs of the drive transistor 22 changes accordingly, the gate-source potential Vgs of the drive transistor 22 is changed by the action of the storage capacitor 24. In order to be kept constant, the current flowing through the organic EL element 21 does not change, and thus the light emission luminance of the organic EL element 21 is also kept constant. The operation for correcting the brightness is a bootstrap operation. By this bootstrap operation, even if the IV characteristic of the organic EL element 21 changes with time, it is possible to display an image without luminance deterioration associated therewith.

(Circuit operation)
Next, the circuit operation of the organic EL display device 10 according to the present embodiment will be described based on the timing chart of FIG. 4 and the operation explanatory diagrams of FIGS. In the operation explanatory diagrams of FIGS. 5 and 6, the write transistor 23 is illustrated by a switch symbol for simplification of the drawing. In addition, the organic EL element 21 has a parasitic capacitance, and the parasitic capacitance and the auxiliary capacitance 25 are illustrated as a combined capacitance Csub.

  In the timing chart of FIG. 4, with a common time axis, the change in potential (scanning signal) WS of the scanning line 31 (31-1 to 31-m) at 1H (H is the horizontal scanning time), the power supply line 32 ( 32-1 to 32 -m), and changes in the gate potential Vg and the source potential Vs of the driving transistor 22. Until time t2, the waveform of the potential (scanning signal) WS of the scanning line 31 is indicated by a one-dot chain line, and the potential DS of the power supply line 32 is indicated by a dotted line so that the two can be identified. After time t3, both are indicated by solid lines.

<Light emission period>
In the timing chart of FIG. 4, before the time t1, the organic EL element 21 is in a light emission state (light emission period). In this light emission period, the potential DS of the power supply line 32 is at the high potential Vccp (first potential), and the drive current is supplied from the power supply line 32 to the organic EL element 21 through the drive transistor 22 as shown in FIG. Since (drain-source current) Ids is supplied, the organic EL element 21 emits light with a luminance corresponding to the drive current Ids.

<Threshold correction preparation period>
Then, at time t1, a new field of line sequential scanning is entered, and as shown in FIG. 5B, the potential DS of the power supply line 32 is sufficiently lower than the offset voltage Vofs of the signal line 33 from the high potential Vccp. When transitioning to Vini (second potential), the source potential Vs of the drive transistor 22 also starts to decrease toward the low potential Vini.

  Next, at time t2, the scanning signal WS is output from the writing scanning circuit 40, and the potential WS of the scanning line 31 shifts to the high potential side, so that the writing transistor 23 is in a conductive state as illustrated in FIG. It becomes. At this time, since the offset voltage Vofs is supplied from the horizontal drive circuit 60 to the signal line 33, the gate potential Vg of the drive transistor 22 becomes the offset voltage Vofs. Further, the source potential Vs of the drive transistor 22 is at a potential Vini that is sufficiently lower than the offset voltage Vofs.

  Here, the low potential Vini is set so that the gate-source voltage Vgs of the drive transistor 22 is larger than the threshold voltage Vth of the drive transistor 22. In this way, the gate voltage Vg of the drive transistor 22 is initialized to the offset voltage Vofs and the source potential Vs is initialized to the low potential Vini, whereby the preparation for the threshold voltage correction operation is completed.

<Threshold correction period>
Next, at time t3, as shown in FIG. 5D, when the potential DS of the power supply line 32 is switched from the low potential Vini to the high potential Vccp, the source potential Vs of the drive transistor 22 starts to rise. Eventually, the gate-source voltage Vgs of the drive transistor 22 becomes the threshold voltage Vth of the drive transistor 22, and a voltage corresponding to the threshold voltage Vth is written into the storage capacitor 24.

  Here, for convenience, a period during which a voltage corresponding to the threshold voltage Vth is written to the storage capacitor 24 is referred to as a threshold correction period. In the threshold correction period, the common power supply line 34 is set so that the organic EL element 21 is cut off in order to prevent the current from flowing exclusively to the storage capacitor 24 side and to the organic EL element 21 side. The potential Vcath is set in advance.

  Next, at time t4, the potential WS of the scanning line 31 shifts to the low potential side, so that the writing transistor 23 is turned off as illustrated in FIG. At this time, the gate of the driving transistor 22 is in a floating state, but the driving transistor 22 is in a cutoff state because the gate-source voltage Vgs is equal to the threshold voltage Vth of the driving transistor 22. Therefore, the drain-source current Ids does not flow.

<Writing period / mobility correction period>
Next, at time t5, as shown in FIG. 6B, the potential of the signal line 33 is switched from the offset voltage Vofs to the signal voltage Vsig of the video signal. Subsequently, at time t6, the potential WS of the scanning line 31 transitions to the high potential side, so that the writing transistor 23 becomes conductive as shown in FIG. 6C, and the signal voltage Vsig of the video signal is sampled. To do.

  By sampling the input signal voltage Vsig by the write transistor 23, the gate potential Vg of the drive transistor 22 becomes the input signal voltage Vsig. At this time, since the organic EL element 21 is initially in a cut-off state (high impedance state), the drain-source current Ids of the drive transistor 22 flows into the combined capacitor Csub connected in parallel to the organic EL element 21. Charging of the combined capacity Csub is started.

  Due to the charging of the composite capacitor Csub, the source potential Vs of the drive transistor 22 starts to rise, and the gate-source voltage Vgs of the drive transistor 22 eventually becomes Vsig + Vth−ΔV. That is, the increase ΔV of the source potential Vs is subtracted from the voltage (Vsig + Vth) held in the holding capacitor 24, in other words, acts to discharge the charged charge of the holding capacitor 24, and negative feedback is applied. It will be. Therefore, the increase ΔV of the source potential Vs becomes a feedback amount of negative feedback.

  As described above, the drain-source current Ids flowing through the drive transistor 22 is negatively fed back to the gate input of the drive transistor 22, that is, the gate-source voltage Vgs, so that the drain-source current Ids of the drive transistor 22 is reduced. Mobility correction is performed to cancel the dependence on the mobility μ, that is, to correct the variation of the mobility μ for each pixel.

  More specifically, since the drain-source current Ids increases as the signal voltage Vsig of the video signal increases, the absolute value of the feedback amount (correction amount) ΔV of negative feedback also increases. Therefore, the mobility correction according to the light emission luminance level is performed. Further, when the signal voltage Vsig of the video signal is constant, the absolute value of the feedback amount ΔV of the negative feedback increases as the mobility μ of the driving transistor 22 increases, so that variation in the mobility μ for each pixel is removed. Can do.

<Light emission period>
Next, at time t7, the potential WS of the scanning line 31 shifts to the low potential side, so that the writing transistor 23 is turned off (off) as illustrated in FIG. 6D. As a result, the gate of the drive transistor 22 is disconnected from the signal line 33. At the same time, the drain-source current Ids starts to flow through the organic EL element 21, whereby the anode potential of the organic EL element 21 rises according to the drain-source current Ids.

  The increase in the anode potential of the organic EL element 21 is nothing but the increase in the source potential Vs of the drive transistor 22. When the source potential Vs of the drive transistor 22 rises, the gate potential Vg of the drive transistor 22 also rises in conjunction with the bootstrap operation of the storage capacitor 24. At this time, the increase amount of the gate potential Vg is equal to the increase amount of the source potential Vs. Therefore, the gate-source voltage Vgs of the drive transistor 22 is kept constant at Vsig + Vth−ΔV during the light emission period. At time t8, the potential of the signal line 33 is switched from the signal voltage Vsig of the video signal to the offset voltage Vofs.

  As is clear from the series of circuit operations described above, the scanning signal WS output from the writing scanning circuit 40 is driven by the writing transistor 23 to sample the offset voltage Vofs and write the first half of the writing pulse and the input signal. The latter half of the write pulse is sampled and written to the voltage Vsig (see FIG. 4).

(Principle of threshold correction)
Here, the principle of threshold correction of the drive transistor 22 will be described. The drive transistor 22 operates as a constant current source because it is designed to operate in the saturation region. As a result, a constant drain-source current (drive current) Ids given by the following equation (1) is supplied from the drive transistor 22 to the organic EL element 21.
Ids = (1/2) · μ (W / L) Cox (Vgs−Vth) ² (1)
Here, W is the channel width of the drive transistor 22, L is the channel length, and Cox is the gate capacitance per unit area.

  FIG. 7 shows characteristics of the drain-source current Ids of the drive transistor 22 versus the gate-source voltage Vgs. As shown in this characteristic diagram, when correction for variation in the threshold voltage Vth of the drive transistor 22 is not performed, when the threshold voltage Vth is Vth1, the drain-source current Ids corresponding to the gate-source voltage Vgs becomes Ids1. On the other hand, when the threshold voltage Vth is Vth2 (Vth2> Vth1), the drain-source current Ids corresponding to the same gate-source voltage Vgs is Ids2 (Ids2 <Ids). That is, when the threshold voltage Vth of the driving transistor 22 varies, the drain-source current Ids varies even if the gate-source voltage Vgs is constant.

On the other hand, in the pixel (pixel circuit) 20 having the above-described configuration, as described above, the gate-source voltage Vgs of the driving transistor 22 at the time of light emission is Vsig + Vth−ΔV. Then, the drain-source current Ids is
Ids = (1/2) · μ (W / L) Cox (Vsig−ΔV) ² (2)
It is represented by

  That is, the term of the threshold voltage Vth of the drive transistor 22 is canceled, and the drain-source current Ids supplied from the drive transistor 22 to the organic EL element 21 does not depend on the threshold voltage Vth of the drive transistor 22. As a result, the drain-source current Ids does not vary even if the threshold voltage Vth of the drive transistor 22 varies for each pixel due to variations in the manufacturing process of the drive transistor 22 and changes over time. The emission brightness does not change.

(Principle of mobility correction)
Next, the principle of mobility correction of the drive transistor 22 will be described. FIG. 8 shows a characteristic curve in a state where a pixel A having a relatively high mobility μ of the driving transistor 22 and a pixel B having a relatively low mobility μ of the driving transistor 22 are compared. When the driving transistor 22 is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels like the pixel A and the pixel B.

  For example, when the input signal voltage Vsig of the same level is written to both the pixels A and B in a state where the mobility μ is varied between the pixel A and the pixel B, the mobility μ is not corrected. A large difference is generated between the drain-source current Ids1 ′ flowing in the pixel A having a large value and the drain-source current Ids2 ′ flowing in the pixel B having the small mobility μ. Thus, if a large difference occurs between the pixels in the drain-source current Ids due to the variation in the mobility μ, the uniformity of the screen is impaired.

  Here, as is clear from the transistor characteristic equation of Equation (1), the drain-source current Ids increases when the mobility μ is large. Therefore, the feedback amount ΔV in the negative feedback increases as the mobility μ increases. As shown in FIG. 8, the feedback amount ΔV1 of the pixel A having a high mobility μ is larger than the feedback amount ΔV2 of the pixel V having a low mobility. Therefore, by negatively feeding back the drain-source current Ids of the drive transistor 22 to the input signal voltage Vsig side by the mobility correction operation, the larger the mobility μ, the more negative feedback is applied. Can be suppressed.

  Specifically, when the feedback amount ΔV1 is corrected in the pixel A having a high mobility μ, the drain-source current Ids greatly decreases from Ids1 ′ to Ids1. On the other hand, since the feedback amount ΔV2 of the pixel B having a low mobility μ is small, the drain-source current Ids decreases from Ids2 ′ to Ids2, and does not decrease that much. As a result, since the drain-source current Ids1 of the pixel A and the drain-source current Ids2 of the pixel B are substantially equal, the variation in the mobility μ is corrected.

  In summary, when there are a pixel A and a pixel B having different mobility μ, the feedback amount ΔV1 of the pixel A having a high mobility μ is smaller than the feedback amount ΔV2 of the pixel B having a low mobility μ. That is, the larger the mobility μ, the larger the feedback amount ΔV, and the larger the amount of decrease in the drain-source current Ids. Therefore, by negatively feeding back the drain-source current Ids of the driving transistor 22 to the input signal voltage Vsig side, the current value of the drain-source current Ids of the pixels having different mobility μ is made uniform. Variation in degree μ can be corrected.

  Here, in the pixel (pixel circuit) 20 shown in FIG. 2, the relationship between the signal potential (sampling potential) Vsig of the video signal and the drain-source current Ids of the drive transistor 22 depending on the presence or absence of threshold correction and mobility correction. This will be described with reference to FIG.

  In FIG. 9, (A) does not perform both threshold correction and mobility correction, (B) does not perform mobility correction, and performs only threshold correction, (C) performs threshold correction and mobility correction. Each case is shown. As shown in FIG. 9A, when neither threshold correction nor mobility correction is performed, the drain-source current Ids is caused by variations in the threshold voltage Vth and the mobility μ for each of the pixels A and B. A large difference occurs between the pixels A and B.

  On the other hand, when only the threshold correction is performed, as shown in FIG. 9B, although the variation in the drain-source current Ids can be reduced to some extent by the threshold correction, the pixels A and B having the mobility μ A difference in the drain-source current Ids between the pixels A and B due to the variation of each pixel remains. Then, by performing both the threshold correction and the mobility correction, as shown in FIG. 9C, the drain between the pixels A and B due to the variation of the threshold voltage Vth and the mobility μ for each of the pixels A and B. -Since the difference between the source currents Ids can be almost eliminated, the luminance variation of the organic EL element 21 does not occur at any gradation, and a display image with good image quality can be obtained.

(Problems in mobility correction)
Here, problems in mobility correction will be described with reference to the timing chart of FIG.

  As is clear from the description of the circuit operation described above, in the pixel 20 having the configuration in which the drive transistor 22 is used as a transistor for controlling the light emission period / non-light emission period of the organic EL element 21, the pixel 20 moves simultaneously with the writing of the input signal voltage Vsig. Degree correction is performed. Here, the mobility correction is preferably performed in a state where the input signal voltage Vsig is completely written.

  However, if the response speed of the rise of the write pulse (scan signal WS in the latter half of FIG. 4) output from the write scanning circuit 40 and driving the write transistor 23 is slow, the writing of the input signal voltage Vsig is completely completed. Since time is required, unstable driving is performed in which the mobility correction is performed while the writing of the input signal voltage Vsig is insufficient.

  As described above, when the mobility correction is performed with the input signal voltage Vsig being insufficiently written, the correction amount of the mobility correction, that is, the feedback amount of the negative feedback is performed between the pixel having the high mobility μ and the pixel having the low mobility μ. Since ΔV is different, the mobility correction varies among pixels, and as a result, unevenness occurs and the image quality deteriorates.

(Characteristics of this embodiment)
Therefore, in the present embodiment, as shown in the timing chart of FIG. 11, the response speed (rising speed in this example) when the write pulse WS transitions to the active state is increased, that is, the response waveform rises sharply. As a result, the time until the writing of the input signal voltage Vsig is completely completed is shortened, and the mobility correction is performed in the state where the writing of the input signal voltage Vsig is completed. It is characterized by eliminating variations.

  In addition, in this embodiment, the response speed (the falling speed in this example) when the write pulse WS transitions to the inactive state is slowed down, that is, the response waveform falls slowly (smooths). This suppresses the decrease in the gate-source voltage Vgs of the drive transistor 22 due to the coupling when the write transistor 23 is turned off, and prevents the decrease in luminance associated with the decrease in the gate-source voltage Vgs, while the input signal voltage It is characterized in that writing of Vsig can be performed stably.

[Example]
The following is a specific example for increasing the response speed when the write pulse WS for writing the input signal voltage Vsig transitions to the active state and for decreasing the response speed when the write pulse WS transitions to the inactive state. Examples will be described.

  As described above, the scanning signal WS (WS 1 to WSm) including the writing pulse is output from the writing scanning circuit 40. As shown in FIG. 12, the write scanning circuit 40 includes a shift register 41, a logic circuit 42, and an output circuit 43 including a plurality of stages of buffers for each pixel row, and drives each pixel 20 of the pixel array unit 30. It is mounted on the display panel 70 as a driving unit.

(Circuit configuration of the output circuit)
FIG. 13 is a circuit diagram showing an example of the configuration of the output circuit 43 in a certain pixel row. Here, an output circuit having a two-stage configuration including the last-stage buffer 431 and the preceding-stage buffer 432 is shown as an example, but the present invention is not limited to the two-stage configuration.

  As is clear from the pixel circuit of FIG. 2, the timing chart of FIG. 4, and the like, in this embodiment, the drive transistor 22 and the write transistor 23 are N-channel transistors, and therefore the write transistor 23 is driven. The write pulse WS becomes active at the positive power supply voltage Vdd and becomes inactive at the negative power supply voltage Vss.

  The final stage buffer 431 includes a P-channel MOS transistor P11 and an N-channel MOS connected in series between a positive power supply line of the power supply voltage Vdd as the first power supply and a negative power supply line of the power supply voltage Vss as the second power supply. For example, the transistor P11 is composed of a CMOS inverter in which the gates and drains of the transistors P11 and N11 are connected in common.

  The front-stage buffer 432 includes a P-channel MOS transistor P12 and an N-channel MOS transistor N12 connected in series between the positive power supply line of the power supply voltage Vdd and the negative power supply line of the power supply voltage Vss. It is constituted by a CMOS inverter in which the gates and drains of P12 and N12 are connected in common.

  By the way, in general, when a buffer is constituted by a P-channel transistor and an N-channel transistor, the mobility μ is about 1.3 to 1.4 times higher in the N-channel transistor than in the P-channel transistor. The transistor size ratio between the two is changed so that the same current flows through both transistors. For example, when the mobility of the N channel transistor is 1.3 times the mobility of the P channel transistor, the size of the P channel transistor is designed to be 1.3 times the size of the N channel transistor.

  In contrast, in the present embodiment, in the final stage buffer 431, the P-channel MOS transistor P11 and the N-channel MOS transistor N11 are intentionally controlled in order to control the transient (transient response) of the write pulse WS output from the buffer 431. The balance of the size (in the above example, 1: 1.3 in the above example) is broken.

The response speed τ of the rise and fall of the write pulse WS is
τ = RC
Defined by Here, R is a resistance component, and the resistance component R includes the ON resistance of the final stage buffer 431, the wiring resistance, the gate resistance of the write transistor 23, and the like. C is a capacitance component, and the capacitance component C mainly includes an overlap capacitance between wirings.

  A more specific explanation will be given with numerical examples. Assuming that a general configuration is adopted, when the size of the P-channel MOS transistor P11 is set to 1.3 times the size of the N-channel MOS transistor N11, the rising response speed τ1 of the write pulse WS is 150 nsec, It is assumed that the response speed τ2 is 180 nsec.

As an example, the response speeds τ1, τ2 of the write pulse WS rise and fall when the ON resistance of the P-channel MOS transistor P11 is 4 kΩ, the wiring resistance is 1 kΩ, and the overlap capacitance between the wirings is 30 pF. is there. That is,
τ1 = (4 kΩ + 1 kΩ) × (30 pF) = 150 nsec
τ2 = (5 kΩ + 1 kΩ) × (30 pF) = 180 nsec
It is.

  On the other hand, in this embodiment, the transistor size ratio (1: 1.3 in the above example) when the same current flows through the P channel MOS transistor P11 and the N channel MOS transistor N11 is used as a reference. The rising response speed τ1 of the write pulse WS is slow (for example, 90 nsec) and the falling response speed τ2 is fast (for example, 300 nsec) compared to the response speed (150 nsec, 180 nsec) at the reference size ratio. ), The ON resistances of the MOS transistors P11 and N11 are set.

  Specifically, the ON resistance of the P-channel MOS transistor P11 is lowered from 4 kΩ to 2 kΩ in order to set the response speeds τ1, τ2 of the rising and falling of the write pulse WS to 90 nsec and 300 nsec, for example, and the N-channel MOS transistor N11 The ON resistances of the MOS transistors P11 and N11 are changed so that the ON resistance of the MOS transistors P11 and N11 is increased from 5 kΩ to 9 kΩ.

By changing the ON resistance, numerical values of 90 nsec and 300 nsec are obtained as the response speeds τ1 and τ2 of the write pulse WS from the following equation.
τ1 = (2 kΩ + 1 kΩ) × (30 pF) = 90 nsec
τ2 = (9 kΩ + 1 kΩ) × (30 pF) = 300 nsec

  To reduce the ON resistance of the P channel MOS transistor P11 to 0.5 times (= 2 kΩ / 4 kΩ) and increase the ON resistance of the N channel MOS transistor N11 to 1.8 times (≈9 kΩ / 5 kΩ), the P channel MOS transistor The size of the MOS transistor P11 is set to 1.8 times the size used as a reference when the same level of current flows through the P11 and the N-channel MOS transistor N11, and the size of the MOS transistor N11 is increased to about 0.5 times. Set it. That is, the size of the P channel MOS transistor P11 may be designed to be about 4.7 times the size of the N channel MOS transistor N11.

(Circuit operation of the output circuit)
Next, the circuit operation of the output circuit 43 configured as described above will be described with reference to the timing waveform diagram of FIG.

  In the output circuit 43, the shift pulse output from the shift register 41 is input to the preceding buffer 432 as an input pulse A that rises at time t11 and falls at time t12 via the logic circuit. The polarity of the input pulse A is inverted by the buffer 432 in the previous stage.

  Here, in the buffer 432 in the previous stage, for example, the mobility of the MOS transistor N12 is set to 1 of the mobility of the MOS transistor P12 so that the same current flows in the P-channel MOS transistor P12 and the N-channel MOS transistor N12. It is assumed that the size of the MOS transistor P12 is designed to be 1.3 times the size of the MOS transistor N12.

  In this case, in the above example, the input pulse A is output from the preceding buffer 432 as an inverted pulse having a falling response speed τ 2 of 180 nsec and a rising response speed τ 1 of 150 nsec. The inverted pulse is further inverted in polarity by the final stage buffer 431 to become an output pulse B.

  Here, in the final stage buffer 431, the size of the MOS transistor P11 is set to about 1.8 times the size of the previous stage MOS transistor P12, and the size of the MOS transistor N11 is about 0.5 times the size of the previous stage MOS transistor N12. By setting the value twice, an output pulse B having a rising response speed τ1 of 90 nsec and a falling response speed τ2 of 300 nsec is output from the final buffer 431.

  The output pulse B is applied as a write pulse WS (scanning number WS) to the gate of the write transistor 23 in each pixel 20 of the corresponding pixel row.

(Operational effect of this embodiment)
As described above, in the last stage buffer 431 of the output circuit 43 in the write scanning circuit 40, the size of the P-channel MOS transistor P11 is set larger than the reference size, so that the write pulse determined by the size of the MOS transistor P11. The response speed τ1 at the rise of WS can be made faster than that when the MOS transistor P11 is the reference size, that is, the write pulse WS can be raised instantly.

  Since the writing pulse WS rises instantaneously, the writing of the input signal voltage Vsig by the writing pulse WS can be completed earlier than the case where the MOS transistor P11 has the reference size, and thus the input signal voltage Vsig is sufficiently written. Mobility correction can be performed in a state where Thereby, the writing of the input signal voltage Vsig and the mobility correction can be stably performed.

  Further, since the size of the N-channel MOS transistor N11 constituting the final stage buffer 431 is set smaller than the reference size, the response speed τ2 of the fall of the write pulse WS determined by the size of the MOS transistor N11 is set to Compared to the case where the transistor N11 is the reference size, it can be delayed, that is, the write pulse WS can be gently lowered.

  As the write pulse WS gradually falls, as shown in FIG. 15, the coupling by the storage capacitor 24 when the write transistor 23 is turned off decreases, so that the gate potential Vg of the drive transistor 22 due to the coupling is reduced. The decrease can be suppressed as compared with the case where the MOS transistor N11 has the reference size and the falling speed of the write pulse WS is fast (the write pulse WS falls sharply).

  As a result, the decrease in the gate-source voltage Vgs of the drive transistor 22 caused by the coupling when the write transistor 23 is turned off can be suppressed, so that the luminance decrease due to the decrease in the gate-source voltage Vgs is prevented. However, the input signal voltage Vsig can be stably written.

  Further, since the falling waveform of the write pulse WS is not steep and gentle like a rectangular wave, the mobility correction period can be optimized even in gray to black gradations, that is, the optimum mobility corresponding to each gradation. A correction period can be set. This will be specifically described below.

  As the gray and black gradations and the input signal voltage Vsig become lower than the white gradation, the optimum mobility correction time becomes longer. As shown in FIG. 16, since the initial current flowing through the driving transistor 22 is smaller than that of the white gradation in the gray gradation, it is necessary to correct the mobility μ due to the operating point of the driving transistor 22. This is because the mobility correction time becomes longer than the white gradation.

  Here, in the case where the writing of the input signal voltage Vsig and the mobility correction are performed at the same time, the ON period of the writing transistor 23 becomes the mobility correction period (signal writing period). The write transistor 23 is turned on when the level difference between the input signal voltage Vsig and the write pulse WS is equal to or higher than the threshold voltage. Therefore, it can be said that the ON period of the write transistor 23, that is, the mobility correction period, depends on the falling waveform of the write pulse WS.

  Therefore, when the input signal voltage Vsig is large as in the white gradation, the write transistor WS is turned off at a high level of the fall of the write pulse WS because the write pulse WS gradually falls. When a short time is set as the mobility correction period of the white gradation and the input signal voltage Vsig is small as in the gray gradation, the writing transistor 23 is turned off at a low level of the writing pulse WS. A long time is set as the mobility correction period for the gray gradation.

  That is, in the organic EL display device 10 having a configuration in which the writing of the input signal voltage Vsig and the mobility correction are performed simultaneously, the writing transistor 23 is controlled under the control of the writing pulse having a gentle falling response waveform, that is, a slow response speed. Thus, by sampling and writing the input signal voltage Vsig, it is possible to set the optimum mobility correction time according to each gradation corresponding to the difference in the optimum mobility correction time between the gray gradation and the white gradation.

  In this way, by setting the optimal mobility correction time corresponding to each gradation, mobility correction that removes the variation in mobility μ for each pixel can be performed over all gradations from white gradation to black gradation. Since it can be performed reliably, it is possible to achieve higher image quality of the display image.

  In this embodiment, the rising response speed τ1 of the write pulse WS is set to 90 nsec and the falling response speed τ2 is set to 300 nsec. However, this is only an example, and the present invention is not limited to these values. Absent.

  However, in order to perform mobility correction in a state where the input signal voltage Vsig is sufficiently written, the P channel MOS transistor P11 is set so that the response speed τ1 of the rising of the write pulse WS is preferably about 100 nsec or less. The transistor size should be set.

  Further, in order to suppress a decrease in the gate potential Vg of the drive transistor 22 due to coupling when the write transistor WS is turned off, the response speed τ2 of the write pulse WS falling is preferably about 200 to 400 nsec or less. The transistor size of the N-channel MOS transistor N11 is preferably set so that

  In the present embodiment described above, the case of generating the positive logic output pulse B that becomes active at a high level as the writing pulse WS (scanning signal WS) has been described as an example, but becomes active at a low level. The same applies to the case of generating a negative logic output pulse B ′.

  In the above embodiment, the case where the present invention is applied to an organic EL display device using an organic EL element as the electro-optical element of the pixel circuit 20 has been described as an example. However, the present invention is not limited to this application example. In addition, the present invention can be applied to all display devices using current-driven electro-optic elements (light-emitting elements) whose light emission luminance changes according to the value of current flowing through the device.

[Application example]
The display device according to the present invention described above is input to various electronic devices shown in FIGS. 17 to 21 such as a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, and a video camera. The present invention can be applied to display devices for electronic devices in various fields that display a video signal or a video signal generated in the electronic device as an image or video. An example of an electronic device to which the present invention is applied will be described below.

  Note that the display device according to the present invention includes a module-shaped one having a sealed configuration. For example, a display module formed by being affixed to an opposing portion such as transparent glass on the pixel array portion 30 is applicable. The transparent facing portion may be provided with a color filter, a protective film, and the like, and further, the above-described light shielding film. Note that the display module may be provided with a circuit unit for inputting / outputting a signal and the like from the outside to the pixel array unit, an FPC (flexible printed circuit), and the like.

  FIG. 17 is a perspective view showing a television to which the present invention is applied. The television according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is created by using the display device according to the present invention as the video display screen unit 101.

  18A and 18B are perspective views showing a digital camera to which the present invention is applied. FIG. 18A is a perspective view seen from the front side, and FIG. 18B is a perspective view seen from the back side. The digital camera according to this application example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using the display device according to the present invention as the display unit 112.

  FIG. 19 is a perspective view showing a notebook personal computer to which the present invention is applied. A notebook personal computer according to this application example includes a main body 121 including a keyboard 122 that is operated when characters and the like are input, a display unit 123 that displays an image, and the like. It is produced by using.

  FIG. 20 is a perspective view showing a video camera to which the present invention is applied. The video camera according to this application example includes a main body 131, a lens 132 for shooting an object on a side facing forward, a start / stop switch 133 at the time of shooting, a display unit 134, and the like. It is manufactured by using such a display device.

  FIG. 21 is a perspective view showing a mobile terminal device to which the present invention is applied, for example, a mobile phone, in which (A) is a front view in an opened state, (B) is a side view thereof, and (C) is closed. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. The mobile phone according to this application example includes an upper housing 141, a lower housing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub display 145, a picture light 146, a camera 147, and the like. And the sub display 145 is manufactured by using the display device according to the present invention.

1 is a system configuration diagram illustrating an outline of a configuration of an organic EL display device according to an embodiment of the present invention. It is a circuit diagram which shows the specific structural example of a pixel (pixel circuit). It is sectional drawing which shows an example of the cross-sectional structure of a pixel. It is a timing chart with which it uses for operation | movement description of the organic electroluminescence display which concerns on one Embodiment of this invention. It is explanatory drawing (the 1) of circuit operation | movement of the organic electroluminescence display which concerns on one Embodiment of this invention. It is explanatory drawing (the 2) of the circuit operation | movement of the organic electroluminescence display which concerns on one Embodiment of this invention. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the threshold voltage Vth of a drive transistor. It is a characteristic view with which it uses for description of the subject resulting from the dispersion | variation in the mobility (mu) of a drive transistor. FIG. 10 is a characteristic diagram for explaining the relationship between the signal voltage Vsig of the video signal and the drain-source current Ids of the drive transistor depending on whether threshold correction and mobility correction are performed. It is a timing chart with which it uses for description of the problem in mobility correction | amendment. It is a timing chart with which it uses for operation | movement description for solving the problem in mobility correction | amendment. It is a block diagram which shows an example of a structure of a writing scanning circuit. It is a circuit diagram which shows an example of the circuit structure of the last stage buffer. FIG. 10 is a timing waveform chart for explaining circuit operation of the final stage buffer. FIG. 6 is a timing waveform diagram for explaining an operation when a write transistor is off. It is a characteristic view with which it uses for description of the optimal mobility correction | amendment time according to a gradation. It is a perspective view which shows the television to which this invention is applied. It is the perspective view which shows the digital camera to which this invention is applied, (A) is the perspective view seen from the front side, (B) is the perspective view seen from the back side. 1 is a perspective view showing a notebook personal computer to which the present invention is applied. It is a perspective view which shows the video camera to which this invention is applied. It is a perspective view showing a cellular phone to which the present invention is applied, (A) is a front view in an open state, (B) is a side view thereof, (C) is a front view in a closed state, (D) Is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. FIG. 5 is a timing waveform diagram for explaining a problem when a write transistor is off.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Organic EL display device, 20 ... Pixel (pixel circuit), 21 ... Organic EL element, 22 ... Drive transistor, 23 ... Write transistor, 24 ... Retention capacity, 25 ... Auxiliary capacity, 30 ... Pixel array part, 31 (31 -1 to 31-m) ... scanning lines, 32 (32 to 1 to 32-m) ... power supply lines, 33 (33-1 to 33-n) ... signal lines, 34 ... common power supply lines, 40 ... write Scanning circuit 50 ... Power supply scanning circuit 60 ... Horizontal driving circuit 70 ... Display panel

Claims (3)

An electro-optic element; a writing transistor that samples and writes an input signal voltage; a holding capacitor that holds the input signal voltage written by the writing transistor; and the electro-optic device based on the input signal voltage held in the holding capacitor A pixel array unit in which pixels including drive transistors for driving elements are arranged in a matrix;
The pixel has a final stage buffer including a P-channel transistor and an N-channel transistor connected in series between a first power source and a second power source, and gives a write pulse to be output through the final stage buffer to the write transistor. A scanning circuit that selectively scans each pixel of the array unit in units of rows,
Based on the size of the P-channel transistor and the size of the N-channel transistor when the same current flows through the P-channel transistor and the N-channel transistor, the size of the P-channel transistor is the size of the P-channel transistor. A display device, wherein the display device is set larger than a reference size, and the size of the N-channel transistor is set smaller than the reference size of the N-channel transistor. Each pixel of the pixel array unit has a drain-source current of the driving transistor by negatively feeding back the drain-source current of the driving transistor to the gate input side during the writing period of the input signal voltage by the writing transistor. The display device according to claim 1, wherein a correction operation is performed to cancel the dependence on the mobility of the display device. An electro-optic element; a writing transistor that samples and writes an input signal voltage; a holding capacitor that holds the input signal voltage written by the writing transistor; and the electro-optic device based on the input signal voltage held in the holding capacitor A pixel array unit in which pixels including drive transistors for driving elements are arranged in a matrix;
The pixel has a final stage buffer including a P-channel transistor and an N-channel transistor connected in series between a first power source and a second power source, and gives a write pulse to be output through the final stage buffer to the write transistor. When each pixel of the array section is selectively scanned in units of rows, and the size of the P channel transistor and the size of the N channel transistor when the same current flows through the P channel transistor and the N channel transistor are used as a reference And a scanning circuit in which the size of the P-channel transistor is set larger than the reference size of the P-channel transistor, and the size of the N-channel transistor is set smaller than the reference size of the N-channel transistor. Have equipment An electronic device characterized by that.

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