JP2002538615A5 - - Google Patents

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Publication number
JP2002538615A5
JP2002538615A5 JP2000603043A JP2000603043A JP2002538615A5 JP 2002538615 A5 JP2002538615 A5 JP 2002538615A5 JP 2000603043 A JP2000603043 A JP 2000603043A JP 2000603043 A JP2000603043 A JP 2000603043A JP 2002538615 A5 JP2002538615 A5 JP 2002538615A5
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JP
Japan
Prior art keywords
image
distorted
camera grid
camera
pixels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000603043A
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English (en)
Japanese (ja)
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JP2002538615A (ja
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Publication date
Priority claimed from US09/261,915 external-priority patent/US6181608B1/en
Application filed filed Critical
Publication of JP2002538615A publication Critical patent/JP2002538615A/ja
Publication of JP2002538615A5 publication Critical patent/JP2002538615A5/ja
Pending legal-status Critical Current

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JP2000603043A 1999-03-03 2000-02-17 ビットライン・リーク制御を備える二重しきい値電圧ｓｒａｍセル Pending JP2002538615A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/261,915 US6181608B1 (en) 1999-03-03 1999-03-03 Dual Vt SRAM cell with bitline leakage control
US09/261,915 1999-03-03
PCT/US2000/004239 WO2000052702A1 (en) 1999-03-03 2000-02-17 Dual threshold voltage sram cell with bit line leakage control

Publications (2)

Publication Number Publication Date
JP2002538615A JP2002538615A (ja) 2002-11-12
JP2002538615A5 true JP2002538615A5 (https=) 2007-03-29

Family

ID=22995437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000603043A Pending JP2002538615A (ja) 1999-03-03 2000-02-17 ビットライン・リーク制御を備える二重しきい値電圧ｓｒａｍセル

Country Status (10)

Country Link
US (1) US6181608B1 (https=)
EP (1) EP1155413B1 (https=)
JP (1) JP2002538615A (https=)
KR (1) KR100479670B1 (https=)
CN (1) CN1253897C (https=)
AU (1) AU3001700A (https=)
BR (1) BR0008704A (https=)
DE (1) DE60029757T2 (https=)
TW (1) TW463169B (https=)
WO (1) WO2000052702A1 (https=)

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US6683804B1 (en) * 2002-07-16 2004-01-27 Analog Devices, Inc. Read/write memory arrays and methods with predetermined and retrievable latent-state patterns
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US6724649B1 (en) * 2002-12-19 2004-04-20 Intel Corporation Memory cell leakage reduction
US7200050B2 (en) * 2003-05-26 2007-04-03 Semiconductor Energy Laboratory Co., Ltd. Memory unit and semiconductor device
CA2529667A1 (en) * 2003-07-01 2005-01-20 Zmos Technology, Inc Sram cell structure and circuits
US6920061B2 (en) * 2003-08-27 2005-07-19 International Business Machines Corporation Loadless NMOS four transistor dynamic dual Vt SRAM cell
JP2005142289A (ja) * 2003-11-05 2005-06-02 Toshiba Corp 半導体記憶装置
US7123500B2 (en) * 2003-12-30 2006-10-17 Intel Corporation 1P1N 2T gain cell
JP4342350B2 (ja) * 2004-03-11 2009-10-14 株式会社東芝 半導体メモリ装置
US7061794B1 (en) * 2004-03-30 2006-06-13 Virage Logic Corp. Wordline-based source-biasing scheme for reducing memory cell leakage
US7469465B2 (en) * 2004-06-30 2008-12-30 Hitachi Global Storage Technologies Netherlands B.V. Method of providing a low-stress sensor configuration for a lithography-defined read sensor
US7079426B2 (en) * 2004-09-27 2006-07-18 Intel Corporation Dynamic multi-Vcc scheme for SRAM cell stability control
US7110278B2 (en) * 2004-09-29 2006-09-19 Intel Corporation Crosspoint memory array utilizing one time programmable antifuse cells
US7321502B2 (en) * 2004-09-30 2008-01-22 Intel Corporation Non volatile data storage through dielectric breakdown
US7321504B2 (en) * 2005-04-21 2008-01-22 Micron Technology, Inc Static random access memory cell
KR100699857B1 (ko) * 2005-07-30 2007-03-27 삼성전자주식회사 무부하 에스램, 그 동작 방법 및 그 제조 방법
US7230842B2 (en) * 2005-09-13 2007-06-12 Intel Corporation Memory cell having p-type pass device
JP2007122814A (ja) * 2005-10-28 2007-05-17 Oki Electric Ind Co Ltd 半導体集積回路及びリーク電流低減方法
US20070153610A1 (en) * 2005-12-29 2007-07-05 Intel Corporation Dynamic body bias with bias boost
US8006164B2 (en) 2006-09-29 2011-08-23 Intel Corporation Memory cell supply voltage control based on error detection
US7558097B2 (en) * 2006-12-28 2009-07-07 Intel Corporation Memory having bit line with resistor(s) between memory cells
US8009461B2 (en) * 2008-01-07 2011-08-30 International Business Machines Corporation SRAM device, and SRAM device design structure, with adaptable access transistors
JP2009295229A (ja) * 2008-06-05 2009-12-17 Toshiba Corp 半導体記憶装置
US20110149667A1 (en) * 2009-12-23 2011-06-23 Fatih Hamzaoglu Reduced area memory array by using sense amplifier as write driver
US9858986B2 (en) * 2010-08-02 2018-01-02 Texas Instruments Incorporated Integrated circuit with low power SRAM
US9111638B2 (en) * 2012-07-13 2015-08-18 Freescale Semiconductor, Inc. SRAM bit cell with reduced bit line pre-charge voltage
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
WO2015009331A1 (en) * 2013-07-15 2015-01-22 Everspin Technologies, Inc. Memory device with page emulation mode
CN109859791B (zh) * 2019-01-31 2020-08-28 西安微电子技术研究所 一种全隔离结构9管sram存储单元及其读写操作方法
CN110277120B (zh) * 2019-06-27 2021-05-14 电子科技大学 一种在低压下提升读写稳定性的单端8管sram存储单元电路
CN111755048B (zh) * 2020-06-22 2024-11-29 上海华力微电子有限公司 下字线驱动读辅助电路和版图设计
US12580008B2 (en) 2024-02-08 2026-03-17 Arm Limited Power gating circuit with memory precharge support
US12525284B2 (en) 2024-02-08 2026-01-13 Arm Limited Column select topology supporting increased throughput for writes to memory
US20250259671A1 (en) * 2024-02-08 2025-08-14 Arm Limited Increased throughput for reads in static random access memory

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JPH0340294A (ja) 1989-07-05 1991-02-21 Mitsubishi Electric Corp スタティック型半導体記憶装置
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US5828597A (en) * 1997-04-02 1998-10-27 Texas Instruments Incorporated Low voltage, low power static random access memory cell
US5939762A (en) 1997-06-26 1999-08-17 Integrated Device Technology, Inc. SRAM cell using thin gate oxide pulldown transistors

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