JP2002521762A5 - - Google Patents

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Publication number
JP2002521762A5
JP2002521762A5 JP2000562823A JP2000562823A JP2002521762A5 JP 2002521762 A5 JP2002521762 A5 JP 2002521762A5 JP 2000562823 A JP2000562823 A JP 2000562823A JP 2000562823 A JP2000562823 A JP 2000562823A JP 2002521762 A5 JP2002521762 A5 JP 2002521762A5
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JP
Japan
Prior art keywords
physical register
register number
physical
register
instruction operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000562823A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002521762A (ja
JP3866920B2 (ja
Filing date
Publication date
Priority claimed from US09/127,094 external-priority patent/US6230262B1/en
Application filed filed Critical
Publication of JP2002521762A publication Critical patent/JP2002521762A/ja
Publication of JP2002521762A5 publication Critical patent/JP2002521762A5/ja
Application granted granted Critical
Publication of JP3866920B2 publication Critical patent/JP3866920B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000562823A 1998-07-31 1999-01-18 命令のリタイアメント時に物理レジスタを選択的に自由にするよう構成されたプロセッサ Expired - Fee Related JP3866920B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/127,094 1998-07-31
US09/127,094 US6230262B1 (en) 1998-07-31 1998-07-31 Processor configured to selectively free physical registers upon retirement of instructions
PCT/US1999/001048 WO2000007097A1 (en) 1998-07-31 1999-01-18 Processor configured to selectively free physical registers upon retirement of instructions

Publications (3)

Publication Number Publication Date
JP2002521762A JP2002521762A (ja) 2002-07-16
JP2002521762A5 true JP2002521762A5 (cg-RX-API-DMAC7.html) 2006-03-09
JP3866920B2 JP3866920B2 (ja) 2007-01-10

Family

ID=22428274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000562823A Expired - Fee Related JP3866920B2 (ja) 1998-07-31 1999-01-18 命令のリタイアメント時に物理レジスタを選択的に自由にするよう構成されたプロセッサ

Country Status (6)

Country Link
US (1) US6230262B1 (cg-RX-API-DMAC7.html)
EP (1) EP1099158B1 (cg-RX-API-DMAC7.html)
JP (1) JP3866920B2 (cg-RX-API-DMAC7.html)
KR (1) KR100572040B1 (cg-RX-API-DMAC7.html)
DE (1) DE69903554T2 (cg-RX-API-DMAC7.html)
WO (1) WO2000007097A1 (cg-RX-API-DMAC7.html)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6253310B1 (en) * 1998-12-31 2001-06-26 Intel Corporation Delayed deallocation of an arithmetic flags register
US6266763B1 (en) * 1999-01-05 2001-07-24 Advanced Micro Devices, Inc. Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values
JP3817436B2 (ja) 2000-09-28 2006-09-06 株式会社東芝 プロセッサおよびリネーミング装置
WO2002054228A1 (en) * 2000-12-06 2002-07-11 University Of Bristol Register renaming
US7043626B1 (en) 2003-10-01 2006-05-09 Advanced Micro Devices, Inc. Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
US20080077782A1 (en) * 2006-09-26 2008-03-27 Arm Limited Restoring a register renaming table within a processor following an exception
US20080148022A1 (en) * 2006-12-13 2008-06-19 Arm Limited Marking registers as available for register renaming
US9052909B2 (en) 2011-12-07 2015-06-09 Arm Limited Recovering from exceptions and timing errors
US8738971B2 (en) 2011-12-07 2014-05-27 Arm Limited Limiting certain processing activities as error rate probability rises
US9075621B2 (en) 2011-12-23 2015-07-07 Arm Limited Error recovery upon reaching oldest instruction marked with error or upon timed expiration by flushing instructions in pipeline pending queue and restarting execution
US8640008B2 (en) 2011-12-23 2014-01-28 Arm Limited Error recovery in a data processing apparatus
GB2496934B (en) * 2012-08-07 2014-06-11 Imagination Tech Ltd Multi-stage register renaming using dependency removal
US20160378480A1 (en) * 2015-06-27 2016-12-29 Pavel G. Matveyev Systems, Methods, and Apparatuses for Improving Performance of Status Dependent Computations
CN114356420B (zh) * 2021-12-28 2023-02-17 海光信息技术股份有限公司 指令流水线的处理方法及装置、电子装置及存储介质

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT354159B (de) 1975-02-10 1979-12-27 Siemens Ag Assoziativspeicher mit getrennt assoziierbaren bereichen
US4453212A (en) 1981-07-13 1984-06-05 Burroughs Corporation Extended address generating apparatus and method
US4928223A (en) 1982-10-06 1990-05-22 Fairchild Semiconductor Corporation Floating point microprocessor with directable two level microinstructions
US4807115A (en) 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
DE3751503T2 (de) 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
AU587714B2 (en) 1986-08-27 1989-08-24 Amdahl Corporation Cache storage queue
US5067069A (en) 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5226126A (en) 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5129067A (en) 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5136697A (en) 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5226130A (en) 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5053631A (en) 1990-04-02 1991-10-01 Advanced Micro Devices, Inc. Pipelined floating point processing unit
US5058048A (en) 1990-04-02 1991-10-15 Advanced Micro Devices, Inc. Normalizing pipelined floating point processing unit
DE69130588T2 (de) 1990-05-29 1999-05-27 National Semiconductor Corp., Santa Clara, Calif. Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
US5197132A (en) 1990-06-29 1993-03-23 Digital Equipment Corporation Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery
US5355457A (en) * 1991-05-21 1994-10-11 Motorola, Inc. Data processor for performing simultaneous instruction retirement and backtracking
GB9112754D0 (en) 1991-06-13 1991-07-31 Int Computers Ltd Data processing apparatus
GB9123271D0 (en) 1991-11-02 1991-12-18 Int Computers Ltd Data processing system
GB2263985B (en) 1992-02-06 1995-06-14 Intel Corp Two stage window multiplexors for deriving variable length instructions from a stream of instructions
SG45269A1 (en) 1992-02-06 1998-01-16 Intel Corp End bit markers for instruction decode
IE80854B1 (en) 1993-08-26 1999-04-07 Intel Corp Processor ordering consistency for a processor performing out-of-order instruction execution
US5784589A (en) 1993-10-18 1998-07-21 Cyrix Corporation Distributed free register tracking for register renaming using an availability tracking register associated with each stage of an execution pipeline
US5630149A (en) 1993-10-18 1997-05-13 Cyrix Corporation Pipelined processor with register renaming hardware to accommodate multiple size registers
DE69429061T2 (de) 1993-10-29 2002-07-18 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5546554A (en) 1994-02-02 1996-08-13 Sun Microsystems, Inc. Apparatus for dynamic register management in a floating point unit
US5481693A (en) 1994-07-20 1996-01-02 Exponential Technology, Inc. Shared register architecture for a dual-instruction-set CPU
US5675759A (en) 1995-03-03 1997-10-07 Shebanow; Michael C. Method and apparatus for register management using issue sequence prior physical register and register association validity information
EP0851343B1 (en) 1996-12-31 2005-08-31 Metaflow Technologies, Inc. System for processing floating point operations
JP3452771B2 (ja) * 1997-10-02 2003-09-29 富士通株式会社 命令制御システム及びその方法
US6119223A (en) * 1998-07-31 2000-09-12 Advanced Micro Devices, Inc. Map unit having rapid misprediction recovery
US6122656A (en) * 1998-07-31 2000-09-19 Advanced Micro Devices, Inc. Processor configured to map logical register numbers to physical register numbers using virtual register numbers

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