JP3866920B2 - 命令のリタイアメント時に物理レジスタを選択的に自由にするよう構成されたプロセッサ - Google Patents

命令のリタイアメント時に物理レジスタを選択的に自由にするよう構成されたプロセッサ Download PDF

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Publication number
JP3866920B2
JP3866920B2 JP2000562823A JP2000562823A JP3866920B2 JP 3866920 B2 JP3866920 B2 JP 3866920B2 JP 2000562823 A JP2000562823 A JP 2000562823A JP 2000562823 A JP2000562823 A JP 2000562823A JP 3866920 B2 JP3866920 B2 JP 3866920B2
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Japan
Prior art keywords
physical register
register
physical
register number
instruction
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Expired - Fee Related
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JP2000562823A
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Japanese (ja)
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JP2002521762A (ja
JP2002521762A5 (cg-RX-API-DMAC7.html
Inventor
ウィット，デイビッド・ビィ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2002521762A5 publication Critical patent/JP2002521762A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP2000562823A 1998-07-31 1999-01-18 命令のリタイアメント時に物理レジスタを選択的に自由にするよう構成されたプロセッサ Expired - Fee Related JP3866920B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/127,094 1998-07-31
US09/127,094 US6230262B1 (en) 1998-07-31 1998-07-31 Processor configured to selectively free physical registers upon retirement of instructions
PCT/US1999/001048 WO2000007097A1 (en) 1998-07-31 1999-01-18 Processor configured to selectively free physical registers upon retirement of instructions

Publications (3)

Publication Number Publication Date
JP2002521762A JP2002521762A (ja) 2002-07-16
JP2002521762A5 JP2002521762A5 (cg-RX-API-DMAC7.html) 2006-03-09
JP3866920B2 true JP3866920B2 (ja) 2007-01-10

Family

ID=22428274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000562823A Expired - Fee Related JP3866920B2 (ja) 1998-07-31 1999-01-18 命令のリタイアメント時に物理レジスタを選択的に自由にするよう構成されたプロセッサ

Country Status (6)

Country Link
US (1) US6230262B1 (cg-RX-API-DMAC7.html)
EP (1) EP1099158B1 (cg-RX-API-DMAC7.html)
JP (1) JP3866920B2 (cg-RX-API-DMAC7.html)
KR (1) KR100572040B1 (cg-RX-API-DMAC7.html)
DE (1) DE69903554T2 (cg-RX-API-DMAC7.html)
WO (1) WO2000007097A1 (cg-RX-API-DMAC7.html)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6253310B1 (en) * 1998-12-31 2001-06-26 Intel Corporation Delayed deallocation of an arithmetic flags register
US6266763B1 (en) * 1999-01-05 2001-07-24 Advanced Micro Devices, Inc. Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values
JP3817436B2 (ja) 2000-09-28 2006-09-06 株式会社東芝 プロセッサおよびリネーミング装置
WO2002054228A1 (en) * 2000-12-06 2002-07-11 University Of Bristol Register renaming
US7043626B1 (en) 2003-10-01 2006-05-09 Advanced Micro Devices, Inc. Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
US20080077782A1 (en) * 2006-09-26 2008-03-27 Arm Limited Restoring a register renaming table within a processor following an exception
US20080148022A1 (en) * 2006-12-13 2008-06-19 Arm Limited Marking registers as available for register renaming
US9052909B2 (en) 2011-12-07 2015-06-09 Arm Limited Recovering from exceptions and timing errors
US8738971B2 (en) 2011-12-07 2014-05-27 Arm Limited Limiting certain processing activities as error rate probability rises
US9075621B2 (en) 2011-12-23 2015-07-07 Arm Limited Error recovery upon reaching oldest instruction marked with error or upon timed expiration by flushing instructions in pipeline pending queue and restarting execution
US8640008B2 (en) 2011-12-23 2014-01-28 Arm Limited Error recovery in a data processing apparatus
GB2496934B (en) * 2012-08-07 2014-06-11 Imagination Tech Ltd Multi-stage register renaming using dependency removal
US20160378480A1 (en) * 2015-06-27 2016-12-29 Pavel G. Matveyev Systems, Methods, and Apparatuses for Improving Performance of Status Dependent Computations
CN114356420B (zh) * 2021-12-28 2023-02-17 海光信息技术股份有限公司 指令流水线的处理方法及装置、电子装置及存储介质

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AT354159B (de) 1975-02-10 1979-12-27 Siemens Ag Assoziativspeicher mit getrennt assoziierbaren bereichen
US4453212A (en) 1981-07-13 1984-06-05 Burroughs Corporation Extended address generating apparatus and method
US4928223A (en) 1982-10-06 1990-05-22 Fairchild Semiconductor Corporation Floating point microprocessor with directable two level microinstructions
US4807115A (en) 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
DE3751503T2 (de) 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
AU587714B2 (en) 1986-08-27 1989-08-24 Amdahl Corporation Cache storage queue
US5067069A (en) 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5226126A (en) 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5129067A (en) 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
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US5226130A (en) 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
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US5197132A (en) 1990-06-29 1993-03-23 Digital Equipment Corporation Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery
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Also Published As

Publication number Publication date
EP1099158B1 (en) 2002-10-16
KR20010053623A (ko) 2001-06-25
EP1099158A1 (en) 2001-05-16
US6230262B1 (en) 2001-05-08
KR100572040B1 (ko) 2006-04-18
DE69903554T2 (de) 2003-06-18
JP2002521762A (ja) 2002-07-16
WO2000007097A1 (en) 2000-02-10
DE69903554D1 (de) 2002-11-21

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