Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30098—Register arrangements
  • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
  • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
  • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
  • G06F9/384—Register renaming
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
  • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
  • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Definitions

• This invention is related to the field of processors and, more particularly, to register renammg features of processors
• Superscalar processors attempt to achieve high performance by issumg and executmg multiple instructions per clock cycle and by employing the highest possible clock frequency consistent with the design
• One method for increasing the number of instructions executed per clock cycle is out of order execution
• instructions may be executed m a different order than that specified m the program sequence (or "program order")
• program order Certain instructions near each other in a program sequence may have dependencies which prohibit their concurrent execution, while subsequent instructions m the program sequence may not have dependencies on the previous instructions Accordingly, out of order execution may mcrease performance of the superscalar processor by increasing the number of instructions executed concurrently (on the average)
• a second mstruction which is subsequent to a first mstruction in program order may update a storage location which is read by the first mstruction
• the destmation operand of the second mstruction may be one of the source operands of the first mstruction
• the first mstruction must receive, as a source operand, the value stored in the storage location prior to execution of the second mstruction
• the result of the second mstruction should be the value stored in the storage location subsequent to executmg both the first and second instructions (and prior to executing a third mstruction which updates the storage location)
• instructions may have one or more source operands and one or more destination operands
• the source operands are input values to be manipulated accordmg to the instruction definition to produce one or more results (which are the destmation operands)
• Source and destmation operands may be memory operands stored m a memory location external to the processor, or may be register operands stored m register storage locations included within the processor
• the mstruction set architecture employed by the processor defines a number of architected registers These registers are defined to exist by the instruction set architecture, and instructions may be coded to use the architected registers as source and destmation operands
• An instruction specifies a particular register as a source or destmation operand via a register number (or register address) m an operand field of the mstruction
• the register number uniquely identifies the selected register among the architected registers
• a source operand is identified by a source register number and a destination operand is identified by a destmation
• a processor employmg out of order execution may experience the above hazards with respect to register operands
• a method for handlmg these hazards is register renammg
• the processor implements a set of physical registers The number of physical registers is greater than the number of logical registers specified by the mstruction set architecture and microarchitecture of the processor
• physical registers are assigned to the destmation register operands of the mstructions
• a physical register number identifying the assigned physical register is provided for each destmation operand, and an indication of which physical registers correspond to the logical registers is mamtamed by the processor
• Subsequent mstructions which have the logical registers as source operands are provided with the corresponding physical register number for readmg the appropriate source operand
• mstructions may freely update then destmation operands m any order, since different physical storage locations are bemg updated
• Register renammg presents difficulties when mstructions experience exception conditions
• an exception refers to an error in the execution of mstructions which requires subsequent mstructions to be discarded and mstruction fetch to be started at a different address
• branch misprediction is an exception condition
• Processors may perform branch prediction to speculatively fetch, issue, and execute mstructions subsequent to conditional branch mstructions If the prediction is incorrect, the mstructions subsequent to the branch mstruction are discarded and mstructions are fetched accordmg to execution of the branch mstruction Additional exception conditions may mclude address translation errors for addresses of memory operands and other architectural or microarchitectural error conditions Because register renammg may have been applied to mstructions which are subsequently discarded due to an exception, the mappmg of logical registers to physical registers must be recovered to a state consistent with the mstruction expenencmg the exception In other words, the mappmg of
• register renammg hardware generally mcludes a mechanism for reusmg physical registers previously assigned to a destination operand of a particular mstruction once the corresponding logical register has been committed to a value corresponding to a subsequent mstruction It is desnable to use the physical registers as efficiently as possible, and to also providmg accurate method for freeing the physical registers once the subsequent state has been committed to the corresponding logical register
• the map unit stores (e g m a map silo) a current lookahead state corresponding to each lme of mstruction operations which are processed by the map unit
• the current lookahead state identifies the physical register numbers assigned to each logical register prior to performing register renaming with respect to the lme of mstruction operations
• the map unit stores an indication of which instruction operations within the lme update logical registers, which logical registers are updated, and the physical register numbers assigned to the mstruction operations
• the current lookahead state corresponding to the lme is restored from the map silo
• physical register numbers corresponding to mstruction operations within the lme which are prior to the mstruction operation expenencmg the exception are restored mto the cunent lookahead state
• the current lookahead state may be rapidly recovered upon detecting an exception Instruction operations fetched m response to the exception may be re
• a computer system compnsmg a processor and an I/O device
• the processor compnses a map unit and an architectural renames block
• the map unit is configured to assign a first physical register to a destmation operand of an mstruction operation, and is further configured to mamtam a free list mdicative of which physical registers are free for assignment
• the map unit is configured to select the first physical register from the free list Coupled to receive an indication that the instruction operation is retiring and a first physical register number correspondmg to the first physical register
• the architectural renames block is configured to provide a second physical register number identifying a second physical register previously corresponding to a first logical register identified by the destmation operand responsive to the mdication that the instruction operation is retiring
• the architectural renames block is configured to capture the first physical register number and retain the first physical register number as correspondmg to the first logical register responsive to the indication that the mstruction operation is retirmg
• the map unit is configured to
• Fig 2 is a block diagram of a map unit, a map silo, and an architectural renames block shown m Fig 1 highlighting interconnection therebetween accordmg to one embodiment of the processor shown m Fig 1
• Fig 3 is a block diagram of one embodiment of a map unit shown m Figs 1 and 2.
• Fig. 4 is a block diagram of one embodiment of a register scan unit shown in Fig 3.
• Fig. 5 is a table illustrating one encoding which may be used for virtual register numbers.
• Fig 7 is a block diagram of another portion of one embodiment of a scan unit shown m Fig 4.
• Fig. 12 is a block diagram of one embodiment of a computer system mcludmg the processor shown m Fig 1.
• processor 10 mcludes a lme predictor 12, an mstruction cache (I-cache) 14, an alignment unit 16, a branch history table 18, an indirect address cache 20, a return stack 22, a decode unit 24, a predictor miss decode unit 26, a microcode unit 28, a map unit 30, a map silo 32, an architectural renames block 34, a pair of mstruction queues 36A-36B, a pair of register files 38A-38B, a parr of execution cores 40A-40B, a load/store unit 42, a data cache (D-cache) 44, an external interface unit 46, a PC silo and redirect unit 48, and an instruction TLB (ITB) 50 Lme predictor 12 is connected to ITB 50, predictor miss decode unit 26, branch history table 18, indirect address cache 20, return stack 22, PC silo and red
• Instruction queues 36A-36B are connected to each other and to respective execution cores 40A-40B and register files 38A-38B.
• Register files 38A-38B are connected to each other and respective execution cores 40A-40B.
• Execution cores 40A-40B are further connected to load/store unit 42, data cache 44, and PC silo and redirect unit 48.
• Load/store unit 42 is connected to PC silo and rednect unit 48, D-cache 44, and external interface unit 46.
• D-cache 44 is connected to register files 38, and external interface unit 46 is connected to an external interface 52
• external interface unit 46 is connected to an external interface 52
• Elements referred to herem by a reference numeral followed by a letter will be collectively referred to by the reference numeral alone
• mstruction queues 36A-36B will be collectively referred to as instruction queues 36
• processor 10 employs a variable byte length, complex instruction set computing (CISC) instruction set architecture
• processor 10 may employ the x86 mstruction set architecture (also refened to as IA-32)
• Other embodiments may employ other mstruction set architectures mcludmg fixed length mstruction set architectures and reduced instruction set computmg (RISC) mstruction set architectures
• CISC complex instruction set computing
• Lme predictor 12 is configured to generate fetch addresses for I-cache 14 and is additionally configured to provide information regardmg a lme of mstruction operations to alignment unit 16 Generally, lme predictor 12 stores lmes of instruction operations previously speculatively fetched by processor 10 and one or more next fetch addresses correspondmg to each lme to be selected upon fetch of the lme In one embodiment, lme predictor 12 is configured to store IK entries, each defining one lme of mstruction operations Lme predictor 12 may be banked into, e g , four banks of 256 entries each to allow concurrent read and update without dual porting, if desired Lme predictor 12 provides the next fetch address to I-cache 14 to fetch the conespondmg mstruction bytes I-cache 14 is a high speed cache memory for stonng mstruction bytes Accordmg to one embodiment I- cache 14 may comprise, for example, a 256 Kbyte, four way set associative organization employmg 64 byte
• line predictor 12 Responsive to a fetch address, provides information regarding a lme of mstruction operations beginning at the fetch address to alignment unit 16 Alignment unit 16 receives mstruction bytes correspondmg to the fetch address from I-cache 14 and selects mstruction bytes mto a set of issue positions accordmg to the provided mstruction operation information More particularly, lme predictor 12 provides a shift amount for each mstruction within the lme mstruction operations, and a mapping of the mstructions to the set of mstruction operations which comprise the line An mstruction may correspond to multiple mstruction operations, and hence the shift amount correspondmg to that mstruction may be used to select instruction bytes into multiple issue positions An issue position is provided for each possible mstruction operation within the lme In one embodiment, a lme of mstruction operations may mclude up to 8 mstruction operations conespondmg to up to 6 instructions Generally, as used herein, a
• a first issue position may be referred to as bemg prior to a second issue position if an mstruction operation withm the first issue position is prior to an mstruction operation concunently withm the second issue position m program order.
• a first issue position may be refened to as bemg subsequent to a second issue position if an instruction operation withm the first issue position is subsequent to mstruction operation concunently withm the second issue position m program order.
• Instruction operations withm the issue positions may also be refened to as bemg pnor to or subsequent to other mstruction operations withm the lme.
• an mstruction operation is an operation which an execution unit withm execution cores 40A-40B is configured to execute as a single entity.
• Simple instructions may conespond to a smgle instruction operation, while more complex mstructions may conespond to multiple mstruction operations Certain of the more complex mstructions may be implemented withm microcode unit 28 as microcode routines.
• embodiments employing non-CISC mstruction sets may employ a smgle mstruction operation for each mstruction (i.e.
• mstruction and instruction operation may be synonymous m such embodiments
• a lme may compnse up to eight mstruction operations conespondmg to up to 6 mstructions. Additionally, the particular embodiment may terminate a lme at less than 6 mstructions and/or 8 mstruction operations if a branch mstruction is detected Additional restrictions regardmg the mstruction operations to the lme may be employed as desired
• Branch history table 18 provides a branch history for a conditional branch mstruction which may terminate the line identified by the next fetch address Lme predictor 12 may use the prediction provided by branch history table 18 to determine if a conditional branch instruction terminating the lme should be predicted taken or not taken
• line predictor 12 may store a branch prediction to be used to select taken or not taken
• branch history table 18 is used to provide a more accurate prediction which may cancel the lme predictor prediction and cause a different next fetch address to be selected
• Indirect address cache 20 is used to predict mdirect branch target addresses which change frequently Lme predictor 12 may store, as a next fetch address, a previously generated mdirect target address Indirect address cache 20 may ovenide the next fetch address provided by lme predictor 12 if the conespondmg line is terminated by an mdirect branch mstruction.
• PC silo and redirect unit 48 stores the fetch address and lme information and is responsible for redirectmg mstruction fetching upon exceptions as well as the orderly retirement of mstructions
• PC silo and rednect unit 48 may mclude a circular buffer for stormg fetch address and mstruction operation mformation conespondmg to multiple lmes of mstruction operations which may be outstanding withm processor 10
• PC silo and rednect unit 48 may update branch history table 18 and indirect address cache 20 accordmg to the execution of a conditional branch and an mdirect branch, respectively
• PC silo and redirect unit 48 may purge entries from return stack 22 which are subsequent to the exception-causing mstruction
• PC silo and redirect unit 48 routes an mdication of the exception-causmg mstruction to map unit 30, mstruction queues 36, and load/store unit 42 so that these units may cancel mstructions which are subsequent to the exception-causm
• lme predictor 12 and I-cache 14 employ physical addressing
• PC silo and redirect unit 48 upon detectmg an exception, PC silo and redirect unit 48 will be supplied a logical (or virtual) address Accordmgly, the redirect addresses are translated by ITB 50 for presentation to lme predictor 12
• PC silo and redirect unit 48 mamtams a virtual lookahead PC value for use m PC relative calculations such as relative branch target addresses
• the virtual lookahead PC conespondmg to each lme is translated by ITB 50 to venfy that the conespondmg physical address matches the physical fetch address produced by lme predictor 12 If a mismatch occurs, lme predictor 12 is updated with the conect physical address and the conect mstructions are fetched PC silo and redirect unit 48 further handles exceptions related to fetchmg beyond protection boundaries, etc
• PC silo and redirect unit 48 also maintains a retire PC value mdicatmg the address of the most recently retired ms
• Map unit 30 is configured to perform register renammg by assignmg physical register numbers (PR#s) to each destination register operand and source register operand of each mstruction operation
• the physical register numbers identify registers withm register files 38A-38B
• map unit 30 assigns a queue number (IQ#) to each mstruction operation, identifying the location within instruction queues 36A-36B assigned to store the mstruction operation
• Map unit 30 additionally provides an indication of the dependencies for each mstruction operation by providing queue numbers of the mstructions which update each physical register number assigned to a source operand of the mstruction operation
• Map unit 30 updates map silo 32 with the physical register numbers and mstruction to numbers assigned to each mstruction operation (as well as the conespondmg logical register numbers)
• map silo 32 may be configured to store a lookahead state conespondmg to the logical registers pnor to the
• Map unit 30 and map silo 32 are further configured to receive a retire indication from PC silo 48 Upon retirmg a lme of mstruction operations, map silo 32 conveys the destination physical register numbers assigned to the lme and conespondmg logical register numbers to architectural renames block 34 for storage
• Architectural renames block 34 stores a physical register number conespondmg to each logical register, representmg the committed register state for each logical register.
• the physical register numbers displaced from architectural renames block 34 upon update of the conespondmg logical register with a new physical register number are returned to the free list of physical register numbers for allocation to subsequent instructions
• the physical register numbers are compared to the remammg physical register numbers withm architectural renames block 34 If a physical register number is still represented within architectural renames block 34 after bemg displaced, the physical register number is not added to the free list
• Such an embodiment may be employed m
• map unit 30 and map silo 32 are configured to receive exception indications from PC silo 48 Lmes of mstruction operations subsequent to the lme mcludmg the exception-causmg mstruction operation are marked invalid withm map silo 32
• the physical register numbers conespondmg to the subsequent lmes of mstruction operations are freed upon selection of the conespondmg lmes for retirement (and architectural renames block 34 is not updated with the invalidated destmation registers)
• the lookahead register state maintained by map unit 30 is restored to the lookahead register state conespondmg to the exception-causmg mstruction
• mstruction queues 36A-36B are symmetrical and can store any mstructions Furthermore, dependencies for a particular mstruction operation may occur with respect to other mstruction operations which are stored m either mstruction queue Map unit 30 may, for example, store a lme of mstruction operations mto one of mstruction queues 36A-36B and store a following lme of instruction operations into the other one of mstruction queues 36A-36B An mstruction operation remains m mstruction queue 36A-36B at least until the prior mstruction operations upon which the mstruction operation is dependent are executed and have updated register files 38A-38B (and the mstruction operation is scheduled for execution)
• mstruction queues 36A-36B are symmetrical and can store any mstructions
• dependencies for a particular mstruction operation may occur with respect to other mstruction operations which are stored m either mstruction queue
• Map unit 30 may,
• Instruction queues 36A-36B upon schedulmg a particular mstruction operation for execution, determine at which clock cycle that particular mstruction operation will update register files 38A-38B Different execution units withm execution cores 40A-40B may employ different numbers of pipeline stages (and hence different latencies) Furthermore, certain mstructions may experience more latency withm a pipeline than others Accordmgly, a countdown is generated which measures the latency for the particular instruction operation (m numbers of clock cycles) Instruction queues 36A-36B await the specified number of clock cycles until the update occurs, and then mdicate that mstruction operations dependent upon that particular mstruction operation may be scheduled Each mstruction queue 36A-36B maintains the countdowns for instruction operations withm that mstruction queue, and internally allow dependent mstruction operations to be scheduled upon expiration of the countdown Additionally, the mstruction queue provides indications to the other instruction queue upon expiration of the countdown Subsequently, the other mstruction queue may schedule dependent
• Instruction operations scheduled from mstruction queue 36A read source operands accordmg to the source physical register numbers from register file 38 A and are conveyed to execution core 40A for execution
• Execution core 40A executes the mstruction operation and updates the physical register assigned to the destination withm register file 38A Some mstruction operations do not have destmation registers, and execution core 40A does not update a destmation physical register m this case Additionally, execution core 40A reports the R# of the mstruction operation and exception mformation regardmg the instruction operation (if any) to PC silo and redirect unit 48 Instruction queue 36B, register file 38B, and execution core 40B may operate m a similar fashion
• execution core 40A and execution core 40B are symmetrical Each execution core 40 may mclude, for example, a floating pomt add unit, a floating pomt multiply unit, two mteger, units a branch unit, a load address generation unit, a store address generation unit, and a store data unit Other configurations of execution units are possible Among the mstruction operations which do not have destination registers are store address generations, store data operations, and branch operations The store address/store data operations provide results to load/store unit 42 Load/store unit 42 provides an interface to D-cache 44 for performing memory data operations Execution cores 40A-40B execute load ROPs and store address ROPs to generate load and store addresses, respectively, based upon the address operands of the mstructions More particularly, load addresses and store addresses may be presented to D-cache 44 upon generation thereof by execution cores 40A-40B (directly via connections between execution cores 40A-40B and D-Cache 44) Load addresses which hit D-cache 44 result
• map unit 30 provides at least the following a valid mdication, an mdication of whether the ROP writes a destmation register, an R#, a logical destination register number, and logical source register numbers (up to two)
• Map unit 30 assigns a destination IQ# to each ROP, and a destmation PR# to each ROP which wntes a destination register
• Map unit 30 provides the assigned PR# and IQ# to map silo 32 upon a destmation PR#/IQ# bus 62
• map unit 30 provides a cunent lookahead register state to map silo 32 upon a cunent lookahead register state bus 64
• the term "lookahead register state" refers to identifying the state of the logical registers (l e the values stored therem) at
• Map silo 32 is connected to receive a retire valid signal upon a retire valid line 66 and a exception valid mdication and R# upon an exception mformation bus 68 Retire valid lme 66 and exception information bus 68 are connected to PC silo 48 In response an asserted retire valid signal, map silo 32 provides retired register mformation on a retire reg ⁇ ster/PR# bus 70 to architectural renames block 34 from the entry at the head of the silo More particularly, retire reg ⁇ ster/PR# bus 70 may convey a logical register number to be updated and the conespondmg physical register number In the present embodiment, retirement of ROPs occurs concunently for a full lme (I e PC silo 48 signals retirement once each of the ROPs m the lme at the head of PC silo 48 and map silo 32 have successfully executed) Accordmgly, a signal to retire the oldest lme may be used m the present embodiment Other embodiments may provide for partial retirement or may organize storage via individual instruction
• Architectural renames block 34 prior to updating entries conespondmg to the logical registers specified on retire reg ⁇ ster/PR# bus 70, reads the cunent physical register numbers conespondmg to those logical registers In other words, the physical register numbers bemg displaced from architectural renames block 34 (the "previous physical register numbers") are popped out of architectural renames block 34
• Architectural renames block 34 provides the previous PR#s on a previous PR# bus 72 which is connected to map unit 30 and updates the specified logical register entries with the PR# provided on retire reg ⁇ ster/PR# bus 70 Generally, the previous PR# are eligible to be added to the free list of PR#s (and for assignment to the destination register of a subsequent ROP)
• processor 10 employs a physical register shanng technique to improve the efficiency of physical register usage
• a physical register may be assigned to store both an mteger value and a condition code value (or flags value)
• a portion of the physical register storage stores the m
• a physical register is "free" if it is available for assignment to the destination operand of an mstruction bemg processed by the renammg hardware
• a physical register is freed upon retirement of a subsequent instruction updatmg the logical register to which the physical register is assigned
• Other embodiments may free the register in alternative fashions
• one or more instruction operations within a lme may update the same logical register
• one of map silo 32 or architectural renames block 34 mcludes logic to scan the logical registers bemg retired to identify the oldest update to each logical register (I e the last update, in program order) and stores the physical register number co ⁇ esponding to that oldest update in architectural renames block 34.
• the newer updates may be freed similar to the above discussion (i.e. cammed and freed if no match occurs).
• Map silo 32 may receive an exception indication from PC silo 48 as well.
• PC silo 48 may assert the exception valid signal and provide an R# of the instruction operation experiencing the exception to map silo 34 via exception information bus 68.
• Map silo 32 selects the silo entry conesponding to the line of ROPs including the instruction operation experiencing the exception (using the portion of the R# which is constant for each ROP in the line).
• Map silo 32 provides the cunent lookahead register state stored in the selected entry to map unit 30 upon recover lookahead register state bus 76. Map unit 30 restores the lookahead register state to the recovered state.
• map silo 32 provides the logical register numbers, PR#s, and IQ#s of ROPs within the line but prior to the ROP experiencing the exception.
• Map unit 30 updates the restored lookahead state with the provided PR#s and IQ#s.
• the lookahead state is rapidly recovered. Instructions fetched in response to the exception condition may be renamed upon reaching map unit 30 due to the rapid recovery of the renames.
• Map silo 32 conveys the PR#s to be freed upon a free PR# bus 78 to map unit 30.
• map silo 32 may be configured to provide the PR#s to be freed at a rate of one line per clock cycle. Additionally, since the ROPs to which the physical registers were assigned were not retired, the physical registers need not be conveyed to architectural renames block 34 for camming.
• map unit 30 includes a register scan unit 80, an IQ#/PR# control unit 82, a lookahead register state 84, a virtual physical register map unit 86, a free list control unit 88, and a free list register 90.
• Register scan unit 80 is connected to receive source and destination register numbers (and a valid indication for each) from decode unit 24 upon bus 60A (a portion of ROP information bus 60 shown in Fig. 2).
• Register scan unit 80 is configured to pass the destination register numbers and source virtual register numbers to virtual physical register map unit 86.
• IQ#/PR# control unit 82 is connected to a bus 60B (a portion of ROP information bus 60 shown in Fig. 2) to receive destination register numbers and valid indications conesponding to the destination register numbers. Instruction queues 36A-36B provide tail pointers upon tail pointers bus 92, indicating which entry in each queue is cunently the tail of the queue. Additionally, IQ#/PR# control unit 82 is connected to destination PR#/IQ# bus 62. Virtual/physical register map unit 86 is connected to recover lookahead register state bus 76 and to lookahead register state 84, which is further connected to cunent lookahead register state bus 64.
• virtual/physical register map unit 86 is connected to provide source PR#s, source IQ#s, destination PR#s, and an IQ# for each ROP within the line upon a source/destination PR# and IQ# bus 94 to instruction queues 36A-36B.
• Free list control unit 88 is connected to IQ#/PR# control unit 82 via a next free PR# bus 96 and an assigned PR# bus 99, and is connected to free list register 90. Furthermore, free list control unit 88 is connected to previous PR# bus 72, cam matches bus 74, and free PR# bus 78.
• the virtual register numbers assigned by register scan unit 80 identify a source for the physical register number.
• physical register numbers conesponding to source registers may be drawn from either lookahead register state 84 (which reflects updates conesponding to the lines of ROPs previously processed by map unit 30) or from a previous issue position within the line of ROPs (if the destination operand of the previous ROP is the same as the source operand...i.e. an intraline dependency exists).
• the physical register number conesponding to a source register number is the physical register number maintained by lookahead register state 84 unless an intraline dependency is detected.
• Register scan unit 80 effectively performs intraline dependency checking.
• Other embodiments may provide for other sources of source operands, as desired.
• each stage may be operated at a higher frequency. Accordingly, the embodiment of map unit 30 shown in Fig. 3 may be operable at a higher frequency than other embodiments which perform intraline dependency checking and destination physical register assignment in parallel with determining source physical register numbers.
• Using the virtual register numbers allows the separation of the functions and, as illustrated in Fig. 8 below, allows for a relatively simple and efficient mapping of source physical register numbers.
• IQ#/PR# control unit 82 assigns instruction queue numbers beginning with the tail pointer of one of instruction queues 36A-36B. In other words, the first ROP within the line receives the tail pointer of the selected instruction queue as an IQ#, and other ROPs receive IQ#s in increasing order from the tail pointer. Control unit 82 assigns each of the ROPs in a line to the same instruction queue 36A-36B, and allocates the next line of ROPs to the other instruction queue 36A-36B. Control unit 82 conveys an indication of the number of ROPs allocated to the instruction queue 36A-36B via ROP allocated bus 98. The receiving instruction queue may thereby update its tail pointer to reflect the allocation of the ROPs to that queue.
• Control unit 82 receives a set of free PR#s from free list control unit 88.
• the set of free PR#s are assigned to the destination registers within the line of instruction operations.
• processor 10 limits the number of logical register updates within a line to four (i.e. if predictor miss decode unit 26 encounters a fifth logical register update, the line is terminated at the previous instruction).
• free list control unit 88 selects four PR#s from free list 90 and conveys the selected registers to control unit 82 upon next free PR# bus 96 .
• Control unit 82 responds with which PR#s were actually assigned via assigned PR# bus 99, and free list control unit 88 deletes the assigned physical registers from the free list.
• Other embodiments may employ different limits to the number of updates within a line, including no limit (i.e. each ROP may update).
• Lookahead register state 84 stores the lookahead register state prior to updates conespondmg to the line of ROPs presented to virtual/physical register map unit 86 More particularly, lookahead register state 84 stores a physical register number conespondmg to each logical register and (m the present embodiment) an instruction queue number conespondmg to the ROP having the physical register number assigned as a destmation register Each clock cycle, lookahead register state 84 conveys the cunent lookahead register state to map silo 32 upon cunent lookahead register state bus 64.
• Virtual/physical register map unit 86 supplies the PR# and IQ# of the conespondmg logical register as indicated by lookahead register state 84 for each source register havmg a virtual register number mdicatmg that the source of the PR# is lookahead register state 84
• Source registers for which the virtual register number mdicates a prior issue position are supplied with the conespondmg PR# and IQ# assigned by contiol unit 82
• virtual/physical register map unit 86 updates the lookahead register state 84 accordmg to the logical destmation registers specified by the lme of ROPs and the destination PR#s/IQ#s assigned by control unit 82.
• Virtual/physical register map unit 86 is further configured to receive a recovery lookahead register state provided by map silo 32 upon recovery lookahead register state bus 76 m response to an exception condition (as descnbed above). Virtual/physical register map unit 86 may ovenide the next lookahead register state generated accordmg to mputs from register scan unit 80 and IQ#/PR# control unit 82 with the recovery lookahead state provided by map silo 32.
• IQ#s are routed for each source operand to mdicate which mstruction queue entries the conespondmg ROP is dependent upon Instruction queues 36A-36B await completion of the ROPs m the conespondmg mstruction queue entries before schedulmg the dependent ROP for execution.
• Each scan unit 100A-100H is connected to a portion of ROP bus 60 A shown m Fig 3 More particularly, each scan unit 100A-100H is connected to receive the source and destmation register numbers of the ROP m the conespondmg issue position Accordmgly, a bus 60AA is connected to scan unit 100 A, providmg the source and destmation register numbers for issue position zero (l e the first ROP in program order withm the lme of ROPs) Similarly, bus 60AB is connected to scan unit 100B, providmg the source and destmation register numbers for issue position one Other buses 60AC-60AH provide source and destmation register numbers conespondmg to the remammg issue positions m order, as shown Each scan unit 100A-100H is configured to provide a source virtual register number for each source register, which is subsequently passed to virtual/physical register map unit 86 Scan unit 100A is coupled to receive a virtual cunent lookahead register state The virtual cunent lookahead
• Scan unit 100B accepts the updated lookahead register state from scan unit 100A and assigns virtual register numbers from the updated lookahead register state to the source register numbers Furthermore, scan unit 100B inserts a new virtual register number mdicatmg issue position one mto the updated lookahead register state provided by scan unit 100A if the ROP m issue position one updates a logical register Scan units 100C-100H similarly assign virtual register numbers for the source registers of ROPs m issue positions 3-8, respectively, responsive to an updated lookahead register state provided by the precedmg scan units, and updates the updated lookahead register state accordmg to the destination register number, if any
• a virtual register number mdicatmg the prior issue position is assigned Otherwise, a virtual register number mdicatmg the cunent lookahead register state for the conesponding logical register is assigned In other words, intraline dependencies and dependencies upon previous lmes of instructions (through the cunent lookahead register state) are indicated by the virtual register numbers
• the updated lookahead register state provided by scan unit 100H is the virtual next lookahead register state, which is conveyed to virtual/physical register map unit 86 along with the source virtual register numbers provided by each of the scan units 100A-100H and the destination register numbers Virtual/physical register map unit 86 may then generate the next lookahead register state conespondmg to the lme of ROPs, m order to update lookahead register state 84 for the subsequent lme of ROPs
• each scan unit 100A-100F includes an integer/temporary scan cncuit handlmg the mteger, temporary, and condition code registers and a floating pomt scan circuit handling the floating pomt registers and floating pomt condition code register
• an mdication of whether each source and destination register is a floating pomt or mteger register is routed with the register number and used to determine which virtual register number to assign to the register or to replace with a new virtual register number
• a table 102 is shown illustrating an exemplary encodmg of virtual register numbers Other encodmgs are possible and contemplated Particularly, for example, the logical state of the most significant bit (MSB) shown m table 102 may be inverted from that shown in the table Still other encodmgs are possible as well Table 102 illustrates a virtual register number encodmg m which the MSB determines whether the source for cones
• the virtual cunent lookahead state provided to scan unit 100A comprises encodmgs with the MSB clear and the conespondmg logical register number provided in the LSBs
• New virtual register numbers inserted mto the updated lookahead register state by scan units 100A-100H comprise encodings with the MSB set and the issue position number conespondmg to the inserting scan unit provided m the LSBs
• a portion of one embodiment of an integer/temporary scan circuit 110 is shown which may be employed withm one embodiment of each of scan units 100A- 100H
• the destination register number of the conespondmg ROP is conveyed upon a destmation bus 112
• the first source (SRCl) register number of the conespondmg ROP is conveyed upon a SRCl bus 114
• the second source (SRC2) register number of the conespondmg ROP is conveyed upon a SRC2 bus 116
• Buses 112, 114, and 116 comprise a portion of bus 60A (e g , if integer/temporary scan cncuit 110 is a portion of scan unit 100A, buses 112, 114, and 116 are portions of bus 60AA)
• Destmation bus 112 is connected to a plurality of destmation identifier units (e g units 118A and 118B shown m Fig
• Destmation identifier unit 118A determines if the destmation register number on destmation register bus 112 selects the EAX register Accordmgly, destmation identifier unit 118 A decodes the destmation register number to determine if EAX is selected, and the decode is qualified with a valid signal indicating that the destmation register number is valid and an integer signal mdicatmg that the destination register number is an integer/temporary/condition code register (l e not a floating point register) If the destination register is the EAX register, destination identifier unit 118A signals pass/write control unit 120A to insert the virtual register number conesponding to the issue position in which integer/temporary scan circuit 110 is employed upon virtual EAX output bus 124A Otherwise, destination identifier unit 118A signals pass/write control unit 120A to pass the virtual register number provided upon virtual EAX mput bus 122 A to virtual EAX output bus 124 A
• SRCl identifier unit 126A determines if the SRCl register number on SRCl register bus 114 selects the EAX register by decodmg the SRCl register number to determine if EAX is selected, and qualifying the decode with a valid signal mdicatmg that the SRCl register number is valid and an mteger signal mdicatmg that the SRCl register number is an lnteger/temporary/condition code register If EAX is selected as SRCl, SRCl identifier unit 126A activates switch 130A to drive the virtual register number provided upon virtual EAX mput bus 122A onto SRCl virtual register bus 132A SRC2 identifier unit 128A is similar to SRCl identifier unit 126A but operates upon the SRC2 register number provided upon SRC2 register bus 116 and controls switch 130B to accordingly drive or not drive SRC2 virtual register bus 132B In this fashion, an updated lookahead state may be passed to the next scan
• a portion of one embodiment of a floatmg pomt scan circuit 140 is shown which may be employed withm one embodiment of each of scan units 100A-100H
• Scan circuit 140 receives SRCl register bus 114 and SRC2 register bus 116, similar to integer/temporary scan cncuit 110, and may drive source virtual register numbers upon SRCl virtual register bus 132A and SRC2 virtual register bus 132B
• the portion shown m Fig 7 receives the virtual stl mput (l e one of stO through st7 registers as defined m the x86 mstruction set architecture, hence 0 ⁇ I ⁇ 7) and provides the virtual stl output for the issue position in which circuit 140 is employed (the "present issue position")
• a SRCl identifier unit 142 A connected to SRCl register bus 114 determmes if the SRCl register number is selectmg the stl register (l e the register number is stl
• the portion of floating pomt scan circuit 114 shown in Fig 7 provides an output virtual register number conespondmg to register stl on virtual stl output bus 146
• a variety of mput virtual register numbers may be selectable as the output virtual register number upon output bus 146, controlled by a vanety of control signals provided by decode unit 24
• the x86 floatmg pomt mstructions treat the floating point register set as a stack StO is the register at the top of the stack, stl is next to the top, etc
• Certain mstructions may cause the stack to be pushed (makmg the cunent stO register stl, etc ) or popped (makmg the cunent stl register stO, etc
• an exchange mstruction is supported which swaps the top of stack register (stO) and one of the other registers The selection of a virtual stl output attempts to handle many of these situations by employing switches
• the portion of floatmg pomt scan circuit 140 conespondmg to stO may mclude each of the virtual stl mputs from the previous scan unit, to arbitranly select any register as the virtual stO output
• the top of stack (TOS) field of the floating point status register and the floatmg point tag word are affected by floatmg pomt manipulations as well
• Lookahead values for the TOS and tag word may be propagated through pushes, pops, and exchanges as well
• a cunent lookahead copy of the TOS and tag word may be mamtamed m lookahead register state 84
• the value of the TOS and tag word conespondmg to each issue position may be stored in map silo 32 for exception recovery (and the last value may be updated mto lookahead register state 84)
• register scan unit 80 may detect the use of a register which is mvalid (as mdicated by the tag word) and note an exception with the ROP usmg the register for later exception handlmg
• integer/temporary scan cncuit 110 and floating pomt scan circuit 140 may handle mteger to floatmg pomt and floating pomt to mteger moves as well If a source register of an ROP is mdicated to be mteger, integer/temporary scan circuit 110 provides the source virtual register number On the other hand, if the source register of an ROP is mdicated to be floating point, floatmg point scan circuit 140 provides the source virtual register number If a destination register is mdicated as floatmg pomt, a new floatmg pomt virtual register number is provided mto the updated lookahead register state by floating pomt scan circuit 140 On the other hand, if a destmation register is mdicated as mteger, a new integer virtual register number is provided mto the updated lookahead register state by integer/temporary scan circuit 110 Accordmgly, an issue position having a floating pomt to mteger register
• virtual/physical register map unit 86 includes a source IQ# mux 160, a next lookahead IQ# mux 162, a source PR# mux 164, a next lookahead PR# mux 168, a trap IQ# mux 170, and a trap PR# mux 172
• Source IQ# mux 160 is connected to receive the cunent lookahead IQ# conespondmg to each logical register from lookahead register state 84, and to receive the destmation IQ#s assigned by IQ#/PR# control unit 82
• Next lookahead IQ# mux 162 is similarly connected to receive the cunent lookahead IQ#s and destmation IQ#s
• the output of source IQ# mux 160 is pipelined to mstruction queues 36A-36B, while the output of next lookahead IQ# mux
• source IQ# mux 160 and source PR# mux 164 select the source IQ# and PR# for each source operand of each ROP responsive to the conespondmg source virtual register number provided by register scan unit 80
• Mux 160 may be implemented, for example, as a parallel set of muxes (one for each source register of each ROP) connected to receive the mputs as shown for mux 160 and receivmg a conespondmg source virtual register number as a selection control
• mux 164 may be implemented as a parallel set of muxes (one for each source register of each ROP) connected to receive the inputs as shown for mux 164 and receivmg a conespondmg source virtual register number as a selection control If the source virtual register number indicates that the cunent lookahead state is the source for the IQ#/PR#, then the logical register number mcluded m the source virtual register number is used to select one of the IQ# and PR# provided by lookahead register state 84 On
• next lookahead IQ# mux 162 and next lookahead PR# mux 168 select the IQ# and PR# for each logical register responsive to the conespondmg virtual next lookahead state provided by register scan unit 80
• Mux 162 may be implemented, for example, as a parallel set of muxes (one for each logical register) connected to receive the mputs as shown for mux 162 and receivmg a conespondmg virtual register number as a selection control
• mux 168 may be implemented as a parallel set of muxes (one for each logical register) connected to receive the mputs as shown for mux 168 and receiving a conespondmg virtual register number as a selection control If the virtual register number mdicates that the cunent lookahead state is the source for the IQ#/PR# of a particular logical register, then the logical register number mcluded in the virtual register number is used to select one of the IQ# and PR# provided by lookahead register state
• Virtual/physical register map unit 86 as shown m Fig 8 further handles the mappmg of a next lookahead register state for lookahead register state 84 m response to exception conditions
• Trap IQ# mux 170 is used when traps are recognized upon execution to route the IQ#s conespondmg to the recovery lookahead register state from map silo 32 to ovenide the next lookahead state provided by mux 162 PC silo 48 may signal the trap as a selection control upon mux 170
• the PR# within the recovery lookahead register state may be selected through trap PR# mux 172 responsive to the trap signal
• other methods for recovermg from exception conditions may be employed For example, exception conditions may be handled upon retirement
• an R# conespondmg to the lme is stored m an R# (line portion) field
• the R# stored is the lme portion of the R#s assigned by PC silo 48 to the lme of ROPs
• the lme portion is the same for each ROP within the lme, while an offset portion of the R# identifies the issue position withm the lme of a particular ROP
• the silo entry (which conesponds to the lme as a whole) can be associated with an ROP expenencmg an exception by comparing the lme portion of the R# for the ROP with the stored R#
• an mdication of which ROPs withm the line are valid is stored m a valid ROPs within Lme field of the map silo entry
• the mdication may be a bit per ROP If the bit is set, the conespondmg ROP withm the line is valid If the bit is clear, the conesponding ROP withm the line is not valid
• an mdication of which ROPs have a destmation logical register is stored m a ROP register writes field Agam
• the indication may be a bit per ROP If the bit is set, the conespondmg ROP within the line updates a destmation register If the bit is clear, the conesponding ROP withm the lme does not update the destmation register
• the mdication of which ROPs have a destmation register is used to decide which of the assigned PR#s and assigned IQ#s become part of the recovery state in the event of an exception, as described below
• the PR#s and IQ#s assigned to the ROPs which have destination registers are mamtamed m assigned PR# and assigned IQ# fields of the entry, respectively Additionally, the logical register number of each destmation register is stored m a logical register numbers field The logical register numbers are used to determine which logical register withm the recovery lookahead state are to receive the assigned PR#s and assigned IQ#s, as descnbed below Additionally, upon successful retirement of the lme, the logical register numbers and conespondmg PR#s are conveyed to architectural renames block 34 for storage An mdication of which ROPs withm the lme update the condition code register is stored in a CC wntes field Each portion of the condition code which is updated separately may be represented by a bit withm the CC writes field, and a set of bits may be associated with each register wnte mdicated withm the ROP register wntes field The PR# and IQ# of the conespondmg ROP (
• the cunent lookahead register state stored withm lookahead register state 84 prior to dispatching the lme of ROPs conespondmg to the map silo entry is stored in a cunent lookahead register state field of the entry
• the cunent lookahead register state serves as a basis for recovermg lookahead register state 84 m the event of an exception withm the lme
• the R# provided by PC silo 48 identifies a particular ROP. However, for purposes of checking against map silo 32, the line portion of the R# is cammed. Entries which are more recent than the provided R# (i.e. instructions subsequent to the exception in program order) are cancelled within map silo 32. The PR# stored in the assigned PR# field of the cancelled entries are freed. In one embodiment, the PR#s of the cancelled entries are freed over multiple clock cycles, at the rate of one entry per clock cycle. The silo entry for which the cam indicates a match is the selected map silo entry.
• the cunent lookahead register state stored in the selected map silo entry i.e. the cunent lookahead state prior to the line of ROPs including the ROP experiencing the exception is restored to the lookahead state in cunent lookahead register state 84 (step 192). Additionally, the FP TOS and valid bits in lookahead register state 84 are restored to the value stored in the selected map silo entry for the issue position of the ROP experiencing the exception (step 194).
• the ROP register writes field in the selected map silo entry is masked to the writes which are prior to the ROP experiencing the exception.
• ROP register writes which are subsequent to the ROP experiencing the exception are masked off, such that they do not appear to be writes subsequent to the masking.
• the remaining writes are scanned to detect the most recent write to each register (i.e. if two or more of the remaining writes are to the same register, the more recent write is retained).
• the current lookahead state is updated with the results (step 196). It is noted that step 192 and step 196 may be performed in map silo 32 prior to transmitting a recovery lookahead register state to lookahead register state 84. Alternatively, the cunent lookahead register state may be restored to lookahead register state 84 and subsequently updated with respect to step 196.
• the ROP register writes field in the selected map silo entry i.e. the original value prior to the masking of step 196) is masked to the register writes which are subsequent to the ROP experiencing the exception.
• the register writes which are prior to the ROP experiencing the exception are masked off.
• the PR#s of the remaining register writes are freed (step 198).
• the flowchart shown in Fig. 11 may advantageously provide a rapid method for recovering the lookahead state in response to the exception.
• source virtual register number and virtual source register number may have been used above. It is intended that these terms have the same meaning. It is further noted that, as mentioned above, embodiments in which each instruction specified in the instruction set architecture employed by processor 10 maps to a single instruction operation are contemplated within the meaning of instruction operation as defined herein.
• Bus bridge 202 provides an interface between processor 10, main memory 204, graphics controller 208, and devices attached to PCI bus 214.
• bus bridge 202 identifies the target of the operation (e.g. a particular device or, in the case of PCI bus 214, that the target is on PCI bus 214).
• Bus bridge 202 routes the operation to the targeted device.
• Bus bridge 202 generally translates an operation from the protocol used by the source device or bus to the protocol used by the target device or bus.
• Main memory 204 is a memory in which application programs are stored and from which processor 10 primarily executes.
• a suitable main memory 204 comprises DRAM (Dynamic Random Access Memory), and preferably a plurality of banks of SDRAM (Synchronous DRAM).
• Graphics controller 208 is provided to control the rendering of text and images on a display 226.
• Graphics controller 208 may embody a typical graphics accelerator generally known in the art to render three- dimensional data structures which can be effectively shifted into and from main memory 204.
• Graphics controller 208 may therefore be a master of AGP bus 210 in that it can request and receive access to a target interface within bus bridge 202 to thereby obtain access to main memory 204.
• a dedicated graphics bus accommodates rapid retrieval of data from main memory 204.
• graphics controller 208 may further be configured to generate PCI protocol transactions on AGP bus 210.
• the AGP interface of bus bridge 202 may thus include functionality to support both AGP protocol transactions as well as PCI protocol target and initiator transactions.
• Display 226 is any electronic display upon which an image or text can be presented.
• a suitable display 226 includes a cathode ray tube ("CRT"), a liquid crystal display (“LCD”), etc.
• computer system 200 may be a multiprocessing computer system including additional processors (e.g. processor 10a shown as an optional component of computer system 200).
• processor 10a may be similar to processor 10. More particularly, processor 10a may be an identical copy of processor 10.
• Processor 10a may share external interface 52 with processor 10 (as shown in Fig. 12) or may be connected to bus bridge 202 via an independent bus.
• a processor has been shown which employs a register renammg scheme.

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