KR100572040B1 - 명령들의 퇴거시 물리적인 레지스터들을 선택적으로 자유화하도록 구성된 프로세서 - Google Patents

명령들의 퇴거시 물리적인 레지스터들을 선택적으로 자유화하도록 구성된 프로세서 Download PDF

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KR100572040B1
KR100572040B1 KR1020017001356A KR20017001356A KR100572040B1 KR 100572040 B1 KR100572040 B1 KR 100572040B1 KR 1020017001356 A KR1020017001356 A KR 1020017001356A KR 20017001356 A KR20017001356 A KR 20017001356A KR 100572040 B1 KR100572040 B1 KR 100572040B1
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KR20010053623A (ko
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위트데이비드비.
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
KR1020017001356A 1998-07-31 1999-01-18 명령들의 퇴거시 물리적인 레지스터들을 선택적으로 자유화하도록 구성된 프로세서 Expired - Fee Related KR100572040B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/127,094 1998-07-31
US09/127,094 US6230262B1 (en) 1998-07-31 1998-07-31 Processor configured to selectively free physical registers upon retirement of instructions

Publications (2)

Publication Number Publication Date
KR20010053623A KR20010053623A (ko) 2001-06-25
KR100572040B1 true KR100572040B1 (ko) 2006-04-18

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KR1020017001356A Expired - Fee Related KR100572040B1 (ko) 1998-07-31 1999-01-18 명령들의 퇴거시 물리적인 레지스터들을 선택적으로 자유화하도록 구성된 프로세서

Country Status (6)

Country Link
US (1) US6230262B1 (cg-RX-API-DMAC7.html)
EP (1) EP1099158B1 (cg-RX-API-DMAC7.html)
JP (1) JP3866920B2 (cg-RX-API-DMAC7.html)
KR (1) KR100572040B1 (cg-RX-API-DMAC7.html)
DE (1) DE69903554T2 (cg-RX-API-DMAC7.html)
WO (1) WO2000007097A1 (cg-RX-API-DMAC7.html)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6253310B1 (en) * 1998-12-31 2001-06-26 Intel Corporation Delayed deallocation of an arithmetic flags register
US6266763B1 (en) * 1999-01-05 2001-07-24 Advanced Micro Devices, Inc. Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values
JP3817436B2 (ja) 2000-09-28 2006-09-06 株式会社東芝 プロセッサおよびリネーミング装置
WO2002054228A1 (en) * 2000-12-06 2002-07-11 University Of Bristol Register renaming
US7043626B1 (en) 2003-10-01 2006-05-09 Advanced Micro Devices, Inc. Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming
US20080077782A1 (en) * 2006-09-26 2008-03-27 Arm Limited Restoring a register renaming table within a processor following an exception
US20080148022A1 (en) * 2006-12-13 2008-06-19 Arm Limited Marking registers as available for register renaming
US9052909B2 (en) 2011-12-07 2015-06-09 Arm Limited Recovering from exceptions and timing errors
US8738971B2 (en) 2011-12-07 2014-05-27 Arm Limited Limiting certain processing activities as error rate probability rises
US9075621B2 (en) 2011-12-23 2015-07-07 Arm Limited Error recovery upon reaching oldest instruction marked with error or upon timed expiration by flushing instructions in pipeline pending queue and restarting execution
US8640008B2 (en) 2011-12-23 2014-01-28 Arm Limited Error recovery in a data processing apparatus
GB2496934B (en) * 2012-08-07 2014-06-11 Imagination Tech Ltd Multi-stage register renaming using dependency removal
US20160378480A1 (en) * 2015-06-27 2016-12-29 Pavel G. Matveyev Systems, Methods, and Apparatuses for Improving Performance of Status Dependent Computations
CN114356420B (zh) * 2021-12-28 2023-02-17 海光信息技术股份有限公司 指令流水线的处理方法及装置、电子装置及存储介质

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT354159B (de) 1975-02-10 1979-12-27 Siemens Ag Assoziativspeicher mit getrennt assoziierbaren bereichen
US4453212A (en) 1981-07-13 1984-06-05 Burroughs Corporation Extended address generating apparatus and method
US4928223A (en) 1982-10-06 1990-05-22 Fairchild Semiconductor Corporation Floating point microprocessor with directable two level microinstructions
US4807115A (en) 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
DE3751503T2 (de) 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
AU587714B2 (en) 1986-08-27 1989-08-24 Amdahl Corporation Cache storage queue
US5067069A (en) 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5226126A (en) 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5129067A (en) 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5136697A (en) 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5226130A (en) 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5053631A (en) 1990-04-02 1991-10-01 Advanced Micro Devices, Inc. Pipelined floating point processing unit
US5058048A (en) 1990-04-02 1991-10-15 Advanced Micro Devices, Inc. Normalizing pipelined floating point processing unit
DE69130588T2 (de) 1990-05-29 1999-05-27 National Semiconductor Corp., Santa Clara, Calif. Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
US5197132A (en) 1990-06-29 1993-03-23 Digital Equipment Corporation Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery
US5355457A (en) * 1991-05-21 1994-10-11 Motorola, Inc. Data processor for performing simultaneous instruction retirement and backtracking
GB9112754D0 (en) 1991-06-13 1991-07-31 Int Computers Ltd Data processing apparatus
GB9123271D0 (en) 1991-11-02 1991-12-18 Int Computers Ltd Data processing system
GB2263985B (en) 1992-02-06 1995-06-14 Intel Corp Two stage window multiplexors for deriving variable length instructions from a stream of instructions
SG45269A1 (en) 1992-02-06 1998-01-16 Intel Corp End bit markers for instruction decode
IE80854B1 (en) 1993-08-26 1999-04-07 Intel Corp Processor ordering consistency for a processor performing out-of-order instruction execution
US5784589A (en) 1993-10-18 1998-07-21 Cyrix Corporation Distributed free register tracking for register renaming using an availability tracking register associated with each stage of an execution pipeline
US5630149A (en) 1993-10-18 1997-05-13 Cyrix Corporation Pipelined processor with register renaming hardware to accommodate multiple size registers
DE69429061T2 (de) 1993-10-29 2002-07-18 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5546554A (en) 1994-02-02 1996-08-13 Sun Microsystems, Inc. Apparatus for dynamic register management in a floating point unit
US5481693A (en) 1994-07-20 1996-01-02 Exponential Technology, Inc. Shared register architecture for a dual-instruction-set CPU
US5675759A (en) 1995-03-03 1997-10-07 Shebanow; Michael C. Method and apparatus for register management using issue sequence prior physical register and register association validity information
EP0851343B1 (en) 1996-12-31 2005-08-31 Metaflow Technologies, Inc. System for processing floating point operations
JP3452771B2 (ja) * 1997-10-02 2003-09-29 富士通株式会社 命令制御システム及びその方法
US6119223A (en) * 1998-07-31 2000-09-12 Advanced Micro Devices, Inc. Map unit having rapid misprediction recovery
US6122656A (en) * 1998-07-31 2000-09-19 Advanced Micro Devices, Inc. Processor configured to map logical register numbers to physical register numbers using virtual register numbers

Also Published As

Publication number Publication date
EP1099158B1 (en) 2002-10-16
KR20010053623A (ko) 2001-06-25
EP1099158A1 (en) 2001-05-16
US6230262B1 (en) 2001-05-08
DE69903554T2 (de) 2003-06-18
JP2002521762A (ja) 2002-07-16
JP3866920B2 (ja) 2007-01-10
WO2000007097A1 (en) 2000-02-10
DE69903554D1 (de) 2002-11-21

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