JP2002513509A - 直径ばらつきと共に出口ヴァイア再デポジットを制御するために吸光コーティングおよび消滅性銅を用いる方法 - Google Patents
直径ばらつきと共に出口ヴァイア再デポジットを制御するために吸光コーティングおよび消滅性銅を用いる方法Info
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- 239000012815 thermoplastic material Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 230000001256 tonic effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 150000003918 triazines Chemical class 0.000 description 1
- ZNOCGWVLWPVKAO-UHFFFAOYSA-N trimethoxy(phenyl)silane Chemical compound CO[Si](OC)(OC)C1=CC=CC=C1 ZNOCGWVLWPVKAO-UHFFFAOYSA-N 0.000 description 1
- AATYKEFFPLPLST-UHFFFAOYSA-N trimethylsilylurea Chemical compound C[Si](C)(C)NC(N)=O AATYKEFFPLPLST-UHFFFAOYSA-N 0.000 description 1
- 229920000785 ultra high molecular weight polyethylene Polymers 0.000 description 1
- 238000002525 ultrasonication Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01019—Potassium [K]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01025—Manganese [Mn]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01078—Platinum [Pt]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0112—Absorbing light, e.g. dielectric layer with carbon filler for laser processing
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1377—Protective layers
- H05K2203/1383—Temporary protective insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
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- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 積層基板の露出した底部表面上に重合体吸光層を設ける段階、 前記基板の上部から該基板を通して該基板の底部まで該基板内にスルーヴァイ アをレーザ穿孔する段階、及び 前記基板の底部表面上に形成された吸光層を除去する段階、 をそなえて成る、積層基板内にスルーヴァイアを形成する方法。 2. 前記基板の露出した底部表面上に吸光層を設ける段階には、伝導(conduct ive)材料の層を該吸光層と密に接触した状態におく段階が含まれている請求項1 に記載の方法。 3. 該基板の該露出した底部表面に設けられた該吸光層の厚みが5μm〜50μ mである請求項2に記載の方法。 4. 該吸光層の厚みが公称で25μmである請求項3に記載の方法。 5. 前記基板の上部表面が露出されており、 該スルーヴァイアをレーザ穿孔する段階の前に前記基板の露出した上部表面上 に重合体吸光層を設ける段階、及び 該スルーヴァイアをレーザ穿孔する段階の後、前記基板の上部表面上に形成さ れた該吸光層を除去する段階、 をさらにそなえて成る請求項3に記載の方法。 6. 前記基板の該露出した上部表面上に設けられた該吸光層の厚みが5μm〜 50μmである請求項5に記載の方法。 7. 前記基板の該露出した上部表面上に設けられた該吸光層の厚みが公称で25 μmである請求項6に記載の方法。 8. 該スルーヴァイアの入口幅が75μm以下である請求項6に記載の方法。 9. 該スルーヴァイアの出口幅が75μm以下である請求項8に記載の方法。 10.該スルーヴァイアの縦横比が3:1以上である請求項9に記載の方法。 11.該スルーヴァイアの縦横比が約10:1であるとき、該スルーヴァイアの出 口幅のばらつきが約20μm2である請求項10に記載の方法。 12.該スルーヴァイアの縦横比が約20:1であるとき、該スルーヴァイアの出 口幅のばらつきが約30μm2である請求項10に記載の方法。 13.前記基板内に該スルーヴァイアをレーザ穿孔する段階が、該基板に複数の レーザパルスを印加する段階を含んでいる請求項10に記載の方法。 14.複数のレーザパルスを印加する段階には、該スルーヴァイアを形成するた め予め定められたパターンで該レーザパルスをトレパニング(trepanning)する段 階が含まれている請求項13に記載の方法。 15.該予め定められたパターンが円形である請求項14に記載の方法。 16.該基板には伝導層が含まれ、前記基板内で該スルーヴァイアをレーザ穿孔 する段階には、伝導材料層のアブレーション(ablation)エネルギー密度しきい値 よりも大きいパルスあたりエネルギー密度を該基板に対し適用することが含まれ る請求項13に記載の方法。 17.該レーザが355nmの波長で発光し、該基板層に適用されるパルスあたりエ ネルギー密度が5J/cm2より大きい請求項16に記載の方法。 18.該パルスあたりエネルギー密度が公称で11J/cm2である請 求項17に記載の方法。 19.各パルスが100ns以下のパルス幅を有する請求項18に記載の方法。 20.該レーザが266nmの波長で発光し、該基板に適用されるパルスあたりエネ ルギー密度が1.5J/cm2より大きい請求項16に記載の方法。 21.該パルスあたりエネルギー密度が公称で5J/cm2である請求項20に記載 の方法。 22.各パルスが100ns以下のパルス幅を有する請求項21に記載の方法。 23.該スルーヴァイアをレーザ穿孔する段階には、該積層基板の中に複数のス ルーヴァイアをレーザ穿孔する段階が含まれ、該基板の中に少なくとも1つのブ ラインドヴァイアをレーザ穿孔する段階をさらにそなえて成る請求項5に記載の 方法。 24.該ブラインドヴァイアの縦横比が1:1以上である請求項23に記載の方法 。 25.該積層基板が誘電体層を内含し、該伝導材料層が該誘電体層上に形成され 該基板の該露出した上部表面であり、該伝導材料層は前記基板内の各々のブライ ンドヴァイアの場所に対応する場所にアパーチャを有し、各々のアパーチャは該 誘電体層の表面を露出させており、 前記基板の中に少なくとも1つのブラインドヴァイアをレーザ穿孔する段階に は、該誘電体層のアブレーションエネルギー密度しきい値より大きく該伝導材料 層のアブレーションエネルギー密度しきい値より小さいパルスあたりエネルギー 密度を各々のブラインドヴァイアについて該基板に適用する段階が含まれている 請求項24に記載の方法。 26.各々のブラインドヴァイアの入口幅が75μm以下である請求項25に記載の 方法。 27.該積層基板内に複数のスルーヴァイアをレーザ穿孔する段階が、該伝導材 料層のアブレーションエネルギー密度しきい値より大きいパルスあたりエネルギ ー密度を各々のスルーヴァイアについて該基板に適用する段階を含んでいる請求 項26に記載の方法。 28.該レーザが355nmの波長で発光し、 各々のスルーヴァイアをレーザ穿孔するために該積層基板に適用されるパルス あたりエネルギー密度が5J/cm2より大きく、 各々のブラインドヴァイアを穿孔するために該誘電体層に適用されるパルスあ たりエネルギー密度が0.5J/cm2〜11J/cm2である請求項27に記載の方法。 29.各々のスルーヴァイアをレーザ穿孔するために該積層基板に適用されるパ ルスあたりエネルギー密度が公称で11J/cm2である請求項28に記載の方法。 30.各パルスが100ns以下のパルス幅を有する請求項29に記載の方法。 31.該レーザが266nmの波長で発光し、 各々のスルーヴァイアを穿孔するために該積層基板に適用されるパルスあたり エネルギー密度が1.5J/cm2より大きく、 各々のブラインドヴァイアを穿孔するために該誘電体層に適用されるパルスあ たりエネルギー密度が0.5J/cm2〜3J/cm2である請求項27に記載の方法。 32.各々のスルーヴァイアを穿孔するために該積層基板に適用されるパルスあ たりエネルギー密度が公称で5J/cm2である請求項31に記載の方法。 33.各パルスが100ns以下のパルス幅を有する請求項32に記載の 方法。 34.基板の露出した底部表面上に重合体吸光層を設ける段階、 前記基板の上部から該基板を通して該基板の底部まで該基板内にスルーヴァイ アをレーザ穿孔する段階、及び 前記基板の底部表面上に形成された該吸光層を除去する段階、 をそなえて成る方法によって形成された、スルーヴァイアを有する積層基板。 35.該基板の該露出した底部表面上に該吸光層を設ける段階には、伝導材料の 層を該吸光層と密に接触した状態におく段階が含まれている請求項34に記載の積 層基板。 36.該基板の該露出した底部表面に設けられる該吸光層の厚みが5μm〜50μ mである請求項35に記載の積層基板。 37.該吸光層の厚みが公称で25μmである請求項36に記載の積層基板。 38.該基板の上部表面が露出されており、前記方法は、 該スルーヴァイアをレーザ穿孔する段階の前に該基板の該露出した上部表面上 に重合体吸光層を設ける段階、及び 該スルーヴァイアをレーザ穿孔する段階の後、該基板の上部表面上に形成され た該吸光層を除去する段階、 をさらにそなえて成る請求項36に記載の積層基板。 39.該基板の該露出した上部表面上に設けられた該吸光層の厚みが5μm〜50 μmである請求項38に記載の積層基板。 40.該基板の該露出した上部表面上に設けられる該吸光層の厚みが公称で25μ mである請求項39に記載の積層基板。 41.該スルーヴァイアの入口幅が75μm以下である請求項39に記載の積層基板 。 42.該スルーヴァイアの出口幅が75μm以下である請求項41に記 載の積層基板。 43.該スルーヴァイアの縦横比が3:1以上である請求項42に記載の積層基板 。 44.該スルーヴァイアの縦横比が10:1であるとき、該スルーヴァイアの出口 幅のばらつきが約20μm2である請求項43に記載の積層基板。 45.該スルーヴァイアの縦横比が20:1であるとき、該スルーヴァイアの出口 幅のばらつきが約30μm2である請求項43に記載の積層基板。 46.該基板内に該スルーヴァイアをレーザ穿孔する段階が、該基板に複数のレ ーザパルスを印加する段階を含んでいる請求項43に記載の積層基板。 47.複数のレーザパルスを印加する段階には、該スルーヴァイアを形成するた め予め定められたパターンで該レーザパルスをトレパニングする段階が含まれて いる請求項46に記載の積層基板。 48.該予め定められたパターンが円形である請求項47に記載の積層基板。 49.該基板が伝導層を含み、基板内で該スルーヴァイアをレーザ穿孔する段階 には、該伝導層のアブレーションエネルギー密度しきい値よりも大きいパルスあ たりエネルギー密度を該基板に対して適用することが含まれる請求項46に記載の 積層基板。 50.該レーザが355nmの波長で発光し、該基板層に適用されるパルスあたりエ ネルギー密度が5J/cm2より大きい請求項49に記載の積層基板。 51.パルスあたりエネルギー密度が公称で11J/cm2である請求項50に記載の 積層基板。 52.各パルスが100ns以下のパルス幅を有する請求項51に記載の 積層基板。 53.該レーザが266nmの波長で発光し、該基板に適用されるパルスあたりエネ ルギー密度が1.5J/cm2より大きい請求項49に記載の積層基板。 54.パルスあたりエネルギー密度が公称で5J/cm2である請求項53に記載の 積層基板。 55.各パルスが100ns以下のパルス幅を有する請求項54に記載の積層基板。 56.該スルーヴァイアをレーザ穿孔する段階には、該基板の中に複数のスルー ヴァイアをレーザ穿孔する段階が含まれ、前記方法には、該基板の中に少なくと も1つのブラインドヴァイアをレーザ穿孔する段階がさらに含まれている請求項 38に記載の積層基板。 57.該ブラインドヴァイアの縦横比が1:1以上である請求項56に記載の積層 基板。 58.該基板が誘電体層を内含し、該伝導層が該誘電体層上に形成され該基板の 露出した上部表面であり、該伝導層は該基板内の各々のブラインドヴァイアの場 所に対応する場所にアパーチャを有し、各々のアパーチャは該誘電体層の表面を 露出させており、 該基板の中に少なくとも1つのブラインドヴァイアをレーザ穿孔する段階には 、該誘電体層のアブレーションエネルギー密度しきい値より大きく該伝導層のア ブレーションエネルギー密度しきい値より小さいパルスあたりエネルギー密度を 各々のブラインドヴァイアについて該基板に適用する段階が含まれている請求項 57に記載の積層基板。 59.各々のブラインドヴァイアの入口幅が75μm以下である請求項58に記載の 積層基板。 60.該基板内に複数のスルーヴァイアをレーザ穿孔する段階が、 該伝導層のアブレーションエネルギー密度しきい値より大きいパルスあたりエネ ルギー密度を各々のスルーヴァイアについて該基板に適用する段階を含んでいる 請求項59に記載の積層基板。 61.該レーザが355nmの波長で発光し、 各々のスルーヴァイアをレーザ穿孔するために該基板に適用されるパルスあた りエネルギー密度が5J/cm2より大きく、 各々のブラインドヴァイアを穿孔するために該誘電体層に適用されるパルスあ たりエネルギー密度が0.5J/cm2〜11J/cm2である請求項60に記載の積層基板 。 62.各々のスルーヴァイアをレーザ穿孔するために該基板に適用されるパルス あたりエネルギー密度が公称で11J/cm2である請求項61に記載の積層基板。 63.各パルスが100ns以下のパルス幅を有する請求項62に記載の積層基板。 64.該レーザが266nmの波長で発光し、 各々のスルーヴァイアを穿孔するために該基板に適用されるパルスあたりエネ ルギー密度が1.5J/cm2より大きく、 各々のブラインドヴァイアを穿孔するために該誘電体層に適用されるパルスあ たりエネルギー密度が0.5J/cm2〜3J/cm2である請求項60に記載の積層基板 。 65.各々のスルーヴァイアを穿孔するために該基板に適用されるパルスあたり エネルギー密度が公称で5J/cm2である請求項64に記載の積層基板。 66.各パルスが100ns以下のパルス幅を有する請求項65に記載の積層基板。 67.コア層、 各々が底部誘電体層及び該誘電体層上に形成された上部伝導層を 有する、該コア層上に形成された少なくとも1つの単層、及び 少なくとも1つの最も外側の単層を通って延び、各々が、最も外側の単層の伝 導層の中に入口アパーチャを有し、このそれぞれの入口アパーチャが各々75μm 以下の入口幅を有する少なくとも1つのヴァイアであって、少なくとも1つのヴ ァイアが3:1以上の縦横比をもつもの、 をそなえてなる積層基板。 68.3:1以上の縦横比をもつ該ヴァイアがスルーヴァイアである請求項67に 記載の積層基板。 69.該スルーヴァイアが約10:1の縦横比をもち、該スルーヴァイアの出口幅 のばらつきが約20μm2である請求項68に記載の積層基板。 70.少なくとも1つのヴァイアが1:1以上の縦横比をもつブラインドバイア である請求項69に記載の積層基板。 71.該スルーヴァイアが約20:1の縦横比をもち、該スルーヴァイアの出口幅 のばらつきが約30μm2である請求項68に記載の積層基板。 72.各々の誘電体層が、高温有機誘電体基板材料である請求項68に記載の積層 基板。 73.各々の誘電体層が、ポリイミド及びポリイミド積層材及びエポキシ樹脂か ら成るグループの中から選ばれた材料で作られている請求項72に記載の積層基板 。 74.各々の誘電体層は、少なくとも一部がポリテトラフルオロエチレンで形成 された誘電体材料で作られている請求項72に記載の積層基板。
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US5541367A (en) * | 1994-10-31 | 1996-07-30 | Dell Usa, L.P. | Printed circuit board having a land with an inwardly facing surface and method for manufacturing same |
US5541731A (en) * | 1995-04-28 | 1996-07-30 | International Business Machines Corporation | Interferometric measurement and alignment technique for laser scanners |
JPH09172120A (ja) * | 1995-12-18 | 1997-06-30 | Dainippon Printing Co Ltd | 金属板の加工方法 |
-
1996
- 1996-11-08 US US08/747,095 patent/US6023041A/en not_active Expired - Lifetime
-
1997
- 1997-10-22 AU AU50842/98A patent/AU5084298A/en not_active Abandoned
- 1997-10-22 JP JP52144198A patent/JP2002513509A/ja not_active Ceased
- 1997-10-22 WO PCT/US1997/018974 patent/WO1998020531A2/en active Application Filing
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013131501A (ja) * | 2006-10-31 | 2013-07-04 | Corning Inc | マイクロ加工された電解質シート、これを利用する燃料電池デバイス、および燃料電池デバイスを作製するマイクロ加工方法 |
JP2009252892A (ja) * | 2008-04-03 | 2009-10-29 | Mitsubishi Electric Corp | レーザ加工方法、プリント基板製造方法およびレーザ加工装置 |
Also Published As
Publication number | Publication date |
---|---|
WO1998020531A3 (en) | 1998-10-22 |
WO1998020531A2 (en) | 1998-05-14 |
US6023041A (en) | 2000-02-08 |
AU5084298A (en) | 1998-05-29 |
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