JP2000505948A - 公称位置合せを向上させるための基準手法を用いる方法 - Google Patents
公称位置合せを向上させるための基準手法を用いる方法Info
- Publication number
- JP2000505948A JP2000505948A JP10521455A JP52145598A JP2000505948A JP 2000505948 A JP2000505948 A JP 2000505948A JP 10521455 A JP10521455 A JP 10521455A JP 52145598 A JP52145598 A JP 52145598A JP 2000505948 A JP2000505948 A JP 2000505948A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- pulse
- laser
- pulses
- laser drilling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/486—Via connections through the substrate with or without pins
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- H05K1/00—Printed circuits
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- H05K1/00—Printed circuits
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- H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/0209—Inorganic, non-metallic particles
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0008—Apparatus or processes for manufacturing printed circuits for aligning or positioning of tools relative to the circuit board
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H—ELECTRICITY
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
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- Y10S430/00—Radiation imagery chemistry: process, composition, or product thereof
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Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. コア層を設ける段階、 前記コア層の上に位置合せマークを形成する段階、 前記位置合せマークを基準位置合せ点として用いて前記コア層の上に第1の層 を形成する段階、 前記コア層の上の前記位置合せマークを露出させるために前記第1の層をレー ザ穿孔する段階、および 前記位置合せマークを基準点として用いて前記第1の層の上に第2の層を形成 する段階、 をそなえて成る、積層基板を作る方法。 2. 前記位置合せマークを露出させるために前記第1の層をレーザ穿孔する前 記の段階は、 第1の複数のパルスを用いて前記第1の層をレーザ穿孔する段階であって、こ こに該第1の複数のパルスの各パルスは第1のパルスあたりエネルギー密度を有 する段階、および 第2の複数のパルスを用いて同一の場所でレーザ穿孔する段階であって、ここ に該第2の複数のパルスの各パルスは第2のパルスあたりエネルギー密度を有し かつこの第2のパルスあたりエネルギー密度は前記第1のパルスあたりエネルギ ー密度と同じかそれより大である段階、 を含む請求項1に記載の方法。 3. 前記第1の層をレーザ穿孔することにより前記積層基板内にヴァイアを形 成する段階をさらに有する請求項2に記載の方法。 4. 前記ヴァイアの入口幅は75μm以下である請求項3に記載の方法。 5. 前記ヴァイアの縦横比は1:1以上である請求項4に記載の 方法。 6. 前記コア層の上の前記位置合せマークを露出させるために前記第2の層を レーザ穿孔する段階、 前記第2の層の上に少なくとも1つの付加的な層を、この付加的な層が形成さ れるときに前記露出した位置合せマークを基準点として用いて、形成する段階、 および 前記コア層の上の前記位置合せマークを露出させるために、前記付加的な層を 形成した後に、該付加的な層をレーザ穿孔する段階、 をさらに有する請求項5に記載の方法。 7. 前記位置合せマークを露出させるために前記第2の層をレーザ穿孔する前 記の段階は、 第3の複数のパルスを用いて前記第2の層をレーザ穿孔する段階であって、こ こに該第3の複数のパルスの各パルスは第1のパルスあたりエネルギー密度を有 する段階、および 第4の複数のパルスを用いて同一の場所でレーザ穿孔する段階であって、ここ に該第4の複数のパルスの各パルスは第2のパルスあたりエネルギー密度を有す る段階、 を含む請求項6に記載の方法。 8. 前記付加的な層をレーザ穿孔することによって前記積層基板内に他のヴァ イアを形成する段階をさらに有する請求項7に記載の方法。 9. 前記他のヴァイアの入口幅は75μm以下である請求項8に記載の方法。 10.前記他のヴァイアの縦横比は1:1以上である請求項9に記載の方法。 11.前記積層基板は露出した伝導(conductive)層を有していて、 前記露出した伝導層の上に吸光層を設ける段階、 前記露出した位置合せマークを基準位置合せ点として用いてダミーパッド用の マスクを形成するために、前記吸光層をレーザ走査する段階、 前記吸光層を除去する段階、および 前記ダミーパッドを基準位置合せ点として用いて前記露出した伝導層の上には んだパッド層を形成する段階、 をさらにそなえて成る請求項10に記載の方法。 12.コア層を設ける段階、 前記コア層の上に位置合せマークを形成する段階、 前記位置合せマークを基準位置合せ点として用いて前記コア層の上に第1の層 を形成する段階、 前記コア層の上の前記位置合せマークを露出させるために前記第1の層をレー ザ穿孔する段階、および 前記位置合せマークを基準点として用いて前記第1の層の上に第2の層を形成 する段階、よりなる方法によって形成される積層基板。 13.前記位置合せマークを露出させるために前記第1の層をレーザ穿孔する前 記の段階は、 第1の複数のパルスを用いて前記第1の層をレーザ穿孔する段階であって、こ こに該第1の複数のパルスの各パルスは第1のパルスあたりエネルギー密度を有 する段階、および 第2の複数のパルスを用いて同一の場所でレーザ穿孔する段階であって、ここ に該第2の複数のパルスの各パルスは第2のパルスあたりエネルギー密度を有し かつこの第2のパルスあたりエネルギー密度は前記第1のパルスあたりエネルギ ー密度と同じかそれより大である段階、 を含んで成る請求項12に記載の積層基板。 14.前記第1の層をレーザ穿孔することにより前記積層基板内にヴァイアを形 成する段階をさらに有する請求項13に記載の積層基板。 15.前記ヴァイアの入口幅は75μm以下である請求項14に記載の積層基板。 16.前記ヴァイアの縦横比は1:1以上である請求項15に記載の積層基板。 17.前記コア層の上の前記位置合せマークを露出させるために前記第2の層を レーザ穿孔する段階、 前記第2の層の上に少なくとも1つの付加的な層を、この付加的な層が形成さ れるときに前記露出した位置合せマークを基準点として用いて、形成する段階、 および 前記コア層の上の前記位置合せマークを露出させるために、前記付加的な層を 形成した後に、該付加的な層をレーザ穿孔する段階、 をさらに有する請求項16に記載の積層基板。 18.前記位置合せマークを露出させるために前記第2の層をレーザ穿孔する前 記の段階は、 第3の複数のパルスを用いて前記第2の層をレーザ穿孔する段階であって、こ こに該第3の複数のパルスの各パルスは第1のパルスあたりエネルギー密度を有 する段階、および 第4の複数のパルスを用いて同一の場所でレーザ穿孔する段階であって、ここ に該第4の複数のパルスの各パルスは第2のパルスあたりエネルギー密度を有す る段階、 を含む請求項17に記載の積層基板。 19.前記付加的な層をレーザ穿孔することによって前記積層基板内に他のヴァ イアを形成する段階をさらに有する請求項18に記載の積層基板。 20.前記他のヴァイアの入口幅は75μm以下である請求項19に記載の積層基板 。 21.前記他のヴァイアの縦横比は1:1以上である請求項20に記載の積層基板 。 22.前記積層基板は露出した伝導層を有していて、その積層基板形成方法が、 前記露出した伝導層の上に吸光層を設ける段階、 前記露出した位置合せマークを基準位置合せ点として用いてダミーパッド用の マスクを形成するために、前記吸光層をレーザ走査する段階、 前記吸光層を除去する段階、および 前記ダミーパッドを基準位置合せ点として用いて前記露出した伝導層の上には んだパッド層を形成する段階、 をさらにそなえて成る請求項21に記載の積層基板。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US74566896A | 1996-11-08 | 1996-11-08 | |
US08/745,668 | 1996-11-08 | ||
PCT/US1997/019083 WO1998020534A1 (en) | 1996-11-08 | 1997-10-22 | Method for using fiducial schemes to increase nominal registration |
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JP2000505948A true JP2000505948A (ja) | 2000-05-16 |
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Family Applications (1)
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JP10521455A Ceased JP2000505948A (ja) | 1996-11-08 | 1997-10-22 | 公称位置合せを向上させるための基準手法を用いる方法 |
Country Status (4)
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US (1) | US6130015A (ja) |
JP (1) | JP2000505948A (ja) |
AU (1) | AU4993797A (ja) |
WO (1) | WO1998020534A1 (ja) |
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-
1997
- 1997-10-22 JP JP10521455A patent/JP2000505948A/ja not_active Ceased
- 1997-10-22 AU AU49937/97A patent/AU4993797A/en not_active Abandoned
- 1997-10-22 WO PCT/US1997/019083 patent/WO1998020534A1/en active Application Filing
-
2000
- 2000-02-03 US US09/496,676 patent/US6130015A/en not_active Expired - Lifetime
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WO1998020534A1 (en) | 1998-05-14 |
AU4993797A (en) | 1998-05-29 |
US6130015A (en) | 2000-10-10 |
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