GB2307352A

GB2307352A - Manufacture of multi-layer printed circuit boards

Info

Publication number: GB2307352A
Application number: GB9523621A
Authority: GB
Inventors: Christopher James Haley; Gary David Panaghiston; Paul Timothy Sharp; Stephen Geoffrey Tyler
Original assignee: GEC Marconi Ltd; Marconi Co Ltd
Current assignee: BAE Systems Electronics Ltd
Priority date: 1995-11-16
Filing date: 1995-11-16
Publication date: 1997-05-21
Also published as: GB9523621D0

Abstract

A multi-layer printed circuit board is manufactured by forming an alignment target (61) and a first printed circuit on a first dielectric substrate (31), laminating a second dielectric substrate (32) and a conductive layer (33) to the first dielectric substrate (31), covering the conductive layer (33) with a layer of photoresist, providing a first phototool (35) defining an alignment sight (62) and the profiles of via holes to be formed through the conductive layer (33) and the second dielectric substrate (32), exposing the photoresist through the first phototool (35) whilst the alignment sight (62) is accurately aligned with the alignment target (61), processing the exposed photoresist to uncover those portions of the conductive layer (33) which need to be removed to define the via holes, etching the uncovered portions to form via holes, removing the remainder of the exposed photoresist layer, extending the via holes through the second dielectric substrate (32) by ablating those portions of the second dielectric substrate exposed by the via holes, forming conductive vias through the extended via holes, and then using a second phototool (43) to form a second printed circuit in the conductive layer (33) whereby the first and second printed circuits are interconnected by the conductive vias.

Description

MULTI-LAYER PRINTED CIRCUIT BOARDS AND THEIR MANUFACTURE The present invention relates to a method of manufacturing multi-layer printed circuit boards, to multi-layer printed circuit boards produced by the method, and also to phototools for use in the method. More particularly the invention is concerned with the manufacture of multilayer printed circuit boards in which the printed circuits are of high density and are interconnected by miniature conductive vias which serve either to conduct electricity and/or heat.

It is well known in the art for mutli-layer printed circuit boards to be manufactured using phototools to generate the printed circuits and the vias, appropriate registration of the vias and printed circuits being achieved by mounting successive phototools in a common jig supporting the printed circuit board during manufacture. The location of such phototools in ajig is typically achieved by the engagement of pins in the jig with corresponding apertures in the phototool.

Although this technique is satisfactory for ensuring proper alignment of conventional vias with conventional printed circuits, it is not suitable for the production of high density multi-layer printed circuit boards with miniature vias because the clearance between, and manufacturing tolerances of, the jig pins and phototool apertures is substantially greater than the precision required to ensure the correct alignment of a miniature via with a high density printed circuit.

From the manufacturer of silicon chips and thin film circuits it is known to achieve alignment using optical parallax systems but these do not address the specific problems that occur in the manufacture of a multi-layer printed circuit board having high density printed circuits connected by miniature vias.

It is an object of the present invention to provide a method of manufacturing multi-layer printed circuit boards having circuits of high density and interconnected by miniature vias.

Without limitation to the density of the printed circuits, or the physical size of the miniature vias, the invention provides a method which is capable of producing multi-layer printed circuit boards of which the printed circuit density uses 75 micron tracks separated by 75 micron gaps and has pads of 150 microns interconnected by miniature vias having a diameter of 75 microns.

According to one feature of the invention a method of manufacturing a multi-layer printed circuit board includes forming an alignment target and a first printed circuit on a first dielectric substrate, laminating a second dielectric substrate and a conductive layer to the first dielectric substrate such that the second dielectric substrate separates the conductive layer from the first printed circuit, covering the conductive layer with a layer of photoresist, providing a first phototool defining an alignment sight and the profiles of via holes to be formed through the conductive layer and the second dielectric substrate, arranging for the position of the alignment target relative to the first printed circuit and the position of the alignment sight relative to the locations of the via hole profiles to be such that the via holes will be accurately positioned relative to the first printed circuit when the alignment sight is aligned with the alignment target, placing the first phototool over the photoresist layer and adjusting the orientation of the first phototool relative to the conductive layer until the alignment sight is accurately aligned with the alignment target, exposing the photoresist through the first phototool whilst the alignment sight is accurately aligned with the alignment target, processing the exposed photoresist to uncover those portions of the conductive layer which need to be removed to define the via holes, etching the uncovered portions of the conductive layer to form via holes through the conductive layer, removing the remainder of the exposed photoresist layer, extending the via holes through the second dielectric substrate by ablating those portions of the second dielectric substrate exposed by the via holes in the conductive layer, forming conductive vias through the extended via holes to interconnect the first printed circuit and the conductive layer, and then using a second phototool to form a second printed circuit in the conductive layer whereby the first and second printed circuits are interconnected by the conductive vias.

Preferably the remainder of the exposed photoresist layer is removed after ablation of those portions of the second dielectric substrate exposed by the via holes in the conductive layer.

In this manner the ablated material is deposited on the remainder of the exposed photoresist layer and is consequently removed at the same time thereby avoiding contamination of the second dielectric substrate and the conductive layer.

The method may include covering the conductive layer with a second layer of photoresist after the formation of the conductive vias, providing the second phototool with an alignment sight and the profile of the second printed circuit, arranging for the position of the alignment sight of the second phototool relative to the location of the profile of the second printed circuit to be such that the profile of the second printed circuit will be accurately positioned relative to the first printed circuit when the alignment sight of the second phototool is aligned with the alignment target on the first dielectric substrate, placing the second phototool over the second photoresist layer and adjusting the orientation of the second phototool relative to the conductive layer until the alignment sight of the second phototool is accurately aligned with the alignment target on the first dielectric substrate, exposing the second layer of photoresist through the second phototool whilst the alignment sight of the second phototool is accurately aligned with the alignment target on the first dielectric substrate, processing the exposed second layer of photoresist to uncover those portions of the conductive layer which need to be retained to define the second printed circuit, protecting the portions of the conductive layer that will define the second printed circuit against etching, then removing the remainder of the exposed second layer of photoresist and etching away the conducting layer to leave only the protected portions.

Alternatively the method may include providing the first phototool with marking corresponding to the negative of an image of a second alignment target, arranging for the position of the marking to produce the second alignment target in the conductive layer in a location spaced from the first alignment target on the first dielectric substrate, covering the conductive layer with a second layer of photoresist after the formation of the conductive vias, providing the second phototool with an alignment sight and the profile of the second printed circuit, arranging for the position of the second alignment target relative to the via holes and the position of the alignment sight of the second phototool relative to the location of the profile of the second printed circuit to be such that the second printed circuit will be accurately positioned relative to the conductive vias when the alignment sight of the second phototool is aligned with the second alignment target, placing the second phototool over the second photoresist layer and adjusting the orientation of the second phototool relative to the conductive layer until the alignment sight of the second phototool is accurately aligned with the second alignment target, exposing the second layer of photoresist through the second phototool whilst the alignment sight of the second phototool is accurately aligned with the second alignment target, processing the exposed second layer of photoresist to uncover those portions of the conductive layer which need to be retained to define the second printed circuit, protecting the portions of the conductive layer that will define the second printed circuit against etching, then removing the remainder of the exposed second layer of photoresist and etching away the conducting layer to leave only the protected portions.

The method may also include additionally providing the second phototool with a second alignment sight, arranging for the position of the second alignment sight relative to the location of the profile of the second printed circuit to be such that the second printed circuit will be accurately positioned relative to the first printed circuit when the second alignment sight on the second phototool is aligned with the first alignment target on the first dielectric substrate.

The method may include forming an aperture through the second dielectric substrate and the conductive layer in a position overlying the alignment target, and optically aligning the alignment sight of the first phototool with the alignment target on the first dielectric substrate.

In this case the method may include forming the aperture through the conductive layer before lamination of the second dielectric substrate and the conductive layer to the first dielectric substrate. In this case the method may also include forming the aperture through the conductive layer before lamination to the second dielectric substrate and extending the aperture through the second dielectric substrate by ablating the portion of the second dielectric substrate exposed by the aperture.

Alternatively, the method may include laminating the conductive layer and the second dielectric substrate prior to their lamination with the first dielectric substrate, forming the aperture through the laminated conductive layer and the second dielectric substrate, positioning the aperture over the alignment target on the first dielectric substrate, and then laminating the first and second dielectric substrates.

The method preferably includes forming each target as at least two spaced target portions, forming each sight as a corresponding number of identically spaced sight portions, and performing the alignment by accurately aligning each sight portion with its corresponding target portion.

The method preferably includes aligning a feature of each sight or sight portion, of substantially the same cross section as the via holes to be formed, within a larger feature of each target or each target portion corresponding substantially with the width of the narrowest feature of the second printed circuit in which a via hole is to be formed.

To produce printed circuit boards having more than two layers, the method may include repeating the claimed steps to produce a printed circuit board having at least three printed circuits separated by respective dielectric substrates. In this case the method may also include spacing the alignment target or target portions for each substrate whereby the completed circuit board will bear a series of used alignment targets or target portions confirming the completion of each of the manufacturing steps.

According to another aspect of the invention a pair of phototools, for use with the method, has the first defining an alignment sight and the profiles of via holes, the second defining an alignment sight and the profile of a printed circuit, and the positions of the respective sights are such that, when both are aligned, the via holes will be correctly aligned with the printed circuit. Preferably each alignment sight comprises at least two spaced sight portions.

Preferably the first phototool also bears a marking corresponding to the negative of an alignment target, the second phototool also bears a second alignment sight, and the positions of the marking and the second alignment sight are such that, when the second alignment sight is aligned with an alignment target produced by the marking, the via holes will be correctly aligned with the printed circuit. In this event the marking preferably comprises at least two spaced markings corresponding to the negatives of two similarly spaced alignment targets, and the second alignment sight comprises a corresponding number of similarly spaced sight portions.

Each marking preferably includes a feature corresponding substantially with the width of the narrowest feature of the printed circuit in which a via hole is to be formed. Each alignment sight or sight portion preferably includes a feature of substantially the same cross-section as the profiles of the via holes.

The invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figures 1 to 18 are diagrams illustrating the sequential steps involved in the manufacture of a multi-layer printed circuit, but with Figures 8 and 9 illustrating a preferred alternative to the steps shown in Figures 6 and 7, Figure 17 illustrating a completed 2-layer printed circuit, and Figure 18 illustrating how the method can be applied to the manufacture of printed circuits having three or more layers.

Figure 19 is a considerably large plan view of a phototool marking in the form of a negative of the image of an alignment target; Figure 20 is a plan view, to the same scale as Figure 19, showing both an alignment target produced using the negative of Figure 19, and the positive of a phototool marking to provide a positive image of an alignment target; Figure 21 is to the same scale as Figures 19 and 20 and is a plan view of a phototool marking providing an alignment sight;; Figure 22 is an exploded isometric diagram illustrating the use of a pair of phototools, bearing the markings of Figures 19, 20 and 21 to ensure their correct alignment for producing a high density printed circuit with miniature vias, and Figure 23 is a diagram illustrating the sequential use of three pairs of phototools to achieve accurate alignment of multiple high density printed circuits interconnected with miniature vias.

Figure 1 diagrammatically illustrates a first printed circuit 30 formed on a first dielectric substrate 31. The first printed circuit 30 and substrate 31 can be of any type, for instance a base printed circuit, or a core which has printed circuits formed on both sides. Although the printed circuit 30 could be of low density, it is preferred that it is of the same density as the remainder of the multi-layer printed circuit board that is to be produced. That is a track width of 75 microns, a track spacing of 75 microns, and connection pads of 150 microns for receiving vias of 75 microns.

Figure 2 shows the lamination of a second dielectric substrate 32 and a conductive layer 33 to the first dielectric substrate 31 such that the second dielectric substrate 32 separates the conductive layer 33 from the first printed circuit 30. It will be noted that the second dielectric substrate 32 adheres to, and mechanically secures together, the first dielectric substrate 31 and the conductive layer 33. It also is adhered to the first printed circuit 30. The first dielectric substrate 31 may be a base formed of a polymer or other organic material, or formed of metal such as copper, or invar/copper, or steel, or aluminium, or aluminium/silicon carbide, or a sandwich of copper, molybdenum and copper. The second dielectric substrate 32 is preferably formed of a sheet of thin polyamide having a thickness typically of 125 microns or less.The laminate formed in Figure 2 may rely on the adhesive properties of the polyamide substrate 32, the laminate being pressed together under a temperature and pressure suitable for ensuring complete lamination. Alternatively the laminate shown in Figure 2 may be secured together by the use of adhesives, for instance between the substrate base 31 and the substrate 32, and between the substrate 32 and the conductive layer 33. Alternatively, the second dielectric substrate 32 can be formed from a layer of adhesive having suitable dielectric properties, the adhesive being positioned between the substrate base 31 and the conductive layer 33 prior to setting.

Preferably the conductive layer 33 is a copper foil having a thickness typically of about 20 microns. This may be prelaminated to the second dielectric substrate 32 before the lamination shown in Figure 2 occurs.

With reference to Figure 3, a first layer of photoresist 34 is applied to the conductive layer 33 and is processed by photolithography using a first phototool 35 marked with a profile 36 for forming a via hole. The first layer of photoresist is then exposed through the first phototool 35 and is processed to provide the structure shown in Figure 4, in which the first layer of photoresist 34 has uncovered a portion 37 of the conductive layer 33 which needs to be removed to define a via hole.

The structure illustrated in Figure 4 is then exposed to an appropriate etching composition which will dissolve the uncovered portion 37 of the conductive layer 33, the remainder of the conductive layer 33 being protected by the remainder of the exposed photoresist layer 34.

Figure 5 illustrates the completion of this etching process, the uncovered portion 37 of the conducting layer 33 having been etched away to form a via hole 38 which extends completely through the conductive layer 33.

In Figure 6, the remainder of the exposed first photoresist layer 34 of Figure 5 has been chemically removed to expose the conductive layer 33.

In Figure 7 an excimer laser is scanned across the conductive layer 33 as indicated by the arrows 39. In this manner the conductive layer 33 protects the second dielectric layer 32 from ablation, but the portion of the second dielectric substrate 32 exposed by the via hole 38 is ablated as shown to extend the via hole 38, as shown, up to the surface of the first printed circuit 30.

The ablated material is ejected from the via hole 38 and a proportion can become adhered to the remaining surface of the conductive layer 33. It is usually necessary to remove the ablated material from the surface 33 before proceeding further.

Figures 8 and 9 illustrate a modification of the process shown in Figures 6 and 7 which considerably simplifies the removal of the ablated material. From Figure 8 it will be noted that the exposed first photoresist layer 34 has been left on the surface of the conductive layer 33 during the ablation process. The ablated material is accordingly deposited on the exposed first photoresist layer 34 which effectively protects the conductive layer 33 from contamination by the ablated material.

As shown in Figure 9, the exposed first photoresist layer 34 has been chemically removed, together with the adhered ablated material, thereby leaving the same structure as shown in Figure 7 but with the surface of the conductive layer 33 already cleaned for the next step in the manufacturing process.

The cleaned assembly shown in Figure 7, or the assembly shown in Figure 9, is then submerged in a bath of activated palladium which conditions and metallises the blind via hole 38 to form a conductive path between the first printed circuit 30 and the conductive layer 33.

As shown in Figure 10, a layer of conductive material 40, such as copper, is plated onto the assembly thereby forming a conductive via 41 through the extended via hole 38 to interconnect the first printed circuit 30 and the conductive layer 33. A preferred method of forming the Es 224ç2.3 miniature blind via 41 is described in our co-pending patent application number X;.(reference P/60771/MRC in the records of the applicants patent department) which is hereby incorporated into this application by way of reference.

The construction shown in Figure 10 is then submitted to a second photolithographic process as illustrated in Figure 11. This process includes the application of a thicker second layer of photoresist 42 to the surface of the layer of conductive material 40. A second phototool 43 is then accurately positioned over the second photoresist layer 42 so that a profile 44 of a second printed circuit is correctly aligned with the position of the miniature via 41. After exposure, the second photoresist layer 42 is processed to leave the construction shown in Figure 12, in which the exposed second photoresist layer 42 has had a portion 45 removed to uncover the miniature conductive via 41 and portions 46 and 47 of the conductive layer 33, 40 which will define the second printed circuit.

Figure 13 shows the next step of the method in which additional conductive material 48 has been deposited onto the uncovered portions 46 and 47 of the conductive layer 33, 40 and into the interior of the miniature blind via 41. The additional conductive material 48 is preferably electro-plated copper. It should be noted that the additional conductive material 48 does not entirely fill the opening 45 which is subsequently pattern plated with a tinned alloy 49 as shown in Figure 14. This pattern plated layer 49 forms an etch-resistant layer protecting the additional conductive material 48 as shown in Figure 14.

The remainder of the second photoresist layer 42 is then removed leaving the structure shown in Figure 15 from which it will be noted that the etch-resistant layer 49 only protects those portions of the conductive layer 33, 40, 48 which are to form the second printed circuit.

In particular it should be noted that the areas 50 and 51 of the conductive layer 33, 40 are not protected by the etch-resistant layer 49.

The structure is then submitted to a further etching process which removes the portions 50 and 51 to leave the structure shown in Figure 16. This is then submitted to a stripping process which removes the lead/tin layer 49 to provide the structure shown in Figure 17. This structure is a two-layer printed circuit board in which the first printed circuit is separated by the second dielectric substrate 32 from a second printed circuit defined by the residue of the conductive layer 33 and the plated layers 40 and 48. The two printed circuits are interconnected by the miniature conductive via 41 which extends through the via hole 38 that was formed through the conductive layer 33 and the second dielectric substrate 32 as has been described with reference to Figures 5 to 9.

From Figure 17 it will particularly be noted that the miniature conductive via 41 comprises a deposit of conductive material which is adhered to the first printed circuit 30, extends through both the ablated via hole 38 in the second substrate 32 and through the aligned hole 38 which was etched in the first conductive layer 33 as described with reference to Figure 5. In this manner the upper end of the miniature conductive via 41 is effectively sandwiched between the conductive layer 33 and the subsequent conductive layer 48 thereby ensuring particularly fine electrical contact between the via 41 and the second printed circuit 33, 48.

The manufacturing process described to this point with reference to Figures 1 to 17 can then be repeated to provide additional printed circuit layers. In this connection it should be noted that Figure 17 would be processed, in the same way as Figure 1, to provide the structure shown in Figure 18. In this manner a third dielectric substrate 52 is laminated between the second dielectric substrate 32 and a further conductive layer 53 which, after processing, will form the third printed circuit.

Although the invention has been described with reference to forming a single miniature via 41 between a first printed circuit 30 and a second printed circuit 33, 48, it should be understood that the first printed circuit 30 and the second printed circuit 33, 48 would typically be complex high density printed circuits interconnected by a multiplicity of conductive vias which would serve to transmit electricity and/or heat between appropriate parts of the respective circuits.

The description of the invention to this point details the various steps necessary to manufacture a multi-layer printed circuit board, such as that shown in Figure 17, using a first phototool 35, as described with reference to Figure 3, and a second phototool 43 as described with reference to Figure 11.

In order to manufacture a multi-layer printed circuit board having circuits of high density and interconnected by miniature vias, it is essential for the phototools 35 and 43 to be very precisely positioned with respect to the first printed circuit 30 and to each other. This precision is achieved by the use of pairs of alignment targets and alignment sights as will now be described with reference to Figures 19 to 23.

The markings shown in Figures 19, 20 and 21 are drawn to the same scale but have been very significantly enlarged to facilitate their description.

Figure 19 depicts a phototool marking 60 which is the negative of an alignment target image to be etched in the conductive layer 33 during the process described with reference to Figure 5.

Figure 20 shows an alignment target 61 which can either be printed (or otherwise delineated) on either of the phototools 35 and 43, and also the alignment target image 61 which would be produced by the use of the phototool marking 60 in Figure 19.

Figure 21 shows a corresponding alignment sight 62 which would be printed, or otherwise delineated, on the phototool 35 and 43 as will hereinafter be described.

The alignment sight 62 is divided by a cross-graticule 64 into four equal segments as shown. Each segment includes a pair of alignment lines 64 disposed at right angles to each other, and a dot 65 which has a diameter equivalent to the smallest via to be formed in the printed circuit. Typically the dot diameter would be of the order of 75 microns.

On the other hand, the alignment target 61 in Figure 20 is provided with a target cross 66 defining four segments each of which contains a larger dot 67 which has a diameter equivalent to the smallest connection pad of the printed circuit. Typically the diameter of the larger dot 67 will be of the order of 150 micron.

Each limb of the cross 66 has the same width as the larger dot 67 and accordingly represents a printed circuit pad having a transverse dimension of 150 microns.

In use the alignment sight 62 of Figure 21 is superimposed over the target 61 of Figure 20 such that all of the alignment sight dots 65 are superimposed on the larger alignment target dots 67. Angular orientation of the alignment sight 62 relative to the alignment target 61 is further achieved by balancing the alignment line 64 against the edges of the target cross 66. To this end the eight alignment lines 64 of the alignment sight 62 define an aperture for receiving the image of the cross 66 on the alignment target 61.

With reference to Figure 22 the lower rectangle represents the first dielectric substrate 31 which of course bears the first printed circuit 30 as shown in Figure 1. Superimposed above the first dielectric substrate 31 is shown the second dielectric substrate 32 covered by the conductive layer 33. The conductive layer 33, together with the second dielectric substrate 32 will be laminated to the first dielectric substrate 31 as described with reference to Figure 2.

However, it should be noted that the first dielectric substrate 31 is marked with two of the targets 61. These will be formed on the substrate 31 typically at the same time as the unshown first printed circuit. The second dielectric substrate 32 and the laminated conductive layer 33 are provided with a pair of apertures 68 which are positioned so that the targets 61 can be seen through the aperture 68 after the first and second substrates 31, 32 have been laminated together.

The position of the alignment targets 61 on the first substrate 31 are arranged, to be in a predetermined position relative to the first printed circuit.

The first phototool 35 is provided with unshown via hole profiles and a pair of alignment sight 62 which are arranged to be in a predetermined position relative to both the via hole profiles and the targets 61 on the first substrate 31.

The first phototool 35 is laid over the first layer of photoresist 34 and the alignment sight 62 are manipulated until they are exactly over the alignment target 61 on the first substrate 31.

This adjustment of the orientation is achieved using optical equipment and extremely fine movements of the first phototool 35. After alignment has been achieved, the first layer of photoresist 34 is exposed thereby starting the process of creating the miniature vias 41 in positions where they will correctly penetrate the pads of the first printed circuit.

Although it is preferred for the alignment to be achieved using an optical system, it is possible for the sight 62 to be aligned with the targets 61 using x-rays, in which case the aperture 68 would not be necessary. It is also possible that alignment could be achieved using other techniques.

The aperture 68 may be formed through the conductive layer 33 and second substrate 32 after they have been laminated together or may be formed in any other convenient manner. For instance, the aperture 68 could be punched in a copper foil comprising the conductive layer 33.

The first phototool additionally bears markings 60 of the type described with reference to Figure 19. These are spaced in the same manner as the alignment sight 62 and are arranged a predetermined distance from them. During the etching of the conductive layer 33, as described with reference to Figure 5, the markings 60 of the first phototool 35 generate alignment targets 61 in the conductive layer 33. At this stage of the process the targets 61 on the first substrate 31 can be seen through the aperture 68 and second targets 61 can also be seen etched into the surface of the conductive layer 33. Either or both of these sets of targets 61 can be used for the next part of the photolithographic process using the second phototool 43.

The second phototool 43 bears the unshown profile of the second printed circuit and also a pair of alignment sights 62 which are in a fixed position relative to both the profile of the second printed circuit and the position of the respective target 61 on the first substrate 31. The process described with reference to Figure 11 is then carried out by aligning the sights 62 of the second phototool 43 directly with the target 61 on the first substrate 31.

The second phototool 43 is preferably provided with a further pair of alignment sights 62A so that these can be aligned with the unshown target 61 etched into the surface of the conductive layer 33. It is preferred that the second pair of sights 62A are used to achieve alignment, with the first pair of sights 62 being used to indicate any cumulative drift from the target 61 on the first substrate 31.

The second phototool 43 additionally bears markings corresponding to alignment target 61 and these are reproduced in the surface of the conductive layer 33 following the process described with reference to Figures 11 to 17. In this manner, the conductive layer 33 is provided with a third pair of the target 61 ready for use with a production of a third printed circuit layer.

It will therefore be noted that each layer of the printed circuit board is formed using a pair of phototools 35 and 43. Also that each phototool is provided with alignment sight 62 for alignment with targets on the previous layer. In this manner a multi-layer printed circuit board will bear two series of target marks 61 thereby providing a visible proof that each stage of the process has been completed.

When the third printed circuit is being formed, the conductive layer will of course have three pairs of apertures 68, one pair revealing the target 61 on the first substrate 31, the second pair revealing the targets produced by the marking 60 on the first phototool 35, and the third pair revealing the new targets produced by the marking 61 on the second phototool 43.

The sequential use of pairs of phototools 35, 43 is illustrated in Figure 23 which shows the successive use of three pairs A, B and C of phototools.

To the left of Figure 23 is shown one of the pair of alignment targets 61 formed on the first substrate 31. The left hand portion of column A shows the alignment sight 62 on the first phototool 35 and also the negative phototool marking 60 necessary to produce the second target for use with the second phototool 43. The right hand column under bracket A depicts the markings on the second phototool 43, the lower most sight 62 being used with the target 61 on the lower substrate 31, the uppermost sight being used for alignment with the target produced by the negative marking 60, and the uppermost marking 61 being used to produce the third target which will be the first target used for the next printed circuit layer.

This process is continued in columns B and C as shown so that each phototool in each pair is provided with appropriate sights for alignment with the preceding targets and additionally producing a target for the next phototool.

Claims

1. A method of manufacturing a multi-layer printed circuit board, including forming an

alignment target and a first printed circuit on a first dielectric substrate, laminating a second dielectric substrate and a conductive layer to the first dielectric substrate such that the second dielectric substrate separates the conductive layer from the first printed circuit, covering the conductive layer with a layer of photoresist, providing a first phototool defining an alignment sight and the profiles of via holes to be formed through the conductive layer and the second dielectric substrate, arranging for the position of the alignment target relative to the first printed circuit and the position of the alignment sight relative to the locations of the via hole profiles to be such that the via holes will be accurately positioned relative to the first printed circuit when the alignment sight is aligned with the alignment target, placing the first phototool over the photoresist layer and adjusting the orientation of the first phototool relative to the conductive layer until the alignment sight is accurately aligned with the alignment target, exposing the photoresist through the first phototool whilst the alignment sight is accurately aligned with the alignment target, processing the exposed photoresist to uncover those portions of the conductive layer which need to be removed to define the via holes, etching the uncovered portions of the conductive layer to form via holes through the conductive layer, removing the remainder of the exposed photoresist layer, extending the via holes through the second dielectric substrate by ablating those portions of the second dielectric substrate exposed by the via holes in the conductive layer, forming conductive vias through the extended via holes to interconnect the first printed circuit and the conductive layer, and then using a second phototool to form a second printed circuit in the conductive layer whereby the first and second printed circuits are interconnected by the conductive vias.

2. A method, as in Claim 1, including removing the remainder of the exposed photoresist layer after the ablation of those portions of the second dielectric substrate exposed by the via holes in the conductive layer.

3. A method, as in Claim 1 or 2, including covering the conductive layer with a second layer of photoresist after the formation of the conductive vias, providing the second phototool with an alignment sight and the profile of the second printed circuit, arranging for the position of the alignment sight of the second phototool relative to the location of the profile of the second printed circuit to be such that the profile of the second printed circuit will be accurately positioned relative to the first printed circuit when the alignment sight of the second phototool is aligned with the alignment target on the first dielectric substrate, placing the second phototool over the second photoresist layer and adjusting the orientation of the second phototool relative to the conductive layer until the alignment sight of the second phototool is accurately aligned with the alignment target on the first dielectric substrate, exposing the second layer of photoresist through the second phototool whilst the alignment sight of the second phototool is accurately aligned with the alignment target on the first dielectric substrate, processing the exposed second layer of photoresist to uncover those portions of the conductive layer which need to be retained to define the second printed circuit, protecting the portions of the conductive layer that will define the second printed circuit against etching, then removing the remainder of the exposed second layer of photoresist and etching away the conducting layer to leave only the protected portions.

4. A method, as in Claim 1 or 2, including providing the first phototool with marking corresponding to the negative of an image of a second alignment target, arranging for the position of the marking to produce the second alignment target in the conductive layer in a location spaced from the first alignment target on the first dielectric substrate, covering the conductive layer with a second layer of photoresist after the formation of the conductive vias, providing the second phototool with an alignment sight and the profile of the second printed circuit, arranging for the position of the second alignment target relative to the via holes and the position of the alignment sight of the second phototool relative to the location of the profile of the second printed circuit to be such that the second printed circuit will be accurately positioned relative to the conductive vias when the alignment sight of the second phototool is aligned with the second alignment target, placing the second phototool over the second photoresist layer and adjusting the orientation of the second phototool relative to the conductive layer until the alignment sight of the second phototool is accurately aligned with the second alignment target, exposing the second layer of photoresist through the second phototool whilst the alignment sight of the second phototool is accurately aligned with the second alignment target, processing the exposed second layer of photoresist to uncover those portions of the conductive layer which need to be retained to define the second printed circuit, protecting the portions of the conductive layer that will define the second printed circuit against etching, then removing the remainder of the exposed second layer of photoresist and etching away the conducting layer to leave only the protected portions.

5. A method, as in Claim 3, including additionally providing the second phototool with a second alignment sight, arranging for the position of the second alignment sight relative to the location of the profile of the second printed circuit to be such that the second printed circuit will be accurately positioned relative to the first printed circuit when the second alignment sight on the second phototool is aligned with the first alignment target on the first dielectric substrate.

6. A method, as in any preceding claim, including forming an aperture through the second dielectric substrate and the conductive layer in a position overlying the alignment target, and optically aligning the alignment sight of the first phototool with the alignment target on the first dielectric substrate.

7. A method, as in Claim 6, including forming the aperture through the conductive layer before lamination of the second dielectric substrate and the conductive layer to the first dielectric substrate.

8. A method, as in Claim 7, including forming the aperture through the conductive layer before lamination to the second dielectric substrate and extending the aperture through the second dielectric substrate by ablating the portion of the second dielectric substrate exposed by the aperture.

9. A method, as in Claim 6, including laminating the conductive layer and the second dielectric substrate prior to their lamination with the first dielectric substrate, forming the aperture through the laminated conductive layer and the second dielectric substrate, positioning the aperture over the alignment target on the first dielectric substrate, and then laminating the first and second dielectric substrates.

10. A method, as in any preceding claim, including forming each target as at least two spaced target portions, forming each sight as a corresponding number of identically spaced sight portions, and performing the alignment by accurately aligning each sight portion with its corresponding target portion.

11. A method, as in any preceding claim, including aligning a feature of each sight or sight portion, of substantially the same cross section as the via holes to be formed, within a larger feature of each target or each target portion corresponding substantially with the width of the narrowest feature of the second printed circuit in which a via hole is to be formed.

12. A method, as in any preceding claim, including repeating the claimed steps to produce a printed circuit board having at least three printed circuits separated by respective dielectric substrates.

13. A method, as in Claim 12, including spacing the alignment target or target portions for each substrate whereby the completed circuit board will bear a series of used alignment targets or target portions confirming the completion of each of the manufacturing steps.

14. A method of manufacturing a multi-layer printed circuit board substantially as described herein with reference to the accompanying drawings.

15. A multi-layer printed circuit board produced by the method of any preceding claims.

16. A pair of phototools, for use in the method of any preceding claim, the first defining an alignment sight and the profiles of via holes, the second defining an alignment sight and the profile of a printed circuit, and the positions of the respective sights are such that, when both are aligned, the via holes will be correctly aligned with the printed circuit.

17. A pair of phototools, according to Claim 16, in which each alignment sight comprises at least two spaced sight portions.

18. A pair of phototools, as in Claim 16, in which the first phototool also bears a marking corresponding to the negative of an alignment target, the second phototool also bears a second alignment sight, and the positions of the marking and the second alignment sight are such that, when the second alignment sight is aligned with an alignment target produced by the marking, the via holes will be correctly aligned with the printed circuit.

19. A pair of phototools, according to Claim 18, in which the marking comprises at least two spaced markings corresponding to the negatives of two similarly spaced alignment targets, and the second alignment sight comprises a corresponding number of similarly spaced sight portions.

20. A pair of phototools, according to Claim 18 or 19, in which each marking includes a feature corresponding substantially with the width of the narrowest feature of the printed circuit in which a via hole is to be formed.

21. A pair of phototools, according to any of Claims 16 to 20, in which each alignment sight or sight portion includes a feature of substantially the same cross-section as the profiles of the via holes.

22. A pair of phototools substantially as described herein with reference to the accompanying drawings.