JP2002507365A - 高度統合イーサネット・ネットワーク要素 - Google Patents
高度統合イーサネット・ネットワーク要素Info
- Publication number
- JP2002507365A JP2002507365A JP50579299A JP50579299A JP2002507365A JP 2002507365 A JP2002507365 A JP 2002507365A JP 50579299 A JP50579299 A JP 50579299A JP 50579299 A JP50579299 A JP 50579299A JP 2002507365 A JP2002507365 A JP 2002507365A
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- Japan
- Prior art keywords
- signal
- clock
- phase
- mode
- during
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/323—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/40—Network security protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
- H04L49/352—Gigabit ethernet switching [GBPS]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/12—Protocol engines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.ネットワーク要素において、媒体アクセス制御(MAC)と物理層(PH Y)間の信号の通信のためのインタフェースであって、前記PHYが、 第1モードにおいてMACから信号の第1部分と第2部分を受信するように連 結され、第2のモードにおいてMACから信号の第2部分を受信するように連結 された第1グループの入力ポートと、 第2モードにおいてMACから信号の第1部分を受信するように連結された第 2グループの入力ポートと、 クロック信号の第1位相中に第1グループの入力ポートを介してMACから信 号の第1部分を受信するように連結された第1レジスタと、 第1モードにおいて第1レジスタから信号の第1部分を受信するように連結さ れ、クロック信号の第2位相中に第2グループの入力ポートを介してMACから 信号の第1部分を受信するように連結された第1マルチプレクサと、 第1グループの入力ポートを介して信号の第2部分を受信するように連結され 、さらにクロック信号の第2位相中に第1マルチプレクサによって出力される信 号の第1部分を受信するように連結された第2レジスタとを備えるインタフェー ス。 2.第1モードで動作する場合に、前記MACがクロック信号の第1位相中に 信号の第1部分を多重化し、クロック信号の第2位相中に信号の第2部分を多重 化するための第2マルチプレクサを備える請求項1に記載のネットワーク要素。 3.PHYが第2モードで動作する場合に、前記MACがクロック信号の第2 位相中に信号の第1部分を第2グループの入力ポートに出力し、信号の第2部分 を第1グループの入力ポートに出力する請求項1に記載のネットワーク要素。 4.ネットワーク要素において、媒体アクセス制御(MAC)と物理層(PH Y)間の信号の通信のためのインタフェースであって、前記PHYが、 第1モードにおいてMACに信号の第1部分と第2部分を送信するように連結 され、第2のモードにおいてMACから信号の第2部分を送信するように連結さ れた第1グループの入力ポートと、 第2モードにおいてクロックの第2位相中にMACに信号の第2部分を送信す るように連結された第2グループの入力ポートと、 第1モードにおいて信号の第1部分を受信するように連結され、さらに第1モ ードにおいてクロックの第1位相中に信号の第1部分を出力するように連結され 、第1モードにおいて信号の第2部分を出力するように連結され、さらに第1モ ードにおいてクロックの第2位相中に信号の第2部分を出力するように連結され た第1マルチプレクサとを備えたインタフェース。 5.前記MACが、 第1モードにおいてクロック・サイクルの第1位相中に信号の第1部分を受信 し、クロック・サイクルの第2位相中に第2部分を受信するように連結され、第 2モードにおいてクロック・サイクルの第2位相中に信号の第1部分を受信する ように連結された第1グループの入力ポートと、 第2モードにおいてクロック・サイクルの第1位相中に信号の第2部分を受信 するように連結された第2グループの入力ポートと、 クロックの第1位相中に第1グループの入力ポートから信号の第1部分を受信 し、クロックの第2位相中に信号の第1部分を出力するように連結され、さらに 第2モードにおいてクロックの第2位相中に1グループの入力ポートから信号の 第1部分を受信し、クロックの第2位相中に第2グループの入力ポートから信号 の第2部分を受信するように連結された第1レジスタとを備えた請求項4に記載 のネットワーク要素。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/884,971 US6044087A (en) | 1997-06-30 | 1997-06-30 | Interface for a highly integrated ethernet network element |
US08/884,971 | 1997-06-30 | ||
PCT/US1998/013362 WO1999001007A1 (en) | 1997-06-30 | 1998-06-25 | Interface for a highly integrated ethernet network element |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2002507365A true JP2002507365A (ja) | 2002-03-05 |
JP3827332B2 JP3827332B2 (ja) | 2006-09-27 |
Family
ID=25385846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50579299A Expired - Lifetime JP3827332B2 (ja) | 1997-06-30 | 1998-06-25 | 高度統合イーサネット・ネットワーク要素 |
Country Status (5)
Country | Link |
---|---|
US (2) | US6044087A (ja) |
EP (2) | EP0995333B1 (ja) |
JP (1) | JP3827332B2 (ja) |
DE (2) | DE69823201T2 (ja) |
WO (1) | WO1999001007A1 (ja) |
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- 1998-06-25 JP JP50579299A patent/JP3827332B2/ja not_active Expired - Lifetime
- 1998-06-25 WO PCT/US1998/013362 patent/WO1999001007A1/en active IP Right Grant
- 1998-06-25 EP EP04008787A patent/EP1443723B1/en not_active Expired - Lifetime
- 1998-06-25 DE DE69823201T patent/DE69823201T2/de not_active Expired - Lifetime
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DE69833708D1 (de) | 2006-05-04 |
EP1443723A1 (en) | 2004-08-04 |
EP1443723B1 (en) | 2006-03-08 |
DE69833708T2 (de) | 2006-08-24 |
US6044087A (en) | 2000-03-28 |
WO1999001007A1 (en) | 1999-01-07 |
JP3827332B2 (ja) | 2006-09-27 |
US6061362A (en) | 2000-05-09 |
EP0995333A4 (en) | 2001-09-05 |
DE69823201D1 (de) | 2004-05-19 |
DE69823201T2 (de) | 2005-04-21 |
EP0995333B1 (en) | 2004-04-14 |
EP0995333A1 (en) | 2000-04-26 |
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