WO2006114032A1 - Appareil de multiplexage, de demultiplexage et de multiplexage serie dans la couche physique du reseau ethernet et son procede - Google Patents

Appareil de multiplexage, de demultiplexage et de multiplexage serie dans la couche physique du reseau ethernet et son procede Download PDF

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Publication number
WO2006114032A1
WO2006114032A1 PCT/CN2005/001985 CN2005001985W WO2006114032A1 WO 2006114032 A1 WO2006114032 A1 WO 2006114032A1 CN 2005001985 W CN2005001985 W CN 2005001985W WO 2006114032 A1 WO2006114032 A1 WO 2006114032A1
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Prior art keywords
signal
port
multiplexing
physical layer
layer
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PCT/CN2005/001985
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English (en)
Chinese (zh)
Inventor
Yang Yu
Wei Wang
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Hangzhou H3C Technologies Co., Ltd.
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Priority claimed from CNB200510066285XA external-priority patent/CN100496001C/zh
Application filed by Hangzhou H3C Technologies Co., Ltd. filed Critical Hangzhou H3C Technologies Co., Ltd.
Publication of WO2006114032A1 publication Critical patent/WO2006114032A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/4013—Management of data rate on the bus
    • H04L12/40136—Nodes adapting their rate to the physical link properties

Definitions

  • the present invention relates to Ethernet physical layer information processing, and in particular, to an Ethernet physical layer multiplexing, demultiplexing, multiplexing and demultiplexing apparatus and method, and an Ethernet physical layer multiplexing cascade apparatus and method. Background technique
  • the specifications of the physical layer access chips on the market today are 10/100M adaptive, GE (Gigabit Ethernet, Gigabit Ethernet), and 10GE.
  • the main function of this type of chip is to complete the physical layer codec, analog-to-digital conversion, clock recovery, and analog amplification, etc., to convert the physical layer signal into the MAC layer signal.
  • the internal structure block diagram of the chip is as shown in FIG. 2 below, including: 8 analog interface units 21, 8 analog/digital conversion units 22, 8 clock and code decoding units 23, 8 MAC layer interface processing units 24, and 8 digital interface units 25, physical layer signals enter the physical layer multiplexing/demultiplexing chip from the analog interface 21, and the analog signals are converted into digital signals by the analog/digital conversion unit 22, and pass through the clock and encoding/decoding unit. 23 performing clock extraction and decoding processing, extracting data information and a clock signal of the MAC layer from the encoded signal of the physical layer, and then converting the decoded signal into a MAC layer signal format of the same specification through the MAC layer interface processing unit 24, Finally, it is sent to the MAC layer through the digital interface unit 25.
  • the number of the analog interface unit 21 of the physical layer and the number of the digital interface unit 25 of the MAC layer is corresponding, and the internal principle block diagram is divided into eight paths.
  • the flow from the digital interface of the MAC layer to the analog interface of the physical layer is exactly the opposite of the flow from the analog interface of the physical layer to the digital interface of the MAC layer.
  • the digital signal of the MAC layer enters the Ethernet physical layer chip from the digital interface unit 25, after
  • the MAC layer interface processing unit 24 obtains the physical layer signal format of different specifications required by each physical port, encodes it by the clock and encoding/decoding unit 23, and converts it into an analog signal through the analog/digital conversion unit 22, and finally passes through the analog interface unit. 21 is sent to the physical layer.
  • broadband access is a technology development trend.
  • the average bandwidth per user access is relatively low, such as 10M.
  • the access bandwidth can meet more than 80% of broadband access applications.
  • the MAC layer chip used in the current Ethernet products is biased toward the enterprise network market, and the access speed of each port is 100M or 1G/10G.
  • the MAC layer chip and the above physical layer chip are applied to the broadband access, Each user needs a corresponding port, which results in a large amount of bandwidth waste.
  • the uplink interface of the physical layer chip is a digital interface, it can only be connected to the MAC layer chip, and cannot support the downlink interface of another physical layer chip.
  • the uplink interface of the physical layer chip is a digital interface, it cannot be directly connected to the downlink physical analog interface of the 100 Mbps physical layer chip. Therefore, it is desirable to be able to provide an apparatus and method for implementing physical layer multiplexing cascades. Summary of the invention
  • the problem to be solved by the present invention is to provide an Ethernet physical layer multiplexing and demultiplexing apparatus and method, which solves the disadvantages of a MAC layer port corresponding to only one physical layer port in the prior art.
  • Another technical problem to be solved by the present invention is to provide a device for implementing Ethernet physical layer multiplexing cascade to overcome the disadvantages that the physical layer chips of different rates cannot be cascaded in the prior art, and simplify the rack.
  • Line card design for devices is to provide a device for implementing Ethernet physical layer multiplexing cascade to overcome the disadvantages that the physical layer chips of different rates cannot be cascaded in the prior art, and simplify the rack.
  • Another technical problem to be solved by the present invention is to provide a method for implementing Ethernet physical layer multiplexing cascade, and the physical layer multiplexing technology and the multiplexing cascade technology are better applied in the broadband access field, and the MAC layer is reduced. Number of chip ports, low network access costs.
  • an Ethernet physical layer multiplexing device which includes:
  • the conversion unit receives one or more physical layer low speed signals, and converts each low speed signal into a MAC layer low speed signal;
  • the signal multiplexing unit receives a MAC layer low-speed signal output by the physical layer signal conversion unit, and sets a port flag for each low-speed signal, and complexes the multi-channel low-speed signal with the port flag set by time division Use to output a MAC layer high speed signal.
  • the signal multiplexing unit further includes: a port tag setting subunit, a port tag a storage subunit and a first random storage subunit,
  • the port tag setting subunit is configured to set a port flag for each low speed signal;
  • the port tag storage subunit is configured to store a port tag set by each low speed signal;
  • the first random storage sub-unit is configured to store a low-speed signal for setting a port flag in units of time slots, and to read a MAC layer high-speed signal driven by the high-speed clock signal.
  • the port flag is set according to an input physical port of the signal multiplexing unit or according to a service characteristic of the input low speed signal.
  • the port flag is set by the data frame of the low speed signal or by the fixed data length of the low speed signal.
  • the high speed clock signal is obtained by multiplying a low speed clock extracted from a low speed signal or directly by a clock generating circuit.
  • the present invention also provides an Ethernet physical layer demultiplexing apparatus, including: a demultiplexing unit, receiving a MAC layer high speed signal, demultiplexing into a low speed signal, and determining a downlink sending port according to a port flag in the low speed signal;
  • the MAC layer signal conversion unit receives the low speed signal sent by the demultiplexing unit, converts the signal into a physical layer signal, and sends the signal to the physical layer.
  • the demultiplexing unit further includes: a port tag determining subunit and a second random storing subunit;
  • the port tag determining subunit determines a downlink signal port according to a port flag in the received high speed signal
  • the second random storage sub-unit is configured to store a high-speed signal, and at least two idle signals are read by driving of the low-speed clock signal, and sent to a corresponding downlink signal port in the signal conversion unit of the MAC layer.
  • the low speed clock signal is derived from a low speed clock extracted from a low speed signal sent from the physical layer, or directly from a clock generation circuit.
  • the present invention also provides an Ethernet physical layer multiplexing and demultiplexing apparatus, comprising: a physical layer signal and a MAC layer signal mutual conversion unit, and a signal multiplexing demultiplexing unit;
  • the conversion unit receives one or more physical layer low speed signals, and converts each low speed signal into a MAC layer low speed signal;
  • the MAC layer signal conversion unit receives the multiplexing demultiplexing unit The low-speed signal sent, converts the signal into a physical layer signal, and sends it to the physical layer;
  • the signal multiplexing demultiplexing unit receives the MAC layer low speed signal output by the physical layer signal and the MAC layer signal mutual conversion unit, and sets a port flag for each low speed signal, and sets the multi-channel low speed signal with the port flag set by time. Multiplexing mode multiplexing output The MAC layer high-speed signal; and receives the MAC layer high-speed signal, demultiplexes into a low-speed signal, and determines the downlink transmission port according to the port flag in the low-speed signal.
  • the present invention provides an Ethernet physical layer multiplexing method, including:
  • the port is marked with the low rate MAC signal, and the port tag is stored;
  • Step C further includes:
  • the MAC layer signal low speed signal for setting the port flag is stored in units of time slots; and the high speed signal of the MAC layer is read by the high speed clock signal.
  • the present invention provides an Ethernet physical layer demultiplexing method, including:
  • the present invention provides an Ethernet physical layer multiplexing demultiplexing method, including: in an uplink direction,
  • the low speed signal is output from the corresponding lower port.
  • the present invention further provides an apparatus for implementing Ethernet physical layer multiplexing cascade, comprising at least two physical layer multiplexing chips, wherein an uplink digital interface of the uppermost physical layer multiplexing chip and a medium access control layer chip interface Connected, the downlink analog interface of the lower layer physical layer multiplexing chip is connected to the user end, and further includes:
  • a digital-to-analog conversion module corresponding to each lower physical layer multiplexing chip, respectively
  • the uplink digital interface of the layer physical layer multiplexing chip and the downlink analog interface of the upper physical layer multiplexing chip are connected, and are used for converting the high-speed digital signal outputted by the lower layer physical layer multiplexing chip uplink digital interface into an analog signal, and The low-speed analog signal outputted by the upper layer physical layer multiplexing chip downlink analog interface is converted into a digital signal.
  • the digital/analog conversion module includes:
  • a signal conversion circuit configured to perform conversion of the upper layer high speed digital signal to an analog signal, and conversion of the lower layer low speed analog signal to the digital signal;
  • a clock circuit coupled to the signal conversion circuit for providing a clock signal required for signal conversion
  • An encoding/decoding circuit is coupled to the signal conversion circuit for providing encoding and decoding required for signal conversion.
  • the clock circuit and the encoding/decoding circuit are provided by the lower physical layer multiplexing chip.
  • the digital/analog conversion module is integrated on a lower physical layer multiplexing chip corresponding thereto.
  • the digital/analog conversion module and all the cascaded physical layer multiplexing chips are integrated on the same chip.
  • the present invention also provides a method for implementing Ethernet physical layer multiplexing cascade, which is used for cascading two or more levels of physical layer multiplexing chips, wherein the upper layer of the physical layer multiplexing chip uplink digital interface and media The access control layer chip interface is connected, and the downlink analog interface of the lower layer physical layer multiplexing chip is connected to the user end, and the method includes the following steps:
  • A When receiving an uplink signal, record a correspondence between the uplink signal and a physical port;
  • the physical port to which the downlink signal should be distributed is searched according to the corresponding relationship between the recorded uplink signal and the physical port, and the downlink signal is sent to the physical port;
  • step A specifically includes:
  • the global physical port number is directly configured on the physical port of the lower layer physical layer multiplexing chip.
  • step A specifically includes:
  • the uplink signal is marked with an offset flag corresponding to the private physical port number according to the private physical port number;
  • step A2 ′ is specifically:
  • the offset flag is added before the frame header of the upstream data frame.
  • the step C includes:
  • the invention also provides an Ethernet multiplexing cascade device, comprising:
  • a lower layer multiplexing device for multiplexing at least two low-speed analog signals from a user upstream direction into a high-speed digital signal, and recording a first-layer VLAN tag; and demultiplexing the high-speed digital signal in a downlink direction A low-speed analog signal, and selecting a downlink port according to the first layer VLAN tag;
  • a signal conversion device having a digital interface coupled to the lower layer multiplexing device
  • An upper multiplexing device coupled to the analog interface of the signal conversion device for multiplexing at least two high-speed analog signals from the upstream direction into higher-speed digital signals and recording corresponding second-layer VLAN tags; Downstream direction demultiplexes the higher speed digital signal into a high speed analog signal; selects the downstream port according to the above second layer VLAN tag.
  • the present invention also provides an Ethernet multiplexing cascade device for connecting a plurality of users to a network, including an upper layer multiplexing device and a lower layer multiplexing device, wherein the upper layer multiplexing device decomposes the downlink signal and ranks first in the signal.
  • the layer VLAN tag finds the correct downlink port; and the lower layer multiplexing device decomposes the downlink signal from the upper layer multiplexing device and finds the correct downlink port according to the second layer VLAN tag in the signal so that the signal arrives at the user.
  • the present invention has the following advantages:
  • the device of the invention adds signal multiplexing, demultiplexing or the existing physical layer chip
  • the multiplexing and demultiplexing unit reaches one or a few high-speed uplink interfaces, and corresponds to multiple low-rate downlink physical interfaces.
  • the method of the present invention is to input multiple low-rate physical ports in the uplink direction and multiplex them to a high rate by multiplexing the input of multiple physical layers.
  • the MAC layer corresponds to the interface, and the multiplexing flag is marked during multiplexing, and source port learning is performed.
  • the service from the high-speed MAC layer to the upper interface is sent to the corresponding downlink physical port through tag search, and the demultiplexing function is completed.
  • one or a few high-speed uplink interfaces are achieved, corresponding to the goals of multiple low-rate downlink physical interfaces.
  • the present invention is directed to the characteristics of an Ethernet physical layer multiplexing chip, and a digital/analog conversion module is added between the digital interface of the lower physical layer multiplexing chip and the analog interface of the upper physical layer multiplexing chip to implement a multi-layer physical layer complex.
  • a digital/analog conversion module is added between the digital interface of the lower physical layer multiplexing chip and the analog interface of the upper physical layer multiplexing chip to implement a multi-layer physical layer complex.
  • a high-density 10GE forwarding chip is a technology development trend. If such a high-performance multi-port 10GE forwarding chip is used as a forwarding engine for a rack-mounted device, the present invention provides a high-density low-speed.
  • the interface board multiplexes multiple FE/GE physical layer interfaces to a higher-speed MAC layer interface, which greatly saves equipment line card costs.
  • FIG. 1 is a view of a prior art Ethernet physical layer multiplexing demultiplexing chip
  • FIG. 2 is an internal structural diagram of an Ethernet physical layer multiplexing demultiplexing chip of FIG. 1;
  • FIG. 3 is a structural diagram of an Ethernet physical layer multiplexing device of the present invention.
  • FIG 4 is an internal structural diagram of the signal multiplexing unit of Figure 3;
  • FIG. 5 is a structural diagram of an Ethernet physical layer demultiplexing apparatus of the present invention.
  • Figure 6 is a diagram showing the internal structure of the signal demultiplexing unit of Figure 5;
  • FIG. 7 is a structural diagram of an Ethernet physical layer multiplexing demultiplexing apparatus of the present invention.
  • FIG. 8 is an internal structural diagram of a signal multiplexing demultiplexing unit in FIG.
  • FIG. 9 is a flowchart of a method for multiplexing an Ethernet physical layer
  • Figure 10 is a flow chart of the Ethernet physical layer demultiplexing method.
  • FIG. 11 is a structural block diagram of an apparatus for implementing Ethernet physical layer multiplexing cascade according to the present invention
  • FIG. 12 is a structural block diagram of a digital/analog conversion module in an apparatus for implementing Ethernet physical layer multiplexing cascade according to the present invention
  • FIG. 15 is a flowchart of implementing a second embodiment of a method for implementing Ethernet physical layer multiplexing cascade according to the present invention. detailed description
  • the Ethernet physical layer multiplexing device of the present invention includes a physical layer signal conversion unit 31, a signal multiplexing unit 32, and a digital interface unit 33.
  • the physical layer signal conversion unit 31 receives one or more physical layer low-speed signals, and converts each physical layer low-speed signal into a corresponding MAC layer low-speed signal by performing analog-to-digital conversion, clock extraction, decoding, and MAC interface processing on each signal.
  • the signal multiplexing unit 32 receives the MAC layer low-speed signal output by the physical layer signal conversion unit 31, and sets a port flag for each MAC layer low-speed signal, and divides the multi-channel low-speed signal with the port flag set by time division multiplexing.
  • the mode is multiplexed into a MAC layer high speed signal, which is sent to the MAC layer through the digital interface unit 33.
  • the internal structure of the signal multiplexing unit 32 is as shown in FIG. 4, and includes: a port label setting subunit 321, a port label storage subunit 322, and a first random storage subunit 323.
  • the port tag setting sub-unit 321 is configured to set a port flag for each MAC layer low-speed signal;
  • the port tag storage sub-unit 322 is configured to store a port flag set for each low-speed signal;
  • the first random storage sub-unit 323 It is used to store a MAC layer low speed signal for setting a port flag in units of time slots, and to read a MAC layer high speed signal driven by a high speed clock signal.
  • the high speed clock signal can be obtained by multiplying the low speed clock extracted from the low layer signal of the physical layer, or directly by the clock generating circuit.
  • the port tag is set by the input physical port of the signal multiplexing unit 32 or according to the traffic characteristics of the input low speed signal.
  • the port tag setting sub-unit 321 in the signal multiplexing unit 32 first sets and inputs the physical basis according to the configuration.
  • the input port tag can be a private tag set according to the input physical port, or a VLAN tag that enters an Ethernet data frame, a VPN tag, or any available tag at the head of the data frame.
  • the port tag storage sub-unit 322 then stores the port tag, establishing a correspondence between the tag and the physical port.
  • the input data frame does not carry the VLAN tag, set the pre-configured VLAN tag according to the corresponding input physical port, and remember which downlink physical ingress port the VLAN tag belongs to. .
  • VLAN tagging if the input data frame itself already carries a VLAN Label, then you can replace the original VLAN tag according to the configuration, or set a VLAN tag in front of the existing tag; you can also recognize the VLAN tag carried by itself.
  • the eight physical layer low-speed signals are FE signals, both of which are 100M, and the MAC layer high-speed signal is one GE.
  • the marked data frame is transmitted from the GE port in time division multiplexing mode, since one GE port can transmit data frames of 10 FE ports, the data frames of the eight FE ports can be sent from one GE port.
  • the port flag can also be set according to the fixed data length of the low speed signal. Just mark it before each fixed length. For example, a 1500-byte Ethernet data frame is normally set to an input physical port mark in front of the entire data frame, but it can also be a fixed length, such as one mark per 500 bytes divided from a physical port three times.
  • Sending to the upstream multiplexed port has the advantage of reducing the storage pressure of the multiplexing and demultiplexing module, but many long data frames are broken down into multiple blocks, so the port tag needs to be able to represent the order of each block.
  • the subsequent corresponding MAC layer processing also needs to support the reorganization of the data frame.
  • the present invention is not limited thereto. It can be a multi-path physical layer low-speed signal multiplexed into one MAC layer high-speed signal, or multiple multi-channel low-speed signals multiplexed into several high-speed signals, thereby realizing one or a few high-speed pairs.
  • the upper interface corresponds to multiple low-speed downlink physical interfaces.
  • the Ethernet physical layer demultiplexing apparatus of the present invention comprises: a MAC layer signal converting unit 41, a signal demultiplexing unit 42 and a digital interface unit 43, and the signal demultiplexing unit 42 receives the MAC layer from the digital interface unit 43 through the digital interface unit 43.
  • a high-speed signal the signal demultiplexing unit 42 demultiplexes the MAC layer high-speed signal into a MAC layer low-speed signal, and determines a downlink transmission port according to the port identifier in the low-speed signal
  • the MAC layer signal conversion unit 41 receives the The low speed signal sent from the demultiplexing unit 42 converts the signal into a physical layer signal and transmits it to the physical layer.
  • the signal demultiplexing unit 42 further includes: a port tag determining subunit 421 and a second random storing subunit 423; the second random storing subunit 423 is configured to store From the MAC layer high speed signal from the digital interface unit 43, the port flag determining subunit 421 receives the port flag in the high speed signal, and determines the downlink signal port by looking up the information in the port tag storage subunit 322; and passes the low speed
  • the driving of the clock signal reads out at least two idle signals and sends them to corresponding downlink signal ports in the MAC layer signal converting unit 41.
  • the low speed clock signal is derived from a low speed clock extracted from a low speed signal sent from the physical layer, or directly from a clock generation circuit.
  • the downlink port is determined to be sent from the corresponding downlink physical port.
  • the port tag For example, according to the VLAN tag of the incoming data frame of the uplink port, after finding the corresponding sending port, the VLAN tag can be carried or the VLAN tag can be removed.
  • the physical layer demultiplexing device corresponding to the above-mentioned 8-port physical layer multiplexing device, the MAC layer high-speed data frame from the GE port must carry the port tag, that is, the specific value of the VLAN must be carried.
  • the private tag is removed, and the internal private VLAN value is removed, and then sent out from the corresponding physical port.
  • the demultiplexing process from one GE port to eight FE ports is completed.
  • an Ethernet physical layer multiplexing and demultiplexing device can be formed, which is demultiplexed by multiplexing between two physical layer low speed signals and one MAC layer high speed signal.
  • the method includes: an analog interface unit 61, an analog-to-digital conversion unit 62, a digital-to-analog conversion unit 63, a decoding unit 64, an encoding unit 65, a MAC interface processing unit 66, and a signal multiplexing demultiplexing unit 67.
  • a digital interface unit 68 in the uplink direction, the two physical layer low speed signals respectively pass through the analog interface unit
  • the signal multiplexing demultiplexing unit 67 receives the MAC layer low speed signal, and sets a port flag of the MAC layer low speed signal, and multiplexes two MAC layer low speed signals into one MAC layer in a time division multiplexing manner.
  • the high speed signal is finally sent by the digital interface unit 68 to the MAC layer.
  • the signal multiplexing and demultiplexing unit 67 receives the high-speed signal from one MAC layer through the digital interface unit 68, demultiplexes it into two MAC layer low-speed signals, and determines the sending port according to the port identifier;
  • the MAC interface processing unit 66, the encoding unit 65, the digital to analog conversion unit 63, and the analog interface unit 61 are sent to the object The management layer.
  • the internal structure of the signal multiplexing demultiplexing unit is as shown in FIG. 8, and includes a port tag setting subunit 671, a first random storage subunit 672, a port tag storage subunit 673, a port tag judging subunit 674, and a second random number.
  • a storage subunit 675 the port tag setting subunit 671 is configured to set a port flag for each low speed signal; the port tag storage subunit 673 is configured to store a port flag set for each low speed signal; the first random storage The sub-unit 672 is configured to store the low-speed signal of the port flag set in units of time slots, and read out a MAC layer high-speed signal by driving the high-speed clock signal.
  • the port tag determining sub-unit 674 determines a downlink signal port according to the port flag in the received high-speed signal and by searching for information in the port tag storage sub-unit 673; the second random storage sub-unit 675 is configured to store a high-speed signal At least two low-speed signals are read by driving of the low-speed clock signal, and sent to the corresponding downlink signal end ⁇ in the MAC layer signal conversion unit.
  • the analog interface unit 61, the analog-to-digital conversion unit 62, the digital-to-analog conversion unit 63, the decoding unit 64, the encoding unit 65, the MAC interface processing unit 66, and the signal multiplexing demultiplexing unit 67 constitute a physical layer signal and a MAC layer.
  • the signal conversion unit may also be an integrated body of the physical layer signal conversion unit and the MAC layer signal conversion unit in the above embodiment.
  • the analog input port, the digital-to-analog conversion unit, the code decoding unit, and the MAC layer data processing unit in the Ethernet physical layer multiplexing demultiplexing device of the present invention correspond to, wherein the digital-to-analog conversion circuit and the analog-to-digital conversion circuit can be integrated.
  • the unit may be a separate unit; the decoding unit and the coding unit may be integrated or may be a separate unit; the signal multiplexing unit and the signal demultiplexing unit may be integrated or may be separate units.
  • An Ethernet physical layer multiplexing method of the present invention includes: sl01, converting at least two low-rate physical layer signals into corresponding low-rate MAC layer signals;
  • Sl03 stores the MAC layer signal low-speed signal of the port flag in the slot unit; sl04, and reads the MAC layer high-speed signal with the high-speed clock signal.
  • An Ethernet physical layer demultiplexing method of the present invention includes: s201, receiving a high-speed signal of a MAC layer;
  • An Ethernet physical layer multiplexing demultiplexing method of the present invention includes:
  • the low speed signal is output from the corresponding downstream port.
  • the present invention is directed to the characteristics of the Ethernet physical layer multiplexing chip, and further increases the digital/analog conversion module between the digital interface of the lower physical layer multiplexing chip and the analog interface of the upper physical layer multiplexing chip, which will be further
  • the digital signal outputted after being converted into an analog signal is output to an analog interface of the upper physical layer multiplexing chip, and the downlink interface of the upper physical layer multiplexing chip supports receiving and processing data frames with a private physical port path, and
  • the learning and forwarding functions based on physical port paths enable the cascading of multiple layers of physical layer multiplexing chips.
  • the added digital/analog conversion module is integrated on the lower physical layer multiplexing chip, so that the lower physical layer multiplexing chip provides an uplink digital interface and an uplink analog interface.
  • the multiplexed chip is used alone, the digital interface is directly connected to the MAC layer chip, and when the cascading application is used, the analog interface is used to interface with the downstream analog interface of the upper chip.
  • the present invention further increases a digital/analog conversion module between the digital interface of the lower physical layer multiplexing chip and the analog interface of the upper physical layer multiplexing chip, and the cascade of the two or more multiplexing chips is realized by the module.
  • FIG. 11 shows an apparatus for implementing Ethernet physical layer multiplexing cascade according to the present invention.
  • the lower physical layer multiplexing chip S11, S12 and the upper physical layer multiplexing chip S3 are common multiplexing chips of different rate grades, and the upper physical layer multiplexing chip S3 uplink digital interface and the same rate MAC layer chip S4 interface Connected, the lower physical layer multiplexing chip provides the user with an analog access port. How many analog ports of the upper physical layer multiplexing chip can provide the number of lower physical layer multiplexing chips to be connected to them.
  • Each lower physical layer multiplexing chip corresponds to a digital/analog conversion module.
  • the digital/analog conversion module S21 corresponds to the lower physical layer multiplexing chip S11
  • the digital/analog conversion modules are respectively connected to the uplink digital interface of the lower physical layer multiplexing chip and the downlink analog interface of the upper physical layer multiplexing chip, and are used for converting the high speed digital signal outputted by the lower physical layer multiplexing chip uplink digital interface into The analog signal is converted into a digital signal by the low-speed analog signal outputted by the upper layer physical layer multiplexing chip downlink analog interface.
  • the same structure as the above two-layer multiplexing cascade can also realize the cascade of multiple layers of physical layer multiplexing chips.
  • the uplink digital interface of the uppermost physical layer multiplexing chip is connected to the MAC layer chip interface, and the downlink analog interface of the lower layer physical layer multiplexing chip is connected to the user end, and the physical layer multiplexing chips of the lowermost layer and the middle layer are connected.
  • Corresponding to a digital-to-analog conversion module the conversion of the downlink physical interface of the lower physical layer multiplexing chip and the downlink analog interface signal of the upper physical layer multiplexing chip is realized.
  • the uppermost physical layer multiplexing chip supports two application modes, one is a separate application mode, that is, a non-cascading physical layer multiplexing chip mode, in which case the physical port number of the multiplexing chip according to the data frame Put the corresponding private physical layer multiplexed port tag.
  • the other is a cascade application mode, in which the multiplex chip recognizes the mark of the lower multiplex chip, and adds an offset mark to the original mark according to the port of the input signal to correctly identify the transmission of the input signal. path.
  • the digital interface of the signal conversion circuit 41 is connected to the digital interface of the lower physical layer multiplexing chip, and the analog interface is connected to the analog interface of the upper physical layer multiplexing chip for completing the conversion of the relatively high speed digital signal from the upper layer to the analog signal. And the conversion of relatively low-speed analog signals from the lower layer to digital signals.
  • the clock circuit 42 and the encoding/decoding circuit 43 respectively connected to the signal conversion circuit 41 supply the signal conversion circuit 41 with the clock signal and codec required for signal conversion, respectively.
  • the common physical layer multiplexing chip includes a clock and a codec processing circuit. Therefore, the clock circuit and the encoding/decoding circuit required by the digital-to-analog conversion module can also be multiplexed by the corresponding lower physical layer.
  • the chip is available.
  • the digital/analog conversion module can also be integrated on the corresponding lower physical layer multiplexing chip, so that the multiplexing chip simultaneously provides a digital interface and an analog interface.
  • the chip is used alone, the digital interface is directly connected to the MAC layer chip; in the cascade application, the analog interface is used to interface with the downlink analog interface of the upper chip.
  • all the cascaded chips and the digital/analog conversion modules required for the cascade can be simultaneously integrated on the same chip to meet the access requirements of the low-end users, while reducing the number of ports of the chip used by the MAC layer. , reduce the cost of broadband access.
  • this multiplexer can be applied to the local office or to the user.
  • the cascading method of multiplexing 10 Mbps signals into 10GE signals as shown in Figure 13: Multiplex cascading 8 x 8 x 8 10 Mbps physical port signals into one 10GE signal.
  • a GE multiplex chip directly cascades eight 100 Mbps multiplexed chips, and each 100 Mbps multiplex chip directly cascades eight 10 Mbps multiplexed chips, so that 8 x 8 x 8 10 Mbps interfaces can be directly output.
  • the line card design of the rack-mounted device can be greatly simplified, and the network access cost can be reduced.
  • FIG. 14 shows an implementation flow of a first embodiment of a method for implementing Ethernet physical layer multiplexing cascade according to the present invention:
  • step 601 the global physical port number is directly configured on the physical port of the lowermost physical layer multiplexing chip.
  • each port corresponds to a unique number, that is, global. Physical port number.
  • the port number traverses the intermediate layer and the uppermost physical layer multiplexing chip to reach the interface of the MAC layer chip, while maintaining the global uniformity of the physical port.
  • Step 602 The multiplexer receives the uplink signal, and establishes a source port path table according to the global physical port number, that is, establishes a correspondence between the uplink signal and the physical port, so that when the downlink signal is received, the downlink signal should be distributed according to the corresponding relationship. Physical port.
  • the physical layer multiplexing chip After receiving the uplink signal, the physical layer multiplexing chip performs analog-to-digital conversion on the signal, and after the clock and the codec process, the data frame with the global physical port mark is sent to the MAC layer processing interface. After processing the data frame, the MAC layer processing interface sends a data frame with a global physical port tag to the upper physical layer multiplexing chip. However, the data frame cannot be directly sent to the analog port of the upper physical layer multiplexing chip, and it needs to be converted first, and the output digital signal is converted into an analog signal. Step 603: Convert the digital signal outputted by the uplink digital interface of the lower layer physical layer multiplexing chip into an analog signal, and output it to the downlink analog interface of the upper physical layer multiplexing chip connected thereto.
  • Step 604 When the physical layer multiplexing chip receives the downlink signal, it searches for a physical port to which the downlink signal should be distributed according to the established source port path table, and sends the downlink signal to the physical port.
  • the source port path table is searched according to the global port flag information in the downlink signal, so that the downlink physical port that the signal should be distributed can be obtained, so that the data frame can be sent out from the correct downlink port through the port.
  • Step 605 Convert the analog signal outputted by the downlink analog interface of the upper layer physical layer multiplexing chip into a digital signal, and output it to the uplink digital interface of the lower physical layer multiplexing chip connected thereto.
  • FIG. 15 shows an implementation flow of a second embodiment of a method for implementing Ethernet physical layer multiplexing cascade according to the present invention:
  • a private physical port number is configured on the physical port of the physical layer multiplexing chip of each layer.
  • each layer of the multiplexed chip has eight physical ports, and each chip separately configures the eight ports, that is, each of the physical layer multiplexed chips is individually configured.
  • Physical port number For example, two 8-port 10Mbps multiplexers are labeled with a private physical port for the data frame coming in from the first physical port. Then, the data frames whose two flags are all 1 belong to the uplink interface of the two physical layer multiplexing chips, and therefore are sent to different downlink interfaces of the upper multiplexing chip.
  • the upper multiplex chip adds a layer of offset mark, for example, the data frame coming in from the first uplink interface is preceded by an offset of 10; the data frame that travels from the second one is It is preceded by an offset of 20.
  • the data frames with the lower physical port tags from the different interfaces are 1 and become physical port tags 11 and 21 respectively.
  • the upper multiplexing chip can know its corresponding downlink physical end ⁇ according to the offset flag in the data frame.
  • Step 702 When the physical layer multiplexing chip receives the uplink signal, the uplink signal is marked with an offset corresponding to the private physical port number according to the private physical port number, that is, the correspondence between the uplink signal and the physical port is established, so as to receive When the downlink signal is received, the physical port to which the downlink signal should be distributed is obtained according to the correspondence.
  • the offset label corresponding to each physical port can be the same as or different from the configured private physical port number.
  • the physical layer multiplexing chip After receiving the uplink signal, the physical layer multiplexing chip performs analog-to-digital conversion on the signal. After the clock and codec processing, the data frame with the lower offset flag is sent to the MAC layer processing interface. The MAC layer processing interface adds an offset flag corresponding to the layered physical port to the data frame. The offset flag can be added in the VLAN domain of the upstream data frame or in front of the frame header of the upstream data frame.
  • the data frame with the multi-layer offset flag is then sent to the upper physical layer multiplexed chip.
  • the data frame cannot be directly sent to the analog port of the upper physical layer multiplexing chip, and it needs to be converted first, and the output digital signal is converted into an analog signal.
  • Step 703 Establish a source port path table on each layer physical layer multiplexing chip according to the offset flag.
  • each layer of the physical layer multiplexing chip maintains its own source port path table, and each port in the source port path table in the physical layer multiplexing chip of each layer only corresponds to one layer of offset flag.
  • Step 704 Convert the digital signal outputted by the uplink digital interface of the lower layer physical layer multiplexing chip into an analog signal, and output it to the downlink analog interface of the upper physical layer multiplexing chip connected thereto.
  • Step 705 When the physical layer multiplexing chip receives the downlink signal, it searches for a physical port to which the downlink signal should be distributed according to the established source port path table, and sends the downlink signal to the physical port.
  • the multiplexed chip acquires its destination address according to the received downlink signal; queries the source port path table maintained by the multiplexed chip according to the destination address, and obtains a physical port to which the downlink signals after demultiplexing should be distributed; The interface strips the offset flag of the outermost layer of the downlink signal; and then sends the downlink signal after the offset offset flag to the corresponding physical end ⁇ .
  • Step 706 Convert the analog signal outputted by the downlink analog interface of the upper layer physical layer multiplexing chip into a digital signal, and output the digital signal to the upper digital interface of the lower physical layer multiplexing chip connected thereto.
  • the present invention performs the functions of the digital interface and the analog interface through the lower layer physical layer multiplexing chip uplink interface, and performs multiplexing layers of different rate levels in two or more layers.
  • the downlink interface of the upper physical layer multiplexing chip receives and processes the data frame with the private physical port path, and supports the learning and forwarding search function based on the physical port path, so that the data frame through the multi-layer cascade multiplexing is correct.
  • the downlink interface is sent out.
  • an Ethernet multiplexing cascade device of the present invention includes: a lower layer multiplexing device for multiplexing at least two low-speed analog signals from a user upstream direction into a high-speed digital signal, and recording a first a VLAN tag of one layer; demultiplexing the high speed digital signal into a low speed analog signal in the downlink direction, and according to the above first layer VLAN tag Selecting a downlink port; a signal conversion device having a digital interface coupled to the lower layer multiplexing device; an upper multiplexing device coupled to the analog interface of the signal conversion device for multiplexing at least two high-speed analog signals from the upstream direction Use as a higher speed digital signal and record the corresponding Layer 2 VLAN tag; Demultiplex the higher speed digital signal into a high speed analog signal in the downstream direction; Select the downstream port according to the Layer 2 VLAN tag above.
  • An Ethernet multiplexing cascade device for connecting multiple users to a network, including an upper layer multiplexing device and a lower layer multiplexing device, wherein the upper layer multiplexing device decomposes the downlink signal according to the first layer VLAN in the signal The tag finds the correct downstream port; and the lower layer multiplexing device decomposes the downstream signal from the upper multiplexing device and finds the correct downstream port according to the second layer VLAN tag in the signal so that the signal reaches the user.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

L’invention concerne un appareil de multiplexage et de démultiplexage dans la couche physique du réseau Ethernet. L’appareil de multiplexage et de démultiplexage selon l’invention comprend un module de conversion servant à convertir un signal de la couche physique et un signal de la couche MAC, et un module de multiplexage et de démultiplexage. L’invention concerne également un procédé de multiplexage et de démultiplexage d’un signal de la couche physique dans le réseau Ethernet, comprenant les étapes consistant à : convertir, sur la liaison montante, un signal de couche physique à faible débit en un signal MAC à faible débit, instaurer et mémoriser un drapeau de port, puis multiplexer le signal MAC pour obtenir un signal MAC à haut débit ; démultiplexer, sur la liaison descendante, le signal MAC à haut débit pour obtenir un signal MAC à faible débit, lire le signal MAC à faible débit et le drapeau de port à l’aide d’un signal d’horloge à faible débit, déterminer le port sur la liaison descendante en fonction du drapeau de port, et fournir un signal MAC à faible débit. L’appareil et le procédé de l’invention permettent d’associer une ou plusieurs interfaces à haut débit sur la liaison montante à des interfaces physiques à faible débit sur la liaison descendante. L’invention concerne également un appareil de multiplexage série dans la couche physique du réseau Ethernet et son procédé.
PCT/CN2005/001985 2005-04-26 2005-11-24 Appareil de multiplexage, de demultiplexage et de multiplexage serie dans la couche physique du reseau ethernet et son procede WO2006114032A1 (fr)

Applications Claiming Priority (4)

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CNB200510066285XA CN100496001C (zh) 2005-04-26 2005-04-26 以太网物理层复用和解复用装置及方法
CN200510066285.X 2005-04-26
CN200510073308.X 2005-05-31
CN200510073308 2005-05-31

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6044087A (en) * 1997-06-30 2000-03-28 Sun Microsystems, Inc. Interface for a highly integrated ethernet network element
US6373848B1 (en) * 1998-07-28 2002-04-16 International Business Machines Corporation Architecture for a multi-port adapter with a single media access control (MAC)
WO2002099979A2 (fr) * 2001-06-01 2002-12-12 Fujitsu Network Communications, Inc. Systeme et procede de multiplexage de donnees en provenance de points d'acces multiples
WO2004023731A1 (fr) * 2002-09-06 2004-03-18 Infineon Technologies Ag Port de donnees gigabit ethernet et fast ethernet configurable

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6044087A (en) * 1997-06-30 2000-03-28 Sun Microsystems, Inc. Interface for a highly integrated ethernet network element
US6373848B1 (en) * 1998-07-28 2002-04-16 International Business Machines Corporation Architecture for a multi-port adapter with a single media access control (MAC)
WO2002099979A2 (fr) * 2001-06-01 2002-12-12 Fujitsu Network Communications, Inc. Systeme et procede de multiplexage de donnees en provenance de points d'acces multiples
WO2004023731A1 (fr) * 2002-09-06 2004-03-18 Infineon Technologies Ag Port de donnees gigabit ethernet et fast ethernet configurable

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