JP2002368590A - プログラマブル遅延クロックゲート - Google Patents

プログラマブル遅延クロックゲート

Info

Publication number
JP2002368590A
JP2002368590A JP2002071930A JP2002071930A JP2002368590A JP 2002368590 A JP2002368590 A JP 2002368590A JP 2002071930 A JP2002071930 A JP 2002071930A JP 2002071930 A JP2002071930 A JP 2002071930A JP 2002368590 A JP2002368590 A JP 2002368590A
Authority
JP
Japan
Prior art keywords
clock
inverter
clock generator
dead time
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002071930A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002368590A5 (enExample
Inventor
Jeffrey C Brauch
ジェフェリー・シー・ブラウチ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2002368590A publication Critical patent/JP2002368590A/ja
Publication of JP2002368590A5 publication Critical patent/JP2002368590A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pulse Circuits (AREA)
JP2002071930A 2001-03-22 2002-03-15 プログラマブル遅延クロックゲート Pending JP2002368590A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/814554 2001-03-22
US09/814,554 US6459318B1 (en) 2001-03-22 2001-03-22 Programmable delay clock gaters

Publications (2)

Publication Number Publication Date
JP2002368590A true JP2002368590A (ja) 2002-12-20
JP2002368590A5 JP2002368590A5 (enExample) 2005-05-19

Family

ID=25215411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002071930A Pending JP2002368590A (ja) 2001-03-22 2002-03-15 プログラマブル遅延クロックゲート

Country Status (2)

Country Link
US (1) US6459318B1 (enExample)
JP (1) JP2002368590A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6809570B2 (en) * 2003-01-21 2004-10-26 Hewlett-Packard Development Company, L.P. Clock gater circuit
US20050050494A1 (en) * 2003-09-02 2005-03-03 Mcguffin Tyson R. Power estimation based on power characterizations of non-conventional circuits
CN100426172C (zh) * 2005-04-13 2008-10-15 通嘉科技股份有限公司 可调整失效时间的适应性失效时间控制器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4692637A (en) * 1985-07-08 1987-09-08 At&T Bell Laboratories CMOS logic circuit with single clock pulse
JP2574839B2 (ja) * 1988-01-20 1997-01-22 株式会社日立製作所 クロック駆動回路
US5418179A (en) * 1988-05-31 1995-05-23 Yamaha Corporation Process of fabricating complementary inverter circuit having multi-level interconnection
USRE36469E (en) * 1988-09-30 1999-12-28 Micron Technology, Inc. Packaging for semiconductor logic devices
US5041738A (en) * 1989-12-04 1991-08-20 Advanced Micro Devices, Inc. CMOS clock generator having an adjustable overlap voltage
US5306962A (en) 1990-11-27 1994-04-26 Hewlett-Packard Company Qualified non-overlapping clock generator to provide control lines with non-overlapping clock timing
US5124572A (en) 1990-11-27 1992-06-23 Hewlett-Packard Co. VLSI clocking system using both overlapping and non-overlapping clocks
US5543736A (en) * 1993-12-10 1996-08-06 United Technologies Corporation Gate array architecture and layout for deep space applications
US5576654A (en) * 1995-05-16 1996-11-19 Harris Corporation BIMOS driver circuit and method
US5760610A (en) 1996-03-01 1998-06-02 Hewlett-Packard Company Qualified universal clock buffer circuit for generating high gain, low skew local clock signals
US5726596A (en) 1996-03-01 1998-03-10 Hewlett-Packard Company High-performance, low-skew clocking scheme for single-phase, high-frequency global VLSI processor
US5701335A (en) 1996-05-31 1997-12-23 Hewlett-Packard Co. Frequency independent scan chain
US5748019A (en) * 1997-05-15 1998-05-05 Vlsi Technology, Inc. Output buffer driver with load compensation

Also Published As

Publication number Publication date
US20020135412A1 (en) 2002-09-26
US6459318B1 (en) 2002-10-01

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