JP2002108967A - 遅延計算用負荷生成方法および記録媒体 - Google Patents

遅延計算用負荷生成方法および記録媒体

Info

Publication number
JP2002108967A
JP2002108967A JP2000294769A JP2000294769A JP2002108967A JP 2002108967 A JP2002108967 A JP 2002108967A JP 2000294769 A JP2000294769 A JP 2000294769A JP 2000294769 A JP2000294769 A JP 2000294769A JP 2002108967 A JP2002108967 A JP 2002108967A
Authority
JP
Japan
Prior art keywords
load
capacitance
delay
parasitic capacitance
model
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000294769A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002108967A5 (OSRAM
Inventor
Michio Komota
道夫 古茂田
Shigeru Kuriyama
茂 栗山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000294769A priority Critical patent/JP2002108967A/ja
Priority to US09/878,352 priority patent/US6552551B2/en
Publication of JP2002108967A publication Critical patent/JP2002108967A/ja
Publication of JP2002108967A5 publication Critical patent/JP2002108967A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2882—Testing timing characteristics
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2000294769A 2000-09-27 2000-09-27 遅延計算用負荷生成方法および記録媒体 Pending JP2002108967A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000294769A JP2002108967A (ja) 2000-09-27 2000-09-27 遅延計算用負荷生成方法および記録媒体
US09/878,352 US6552551B2 (en) 2000-09-27 2001-06-12 Method of producing load for delay time calculation and recording medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000294769A JP2002108967A (ja) 2000-09-27 2000-09-27 遅延計算用負荷生成方法および記録媒体

Publications (2)

Publication Number Publication Date
JP2002108967A true JP2002108967A (ja) 2002-04-12
JP2002108967A5 JP2002108967A5 (OSRAM) 2007-03-29

Family

ID=18777305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000294769A Pending JP2002108967A (ja) 2000-09-27 2000-09-27 遅延計算用負荷生成方法および記録媒体

Country Status (2)

Country Link
US (1) US6552551B2 (OSRAM)
JP (1) JP2002108967A (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7808291B2 (en) 2005-06-01 2010-10-05 Advantest Corporation Jitter generating circuit

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100331567B1 (ko) * 2000-03-21 2002-04-06 윤종용 부유 도전 패턴을 고려한 집적회로의 배선간 기생커패시턴스 계산 방법 및 이를 기록한 기록매체
US7707524B2 (en) * 2003-05-27 2010-04-27 Mentor Graphics Corporation Osculating models for predicting the operation of a circuit structure
CN119780773A (zh) * 2024-12-05 2025-04-08 云南电网有限责任公司文山供电局 寄生回路的检测装置
CN120629791B (zh) * 2025-08-15 2025-10-17 四川职业技术学院 一种电子元器件测试系统、方法、设备及介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0358279A (ja) 1989-07-27 1991-03-13 Nec Corp 論理シミュレータ
US6038383A (en) * 1997-10-13 2000-03-14 Texas Instruments Incorporated Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability
US6378109B1 (en) * 1999-07-15 2002-04-23 Texas Instruments Incorporated Method of simulation for gate oxide integrity check on an entire IC

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7808291B2 (en) 2005-06-01 2010-10-05 Advantest Corporation Jitter generating circuit

Also Published As

Publication number Publication date
US6552551B2 (en) 2003-04-22
US20020036508A1 (en) 2002-03-28

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