JP2002076135A - Mosトランジスタ、インバータ、レシオ回路及びラッチ回路 - Google Patents
Mosトランジスタ、インバータ、レシオ回路及びラッチ回路Info
- Publication number
- JP2002076135A JP2002076135A JP2000265797A JP2000265797A JP2002076135A JP 2002076135 A JP2002076135 A JP 2002076135A JP 2000265797 A JP2000265797 A JP 2000265797A JP 2000265797 A JP2000265797 A JP 2000265797A JP 2002076135 A JP2002076135 A JP 2002076135A
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- region
- transistor
- mos transistor
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000265797A JP2002076135A (ja) | 2000-09-01 | 2000-09-01 | Mosトランジスタ、インバータ、レシオ回路及びラッチ回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000265797A JP2002076135A (ja) | 2000-09-01 | 2000-09-01 | Mosトランジスタ、インバータ、レシオ回路及びラッチ回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002076135A true JP2002076135A (ja) | 2002-03-15 |
| JP2002076135A5 JP2002076135A5 (enExample) | 2007-10-04 |
Family
ID=18753010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000265797A Withdrawn JP2002076135A (ja) | 2000-09-01 | 2000-09-01 | Mosトランジスタ、インバータ、レシオ回路及びラッチ回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002076135A (enExample) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08213477A (ja) * | 1995-02-07 | 1996-08-20 | Semiconductor Energy Lab Co Ltd | 薄膜半導体集積回路 |
| JPH098612A (ja) * | 1995-06-16 | 1997-01-10 | Nec Corp | ラッチ回路 |
| JPH09326685A (ja) * | 1996-06-05 | 1997-12-16 | Fujitsu Ltd | 半導体装置 |
| JPH11220124A (ja) * | 1998-01-30 | 1999-08-10 | Sanyo Electric Co Ltd | 半導体装置 |
| JP2000150883A (ja) * | 1998-09-07 | 2000-05-30 | Seiko Epson Corp | Mos型トランジスタおよび半導体装置 |
| JP2000278098A (ja) * | 1999-03-24 | 2000-10-06 | Texas Instr Japan Ltd | レシオ回路、ラッチ回路及びmosトランジスタ |
-
2000
- 2000-09-01 JP JP2000265797A patent/JP2002076135A/ja not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08213477A (ja) * | 1995-02-07 | 1996-08-20 | Semiconductor Energy Lab Co Ltd | 薄膜半導体集積回路 |
| JPH098612A (ja) * | 1995-06-16 | 1997-01-10 | Nec Corp | ラッチ回路 |
| JPH09326685A (ja) * | 1996-06-05 | 1997-12-16 | Fujitsu Ltd | 半導体装置 |
| JPH11220124A (ja) * | 1998-01-30 | 1999-08-10 | Sanyo Electric Co Ltd | 半導体装置 |
| JP2000150883A (ja) * | 1998-09-07 | 2000-05-30 | Seiko Epson Corp | Mos型トランジスタおよび半導体装置 |
| JP2000278098A (ja) * | 1999-03-24 | 2000-10-06 | Texas Instr Japan Ltd | レシオ回路、ラッチ回路及びmosトランジスタ |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6924560B2 (en) | Compact SRAM cell with FinFET | |
| US7336103B1 (en) | Stacked inverter delay chain | |
| JP3900465B2 (ja) | Soi電界効果トランジスタ | |
| JP2746087B2 (ja) | 半導体集積回路 | |
| JP3169333B2 (ja) | 両方向性の高電圧トランジスタを利用したアナログマルチプレクサ回路 | |
| JPH0552687B2 (enExample) | ||
| JP3107545B2 (ja) | 低電力cmos回路 | |
| JP3264622B2 (ja) | 半導体装置 | |
| US6548870B1 (en) | Semiconductor device | |
| JPS6043693B2 (ja) | 駆動回路 | |
| JP4397066B2 (ja) | ラッチ回路 | |
| JP2002076135A (ja) | Mosトランジスタ、インバータ、レシオ回路及びラッチ回路 | |
| US7652330B1 (en) | Independently-double-gated combinational logic | |
| JPH0441505B2 (enExample) | ||
| US6597043B1 (en) | Narrow high performance MOSFET device design | |
| JPS62276868A (ja) | 半導体集積回路装置 | |
| US6410966B2 (en) | Ratio circuit | |
| JPH06275826A (ja) | 半導体装置 | |
| US6420774B1 (en) | Low junction capacitance semiconductor structure and I/O buffer | |
| JP3119177B2 (ja) | 半導体装置 | |
| JP2002190576A (ja) | 半導体装置およびその製造方法 | |
| JP2002185012A (ja) | Soimosトランジスタを備えた半導体素子及び信号処理装置 | |
| JP3537431B2 (ja) | 半導体装置 | |
| JPH02201964A (ja) | Mos型トランジスタ | |
| US8460991B2 (en) | Differentially recessed contacts for multi-gate transistor of SRAM cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070820 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070820 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20090928 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110214 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110502 |
|
| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20110628 |