JP2002006002A - バウンダリスキャンによるハードウェアコントロールステータスレジスタの操作 - Google Patents
バウンダリスキャンによるハードウェアコントロールステータスレジスタの操作Info
- Publication number
- JP2002006002A JP2002006002A JP2001121877A JP2001121877A JP2002006002A JP 2002006002 A JP2002006002 A JP 2002006002A JP 2001121877 A JP2001121877 A JP 2001121877A JP 2001121877 A JP2001121877 A JP 2001121877A JP 2002006002 A JP2002006002 A JP 2002006002A
- Authority
- JP
- Japan
- Prior art keywords
- ring
- data
- scan
- field
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000872 buffer Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000012360 testing method Methods 0.000 abstract description 22
- 238000010586 diagram Methods 0.000 description 5
- 208000035217 Ring chromosome 1 syndrome Diseases 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 208000032825 Ring chromosome 2 syndrome Diseases 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- GHOKWGTUZJEAQD-ZETCQYMHSA-N (D)-(+)-Pantothenic acid Chemical compound OCC(C)(C)[C@@H](O)C(=O)NCCC(O)=O GHOKWGTUZJEAQD-ZETCQYMHSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
- G01R31/318563—Multiple simultaneous testing of subparts
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/563,001 US6643812B1 (en) | 2000-04-29 | 2000-04-29 | Manipulation of hardware control status registers via boundary scan |
| US09/563001 | 2000-04-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002006002A true JP2002006002A (ja) | 2002-01-09 |
| JP2002006002A5 JP2002006002A5 (enExample) | 2006-11-24 |
Family
ID=24248668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001121877A Withdrawn JP2002006002A (ja) | 2000-04-29 | 2001-04-20 | バウンダリスキャンによるハードウェアコントロールステータスレジスタの操作 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6643812B1 (enExample) |
| JP (1) | JP2002006002A (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7146538B2 (en) * | 2003-03-28 | 2006-12-05 | Hewlett-Packard Development Company, L.P. | Bus interface module |
| US7188277B2 (en) * | 2003-03-28 | 2007-03-06 | Hewlett-Packard Development Company, L.P. | Integrated circuit |
| DE102016123400B3 (de) * | 2016-01-19 | 2017-04-06 | Elmos Semiconductor Aktiengesellschaft | Eindrahtlichtsteuerbus mit mehreren Pegeln |
| EP3570056B1 (de) * | 2016-01-19 | 2023-04-12 | Elmos Semiconductor SE | Jtag-schnittstellen zur steuerung der ansteuervorrichtung von leuchtmitteln einer leuchtkette |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3357534B2 (ja) * | 1995-10-06 | 2002-12-16 | 富士通株式会社 | テスト機構を有する処理システム |
| US6389565B2 (en) * | 1998-05-29 | 2002-05-14 | Agilent Technologies, Inc. | Mechanism and display for boundary-scan debugging information |
| US6430718B1 (en) * | 1999-08-30 | 2002-08-06 | Cypress Semiconductor Corp. | Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom |
-
2000
- 2000-04-29 US US09/563,001 patent/US6643812B1/en not_active Expired - Lifetime
-
2001
- 2001-04-20 JP JP2001121877A patent/JP2002006002A/ja not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| US6643812B1 (en) | 2003-11-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061006 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061006 |
|
| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20061017 |