JP2002006002A5 - - Google Patents
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- Publication number
- JP2002006002A5 JP2002006002A5 JP2001121877A JP2001121877A JP2002006002A5 JP 2002006002 A5 JP2002006002 A5 JP 2002006002A5 JP 2001121877 A JP2001121877 A JP 2001121877A JP 2001121877 A JP2001121877 A JP 2001121877A JP 2002006002 A5 JP2002006002 A5 JP 2002006002A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/563,001 US6643812B1 (en) | 2000-04-29 | 2000-04-29 | Manipulation of hardware control status registers via boundary scan |
| US09/563001 | 2000-04-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002006002A JP2002006002A (ja) | 2002-01-09 |
| JP2002006002A5 true JP2002006002A5 (enExample) | 2006-11-24 |
Family
ID=24248668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001121877A Withdrawn JP2002006002A (ja) | 2000-04-29 | 2001-04-20 | バウンダリスキャンによるハードウェアコントロールステータスレジスタの操作 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6643812B1 (enExample) |
| JP (1) | JP2002006002A (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7146538B2 (en) * | 2003-03-28 | 2006-12-05 | Hewlett-Packard Development Company, L.P. | Bus interface module |
| US7188277B2 (en) * | 2003-03-28 | 2007-03-06 | Hewlett-Packard Development Company, L.P. | Integrated circuit |
| DE102016123400B3 (de) * | 2016-01-19 | 2017-04-06 | Elmos Semiconductor Aktiengesellschaft | Eindrahtlichtsteuerbus mit mehreren Pegeln |
| EP3570056B1 (de) * | 2016-01-19 | 2023-04-12 | Elmos Semiconductor SE | Jtag-schnittstellen zur steuerung der ansteuervorrichtung von leuchtmitteln einer leuchtkette |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3357534B2 (ja) * | 1995-10-06 | 2002-12-16 | 富士通株式会社 | テスト機構を有する処理システム |
| US6389565B2 (en) * | 1998-05-29 | 2002-05-14 | Agilent Technologies, Inc. | Mechanism and display for boundary-scan debugging information |
| US6430718B1 (en) * | 1999-08-30 | 2002-08-06 | Cypress Semiconductor Corp. | Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom |
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2000
- 2000-04-29 US US09/563,001 patent/US6643812B1/en not_active Expired - Lifetime
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2001
- 2001-04-20 JP JP2001121877A patent/JP2002006002A/ja not_active Withdrawn