JP2001308262A - 樹脂封止ｂｇａ型半導体装置 - Google Patents

樹脂封止ｂｇａ型半導体装置

Info

Publication number
JP2001308262A
JP2001308262A JP2000125579A JP2000125579A JP2001308262A JP 2001308262 A JP2001308262 A JP 2001308262A JP 2000125579 A JP2000125579 A JP 2000125579A JP 2000125579 A JP2000125579 A JP 2000125579A JP 2001308262 A JP2001308262 A JP 2001308262A
Authority
JP
Japan
Prior art keywords
chip
resin
semiconductor device
type semiconductor
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000125579A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001308262A5 (enExample
Inventor
Takashi Kondo
隆 近藤
Koji Bando
晃司 板東
Jun Shibata
潤 柴田
Kazuko Narutaki
和子 鳴瀧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000125579A priority Critical patent/JP2001308262A/ja
Priority to US09/781,237 priority patent/US6545365B2/en
Priority to KR1020010021691A priority patent/KR20010099722A/ko
Publication of JP2001308262A publication Critical patent/JP2001308262A/ja
Publication of JP2001308262A5 publication Critical patent/JP2001308262A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP2000125579A 2000-04-26 2000-04-26 樹脂封止ｂｇａ型半導体装置 Pending JP2001308262A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000125579A JP2001308262A (ja) 2000-04-26 2000-04-26 樹脂封止ｂｇａ型半導体装置
US09/781,237 US6545365B2 (en) 2000-04-26 2001-02-13 Resin-sealed chip stack type semiconductor device
KR1020010021691A KR20010099722A (ko) 2000-04-26 2001-04-23 수지 봉지 칩 적층형 반도체 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000125579A JP2001308262A (ja) 2000-04-26 2000-04-26 樹脂封止ｂｇａ型半導体装置

Publications (2)

Publication Number Publication Date
JP2001308262A true JP2001308262A (ja) 2001-11-02
JP2001308262A5 JP2001308262A5 (enExample) 2007-06-07

Family

ID=18635508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000125579A Pending JP2001308262A (ja) 2000-04-26 2000-04-26 樹脂封止ｂｇａ型半導体装置

Country Status (3)

Country Link
US (1) US6545365B2 (enExample)
JP (1) JP2001308262A (enExample)
KR (1) KR20010099722A (enExample)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030007098A (ko) * 2001-07-11 2003-01-23 닛뽕덴끼 가부시끼가이샤 치수를 감소시킬 수 있는 적층형 칩-사이즈 패키지 반도체장치
JP2004221555A (ja) * 2002-12-27 2004-08-05 Sumitomo Bakelite Co Ltd フィルム付き半導体素子、半導体装置およびそれらの製造方法
JP2004282056A (ja) * 2003-02-27 2004-10-07 Sumitomo Bakelite Co Ltd 半導体装置、半導体素子の製造方法、および半導体装置の製造方法
US6930396B2 (en) 2002-04-05 2005-08-16 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US7030489B2 (en) 2003-07-31 2006-04-18 Samsung Electronics Co., Ltd. Multi-chip module having bonding wires and method of fabricating the same
JP2006183020A (ja) * 2004-04-20 2006-07-13 Hitachi Chem Co Ltd 接着シート、半導体装置、及び半導体装置の製造方法
WO2006109506A1 (ja) * 2005-03-30 2006-10-19 Nippon Steel Chemical Co., Ltd. 半導体装置の製造方法及び半導体装置
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
JP2009065034A (ja) * 2007-09-07 2009-03-26 Renesas Technology Corp 半導体装置の製造方法
JP2009099922A (ja) * 2007-10-16 2009-05-07 Hynix Semiconductor Inc 積層半導体パッケージ及びこれの製造方法
US7615413B2 (en) 2005-03-28 2009-11-10 Kabushiki Kaisha Toshiba Method of manufacturing stack-type semiconductor device and method of manufacturing stack-type electronic component
US7633144B1 (en) 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
US7675180B1 (en) 2006-02-17 2010-03-09 Amkor Technology, Inc. Stacked electronic component package having film-on-wire spacer
US7736999B2 (en) 2006-03-16 2010-06-15 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
JP2010192937A (ja) * 2010-06-07 2010-09-02 Oki Semiconductor Co Ltd 半導体装置及び半導体装置の製造方法
US7888805B2 (en) 2004-02-25 2011-02-15 Renesas Electronics Corporation Semiconductor device package of stacked semiconductor chips with spacers provided therein
US7994620B2 (en) 2006-03-16 2011-08-09 Kabushiki Kaisha Toshiba Stacked semiconductor device
US8017444B2 (en) 2004-04-20 2011-09-13 Hitachi Chemical Company, Ltd. Adhesive sheet, semiconductor device, and process for producing semiconductor device
US8779586B2 (en) 2010-03-01 2014-07-15 Nitto Denko Corporation Die bond film, dicing die bond film, and semiconductor device
US8890334B2 (en) 2012-07-26 2014-11-18 Renesas Electronics Corporation Semiconductor device, a mobile communication device, and a method for manufacturing a semiconductor device
JP2019186552A (ja) * 2018-04-12 2019-10-24 アナログ・ディヴァイシス・グローバル・アンリミテッド・カンパニー 集積デバイスパッケージの実装構造体

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020010367A (ko) * 2000-07-29 2002-02-04 마이클 디. 오브라이언 멀티칩 모듈 및 그 제조 방법
JP3913481B2 (ja) * 2001-01-24 2007-05-09 シャープ株式会社 半導体装置および半導体装置の製造方法
US20030038356A1 (en) * 2001-08-24 2003-02-27 Derderian James M Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods
US7518223B2 (en) * 2001-08-24 2009-04-14 Micron Technology, Inc. Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
DE10142120A1 (de) * 2001-08-30 2003-03-27 Infineon Technologies Ag Elektronisches Bauteil mit wenigstens zwei gestapelten Halbleiterchips sowie Verfahren zu seiner Herstellung
US20030042615A1 (en) * 2001-08-30 2003-03-06 Tongbi Jiang Stacked microelectronic devices and methods of fabricating same
US6700206B2 (en) * 2002-08-02 2004-03-02 Micron Technology, Inc. Stacked semiconductor package and method producing same
KR100472286B1 (ko) * 2002-09-13 2005-03-10 삼성전자주식회사 접착 테이프가 본딩와이어에 부착된 반도체 칩 패키지
US7205647B2 (en) * 2002-09-17 2007-04-17 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US20040061213A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US6972481B2 (en) * 2002-09-17 2005-12-06 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US6838761B2 (en) * 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US7064426B2 (en) * 2002-09-17 2006-06-20 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US7053476B2 (en) * 2002-09-17 2006-05-30 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US7034387B2 (en) 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
WO2004034433A2 (en) * 2002-10-08 2004-04-22 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US6818978B1 (en) * 2002-11-19 2004-11-16 Asat Ltd. Ball grid array package with shielding
US7071545B1 (en) 2002-12-20 2006-07-04 Asat Ltd. Shielded integrated circuit package
JP3819851B2 (ja) * 2003-01-29 2006-09-13 松下電器産業株式会社 半導体装置およびその製造方法
US7144640B2 (en) * 2003-08-01 2006-12-05 Agency For Science, Technology And Research Tilted media for hard disk drives and magnetic data storage devices
KR100506035B1 (ko) 2003-08-22 2005-08-03 삼성전자주식회사 반도체 패키지 및 그 제조방법
US8970049B2 (en) * 2003-12-17 2015-03-03 Chippac, Inc. Multiple chip package module having inverted package stacked over die
US20050258527A1 (en) * 2004-05-24 2005-11-24 Chippac, Inc. Adhesive/spacer island structure for multiple die package
US8552551B2 (en) 2004-05-24 2013-10-08 Chippac, Inc. Adhesive/spacer island structure for stacking over wire bonded die
US20050258545A1 (en) * 2004-05-24 2005-11-24 Chippac, Inc. Multiple die package with adhesive/spacer structure and insulated die surface
US20050269692A1 (en) * 2004-05-24 2005-12-08 Chippac, Inc Stacked semiconductor package having adhesive/spacer structure and insulation
US7253511B2 (en) * 2004-07-13 2007-08-07 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US7015587B1 (en) * 2004-09-07 2006-03-21 National Semiconductor Corporation Stacked die package for semiconductor devices
WO2006105514A2 (en) * 2005-03-31 2006-10-05 Stats Chippac Ltd. Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
KR101213661B1 (ko) * 2005-03-31 2012-12-17 스태츠 칩팩, 엘티디. 칩 스케일 패키지 및 제 2 기판을 포함하고 있으며 상부면및 하부면에서 노출된 기판 표면들을 갖는 반도체 어셈블리
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7429786B2 (en) * 2005-04-29 2008-09-30 Stats Chippac Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7354800B2 (en) 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7582960B2 (en) * 2005-05-05 2009-09-01 Stats Chippac Ltd. Multiple chip package module including die stacked over encapsulated package
US7394148B2 (en) * 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
US7456088B2 (en) 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7768125B2 (en) 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US7750482B2 (en) 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US20080128879A1 (en) * 2006-12-01 2008-06-05 Hem Takiar Film-on-wire bond semiconductor device
US20080131998A1 (en) * 2006-12-01 2008-06-05 Hem Takiar Method of fabricating a film-on-wire bond semiconductor device
JP4489094B2 (ja) * 2007-04-27 2010-06-23 株式会社東芝 半導体パッケージ
US8148825B2 (en) * 2007-06-05 2012-04-03 Stats Chippac Ltd. Integrated circuit package system with leadfinger
US7800208B2 (en) 2007-10-26 2010-09-21 Infineon Technologies Ag Device with a plurality of semiconductor chips
WO2011030516A1 (ja) * 2009-09-08 2011-03-17 住友ベークライト株式会社 半導体装置
KR20170053416A (ko) 2015-11-06 2017-05-16 주식회사 엘지화학 반도체 장치 및 반도체 장치의 제조 방법
JP2023121355A (ja) * 2022-02-21 2023-08-31 キオクシア株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3786314D1 (de) * 1986-09-23 1993-07-29 Siemens Ag Halbleiterbauelemente mit leistungs-mosfet und steuerschaltung.
JPH05226565A (ja) 1992-02-15 1993-09-03 Hitachi Cable Ltd 半導体装置
JPH08107178A (ja) 1994-10-05 1996-04-23 Toshiba Microelectron Corp 樹脂封止型半導体装置及びその製造方法
JPH08288455A (ja) 1995-04-11 1996-11-01 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
KR100467946B1 (ko) * 1997-01-24 2005-01-24 로무 가부시키가이샤 반도체 칩의 제조방법
US6157074A (en) * 1997-07-16 2000-12-05 Hyundai Electronics Industries Co., Ltd. Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
JPH11251512A (ja) 1998-03-06 1999-09-17 Sumitomo Metal Mining Co Ltd 半導体チップの積層方法およびこれを用いた半導体装置

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US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US7863723B2 (en) 2001-03-09 2011-01-04 Amkor Technology, Inc. Adhesive on wire stacked semiconductor package
KR20030007098A (ko) * 2001-07-11 2003-01-23 닛뽕덴끼 가부시끼가이샤 치수를 감소시킬 수 있는 적층형 칩-사이즈 패키지 반도체장치
US6930396B2 (en) 2002-04-05 2005-08-16 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
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US7030489B2 (en) 2003-07-31 2006-04-18 Samsung Electronics Co., Ltd. Multi-chip module having bonding wires and method of fabricating the same
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JP2006183020A (ja) * 2004-04-20 2006-07-13 Hitachi Chem Co Ltd 接着シート、半導体装置、及び半導体装置の製造方法
US8017444B2 (en) 2004-04-20 2011-09-13 Hitachi Chemical Company, Ltd. Adhesive sheet, semiconductor device, and process for producing semiconductor device
US7785926B2 (en) 2005-03-28 2010-08-31 Kabushiki Kaisha Toshiba Method of manufacturing stack-type semiconductor device and method of manufacturing stack-type electronic component
US7615413B2 (en) 2005-03-28 2009-11-10 Kabushiki Kaisha Toshiba Method of manufacturing stack-type semiconductor device and method of manufacturing stack-type electronic component
WO2006109506A1 (ja) * 2005-03-30 2006-10-19 Nippon Steel Chemical Co., Ltd. 半導体装置の製造方法及び半導体装置
US7675180B1 (en) 2006-02-17 2010-03-09 Amkor Technology, Inc. Stacked electronic component package having film-on-wire spacer
US8039364B2 (en) 2006-03-16 2011-10-18 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US7994620B2 (en) 2006-03-16 2011-08-09 Kabushiki Kaisha Toshiba Stacked semiconductor device
US7736999B2 (en) 2006-03-16 2010-06-15 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US8227296B2 (en) 2006-03-16 2012-07-24 Kabushiki Kaisha Toshiba Stacked semiconductor device
US7633144B1 (en) 2006-05-24 2009-12-15 Amkor Technology, Inc. Semiconductor package
US8129849B1 (en) 2006-05-24 2012-03-06 Amkor Technology, Inc. Method of making semiconductor package with adhering portion
JP2009065034A (ja) * 2007-09-07 2009-03-26 Renesas Technology Corp 半導体装置の製造方法
JP2009099922A (ja) * 2007-10-16 2009-05-07 Hynix Semiconductor Inc 積層半導体パッケージ及びこれの製造方法
US8779586B2 (en) 2010-03-01 2014-07-15 Nitto Denko Corporation Die bond film, dicing die bond film, and semiconductor device
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US8890334B2 (en) 2012-07-26 2014-11-18 Renesas Electronics Corporation Semiconductor device, a mobile communication device, and a method for manufacturing a semiconductor device
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