JP2001216783A - 制御信号発生回路およびそれを備える半導体装置 - Google Patents

制御信号発生回路およびそれを備える半導体装置

Info

Publication number
JP2001216783A
JP2001216783A JP2000169137A JP2000169137A JP2001216783A JP 2001216783 A JP2001216783 A JP 2001216783A JP 2000169137 A JP2000169137 A JP 2000169137A JP 2000169137 A JP2000169137 A JP 2000169137A JP 2001216783 A JP2001216783 A JP 2001216783A
Authority
JP
Japan
Prior art keywords
delay
signal
circuit
signals
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000169137A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001216783A5 (enExample
Inventor
Tadaaki Yamauchi
忠昭 山内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000169137A priority Critical patent/JP2001216783A/ja
Publication of JP2001216783A publication Critical patent/JP2001216783A/ja
Priority to US10/117,211 priority patent/US6486722B2/en
Publication of JP2001216783A5 publication Critical patent/JP2001216783A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks

Landscapes

  • Dram (AREA)
  • Pulse Circuits (AREA)
JP2000169137A 1999-11-22 2000-06-06 制御信号発生回路およびそれを備える半導体装置 Pending JP2001216783A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000169137A JP2001216783A (ja) 1999-11-22 2000-06-06 制御信号発生回路およびそれを備える半導体装置
US10/117,211 US6486722B2 (en) 1999-11-22 2002-04-08 Semiconductor device including a control signal generation circuit allowing reduction in size

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11-331573 1999-11-22
JP33157399 1999-11-22
JP2000169137A JP2001216783A (ja) 1999-11-22 2000-06-06 制御信号発生回路およびそれを備える半導体装置

Publications (2)

Publication Number Publication Date
JP2001216783A true JP2001216783A (ja) 2001-08-10
JP2001216783A5 JP2001216783A5 (enExample) 2007-07-12

Family

ID=26573892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000169137A Pending JP2001216783A (ja) 1999-11-22 2000-06-06 制御信号発生回路およびそれを備える半導体装置

Country Status (2)

Country Link
US (1) US6486722B2 (enExample)
JP (1) JP2001216783A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008103054A (ja) * 2006-10-17 2008-05-01 Hynix Semiconductor Inc 半導体素子のカラム経路制御信号生成回路及びカラム経路制御信号生成方法
CN115116509A (zh) * 2021-03-23 2022-09-27 华邦电子股份有限公司 具有共用延迟电路的方法和存储器装置

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7233185B2 (en) * 2003-10-10 2007-06-19 Atmel Corporation Vernier circuit for fine control of sample time
US7242233B2 (en) * 2003-10-23 2007-07-10 International Business Machines Corporation Simplified method for limiting clock pulse width
US8054119B2 (en) * 2005-04-19 2011-11-08 International Business Machines Corporation System and method for on/off-chip characterization of pulse-width limiter outputs
US7579877B2 (en) * 2005-08-15 2009-08-25 Winbond Electronics Corporation Comparator
US7358785B2 (en) * 2006-04-06 2008-04-15 International Business Machines Corporation Apparatus and method for extracting a maximum pulse width of a pulse width limiter
KR100980061B1 (ko) * 2008-12-23 2010-09-03 주식회사 하이닉스반도체 제어신호 생성회로
US8451144B2 (en) * 2009-02-04 2013-05-28 Honeywell International Inc. Flaps overspeed advisory system
US9621141B1 (en) * 2016-01-11 2017-04-11 Oracle International Corporation Micro-pipeline frequency-comparison circuit
KR20180053113A (ko) * 2016-11-11 2018-05-21 에스케이하이닉스 주식회사 반도체장치
US11190174B1 (en) 2021-04-26 2021-11-30 Qualcomm Incorporated Delay interpolator

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
US5812626A (en) * 1995-06-13 1998-09-22 Matsushita Electric Industrial Co., Ltd. Time counting circuit sampling circuit skew adjusting circuit and logic analyzing circuit
JP3333429B2 (ja) * 1997-06-30 2002-10-15 株式会社東芝 半導体集積回路
US5942937A (en) * 1997-11-19 1999-08-24 Advanced Micro Devices, Inc. Signal detection circuit using a plurality of delay stages with edge detection logic
JPH11238381A (ja) 1998-02-19 1999-08-31 Nec Corp メモリ読み出し回路およびｓｒａｍ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008103054A (ja) * 2006-10-17 2008-05-01 Hynix Semiconductor Inc 半導体素子のカラム経路制御信号生成回路及びカラム経路制御信号生成方法
CN115116509A (zh) * 2021-03-23 2022-09-27 华邦电子股份有限公司 具有共用延迟电路的方法和存储器装置

Also Published As

Publication number Publication date
US20020109538A1 (en) 2002-08-15
US6486722B2 (en) 2002-11-26

Similar Documents

Publication Publication Date Title
JP4390305B2 (ja) 半導体装置
US6798711B2 (en) Memory with address management
US8027203B2 (en) Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure
JP2009277341A (ja) Ｓｒａｍセルの書き込みマージンを改善する書き込みアシスト回路
US8988952B2 (en) Semiconductor device having ODT function
US6198686B1 (en) Memory device having row decoder
JP2001216783A (ja) 制御信号発生回路およびそれを備える半導体装置
US6856574B2 (en) Semiconductor memory device
US6809975B2 (en) Semiconductor memory device having test mode and memory system using the same
JP2005322376A (ja) マルチポートメモリ素子
JPH09320261A (ja) 半導体記憶装置および制御信号発生回路
JP6797010B2 (ja) 半導体装置
JP4007823B2 (ja) 半導体記憶装置
JP4277961B2 (ja) 半導体記憶装置及びそのテスト方法
US5365482A (en) Semiconductor memory device with provision of pseudo-acceleration test
JP4163476B2 (ja) 半導体メモリ装置
JPH0628846A (ja) 半導体記憶装置
KR100910194B1 (ko) 반도체 기억 장치
US6377513B2 (en) Method for writing data to semiconductor memory and semiconductor memory
JP2003196985A (ja) 半導体メモリ及び半導体メモリのビットライト又はバイトライト方法
JP2010267355A (ja) スタティックランダムアクセスメモリ
JPH08147980A (ja) 半導体記憶装置
JP2015158960A (ja) 半導体装置
US6246633B1 (en) Semiconductor memory device permitting stabilized operation and high-speed access
KR100674981B1 (ko) 칼럼선택 라인을 개선한 반도체 메모리 장치 및 그구동방법

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070528

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070528

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090609

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20091020