JP2001202796A - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JP2001202796A
JP2001202796A JP2000012723A JP2000012723A JP2001202796A JP 2001202796 A JP2001202796 A JP 2001202796A JP 2000012723 A JP2000012723 A JP 2000012723A JP 2000012723 A JP2000012723 A JP 2000012723A JP 2001202796 A JP2001202796 A JP 2001202796A
Authority
JP
Japan
Prior art keywords
potential
circuit
test
memory device
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000012723A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001202796A5 (enExample
Inventor
Yoshiyuki Hikiyama
義之 引山
Toshio Kobashi
寿夫 小橋
Tetsuji Hoshida
哲司 星田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000012723A priority Critical patent/JP2001202796A/ja
Priority to US09/615,898 priority patent/US6392939B1/en
Priority to TW089116507A priority patent/TW473718B/zh
Priority to KR10-2000-0054561A priority patent/KR100380541B1/ko
Publication of JP2001202796A publication Critical patent/JP2001202796A/ja
Publication of JP2001202796A5 publication Critical patent/JP2001202796A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2000012723A 2000-01-21 2000-01-21 半導体記憶装置 Pending JP2001202796A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000012723A JP2001202796A (ja) 2000-01-21 2000-01-21 半導体記憶装置
US09/615,898 US6392939B1 (en) 2000-01-21 2000-07-13 Semiconductor memory device with improved defect elimination rate
TW089116507A TW473718B (en) 2000-01-21 2000-08-16 Semiconductor memory device
KR10-2000-0054561A KR100380541B1 (ko) 2000-01-21 2000-09-18 불량 제거율이 향상된 반도체 기억장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000012723A JP2001202796A (ja) 2000-01-21 2000-01-21 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2001202796A true JP2001202796A (ja) 2001-07-27
JP2001202796A5 JP2001202796A5 (enExample) 2006-09-14

Family

ID=18540406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000012723A Pending JP2001202796A (ja) 2000-01-21 2000-01-21 半導体記憶装置

Country Status (4)

Country Link
US (1) US6392939B1 (enExample)
JP (1) JP2001202796A (enExample)
KR (1) KR100380541B1 (enExample)
TW (1) TW473718B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422952B1 (ko) * 2002-06-14 2004-03-16 주식회사 하이닉스반도체 반도체 메모리의 비트라인 균등화 신호 제어회로

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7218564B2 (en) * 2004-07-16 2007-05-15 Promos Technologies Inc. Dual equalization devices for long data line pairs
US8120976B2 (en) * 2006-08-28 2012-02-21 Samsung Electronics Co., Ltd. Line defect detection circuit for detecting weak line
JP4984759B2 (ja) * 2006-09-05 2012-07-25 富士通セミコンダクター株式会社 半導体記憶装置
KR101027338B1 (ko) * 2009-03-30 2011-04-11 주식회사 하이닉스반도체 번인 테스트 방법 및 집적회로
CN116564397B (zh) * 2023-07-07 2023-11-14 长鑫存储技术有限公司 存储器老化测试方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1146260B (it) * 1981-02-26 1986-11-12 Pellegrinuzzi E & Co Udl Snc Utensili di macchine per la levigatura di lastre e pavimentazioni di marmo, granito e simili
JPH05180907A (ja) 1991-09-18 1993-07-23 Sony Corp アドレス線選択回路
US5241500A (en) * 1992-07-29 1993-08-31 International Business Machines Corporation Method for setting test voltages in a flash write mode
KR0185643B1 (ko) * 1996-08-05 1999-04-15 삼성전자주식회사 반도체 메모리장치의 스트레스 전압 인가장치
KR100228530B1 (ko) * 1996-12-23 1999-11-01 윤종용 반도체 메모리 장치의 웨이퍼 번인 테스트회로
US5854770A (en) * 1997-01-30 1998-12-29 Sgs-Thomson Microelectronics S.R.L. Decoding hierarchical architecture for high integration memories
JPH10269800A (ja) * 1997-03-27 1998-10-09 Mitsubishi Electric Corp 半導体記憶装置
JP3863968B2 (ja) * 1997-06-10 2006-12-27 株式会社ルネサステクノロジ 半導体記憶装置
JP3938229B2 (ja) * 1997-10-13 2007-06-27 沖電気工業株式会社 半導体記憶装置
KR100257580B1 (ko) * 1997-11-25 2000-06-01 윤종용 반도체 메모리 장치의 번-인 제어 회로
KR19990049863A (ko) * 1997-12-15 1999-07-05 윤종용 웨이퍼 번인 테스트 회로
JP2000100195A (ja) * 1998-09-22 2000-04-07 Nec Corp 冗長回路を有する半導体記憶装置
US6055199A (en) * 1998-10-21 2000-04-25 Mitsubishi Denki Kabushiki Kaisha Test circuit for a semiconductor memory device and method for burn-in test
KR100311175B1 (ko) * 1998-12-28 2001-12-17 김영환 반도체메모리

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422952B1 (ko) * 2002-06-14 2004-03-16 주식회사 하이닉스반도체 반도체 메모리의 비트라인 균등화 신호 제어회로

Also Published As

Publication number Publication date
US6392939B1 (en) 2002-05-21
TW473718B (en) 2002-01-21
KR100380541B1 (ko) 2003-04-23
KR20010077870A (ko) 2001-08-20

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