JP2001126474A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JP2001126474A
JP2001126474A JP30032299A JP30032299A JP2001126474A JP 2001126474 A JP2001126474 A JP 2001126474A JP 30032299 A JP30032299 A JP 30032299A JP 30032299 A JP30032299 A JP 30032299A JP 2001126474 A JP2001126474 A JP 2001126474A
Authority
JP
Japan
Prior art keywords
output
circuit
clock signal
signal
internal clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30032299A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001126474A5 (https=
Inventor
Yozo Saiki
陽造 齋木
Satoshi Aoyama
聡 青山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP30032299A priority Critical patent/JP2001126474A/ja
Publication of JP2001126474A publication Critical patent/JP2001126474A/ja
Publication of JP2001126474A5 publication Critical patent/JP2001126474A5/ja
Pending legal-status Critical Current

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JP30032299A 1999-10-22 1999-10-22 半導体集積回路装置 Pending JP2001126474A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30032299A JP2001126474A (ja) 1999-10-22 1999-10-22 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30032299A JP2001126474A (ja) 1999-10-22 1999-10-22 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2001126474A true JP2001126474A (ja) 2001-05-11
JP2001126474A5 JP2001126474A5 (https=) 2005-06-09

Family

ID=17883392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30032299A Pending JP2001126474A (ja) 1999-10-22 1999-10-22 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JP2001126474A (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815985B2 (en) 2002-06-28 2004-11-09 Hynix Semiconductor Inc. Clock divider and method for dividing a clock signal in a DLL circuit
US6842396B2 (en) 2002-09-17 2005-01-11 Renesas Technology Corp. Semiconductor memory device with clock generating circuit
US6897695B2 (en) 2002-12-06 2005-05-24 Elpida Memory Inc. Semiconductor integrated circuit device and method of detecting delay error in the same
US7969816B2 (en) 2009-08-26 2011-06-28 Spansion Llc Memory device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815985B2 (en) 2002-06-28 2004-11-09 Hynix Semiconductor Inc. Clock divider and method for dividing a clock signal in a DLL circuit
US6842396B2 (en) 2002-09-17 2005-01-11 Renesas Technology Corp. Semiconductor memory device with clock generating circuit
US6897695B2 (en) 2002-12-06 2005-05-24 Elpida Memory Inc. Semiconductor integrated circuit device and method of detecting delay error in the same
US7969816B2 (en) 2009-08-26 2011-06-28 Spansion Llc Memory device

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