JP2000515707A - 位相ロックループを有する受信機 - Google Patents
位相ロックループを有する受信機Info
- Publication number
- JP2000515707A JP2000515707A JP10529433A JP52943398A JP2000515707A JP 2000515707 A JP2000515707 A JP 2000515707A JP 10529433 A JP10529433 A JP 10529433A JP 52943398 A JP52943398 A JP 52943398A JP 2000515707 A JP2000515707 A JP 2000515707A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- locked loop
- phase locked
- oscillator
- osc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008859 change Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
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- 235000005806 ruta Nutrition 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 11
- 238000005259 measurement Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- SGTNSNPWRIOYBX-UHFFFAOYSA-N 2-(3,4-dimethoxyphenyl)-5-{[2-(3,4-dimethoxyphenyl)ethyl](methyl)amino}-2-(propan-2-yl)pentanenitrile Chemical compound C1=C(OC)C(OC)=CC=C1CCN(C)CCCC(C#N)(C(C)C)C1=CC=C(OC)C(OC)=C1 SGTNSNPWRIOYBX-UHFFFAOYSA-N 0.000 description 1
- 241001417523 Plesiopidae Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
- H03J7/02—Automatic frequency control
- H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
- H03J7/06—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/02—Automatic control of frequency or phase; Synchronisation using a frequency discriminator comprising a passive frequency-determining element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J2200/00—Indexing scheme relating to tuning resonant circuits and selecting resonant circuits
- H03J2200/29—Self-calibration of a receiver
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Superheterodyne Receivers (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 入力信号(Srf)を処理して中間信号(Sif)を得るフロントエンド(F RE)と、 位相ロックループの一部を構成する発振器(OSC)を中間信号(Sif)の一 部を構成する搬送波(CA)と同期させる位相ロックループ(PLL)と、 位相ロックループの発振器(OSC)を校正する校正回路(CAL)と、 を具えた受信機において、前記校正回路(CAL)は、 前記搬送波(CA)の公称周波数(Fnom)と位相ロックループの発振器(O SC)の周波数(Fosc)との間の周波数差(dF)を測定する周波数測定回路( FAC)と、 位相ロックループの発振器(OSC)の周波数(Fosc)を前記測定周波数差 (dF)に従って調整する周波数調整回路(FAC)と、 を具えていることを特徴とする受信機。 2. 前記周波数調整回路(FAC)は位相ロックループの発振器(OSC)の 周波数(Fosc)をほぼ零(0)を中心とする周波数差(dF)の所定の範囲(W IN)に亘って調整しないことを特徴とする請求項1記載の受信機。 3. 前記周波数調整回路(FAC)は位相ロックループの発振器(OSC)の 周波数(Fosc)を2つの周波数差(dF1、dF2)に対し少なくとも2つの異 なる力(FO1、FO2)で調整し、2つの力の強い方(FO1)が2つの周波 数差の大きい方(dF1)に適用されることを特徴とする請求項1記載の受信機 。 4. 位相ロックループの発振器(OSC)は粗周波数調整入力端子(INC) と精周波数調整入力端子(INF)を有し、位相ロックループの発振器(OSC )の周波数(Fosc)は、所定の変化(Δ)が粗周波数調整入力端子(INC) に発生するとき、同一の変化(Δ)が精周波数調整入力端子(INF)に発生す る場合より大きな程度で調整され、粗周波数調整入力端子(INC)が周波数調 整回路(FAC)に結合され、精周波数調整入力端子(INF)が位相ロックル ープの位相検出器(PD)に結合されていることを特徴とする請求項1記載の受 信 機。 5. 前記フロントエンド(FRE)は、 入力信号(Srf)を周波数シフトさせて周波数シフトされた入力信号(Srfs )を得るチューナ(TUN)と、 周波数シフトされた入力信号(Srfs)から中間信号(Sif)を抽出するフィ ルタ(FIL)とを具え、 当該受信機は、 チューナ(TUN)により行われる周波数シフト(Fshift)を中間信号(Si f)の公称周波数(Fnom)と位相ロックループの発振器(OSC)の周波数(F osc)との間の測定周波数差(dF)に従って調整する同調調整回路(TAC)を 具えていることを特徴とする請求項1記載の受信機。 6. 位相ロックループの一部を構成する発振器(OSC)を搬送波(CA)と 同期させる位相ロックループ(PLL)と、 位相ロックループの発振器(OSC)を校正する校正回路(CAL)と、 を具えた受信機において、前記校正回路(CAL)は、 前記搬送波(CA)の公称周波数(Fnom)と位相ロックループの発振器(O SC)の周波数(Fosc)との間の周波数差(dF)を測定する周波数測定回路( FAC)と、 位相ロックループの発振器(OSC)の周波数(Fosc)を前記測定周波数差 (dF)に従って調整する周波数調整回路(FAC)と、 を具えていることを特徴とする集積回路(IC)。 7. 搬送波(CA)と同期させるために位相ロックループの一部を構成する発 振器(OSC)を校正するに当たり、 前記搬送波(CA)の公称周波数(Fnom)と位相ロックループの発振器(O SC)の周波数(Fosc)との間の周波数差(dF)を測定し、 位相ロックループの発振器(OSC)の周波数(Fosc)を前記測定周波数差 (dF)に従って調整することを特徴とする位相ロックループの発振器の校正方 法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97201542 | 1997-05-23 | ||
EP97201542.4 | 1997-05-23 | ||
PCT/IB1998/000632 WO1998053554A2 (en) | 1997-05-23 | 1998-04-27 | Receiver having a phase-locked loop |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2000515707A true JP2000515707A (ja) | 2000-11-21 |
JP2000515707A5 JP2000515707A5 (ja) | 2005-12-02 |
JP4097709B2 JP4097709B2 (ja) | 2008-06-11 |
Family
ID=8228344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52943398A Expired - Lifetime JP4097709B2 (ja) | 1997-05-23 | 1998-04-27 | 位相ロックループを有する受信機 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6795695B1 (ja) |
EP (1) | EP0914714B1 (ja) |
JP (1) | JP4097709B2 (ja) |
CN (1) | CN1148001C (ja) |
DE (1) | DE69821863T2 (ja) |
WO (1) | WO1998053554A2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001339320A (ja) * | 2000-05-25 | 2001-12-07 | Sony Corp | 干渉波除去回路とデジタルテレビ受信機 |
US7158587B2 (en) * | 2001-09-18 | 2007-01-02 | Agere Systems Inc. | Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof |
EP1438841A2 (en) * | 2001-10-16 | 2004-07-21 | Rfstream Corporation | Monolithic integrated circuit for a television receiver |
US6998887B2 (en) | 2002-08-16 | 2006-02-14 | Sun Microsystems, Inc. | Calibration technique for phase locked loop leakage current |
AU2003265339A1 (en) * | 2002-08-13 | 2004-02-25 | Sun Microsystems, Inc. | Calibration technique for locked loop circuit leakage current |
US7720469B2 (en) * | 2005-12-29 | 2010-05-18 | Nokia Corporation | Frequency calibration of wireless telecommunication device |
KR101419892B1 (ko) * | 2007-12-07 | 2014-07-16 | 삼성전자주식회사 | 수신기 및 이를 포함하는 통신 시스템 |
CN106897645A (zh) * | 2016-12-28 | 2017-06-27 | 深圳天珑无线科技有限公司 | 一种移动设备 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5580928A (en) * | 1978-12-15 | 1980-06-18 | Sony Corp | Channel selection device |
FI91821C (fi) * | 1991-02-22 | 1994-08-10 | Nokia Mobile Phones Ltd | Radiopuhelimen automaattinen taajuudensäätökytkentä |
SG44865A1 (en) * | 1991-05-10 | 1997-12-19 | Philips Electronics Nv | Television receiver with automatic tuning control |
JPH0548483A (ja) * | 1991-08-12 | 1993-02-26 | Fujitsu Ltd | 周波数変換回路 |
US5408196A (en) * | 1993-03-29 | 1995-04-18 | U.S. Philips Corporation | Tunable device |
DE4319769C1 (de) * | 1993-06-15 | 1994-07-14 | Grundig Emv | Verfahren und Anordnung zur Einstellung der lokalen Oszillatoren eines Empfängers in einem Mehrkanalübertragungssystem |
US5446416A (en) * | 1993-10-20 | 1995-08-29 | Industrial Technology Research Institute | Time acquisition system with dual-loop for independent frequency phase lock |
AUPM972594A0 (en) * | 1994-11-28 | 1994-12-22 | Curtin University Of Technology | Steered frequency phase locked loop |
FR2737626B1 (fr) * | 1995-07-31 | 1997-09-05 | Sgs Thomson Microelectronics | Dispositif et procede pour regler la frequence d'accord d'un demodulateur pll |
-
1998
- 1998-04-27 EP EP98913988A patent/EP0914714B1/en not_active Expired - Lifetime
- 1998-04-27 CN CNB988009730A patent/CN1148001C/zh not_active Expired - Fee Related
- 1998-04-27 JP JP52943398A patent/JP4097709B2/ja not_active Expired - Lifetime
- 1998-04-27 WO PCT/IB1998/000632 patent/WO1998053554A2/en active IP Right Grant
- 1998-04-27 DE DE69821863T patent/DE69821863T2/de not_active Expired - Lifetime
- 1998-05-20 US US09/082,449 patent/US6795695B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0914714B1 (en) | 2004-02-25 |
DE69821863D1 (de) | 2004-04-01 |
WO1998053554A3 (en) | 1999-03-25 |
DE69821863T2 (de) | 2004-12-30 |
EP0914714A2 (en) | 1999-05-12 |
CN1148001C (zh) | 2004-04-28 |
US6795695B1 (en) | 2004-09-21 |
CN1234924A (zh) | 1999-11-10 |
JP4097709B2 (ja) | 2008-06-11 |
WO1998053554A2 (en) | 1998-11-26 |
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