JP2000332146A - Resin-sealed semiconductor device, circuit material usable therefor and manufacture thereof - Google Patents

Resin-sealed semiconductor device, circuit material usable therefor and manufacture thereof

Info

Publication number
JP2000332146A
JP2000332146A JP11136705A JP13670599A JP2000332146A JP 2000332146 A JP2000332146 A JP 2000332146A JP 11136705 A JP11136705 A JP 11136705A JP 13670599 A JP13670599 A JP 13670599A JP 2000332146 A JP2000332146 A JP 2000332146A
Authority
JP
Japan
Prior art keywords
terminal
semiconductor element
resin
thin film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11136705A
Other languages
Japanese (ja)
Other versions
JP3992877B2 (en
Inventor
Masahito Sasaki
将人 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP13670599A priority Critical patent/JP3992877B2/en
Publication of JP2000332146A publication Critical patent/JP2000332146A/en
Application granted granted Critical
Publication of JP3992877B2 publication Critical patent/JP3992877B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To enhance the occupancy ratio of semiconductor elements, enable downsizing, and improve the packing density on a circuit board by sealing terminals, the semiconductor elements and bonding wires with sealing members so as to expose the top end of outer terminals of each terminal part to the outside. SOLUTION: A resin-sealed semiconductor device 11 comprises a plurality of terminal parts 12 of inner and outer terminals 13, 14 disposed in two rows at prescribed spacings, a semiconductor element 15 located in approximately the center of a space where the terminal parts 12 are disposed, bonding wires 17 connecting terminals 15a of the semiconductor element 15 to the terminal parts 12, and sealing members 18 for sealing the terminal parts 12, the bonding wires 17 and the semiconductor element 15. Each terminal part 12 is electrically disposed independently being approximately flush with the inner terminal 13 facing the same plane. The outer terminal 14 is composed of a buried part 14a located in the seal member 18 and a top end part 14b exposed to protrude from the back side of the resin-sealed semiconductor device 11.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子を搭載し
た樹脂封止型の半導体装置とそれに用いられる回路部材
およびそれらの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device having a semiconductor element mounted thereon, a circuit member used for the semiconductor device, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年、半導体装置は、高集積化や小型化
技術の進歩、電気機器の高性能化と軽薄短小化の傾向
(時流)から、LSIのASICに代表されるように、
ますます高集積化、高機能化になってきている。
2. Description of the Related Art In recent years, semiconductor devices have been typified by LSI ASICs due to advances in high integration and miniaturization technologies, and the trend toward higher performance and lighter, thinner and smaller electric appliances (current trend).
It is becoming more and more highly integrated and highly functional.

【0003】これに伴い、リードフレームを用いた封止
型の半導体装置においても、その開発のトレンドが、S
OJ(Small Outline J−Leaded
Package)やQFP(Quad Flat P
ackage)のような表面実装型のパッケージを経
て、TSOP(Thin Small Outline
Package)の開発による薄型化を主軸としたパッ
ケージの小型化へ、さらにはパッケージ内部の3次元化
によるチップ収納効率向上を目的としたLOC(Lea
d On Chip)の構造へと進展してきた。
Accordingly, the development trend of the sealing type semiconductor device using the lead frame has been
OJ (Small Outline J-Leaded
Package or QFP (Quad Flat P)
through a surface mount type package such as a TSOP (Thin Small Outline).
LOC (Lea) for the purpose of package miniaturization with the main axis of thinning due to the development of Package) and improvement of chip storage efficiency by making the package three-dimensional.
d On Chip).

【0004】しかし、樹脂封止型の半導体装置パッケー
ジには、高集積化、高機能化とともに、更に一層の多ピ
ン化、薄型化、小型化が求められており、上記従来のパ
ッケージにおいても半導体素子外周部分のリードの引き
回しがあるため、パッケージの小型化に限界が見えてき
た。
[0004] However, resin-encapsulated semiconductor device packages are required to have higher integration, higher functionality, and more pins, thinner, and smaller. Due to the arrangement of leads on the outer peripheral portion of the element, a limit has been seen in miniaturization of the package.

【0005】[0005]

【発明が解決しようとする課題】このため、近年、エリ
アアレー状に配設された半田ボールにより回路基板に実
装可能なBGA(Ball Grid Array)タ
イプの樹脂封止型半導体装置が開発されている。
Therefore, in recent years, a BGA (Ball Grid Array) type resin-sealed semiconductor device that can be mounted on a circuit board by solder balls arranged in an area array has been developed. .

【0006】しかし、このようなBGAタイプの樹脂封
止型半導体装置は、半田ボールを用いることにより、回
路基板への実装時の信頼性に優れるものの、半田ボール
搭載工程において高価な搭載装置およびマスクが必要で
あり、さらに、半田ボール自体のコストが高く、半導体
装置の製造コスト低減に支障を来していた。
However, such a BGA-type resin-encapsulated semiconductor device has excellent reliability when mounted on a circuit board by using a solder ball, but is expensive in a solder ball mounting process and a mask. And the cost of the solder ball itself is high, which hinders a reduction in the manufacturing cost of the semiconductor device.

【0007】本発明は、上記のような事情に鑑みてなさ
れたものであり、半導体素子の占有率が高く小型化が可
能で、回路基板への実装密度を向上させることができ、
さらに、多ピン化への対応が可能でありながら半田ボー
ルを搭載する必要のない樹脂封止型の半導体装置と、こ
の半導体装置に用いられる回路部材、および、これら回
路部材と半導体装置の製造方法を提供することを目的と
する。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a high occupancy rate of a semiconductor element, can be reduced in size, and can improve a mounting density on a circuit board.
Furthermore, a resin-encapsulated semiconductor device capable of coping with the increase in the number of pins while not having to mount a solder ball, a circuit member used in the semiconductor device, and a method of manufacturing the circuit member and the semiconductor device The purpose is to provide.

【0008】[0008]

【課題を解決するための手段】このような目的を達成す
るために、本発明の樹脂封止型半導体装置は、薄膜状の
内部端子と柱状の外部端子とを一体的に有する複数の端
子部が前記内部端子面を同一方向に向けて略一平面上に
位置するように電気的に独立して配設され、該端子部が
配設された空間の略中央に回路形成面側が前記内部端子
面と同一方向を向くように半導体素子が電気的に独立し
て配置され、各端子部の内部端子と半導体素子の端子と
がボンディングワイヤにより電気的に接続され、各端子
部の外部端子の先端側を外部に露出させるように前記端
子部、半導体素子およびボンディングワイヤが封止部材
により封止されているような構成とした。
In order to achieve the above object, a resin-encapsulated semiconductor device according to the present invention comprises a plurality of terminal portions integrally having a thin-film internal terminal and a columnar external terminal. Are arranged electrically independently so that the internal terminal faces are oriented substantially in the same direction in the same direction, and the circuit forming surface side is located substantially at the center of the space in which the terminal portion is provided. The semiconductor elements are electrically independent of each other so as to face the same direction as the surface, and the internal terminals of each terminal and the terminals of the semiconductor element are electrically connected by bonding wires. The terminal part, the semiconductor element, and the bonding wire were sealed by a sealing member so that the side was exposed to the outside.

【0009】また、本発明の樹脂封止型半導体装置は、
前記半導体素子の回路形成面と反対面側に電気絶縁性の
樹脂層を有し、該樹脂層が裏面側に露出しているような
構成とした。
Further, the resin-encapsulated semiconductor device of the present invention comprises:
An electrically insulating resin layer was provided on the surface opposite to the circuit forming surface of the semiconductor element, and the resin layer was exposed on the back surface.

【0010】本発明の回路部材は、金属製の平板状の基
部と、該基部の一方の面の半導体素子搭載用領域の外側
に所定のパターンで配設された複数の金属製の柱状凸部
と、該柱状凸部の上端面に設けられた導電性の薄膜と、
を備えるような構成とした。
A circuit member according to the present invention comprises a metal flat base and a plurality of metal columnar protrusions arranged in a predetermined pattern on one surface of the base outside the semiconductor element mounting area. And a conductive thin film provided on the upper end surface of the columnar protrusion,
It was configured to be provided with.

【0011】また、本発明の回路部材は、前記基部の半
導体素子搭載用領域の少なくとも一部に電気絶縁性の接
着部材が設けられているような構成とした。
Further, the circuit member of the present invention is configured such that an electrically insulating adhesive member is provided on at least a part of the semiconductor element mounting area of the base.

【0012】本発明の回路部材の製造方法は、金属製の
基板にレジストパターンを形成するパターン形成工程
と、基板の露出面に導電性の薄膜を形成する薄膜形成工
程と、前記レジストパターンを剥離除去し、前記薄膜を
マスクとして前記基板をハーフエッチングするエッチン
グ工程と、を有するような構成とした。
According to the method of manufacturing a circuit member of the present invention, there are provided a pattern forming step of forming a resist pattern on a metal substrate, a thin film forming step of forming a conductive thin film on an exposed surface of the substrate, and peeling of the resist pattern. An etching step of removing the substrate and half-etching the substrate using the thin film as a mask.

【0013】本発明の樹脂封止型半導体装置の製造方法
は、上述の回路部材の半導体素子搭載用領域に半導体素
子の回路形成面と反対面側を電気的に絶縁して固着する
ことにより搭載する半導体素子搭載工程と、回路部材の
導電性の薄膜と半導体素子の端子とをボンディングワイ
ヤで電気的に接続するワイヤボンディング工程と、前記
薄膜、半導体素子およびボンディングワイヤを樹脂材料
で封止する封止工程と、前記回路部材の基部および柱状
凸部を溶解除去するエッチング工程と、前記柱状凸部が
溶解除去され前記薄膜が露出した状態で形成された凹部
に導電性材料を充填して、前記薄膜からなる内部端子と
前記導電性材料からなる柱状の外部端子とが一体化して
なる端子部を形成する充填工程と、を備えるような構成
とした。
In the method of manufacturing a resin-encapsulated semiconductor device according to the present invention, the semiconductor device is mounted on the above-mentioned circuit member by electrically insulating and fixing the surface opposite to the circuit forming surface of the semiconductor element to the semiconductor element mounting area. A semiconductor element mounting step, a wire bonding step of electrically connecting a conductive thin film of a circuit member and a terminal of the semiconductor element with a bonding wire, and a sealing step of sealing the thin film, the semiconductor element and the bonding wire with a resin material. A stopping step, an etching step of dissolving and removing the base and the columnar protrusion of the circuit member, and filling the recess formed in a state where the columnar protrusion is dissolved and removed and the thin film is exposed with a conductive material, And a filling step of forming a terminal portion in which the internal terminal made of a thin film and the columnar external terminal made of the conductive material are integrated.

【0014】また、本発明の樹脂封止型半導体装置の製
造方法は、前記充填工程において導電性材料として半田
ペーストを使用し、前記凹部に充填した半田ペーストを
固化するために加熱するリフロー工程を有するような構
成とした。
Further, the method of manufacturing a resin-encapsulated semiconductor device according to the present invention includes a reflow step in which a solder paste is used as a conductive material in the filling step, and the solder paste filled in the recess is heated to be solidified. It was configured to have.

【0015】また、本発明の樹脂封止型半導体装置の製
造方法は、回路部材として、半導体素子搭載領域と該領
域に対応した複数の薄膜からなる組み合わせを複数組備
える回路部材を使用し、前記充填工程の後に、各半導体
素子ごとに分離する分離工程を備えるような構成とし
た。
Further, in the method of manufacturing a resin-encapsulated semiconductor device according to the present invention, a circuit member provided with a plurality of combinations of a semiconductor element mounting region and a plurality of thin films corresponding to the region is used as the circuit member. After the filling step, the semiconductor device is provided with a separating step for separating each semiconductor element.

【0016】さらに、本発明の樹脂封止型半導体装置の
製造方法は、前記分離工程が金型を用いた打ち抜き工程
であるような構成、あるいは、ダイサーを用いたダイシ
ング工程であるような構成とした。
Further, in the method of manufacturing a resin-sealed semiconductor device according to the present invention, the separation step may be a punching step using a die or a dicing step using a dicer. did.

【0017】このような本発明では、外部に露出してい
る外部端子の先端側を用いて、樹脂封止型半導体装置を
回路基板に実装することができ、この際の半導体装置の
高さは、従来の半田ボールを用いた実装に比べて低いも
のとなる。また、回路部材の半導体素子搭載用領域は基
板をハーフエッチングして形成されているので、端子部
が配設された空間の略中央に半導体素子を配設すること
ができ、これにより半導体素子の端子と内部端子とを電
気的に接続するボンディングワイヤの長さが短いものと
なる。
According to the present invention, the resin-encapsulated semiconductor device can be mounted on the circuit board by using the distal end of the external terminal exposed to the outside. This is lower than mounting using conventional solder balls. In addition, since the semiconductor element mounting area of the circuit member is formed by half-etching the substrate, the semiconductor element can be disposed substantially at the center of the space in which the terminal portion is disposed. The length of the bonding wire for electrically connecting the terminal and the internal terminal is reduced.

【0018】[0018]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0019】回路部材 図1は本発明の回路部材の一実施形態を示す平面図、図
2は図1に示される回路部材のA−A線における縦断面
図である。図1および図2において、本発明の回路部材
1は、平板状の基部2と、この基部2の一方の面の半導
体素子搭載用領域3の外側に所定のパターンで配設され
た複数の柱状凸部4と、この柱状凸部4の上端面4aに
設けられた導電性の薄膜5とを備えている。
Circuit Member FIG. 1 is a plan view showing an embodiment of the circuit member of the present invention, and FIG. 2 is a longitudinal sectional view taken along line AA of the circuit member shown in FIG. 1 and 2, a circuit member 1 according to the present invention includes a flat base 2 and a plurality of pillars arranged in a predetermined pattern outside a semiconductor element mounting region 3 on one surface of the base 2. The projection includes a convex portion and a conductive thin film provided on an upper end surface of the columnar convex portion.

【0020】基部2と柱状凸部4は共に金属製であり、
柱状凸部4は基部2に一体的に形成されている。基部2
の厚みは、使用する材料に応じて適宜設定することがで
き、例えば、50〜150μm程度とするこができる。
また、柱状凸部4の形状は、図示例では横断面形状が長
方形の角柱であるが、これに限定されるものではない。
このような柱状凸部4の高さは、作製する樹脂封止型半
導体装置の外部端子の高さに対応させて設定することが
でき、例えば、50〜150μmの範囲で設定する。そ
して、複数の柱状凸部4に両側を囲まれるように、長方
形状の半導体素子搭載用領域3(図1に鎖線で囲んで示
した領域)が設けられている。
The base 2 and the columnar projection 4 are both made of metal.
The columnar protrusions 4 are formed integrally with the base 2. Base 2
Can be appropriately set according to the material used, and can be, for example, about 50 to 150 μm.
In the illustrated example, the shape of the columnar protrusion 4 is a rectangular prism having a rectangular cross-sectional shape, but is not limited to this.
The height of such columnar protrusions 4 can be set in accordance with the height of the external terminals of the resin-encapsulated semiconductor device to be manufactured, and is set, for example, in the range of 50 to 150 μm. A rectangular semiconductor element mounting region 3 (a region surrounded by a chain line in FIG. 1) is provided so as to surround both sides of the plurality of columnar protrusions 4.

【0021】このような基部2と柱状凸部4を構成する
金属材料としては、導電性の薄膜5を形成する後述の材
料よりもエッチングが容易な材料を選定することがで
き、例えば、42合金(Ni42%のFe合金)、銅、
銅合金等を挙げることができる。
As the metal material forming the base 2 and the columnar protrusions 4, a material which can be more easily etched than a material described later for forming the conductive thin film 5 can be selected. (Ni 42% Fe alloy), copper,
Copper alloys and the like can be mentioned.

【0022】導電性の薄膜5は、樹脂封止型半導体装置
の内部端子となるものであり、Ag、Pt、Au等の貴
金属単独からなる薄膜、あるいは、これらの貴金属の組
み合わせからなる積層薄膜、さらには、上記の貴金属と
Ni等の金属との積層薄膜(最外層は貴金属層とする)
である。このような薄膜5の厚みは0.5〜10μmの
範囲で設定することができる。
The conductive thin film 5 serves as an internal terminal of the resin-encapsulated semiconductor device, and is a thin film made of a noble metal alone such as Ag, Pt, or Au, or a laminated thin film made of a combination of these noble metals. Furthermore, a laminated thin film of the above noble metal and a metal such as Ni (the outermost layer is a noble metal layer)
It is. The thickness of such a thin film 5 can be set in the range of 0.5 to 10 μm.

【0023】このような回路部材1では、半導体素子搭
載用領域3に半導体素子が搭載された場合、この半導体
素子は柱状凸部4が配設された空間の略中央に位置する
ことになる。
In such a circuit member 1, when a semiconductor element is mounted on the semiconductor element mounting area 3, this semiconductor element is located substantially at the center of the space in which the columnar projections 4 are provided.

【0024】本発明の回路部材1は、図3に示されるよ
うに、基部2の半導体素子搭載用領域3の少なくとも一
部に電気絶縁性の接着部材6を設けたものであってもよ
い。接着部材6は特に制限はなく、電気絶縁性のベース
フィルムの両面に接着剤層を備えたもの、例えば、ユー
ピレックス(宇部興産(株)製の電気絶縁性のベースフ
ィルム)の両面にRXF((株)巴川製紙所製の接着
剤)層を備えたUXIW((株)巴川製紙所製)のよう
な両面接着テープを使用することができる。
As shown in FIG. 3, the circuit member 1 of the present invention may have an electrically insulating adhesive member 6 provided on at least a part of the semiconductor element mounting area 3 of the base 2. The adhesive member 6 is not particularly limited, and includes an electrically insulating base film provided with an adhesive layer on both surfaces thereof, for example, RXF ((UPILEX (electrically insulating base film manufactured by Ube Industries, Ltd.)) on both surfaces. A double-sided adhesive tape such as UXIW (manufactured by Hamakawa Paper Co., Ltd.) having a layer of an adhesive (Hamakawa Paper Co., Ltd.) can be used.

【0025】本発明の回路部材は、上述のような回路部
材が複数連設されたもの、すなわち、半導体素子搭載領
域3と、この領域3に対応した複数の薄膜5からなる組
み合わせを複数組備える回路部材であってもよい。図4
は、このような回路部材を示す断面図である。図4に示
される回路部材1′は、図1および図2に示される回路
部材1が、柱状凸部4の配列方向と直角方向(図の左右
方向)に5個連設されたものである。すなわち、この回
路部材1′は、平板状の基部2と、この基部2の一方の
面に所定のピッチPで設定された5つの半導体素子搭載
用領域3と、各半導体素子搭載用領域3に対応して外側
に所定のパターンで配設された複数の柱状凸部4と、こ
の柱状凸部4の上端面4aに設けられた導電性の薄膜5
とを備えている。さらに、基部2の端部には外枠部材7
が上端面7aに導電性薄膜5を備えた状態で形成されて
いる。尚、上述の回路部材1および回路部材1′におけ
る端子数、端子配列等は例示であり、本発明の回路部材
がこれに限定されないことは勿論である。
The circuit member of the present invention has a plurality of the above-described circuit members connected in series, that is, a plurality of combinations of a semiconductor element mounting area 3 and a plurality of thin films 5 corresponding to the area 3. It may be a circuit member. FIG.
Is a cross-sectional view showing such a circuit member. The circuit member 1 'shown in FIG. 4 is one in which five circuit members 1 shown in FIGS. 1 and 2 are continuously provided in a direction perpendicular to the arrangement direction of the columnar protrusions 4 (the left-right direction in the drawing). . That is, the circuit member 1 ′ includes a flat base 2, five semiconductor element mounting areas 3 set at a predetermined pitch P on one surface of the base 2, and each semiconductor element mounting area 3. Correspondingly, a plurality of columnar protrusions 4 arranged in a predetermined pattern on the outside, and a conductive thin film 5 provided on an upper end surface 4a of the columnar protrusion 4
And Further, an outer frame member 7 is provided at an end of the base 2.
Are formed with the conductive thin film 5 provided on the upper end surface 7a. Note that the number of terminals, the terminal arrangement, and the like in the above-described circuit member 1 and the circuit member 1 'are merely examples, and the circuit member of the present invention is not limited thereto.

【0026】樹脂封止型半導体装置 図5は図1および図2に示される本発明の回路部材を使
用した本発明の樹脂封止型半導体装置の一実施形態を示
す平面図、図6は図5に示される樹脂封止型半導体装置
のB−B線における縦断面図である。尚、樹脂封止型半
導体装置の構成を理解しやすくするために、図5では封
止部材を省略し、その輪郭を仮想線(2点鎖線)で示し
ている。
The resin-sealed semiconductor device Figure 5 is a plan view showing an embodiment of a resin-sealed semiconductor device of the present invention using a circuit member of the invention shown in Figures 1 and 2, FIG. 6 FIG. FIG. 6 is a vertical sectional view of the resin-sealed semiconductor device shown in FIG. 5 taken along line BB. In order to make the configuration of the resin-encapsulated semiconductor device easy to understand, the sealing member is omitted in FIG. 5 and its outline is indicated by a virtual line (two-dot chain line).

【0027】図5および図6において、本発明の樹脂封
止型半導体装置11は、所定の間隔で2列に配列された
複数の端子部12と、端子部12が配列された空間の略
中央に位置する半導体素子15と、半導体素子15の端
子15aと端子部12とを接続するボンディングワイヤ
17と、これらの端子部12とボンディングワイヤ17
および半導体素子15とを封止する封止部材18とを備
えている。
Referring to FIGS. 5 and 6, a resin-sealed semiconductor device 11 according to the present invention includes a plurality of terminal portions 12 arranged in two rows at a predetermined interval, and a substantially central portion of a space in which the terminal portions 12 are arranged. , A bonding wire 17 for connecting the terminal 15 a of the semiconductor element 15 to the terminal portion 12, and a bonding wire 17 for connecting the terminal portion 12 and the bonding wire 17.
And a sealing member 18 for sealing the semiconductor element 15.

【0028】端子部12は、薄膜状の内部端子13と柱
状の外部端子14とを一体的に有するものであり、各端
子部12は内部端子13面を同一方向に向けて略一平面
上に位置するように電気的に独立して配設されている。
内部端子13は、Ag、Pt、Au等の貴金属単独から
なる薄膜、あるいは、これらの貴金属の組み合わせから
なる積層薄膜、さらには、上記の貴金属とNi等の金属
との積層薄膜(最外層は貴金属層とする)であり、厚み
は0.5〜10μm程度である。また、外部端子14
は、封止部材18中に位置する埋没部14aと、樹脂封
止型半導体装置11の裏面に突出するように露出する先
端部14bとからなる。図示例では、埋没部14aは横
断面形状が長方形の角柱であり、先端部14bは長屋根
ドーム状に突出している。この先端部14bの突出量は
50〜150μm程度とすることが好ましい。このよう
な外部端子14は、半田、銅ペースト等の導電性金属材
料により形成され、特に半田が好ましい。
The terminal portions 12 integrally have a thin film-shaped internal terminal 13 and a columnar external terminal 14, and each terminal portion 12 is substantially coplanar with the surface of the internal terminal 13 facing in the same direction. It is electrically independent so as to be located.
The internal terminal 13 is a thin film made of a noble metal such as Ag, Pt, or Au alone, a laminated thin film made of a combination of these noble metals, or a laminated thin film of the above noble metal and a metal such as Ni (the outermost layer is made of a noble metal. And a thickness of about 0.5 to 10 μm. Also, the external terminal 14
Is composed of a buried portion 14a located in the sealing member 18 and a tip portion 14b exposed so as to protrude from the back surface of the resin-sealed semiconductor device 11. In the illustrated example, the buried portion 14a is a rectangular prism having a rectangular cross section, and the tip portion 14b projects in a long roof dome shape. It is preferable that the amount of protrusion of the tip portion 14b is about 50 to 150 μm. Such external terminals 14 are formed of a conductive metal material such as solder or copper paste, and solder is particularly preferable.

【0029】半導体素子15は、上記の複数の端子部1
2が配設された空間の略中央に、回路形成面側が内部端
子13面と同一方向を向くように電気的に独立して配置
されている。そして、各端子部12の内部端子13と半
導体素子15の端子15aとがボンディングワイヤ17
により電気的に接続されている。図示例では、半導体素
子15の回路形成面と反対面側に電気絶縁性の樹脂層1
6が配設されており、この樹脂層16が樹脂封止型半導
体装置11の裏面に露出している。封止部材18は、樹
脂封止型半導体装置に使用されている公知の樹脂材料を
用いて形成することができる。
The semiconductor element 15 includes the plurality of terminal portions 1 described above.
The circuit forming surface 2 is arranged electrically substantially in the center of the space where the 2 is provided, so that the circuit forming surface side faces the same direction as the internal terminal 13 surface. Then, the internal terminal 13 of each terminal portion 12 and the terminal 15 a of the semiconductor element 15 are connected to the bonding wire 17.
Are electrically connected to each other. In the illustrated example, the electrically insulating resin layer 1 is provided on the side opposite to the circuit forming surface of the semiconductor element 15.
The resin layer 16 is exposed on the back surface of the resin-encapsulated semiconductor device 11. The sealing member 18 can be formed using a known resin material used for a resin-sealed semiconductor device.

【0030】このような樹脂封止型半導体装置11で
は、外部端子14の先端部14bが外部に露出している
ので、BGA(Ball Grid Array)タイ
プの半導体装置となっている。そして、この外部端子1
4の先端部14bを用いて回路基板に実装した際の半導
体装置11の高さは、従来の半田ボールを用いた実装に
比べて低いものとなる。これは、先端部14bの突出量
(50〜150μm程度)は、半田ボールの直径(30
0〜750μm程度)よりも小さいことによる。また、
端子部12が配設された空間の略中央に半導体素子15
が配設されているので、内部端子13と半導体素子15
の端子15aとが近接しており、このため内部端子13
と端子15aとを電気的に接続するボンディングワイヤ
17の長さが短いものとなる。尚、上述の樹脂封止型半
導体装置11における端子数、端子配列等は例示であ
り、本発明の樹脂封止型半導体装置がこれに限定されな
いことは勿論である。
The resin-encapsulated semiconductor device 11 is a BGA (Ball Grid Array) type semiconductor device because the tip 14b of the external terminal 14 is exposed to the outside. And this external terminal 1
The height of the semiconductor device 11 when it is mounted on a circuit board using the tip 14b of No. 4 is lower than that of a conventional mounting using solder balls. This is because the amount of protrusion of the tip portion 14b (about 50 to 150 μm) depends on the diameter of the solder ball (30 μm).
(About 0 to 750 μm). Also,
A semiconductor element 15 is provided substantially at the center of the space in which the terminal portion 12 is provided.
Are provided, the internal terminal 13 and the semiconductor element 15
Of the internal terminal 13a.
The length of the bonding wire 17 for electrically connecting the terminal 15a to the terminal 15a is short. The number of terminals, terminal arrangement, and the like in the above-described resin-sealed semiconductor device 11 are examples, and the resin-sealed semiconductor device of the present invention is not limited to this.

【0031】回路部材の製造方法 次に、本発明の回路部材の製造方法について説明する。The method of manufacturing a circuit member Next, a method for manufacturing a circuit member of the present invention.

【0032】図7は、図4に示される本発明の回路部材
1′を例とした本発明の回路部材の製造方法の一実施形
態を示す工程図である。各工程は、上記の図4に対応す
る回路部材の縦断面図で示してある。
FIG. 7 is a process chart showing one embodiment of a method for manufacturing a circuit member of the present invention using the circuit member 1 'of the present invention shown in FIG. 4 as an example. Each step is shown in a longitudinal sectional view of the circuit member corresponding to FIG. 4 described above.

【0033】図7において、まず、パターン形成工程と
して、金属製の基板21の表面に耐めっき性をもつ感光
性レジストを塗布、乾燥してレジスト層22を形成し、
基板21の裏面に耐めっき性をもつフィルム23を固着
する(図7(A))。次に、レジスト層22を所望のフ
ォトマスクを介して露光した後、現像してレジストパタ
ーン22′を形成する(図7(B))。基板21として
は、次の薄膜形成工程で形成する薄膜よりもエッチング
が容易な材料を選定することができ、例えば、42合金
(Ni41%のFe合金)、銅、銅合金等の金属基板
(厚み100〜250μm)を使用することができる。
この基板21は、両面を脱脂等を行い洗浄処理を施した
ものを使用することが好ましい。また、耐めっき性をも
つ感光性レジストとしては、例えば、旭化成(株)製D
FR サンフォートAQ等を挙げることができ、耐めっ
き性をもつフィルム23としては、例えば、日東電工
(株)製リバアルファ(熱剥離フィルム)等のフィルム
を挙げることができる。
In FIG. 7, first, as a pattern forming step, a photosensitive resist having plating resistance is applied to the surface of a metal substrate 21 and dried to form a resist layer 22.
A film 23 having plating resistance is fixed to the back surface of the substrate 21 (FIG. 7A). Next, the resist layer 22 is exposed through a desired photomask and then developed to form a resist pattern 22 '(FIG. 7B). As the substrate 21, a material that can be more easily etched than a thin film formed in the next thin film forming step can be selected. For example, a metal substrate (thickness: 42 alloy (Ni 41% Fe alloy), copper, copper alloy, or the like) 100-250 μm) can be used.
As the substrate 21, it is preferable to use a substrate which has been subjected to a cleaning treatment after degreasing both surfaces. Further, as a photosensitive resist having plating resistance, for example, D-manufactured by Asahi Kasei Corporation
FR Sunfort AQ and the like can be mentioned, and as the film 23 having plating resistance, for example, a film such as Riba Alpha (thermal release film) manufactured by Nitto Denko Corporation can be mentioned.

【0034】次いで、薄膜形成工程において、上記のレ
ジストパターン22′とフィルム23をマスクとして、
基板21の露出面に導電性の薄膜5を形成する(図7
(C))。この薄膜5は、通常、電気めっきにより形成
され、Ag、Pt、Au等の貴金属単独からなる薄膜、
あるいは、これらの貴金属の組み合わせからなる積層薄
膜、さらには、上記の貴金属とNi等の金属との積層薄
膜(最外層は貴金属層とする)である。このような薄膜
5の厚みは0.5〜10μmの範囲で設定することがで
きる。
Next, in the thin film forming step, using the resist pattern 22 'and the film 23 as a mask,
The conductive thin film 5 is formed on the exposed surface of the substrate 21 (FIG. 7).
(C)). The thin film 5 is usually formed by electroplating, and is made of a noble metal such as Ag, Pt, or Au alone.
Alternatively, it is a laminated thin film composed of a combination of these noble metals, or a laminated thin film of the above-mentioned noble metal and a metal such as Ni (the outermost layer is a noble metal layer). The thickness of such a thin film 5 can be set in the range of 0.5 to 10 μm.

【0035】次に、エッチング工程において、上記のレ
ジストパターン22′を剥離除去することにより露出し
た基板21を、薄膜5と耐めっき性をもつフィルム23
をマスクとして腐蝕液でエッチングを行う(図7
(D))。腐蝕液は、基板21の材質に応じて塩化第二
鉄水溶液や過硫酸アンモニウム等を使用し、例えば、基
板21の両面からスプレーエッチングにて行うことがで
きる。このエッチング工程におけるエッチング量は、回
路部材1′の柱状凸部4の高さを決定するものであり、
基板21の厚さ方向で貫通しないエッチング量とされ、
いわゆるハーフエッチングが行われる。次いで、耐めっ
き性をもつフィルム23を剥離することにより、図4に
示されるような回路部材1′が得られる。
Next, in the etching step, the substrate 21 exposed by peeling and removing the resist pattern 22 ′ is separated from the thin film 5 and the film 23 having plating resistance.
Etching is performed with a corrosive solution using as a mask (FIG. 7
(D)). The corrosive liquid can be, for example, spray-etched from both surfaces of the substrate 21 using an aqueous solution of ferric chloride, ammonium persulfate, or the like depending on the material of the substrate 21. The amount of etching in this etching step determines the height of the columnar convex portion 4 of the circuit member 1 '.
The etching amount does not penetrate in the thickness direction of the substrate 21,
So-called half etching is performed. Next, the circuit member 1 ′ as shown in FIG. 4 is obtained by peeling the film 23 having plating resistance.

【0036】樹脂封止型半導体装置の製造方法 次に、本発明の樹脂封止型半導体装置の製造方法につい
て説明する。図8は、図5および図6に示される本発明
の樹脂封止型半導体装置を図4に示される本発明の回路
部材1′を用いて製造する方法の一実施形態を示す工程
図である。各工程は、上記の図4に対応する縦断面図で
示してある。
Next, a method for manufacturing the resin-sealed semiconductor device of the present invention will be described. FIG. 8 is a process chart showing one embodiment of a method for manufacturing the resin-sealed semiconductor device of the present invention shown in FIGS. 5 and 6 using the circuit member 1 'of the present invention shown in FIG. . Each step is shown in a vertical sectional view corresponding to FIG. 4 described above.

【0037】図8において、まず、回路部材1′の各半
導体素子搭載領域3に、電気絶縁性の接着部材6(例え
ば、電気絶縁性のベースフィルムの両面に接着剤層を備
えたテープ等)を介して半導体素子15を搭載する(図
8(A)半導体素子搭載工程)。
In FIG. 8, first, an electrically insulating adhesive member 6 (for example, a tape having an adhesive layer on both sides of an electrically insulating base film) is provided on each semiconductor element mounting area 3 of the circuit member 1 '. The semiconductor element 15 is mounted via the process (FIG. 8A).

【0038】次に、搭載した半導体素子15の端子15
aと回路部材1′の導電性の薄膜5とを、ボンディング
ワイヤ17で電気的に接続する(図8(B)ワイヤボン
ディング工程)。
Next, the terminal 15 of the mounted semiconductor element 15
a and the conductive thin film 5 of the circuit member 1 'are electrically connected by the bonding wires 17 (FIG. 8 (B) wire bonding step).

【0039】次いで、回路部材1′の薄膜5と半導体素
子15およびボンディングワイヤ17とを樹脂材料18
により封止する(図8(C)封止工程)。
Next, the thin film 5 of the circuit member 1 ′, the semiconductor element 15 and the bonding wires 17 are
(FIG. 8 (C) sealing step).

【0040】次に、上記の樹脂材料18で覆われていな
い回路部材1′の裏面側から基部2と柱状凸部4を腐蝕
液により溶解除去する(図8(D)エッチング工程)。
このエッチング工程によって柱状凸部4が溶解除去され
て出現した凹部内には、薄膜5が露出している。
Next, the base 2 and the columnar projections 4 are dissolved and removed with a corrosive liquid from the back side of the circuit member 1 'not covered with the resin material 18 (FIG. 8D etching step).
The thin film 5 is exposed in a concave portion that appears after the columnar convex portion 4 is dissolved and removed by this etching process.

【0041】上記のエッチング工程で出現した凹部内に
導電材料を充填して、柱状の外部端子14を形成する
(図8(E)充填工程)。導電材料の充填は、例えば、
導電材料として半田ペーストを使用し、スクリーン印刷
法により行うことができる。この場合、凹部に充填した
半田ペーストを固化するために加熱するリフロー工程を
付加することができる。このようにして形成された外部
端子14は、柱状であり、樹脂材料(封止部材)18中
に位置する埋没部14aと、外部に突出するように露出
する先端部14bをもち、埋没部14aの先端は、回路
部材1′の薄膜5と一体となっており、この薄膜5が内
部端子13となる。これにより、薄膜状の内部端子13
と柱状の外部端子14とを一体的に有する端子部12が
形成される。
A conductive material is filled in the concave portions appearing in the above etching step to form columnar external terminals 14 (FIG. 8 (E) filling step). The filling of the conductive material, for example,
It can be performed by a screen printing method using a solder paste as a conductive material. In this case, a reflow step of heating to solidify the solder paste filled in the concave portion can be added. The external terminal 14 thus formed has a columnar shape and has a buried portion 14a located in a resin material (sealing member) 18 and a tip portion 14b exposed so as to protrude to the outside. Is integrated with the thin film 5 of the circuit member 1 ′, and this thin film 5 becomes the internal terminal 13. Thereby, the thin-film internal terminal 13
And a terminal portion 12 integrally formed with the external terminal 14 having a columnar shape.

【0042】図1および図2に示されるような回路部材
1(半導体素子搭載領域3と、この領域3に対応した複
数の薄膜5からなる組み合わせを1組備えたもの)を使
用した場合、上記の充填工程により外部端子14を形成
した段階で、図5および図6に示される本発明の樹脂封
止型半導体装置11が得られる。
When a circuit member 1 (a combination of a semiconductor element mounting area 3 and a plurality of thin films 5 corresponding to the area 3 is provided) as shown in FIGS. When the external terminals 14 are formed by the filling step, the resin-sealed semiconductor device 11 of the present invention shown in FIGS. 5 and 6 is obtained.

【0043】一方、上述したような回路部材1′(半導
体素子搭載領域3と、この領域3に対応した複数の薄膜
5からなる組み合わせを複数組備える回路部材)を使用
する場合、次に、各半導体素子ごとに分離することによ
り、図5および図6に示される本発明の樹脂封止型半導
体装置11が得られる。このような分離工程では、各半
導体素子に対応した領域の境界(図8(E)に矢印で示
される部位)で個々の半導体装置に分離し、また、外枠
部材7を除去する。この分離工程は、金型を用いた打ち
抜き、あるいは、ダイサーを用いたダイシングにより行
うことができる。
On the other hand, when the above-described circuit member 1 '(a circuit member having a plurality of combinations of the semiconductor element mounting region 3 and the plurality of thin films 5 corresponding to the region 3) is used, By separating each semiconductor element, the resin-sealed semiconductor device 11 of the present invention shown in FIGS. 5 and 6 is obtained. In such a separation step, the semiconductor device is separated into individual semiconductor devices at the boundary of the region corresponding to each semiconductor element (the part indicated by an arrow in FIG. 8E), and the outer frame member 7 is removed. This separation step can be performed by punching using a mold or dicing using a dicer.

【0044】[0044]

【実施例】次に、具体的な実施例を挙げて本発明を更に
詳細に説明する。
Next, the present invention will be described in more detail with reference to specific examples.

【0045】(回路部材の作製)金属製の基板として厚
み0.125mmの銅合金板(古河電気工業(株)製E
FTEC64T−1/2H)を準備し、脱脂処理、洗浄
処理を行った。次に、この銅合金板の表面側に、耐めっ
き性のある紫外線硬化型レジストフィルム(旭化成
(株)製 サンフォートAQ 厚み25μm)を貼り付
け、銅合金板の裏面側に、耐めっき性のある樹脂フィル
ム(日東電工(株)製 リバアルファ)を貼り付けた。
次に、表面側のレジストフィルムを所定のフォトマスク
を介して露光した後、現像してレジストパターンを形成
した。(以上、パターン形成工程)
(Preparation of Circuit Member) A copper alloy plate having a thickness of 0.125 mm (made by Furukawa Electric Co., Ltd.) was used as a metal substrate.
FTEC64T-1 / 2H) was prepared, and degreased and washed. Next, a plating-resistant UV-curable resist film (Sunfort AQ, thickness 25 μm, manufactured by Asahi Kasei Corporation) is attached to the front side of the copper alloy sheet, and the plating-resistant A resin film (Riba Alpha manufactured by Nitto Denko Corporation) was attached.
Next, the resist film on the front side was exposed through a predetermined photomask, and then developed to form a resist pattern. (The above is the pattern forming process)

【0046】次いで、銅合金板の表面のレジストパター
ンと裏面の樹脂フィルムをマスクとして、銅合金板の露
出面に1μmのPdめっき層、5μmのNiめっき層、
1μmのPdめっき層の3層構造からなる導電性の薄膜
を形成した。(以上、薄膜形成工程)
Next, using the resist pattern on the front surface of the copper alloy plate and the resin film on the back surface as a mask, a 1 μm Pd plating layer and a 5 μm Ni plating layer were formed on the exposed surface of the copper alloy plate.
A conductive thin film having a three-layer structure of a 1 μm Pd plating layer was formed. (The above is the thin film forming process)

【0047】次に、表面側のレジストパターンを剥離除
去し、上記の薄膜と耐めっき性をもつ樹脂フィルムをマ
スクとして銅合金板のエッチングを行った。このエッチ
ングは腐蝕液として過硫酸アンモニウムを使用し、エッ
チング量は導電性の薄膜の間に露出している銅合金板の
エッチング深さが100μmとなるハーフエッチングと
した。(以上、エッチング工程)
Next, the resist pattern on the surface side was peeled off and the copper alloy plate was etched using the thin film and the resin film having plating resistance as a mask. In this etching, ammonium persulfate was used as a corrosive solution, and the amount of etching was half etching in which the etching depth of the copper alloy plate exposed between the conductive thin films was 100 μm. (The above is the etching process)

【0048】次いで、ホットプレート上で加熱(150
℃、1分間)して裏面側の樹脂フィルムを剥離し、図4
に示されるような回路部材を得た。この回路部材は、高
さ100μmの複数の柱状凸部と、この柱状凸部の上端
面に設けられた厚み7μmの導電性薄膜を備えたもので
ある。
Next, heating on a hot plate (150
(° C., 1 minute) to peel off the resin film on the back side.
As a result, a circuit member was obtained. This circuit member is provided with a plurality of columnar projections having a height of 100 μm and a conductive thin film having a thickness of 7 μm provided on the upper end surface of the columnar projections.

【0049】(半導体装置の作製)上述のように作製し
た回路部材の半導体素子搭載領域に、電気絶縁性のダイ
アタッチフィルム(日本ゴアテックス(株)製アブソー
ボンド)を介して半導体素子(厚み約0.25mm)の
回路形成面の反対側を固着して半導体素子を搭載した。
(以上、半導体素子搭載工程)
(Preparation of Semiconductor Device) The semiconductor element (about 0 thickness) was placed on the semiconductor element mounting area of the circuit member prepared as described above via an electrically insulating die attach film (Asosorbon, manufactured by Nippon Gore-Tex Co., Ltd.). .25 mm), and the semiconductor element was mounted on the opposite side of the circuit formation surface.
(The above is the semiconductor element mounting process)

【0050】次いで、回路部材の導電性薄膜と、搭載し
た半導体素子(厚み0.25mm)の端子とを金ワイヤ
ー(田中電子工業(株)製 FA−30)により結線し
た。この場合、回路部材の薄膜と半導体素子の端子との
段差は185μmであった。(以上、ワイヤボンディン
グ工程)
Next, the conductive thin film of the circuit member and the terminal of the mounted semiconductor element (0.25 mm in thickness) were connected by a gold wire (FA-30 manufactured by Tanaka Electronics Industry Co., Ltd.). In this case, the step between the thin film of the circuit member and the terminal of the semiconductor element was 185 μm. (The above is the wire bonding process)

【0051】次に、回路部材の導電性薄膜と半導体素子
と金ワイヤーを樹脂材料(日東電工(株)製MP−74
00)で封止した。(以上、封止工程)
Next, the conductive thin film of the circuit member, the semiconductor element, and the gold wire are made of a resin material (MP-74 manufactured by Nitto Denko Corporation).
00). (The above is the sealing process)

【0052】その後、樹脂材料で覆われていない回路部
材の裏面側から過硫酸アンモニウムを使用して回路部材
のエッチングを行った。このエッチングは、回路部材の
柱状凸部が溶解除去されて導電性薄膜が露出するまでと
した。(以上、エッチング工程)
Thereafter, the circuit member was etched with ammonium persulfate from the back side of the circuit member not covered with the resin material. This etching was performed until the column-shaped convex portions of the circuit member were dissolved and removed to expose the conductive thin film. (The above is the etching process)

【0053】次いで、エッチング工程で形成した凹部内
に半田ペーストをスクリーン印刷法で充填し、加熱(2
30℃、2分間)によるリフロー工程で固化して外部端
子を形成した。この外部端子は、上記の樹脂材料からな
る封止部材中に埋没して導電性薄膜(内部端子)と一体
化する柱状の埋没部(高さ100μm)と、外部に約5
0μm突出する先端部をもつものであった。(以上、充
填工程)
Next, a solder paste is filled into the recesses formed in the etching step by screen printing, and heated (2).
(30 ° C., 2 minutes) to form an external terminal by solidification. The external terminal has a columnar buried portion (height: 100 μm) buried in the sealing member made of the above resin material and integrated with the conductive thin film (internal terminal).
It had a tip protruding 0 μm. (The above is the filling process)

【0054】次に、ダイサーで所望の位置で断裁して個
々の半導体装置を得た。このようにして作製した個々の
樹脂封止型半導体装置は、外部端子数が16ピンであ
り、その外形寸法は5mm四方、厚みが0.5mmであ
り、非常に小型で薄いものであった。
Next, individual semiconductor devices were obtained by cutting at desired positions with a dicer. Each of the resin-sealed semiconductor devices manufactured in this manner had 16 external pins, external dimensions of 5 mm square and a thickness of 0.5 mm, and were extremely small and thin.

【0055】この樹脂封止型半導体装置を、半田ボール
を使用しないで回路基板に実装し、温度サイクル試験
(−45℃から+125℃までの温度変化を60分サイ
クルで繰り返す)を実施した結果、500サイクル経過
しても何ら問題は生じなかった。
This resin-encapsulated semiconductor device was mounted on a circuit board without using solder balls, and subjected to a temperature cycle test (a temperature change from −45 ° C. to + 125 ° C. was repeated in a 60-minute cycle). No problems occurred after 500 cycles.

【0056】[0056]

【発明の効果】以上詳述したように、本発明によれば半
導体素子の占有率が高くなり小型化が可能となって回路
基板への実装密度を向上させることができ、この回路基
板の実装は樹脂封止型半導体装置の外部に露出している
外部端子の先端側を用いて行うことができるので、従来
の半田ボールを用いたBGA(Ball Grid A
rray)タイプの半導体装置と同様の実装作業性が得
られるとともに、半田ボールを使用する場合に比べて実
装された半導体装置の高さを低くすることができる。ま
た、半田ボールの搭載装置や搭載用マスクおよび半田ボ
ールが不要となるので、製造コストの低減が可能であ
る。さらに、半導体素子の端子と内部端子とを電気的に
接続するボンディングワイヤの長さが従来の半導体装置
に比べて短いものとなる。そして、本発明の回路部材を
使用することにより、上記のような効果を奏する樹脂封
止型半導体装置を容易に作製することができ、このよう
な本発明の回路部材および半導体装置は、本発明の製造
方法により簡便に製造することができる。
As described in detail above, according to the present invention, the occupancy of the semiconductor element is increased, the size of the semiconductor element can be reduced, and the mounting density on the circuit board can be improved. Can be performed using the front end side of the external terminal exposed to the outside of the resin-encapsulated semiconductor device, so that a BGA (Ball Grid A) using a conventional solder ball can be used.
The same mounting workability as that of the (rray) type semiconductor device can be obtained, and the height of the mounted semiconductor device can be reduced as compared with the case where solder balls are used. Further, since a solder ball mounting device, a mounting mask, and a solder ball are not required, manufacturing costs can be reduced. Further, the length of the bonding wire for electrically connecting the terminal of the semiconductor element and the internal terminal is shorter than that of a conventional semiconductor device. By using the circuit member of the present invention, a resin-sealed semiconductor device having the above-described effects can be easily manufactured. Can be easily produced by the production method described above.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の回路部材の一実施形態を示す平面図で
ある。
FIG. 1 is a plan view showing one embodiment of a circuit member of the present invention.

【図2】図1に示される回路部材のA−A線における縦
断面図である。
FIG. 2 is a longitudinal sectional view of the circuit member shown in FIG. 1 taken along line AA.

【図3】本発明の回路部材の他の実施形態を示す縦断面
図である。
FIG. 3 is a longitudinal sectional view showing another embodiment of the circuit member of the present invention.

【図4】本発明の回路部材の他の実施形態を示す縦断面
図である。
FIG. 4 is a longitudinal sectional view showing another embodiment of the circuit member of the present invention.

【図5】図1に示される本発明の回路部材を使用した本
発明の樹脂封止型半導体装置の一実施形態を示す平面図
である。
FIG. 5 is a plan view showing one embodiment of the resin-sealed semiconductor device of the present invention using the circuit member of the present invention shown in FIG. 1;

【図6】図5に示される樹脂封止型半導体装置のB−B
線における縦断面図である。
FIG. 6 is a cross-sectional view of the resin-sealed semiconductor device shown in FIG.
It is a longitudinal cross-sectional view in a line.

【図7】本発明の回路部材の製造方法の一実施形態を示
す工程図である。
FIG. 7 is a process chart showing one embodiment of a method for manufacturing a circuit member of the present invention.

【図8】本発明の樹脂封止型半導体装置の製造方法の一
実施形態を示す工程図である。
FIG. 8 is a process chart showing one embodiment of a method for manufacturing a resin-sealed semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

1,1´…回路部材 2…基部 3…半導体素子搭載領域 4…柱状凸部 5…導電性の薄膜 6…電気絶縁性の接着部材 11…樹脂封止型半導体装置 12…端子部 13…内部端子 14…外部端子 15…半導体素子 17…ボンディングワイヤ 18…封止部材 21…金属製基板 22′…レジストパターン 1, 1 '... circuit member 2 ... base 3 ... semiconductor element mounting area 4 ... columnar convex part 5 ... conductive thin film 6 ... electrically insulating adhesive member 11 ... resin-sealed semiconductor device 12 ... terminal part 13 ... inside Terminal 14: External terminal 15: Semiconductor element 17: Bonding wire 18: Sealing member 21: Metal substrate 22 ': Resist pattern

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 薄膜状の内部端子と柱状の外部端子とを
一体的に有する複数の端子部が前記内部端子面を同一方
向に向けて略一平面上に位置するように電気的に独立し
て配設され、該端子部が配設された空間の略中央に回路
形成面側が前記内部端子面と同一方向を向くように半導
体素子が電気的に独立して配置され、各端子部の内部端
子と半導体素子の端子とがボンディングワイヤにより電
気的に接続され、各端子部の外部端子の先端側を外部に
露出させるように前記端子部、半導体素子およびボンデ
ィングワイヤが封止部材により封止されていることを特
徴とする樹脂封止型半導体装置。
A plurality of terminal portions integrally having a thin film-shaped internal terminal and a columnar external terminal are electrically independent so that the internal terminal faces face in the same direction and are located on substantially one plane. The semiconductor elements are electrically independently arranged so that the circuit forming surface side faces the same direction as the internal terminal surface at substantially the center of the space in which the terminal portions are disposed. The terminal, the semiconductor element, and the bonding wire are sealed by a sealing member so that the terminal and the terminal of the semiconductor element are electrically connected by a bonding wire, and the distal end side of the external terminal of each terminal is exposed to the outside. A resin-sealed semiconductor device.
【請求項2】 前記半導体素子の回路形成面と反対面側
に電気絶縁性の樹脂層を有し、該樹脂層が裏面側に露出
していることを特徴とする請求項1に記載の樹脂封止型
半導体装置。
2. The resin according to claim 1, further comprising an electrically insulating resin layer on a surface of the semiconductor element opposite to a circuit forming surface, wherein the resin layer is exposed on a back surface side. Sealed semiconductor device.
【請求項3】 金属製の平板状の基部と、該基部の一方
の面の半導体素子搭載用領域の外側に所定のパターンで
配設された複数の金属製の柱状凸部と、該柱状凸部の上
端面に設けられた導電性の薄膜と、を備えることを特徴
とする回路部材。
3. A metal plate-shaped base, a plurality of metal columnar protrusions arranged in a predetermined pattern outside a semiconductor element mounting region on one surface of the base, and the columnar protrusions. A conductive thin film provided on an upper end surface of the portion.
【請求項4】 前記基部の半導体素子搭載用領域の少な
くとも一部に電気絶縁性の接着部材が設けられているこ
とを特徴とする請求項3に記載の回路部材。
4. The circuit member according to claim 3, wherein an electrically insulating adhesive member is provided on at least a part of the semiconductor element mounting region of the base.
【請求項5】 金属製の基板にレジストパターンを形成
するパターン形成工程と、 基板の露出面に導電性の薄膜を形成する薄膜形成工程
と、 前記レジストパターンを剥離除去し、前記薄膜をマスク
として前記基板をハーフエッチングするエッチング工程
と、を有することを特徴とする回路部材の製造方法。
5. A pattern forming step of forming a resist pattern on a metal substrate, a thin film forming step of forming a conductive thin film on an exposed surface of the substrate, and the resist pattern is peeled off and the thin film is used as a mask. An etching step of half-etching the substrate.
【請求項6】 請求項3または請求項4に記載の回路部
材の半導体素子搭載用領域に半導体素子の回路形成面と
反対面側を電気的に絶縁して固着することにより搭載す
る半導体素子搭載工程と、 回路部材の導電性の薄膜と半導体素子の端子とをボンデ
ィングワイヤで電気的に接続するワイヤボンディング工
程と、 前記薄膜、半導体素子およびボンディングワイヤを樹脂
材料で封止する封止工程と、 前記回路部材の基部および柱状凸部を溶解除去するエッ
チング工程と、 前記柱状凸部が溶解除去され前記薄膜が露出した状態で
形成された凹部に導電性材料を充填して、前記薄膜から
なる内部端子と前記導電性材料からなる柱状の外部端子
とが一体化してなる端子部を形成する充填工程と、を備
えることを特徴とする樹脂封止型半導体装置の製造方
法。
6. A semiconductor element mounting device which is mounted by electrically insulating and fixing a surface opposite to a circuit forming surface of a semiconductor device to a semiconductor element mounting region of the circuit member according to claim 3 or 4. A wire bonding step of electrically connecting the conductive thin film of the circuit member and the terminal of the semiconductor element with a bonding wire, a sealing step of sealing the thin film, the semiconductor element and the bonding wire with a resin material, An etching step of dissolving and removing the base and the columnar protrusions of the circuit member; and filling a recess formed in a state where the columnar protrusions are dissolved and removed and exposing the thin film with a conductive material to form an inner portion formed of the thin film. A filling step of forming a terminal portion in which the terminal and the columnar external terminal made of the conductive material are integrated. Method.
【請求項7】 前記充填工程は、導電性材料として半田
ペーストを使用し、前記凹部に充填した半田ペーストを
固化するために加熱するリフロー工程を有することを特
徴とする請求項6に記載の樹脂封止型半導体装置の製造
方法。
7. The resin according to claim 6, wherein the filling step uses a solder paste as a conductive material, and includes a reflow step of heating the solder paste filled in the concave portion so as to solidify the solder paste. A method for manufacturing a sealed semiconductor device.
【請求項8】 回路部材として、半導体素子搭載領域と
該領域に対応した複数の薄膜からなる組み合わせを複数
組備える回路部材を使用し、前記充填工程の後に、各半
導体素子ごとに分離する分離工程を備えることを特徴と
する請求項6または請求項7に記載の樹脂封止型半導体
装置の製造方法。
8. A separating step of using a circuit member having a plurality of combinations of a semiconductor element mounting area and a plurality of thin films corresponding to the area as a circuit member, and separating the semiconductor element for each semiconductor element after the filling step. The method of manufacturing a resin-encapsulated semiconductor device according to claim 6, further comprising:
【請求項9】 前記分離工程は、金型を用いた打ち抜き
工程であることを特徴とする請求項8に記載の樹脂封止
型半導体装置の製造方法。
9. The method according to claim 8, wherein the separating step is a punching step using a mold.
【請求項10】 前記分離工程は、ダイサーを用いたダ
イシング工程であることを特徴とする請求項8に記載の
樹脂封止型半導体装置の製造方法。
10. The method for manufacturing a resin-encapsulated semiconductor device according to claim 8, wherein the separation step is a dicing step using a dicer.
JP13670599A 1999-05-18 1999-05-18 Manufacturing method of resin-encapsulated semiconductor device Expired - Lifetime JP3992877B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100405948B1 (en) * 2001-03-16 2003-11-14 황길남 Semiconductor chip package and manufacturing method thereof
JP2009049442A (en) * 2008-12-04 2009-03-05 Dainippon Printing Co Ltd Semiconductor device
JP2016201384A (en) * 2015-04-07 2016-12-01 Shマテリアル株式会社 Semiconductor element mounting substrate, semiconductor device and manufacturing methods for those
JP2019057587A (en) * 2017-09-20 2019-04-11 大口マテリアル株式会社 Substrate for mounting semiconductor element thereon and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100405948B1 (en) * 2001-03-16 2003-11-14 황길남 Semiconductor chip package and manufacturing method thereof
JP2009049442A (en) * 2008-12-04 2009-03-05 Dainippon Printing Co Ltd Semiconductor device
JP2016201384A (en) * 2015-04-07 2016-12-01 Shマテリアル株式会社 Semiconductor element mounting substrate, semiconductor device and manufacturing methods for those
JP2019057587A (en) * 2017-09-20 2019-04-11 大口マテリアル株式会社 Substrate for mounting semiconductor element thereon and method of manufacturing the same
TWI787343B (en) * 2017-09-20 2022-12-21 日商大口電材股份有限公司 Substrate for mounting semiconductor element and manufacturing method thereof

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