JP2000294881A - Element isolation structure and light emitting element array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size (width and depth) of an element isolation region. SOLUTION: A semi-insulating semiconductor layer (for example, a semi- insulating AlGaAs epitaxial layer) 2 is formed on a semiconductor substrate layer (for example, a GaAs substrate layer) 1 in this semiconductor substrate. Then, first conductive impurity (for example, Sn being n type impurity or Zn being p type impurity) is selectively thermally diffused on the semi-insulating semiconductor layer 2. Thus, a plurality of element region blocks 4 constituted of the first conductive diffused regions can be formed so that element isolation regions 3 constituted of semi-insulating regions can remain between the boundaries.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an element isolation structure in which a plurality of conductive element regions insulated and separated from each other are formed in a semiconductor layer, and to a light emitting element array using the above element isolation structure. Things.

[0002]

2. Description of the Related Art A light emitting element array has a plurality of light emitting elements linearly arranged at regular intervals.
A light emitting element array using an ED (light emitting diode)
It is called an ED array.

FIG. 37 is a diagram showing an example of the structure of a conventional LED array. The LED array of FIG.
An n-type GaAsP epitaxial layer 1 on an s substrate 101
02, a plurality of p-type diffusion regions (light-emitting portions) 113 are formed in the GaAsP layer 102 at equal intervals, and the p-side electrode 1 is formed.
14 and an n-side electrode 115 are provided. Such an LED array is used as a light source of an optical printer.

Further, there is an LED array having a multilayer wiring structure for the purpose of reducing the number of electrode pads.

A multilayer wiring type LED array uses a semiconductor substrate in which, for example, an n-type semiconductor layer is formed on a high-resistance substrate layer, and forms M element regions by forming element isolation regions in the n-type semiconductor layer. By electrically separating into blocks and selectively diffusing p-type impurities through a diffusion mask, N p-type diffusion regions (light-emitting portions) of the LED are formed in each block, and p-type diffusion regions are formed. N pieces of p-side electrode wirings individually connected to the region are formed in each block, a p-side electrode pad is integrally formed at an end of the selected p-side electrode wiring, and an n-side electrode connecting to the n-type semiconductor layer is formed. An electrode is formed in each of the M blocks, an interlayer insulating film for forming a multilayer wiring structure is formed, and a second-layer wiring for connecting p-side electrode wirings formed in different blocks is formed with the above-mentioned interlayer insulating film. With the one formed above That.

Conventional element isolation structures for insulating and isolating, for example, an n-type semiconductor layer formed on a high-resistance substrate layer into a plurality of element region blocks include pn junction isolation and air isolation. In the pn junction isolation, an element isolation region including a p-type diffusion region is provided in an n-type semiconductor layer by a thermal diffusion method or the like so as to reach a high-resistance substrate layer. On the other hand, in the air separation, an element isolation groove reaching the high-resistance substrate layer is provided in an n-type semiconductor layer by an etching method or the like.

[0007]

The pitch of the light emitting portion of the LED array is currently 600 [dpi] or 1200 [dpi].
[Dpi], but it is expected that the density will be further increased in the future. If the light emitting unit pitch is further increased in the future, the width of the element isolation region must be narrowed. Therefore, in the above-described conventional element isolation structure, the element isolation region becomes close to the element isolation region due to the proximity of the element isolation region to the light emitting unit. However, there is a possibility that the light emitting characteristics of the device may be deteriorated, and the reliability of the wiring formation on the device isolation groove may be reduced due to the formation of the narrow and deep device isolation groove. For this reason, it is desired to develop an element isolation structure that can cope with a higher density of the light emitting unit pitch.

The present invention has been made to solve such a conventional problem, and has an element isolation structure capable of forming an element isolation region having a small size (width and depth) and a structure using the element isolation structure. It is an object of the present invention to provide a light-emitting element array that has been manufactured.

[0009]

In order to achieve the above object, an element isolation structure according to the present invention comprises: a plurality of element regions which are insulated and separated from each other in a semiconductor layer; Is semi-insulating, by selectively doping impurities into this semi-insulating semiconductor layer,
A plurality of element regions are formed such that a semi-insulating region remains at a boundary between each other.

According to another aspect of the present invention, there is provided an element isolation structure in which a plurality of element regions which are insulated and separated from each other are formed in a semiconductor layer, wherein the semiconductor layer is semi-insulating. A plurality of element regions by selectively doping a conductive semiconductor layer with a first conductivity type impurity, and selectively doping a second conductivity type impurity at a boundary between adjacent element regions. The feature is that an isolation region of the second conductivity type is formed so as to include all the overlapping portions of both element regions.

According to still another aspect of the present invention, there is provided an element isolation structure in which a plurality of element regions insulated and separated from each other are formed in a semiconductor layer, wherein the semiconductor layer is semi-insulating. By selectively doping impurities into the insulating semiconductor layer, a plurality of element regions are formed,
An isolation groove is formed at a boundary between adjacent element regions so as to include all the overlapped portions of both element regions.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a diagram showing an element isolation structure according to a first embodiment of the present invention. In the element isolation structure shown in FIG. 1, the element of the first conductivity type is selectively thermally diffused into the semi-insulating semiconductor layer 2, so that an element isolation region 3 composed of a semi-insulating region remains at the boundary between the two. In this manner, a plurality of element region blocks 4 each formed of a diffusion region of the first conductivity type are formed. First
In the embodiment, the width of the element isolation region can be made very narrow, and the element can be isolated in a planar type.

As shown in FIG. 1, in the first embodiment, a semiconductor substrate having a semi-insulating semiconductor layer 2 formed on a semiconductor substrate layer 1 is used. For example, a semi-insulating A
A semiconductor substrate obtained by epitaxially growing an lGaAs layer is used. The semiconductor substrate layer 1 is semi-insulating, n-type, p-type.
Any of the types may be used. Further, the semi-insulating semiconductor layer 2 may be a semi-insulating GaAs layer according to a desired emission wavelength,
Alternatively, an AlGaAs layer having a laminated structure of a clad layer, an active layer, and a clad layer may be used to increase the light emission intensity. Further, the semiconductor substrate described above may be a simple semi-insulating semiconductor substrate instead of the two-layer structure of the substrate layer and the semi-insulating layer. In this case, the entire semiconductor substrate corresponds to a semi-insulating semiconductor layer.

An impurity of the first conductivity type is selectively thermally diffused into the semi-insulating semiconductor layer 2 via a diffusion mask, and the first diffusion region is diffused from the first conductivity type diffusion region under the condition that the side diffusion portions do not overlap (connect) with each other. The plurality of element region blocks 4 are formed. For example, when the first conductivity type is formed of an n-type semiconductor, Sn (tin), Se (selenium), Te (tellurium), or the like is diffused as an impurity.

When the impurity is selectively thermally diffused into the semiconductor layer through the diffusion mask, as shown in FIG. 2, the diffusion distance in the vertical direction to the semiconductor layer 2 (hereinafter referred to as junction depth).
The relationship between Xj and the lateral diffusion distance ds (hereinafter referred to as side diffusion) from the end of the diffusion mask 5 is approximately d
s / Xj = 1.3, and the relationship of ds> Xj holds. The junction surface formed by the lateral diffusion portion of the diffusion region 4 becomes shallower as it spreads in the lateral direction.

FIG. 3 is a view for explaining an example of a step of forming an element isolation structure according to the first embodiment of the present invention. 3, (a) to (e) are cross-sectional views, (B) and (E) are top views, (b) is a cross-sectional view taken along line AA 'of (B),
(E) is a sectional view taken along line AA 'of (E).

First, in FIG. 3A, a semi-insulating semiconductor layer 2 is epitaxially grown on a semiconductor substrate layer 1. For example, a semi-insulating AIGaAs epitaxial layer is formed on a GaAs substrate.

Next, in FIGS. 3B and 3B, a diffusion mask 5 for selectively diffusing first conductivity type impurities is formed on the semi-insulating semiconductor layer 2. For example, SiN
Using the film as the diffusion mask 5, the SiN film is patterned by the photolithography method and the etching method so that an opening is formed on a region to be an element region block.

Next, in FIG. 3C, a diffusion source 6 containing an impurity of the first conductivity type is formed on the semi-insulating semiconductor layer 2 of FIG.
Is formed, and an annealing cap 7 is formed thereon. For example, Sn-SiO ₂ film as a diffusion source 6 uses a SiO ₂ film as annealing cap 7.

Next, in FIG. 3D, annealing is performed so that the first conductive type is left in the semi-insulating semiconductor layer 2 so that the semi-insulating semiconductor region which becomes the element isolation region 3 is left at the boundary between each other. Are formed as the plurality of diffusion regions (element region blocks) 4.
For example, thermal diffusion is performed using an open-tube annealing furnace, and the first conductivity type impurity of the diffusion source 6 is introduced from the opening of the diffusion mask 5 into the semi-insulating semiconductor layer 2 so that the side diffusion portions do not overlap each other. To selectively diffuse.

Next, in FIGS. 3E and 3E, the annealing cap 7, the diffusion source 6, and the diffusion mask 5 are all removed. As described above, the element isolation structure of the first embodiment in which the plurality of element region blocks 4 formed of the diffusion regions of the first conductivity type are insulated from each other by the element isolation regions 3 formed of the semi-insulating semiconductor region is formed.

As described above, according to the first embodiment, the first conductivity type impurity is selectively diffused into the semi-insulating semiconductor layer 2, and the element isolation region 3 composed of the semi-insulating region is formed at the boundary between the two. Are formed, so that the element isolation region 3 is formed by forming the plurality of element regions 4 including the diffusion regions of the first conductivity type.
Can be narrowed. Further, the element can be separated in a planar type, and no groove is formed in the element isolation region 3. Therefore, the device characteristics near the device isolation region and the reliability of wiring formation on the device isolation region are improved.

In the first embodiment, the first conductivity type element region block is formed by the thermal diffusion method. However, the element region block may be formed by the ion implantation method. FIG. 4 is a view showing an element isolation structure according to the first embodiment in which an element region block is formed by an ion implantation method. If an element region block is formed by ion implantation, FIG.
As shown in (1), the side surface of the element region block 4 (therefore, the side surface of the element isolation region 3) can be made steeper, and the boundary position between the element region block and the element isolation region can be more accurately controlled. The width can be further reduced. Second Embodiment FIG. 5 is a diagram showing an element isolation structure according to a second embodiment of the present invention. FIG. 6 is an enlarged view around the element isolation region of FIG. The element isolation structure shown in FIGS.
A plurality of element region blocks 14 composed of diffusion regions of the first conductivity type are formed by selectively thermally diffusing impurities of the first conductivity type into the semi-insulating semiconductor layer 2, and boundaries between adjacent element region blocks 14 are formed. Then, an isolation region 13 composed of a diffusion region of the second conductivity type is formed by thermally diffusing the impurity of the second conductivity type so as to include all the overlapping portions of the two element region blocks 14. In the second embodiment, the width of the element isolation region can be made narrower than before, and the element can be isolated in a planar type.

As shown in FIG. 5, in the second embodiment, a semiconductor substrate having a semi-insulating semiconductor layer 2 formed on a semiconductor substrate layer 1 is used as in the first embodiment. Note that the semiconductor substrate described above may be a simple semi-insulating semiconductor substrate instead of a two-layer structure of a substrate layer and a semi-insulating layer. in this case,
The entire semiconductor substrate corresponds to a semi-insulating semiconductor layer.

An impurity of the first conductivity type is selectively thermally diffused into the semi-insulating semiconductor layer 2 via a diffusion mask to form a plurality of element region blocks 14 each including a diffusion region of the first conductivity type. At this time, different from the first embodiment, the side diffusion portions of the adjacent element region blocks 14 may overlap. Further, a second conductivity type impurity is thermally diffused at a boundary between adjacent device region blocks 14 through a diffusion mask under conditions that include all the overlapped portions of the device region blocks 14, thereby forming a second conductivity type diffusion region. Is formed. For example, when the first conductivity type is formed of an n-type semiconductor, Sn, Se, or Te is diffused as an impurity. When the second conductivity type is formed of a p-type semiconductor, Zn (zinc) is diffused. Let it.

As shown in FIG. 6, in the second embodiment, the junction depth Xj2 of the second conductivity type diffusion region (element isolation region) 13 is changed to the first conductivity type diffusion region (element region block).
14 can be made shallower than the junction depth Xj1. That is, Xj2 <Xj1 holds.

FIGS. 7 and 8 are views for explaining an example of a process for forming an element isolation structure according to the second embodiment of the present invention.
7 and 8, (a) to (i) are cross-sectional views,
(B), (E), (F), (I) are top views,
(B), (e), (f), and (i) are (B),
It is sectional drawing between AA 'of (E), (F), (I).

First, in FIG. 7A, a semi-insulating semiconductor layer 2 is epitaxially grown on a semiconductor substrate layer 1. For example, a semi-insulating AIGaAs epitaxial layer is formed on a GaAs substrate.

Next, in FIGS. 7B and 7B, a diffusion mask 15 for selectively diffusing impurities of the first conductivity type is formed on the semi-insulating semiconductor layer 2. For example, Si
Using the N film as the diffusion mask 15, the SiN film is patterned by a photolithography method and an etching method so that an opening is formed on a region to be an element region block.

Next, in FIG. 7C, a diffusion source 6 containing an impurity of the first conductivity type is formed on the semi-insulating semiconductor layer 2 of FIG.
Is formed, and an annealing cap 7 is formed thereon. For example, Sn-SiO ₂ film as a diffusion source 6 uses a SiO ₂ film as annealing cap 7.

Next, in FIG. 7D, annealing is performed to form a plurality of diffusion regions (element region blocks) 14 of the first conductivity type in the semi-insulating semiconductor layer 2. At this time, the side diffusion portions of the adjacent first conductivity type diffusion regions 14 may overlap to form an overlap portion 14a. For example, thermal diffusion is performed using an open tube annealing furnace,
The first conductivity type impurity of the diffusion source 6 is selectively diffused from the opening of the diffusion mask 15 into the semi-insulating semiconductor layer 2.

Next, in FIGS. 7E and 7E, the annealing cap 7, the diffusion source 6, and the diffusion mask 15 are all removed.

Next, in FIGS. 8F and 8F, FIG.
(E) An element isolation block 1 is formed on the semi-insulating semiconductor layer 2.
A diffusion mask 18 for diffusing impurities of the second conductivity type is formed at the boundary of No. 4. For example, a SiN film is used for the diffusion mask 18 and a photolithography method and an etching method are used.
The SiN film is patterned so that an opening is formed on the boundary region of the element isolation block.

Next, in FIG. 8G, the diffusion source 1 containing the impurity of the second conductivity type is formed on the semi-insulating semiconductor layer 2 of FIG.
6 and an annealing cap 17 is formed thereon. For example, a ZnO—SiO ₂ film is used as the diffusion source 16 and an AlN film is used as the annealing cap 17.

Next, in FIG. 8H, annealing is performed to form a second conductivity type diffusion region (element isolation region) 13 in the boundary region of the first conductivity type diffusion region (element region block) 14. For example, thermal diffusion is performed using an open-tube annealing furnace, and the second conductivity type impurity of the diffusion source 16 is diffused through the opening of the diffusion mask 18 so as to include all the overlaps 14 a of the first conductivity type diffusion region 14. To the boundary region of.

Next, in FIGS. 8I and 8I, the annealing cap 17, the diffusion source 16, and the diffusion mask 18 are all stripped. As described above, the first semi-insulating semiconductor layer 2
Plural element region blocks 14 composed of conductive diffusion regions
Is formed, and the element isolation block of the second embodiment is formed in which the element region block 14 is insulated and isolated from each other by the element isolation region 13 composed of the diffusion region of the second conductivity type and the semi-insulating region.

As described above, according to the second embodiment, the first conductivity type impurity is selectively diffused into the semi-insulating semiconductor layer 2 to form a plurality of element region blocks each including the first conductivity type diffusion region. 14 is formed, and a second conductivity type impurity is thermally diffused at a boundary between adjacent element region blocks 14, and is formed of a second conductivity type diffusion region so as to include all the overlapped portions of both element region blocks 14. By forming the element isolation region 13, the width of the element isolation region 13 can be reduced, and the elements can be isolated with a high yield. In addition, the element can be separated by a planar type, and the element isolation region 1
No groove is formed in 3. Therefore, the device characteristics near the device isolation region and the reliability of wiring formation on the device isolation region are improved.

In the second embodiment, the second conductivity type element isolation region is formed by the thermal diffusion method. However, the element isolation region may be formed by the ion implantation method. FIG. 9 is a diagram showing an element isolation structure of the second embodiment formed by an ion implantation method. FIG. 10 is an enlarged view around the element isolation region of FIG. If the element isolation region is formed by the ion implantation method, as shown in FIGS. 9 and 10,
Since the side surface of the element isolation region 13 can be made steeper, the width of the element isolation region can be further reduced. Third Embodiment FIG. 11 is a view showing an element isolation structure according to a third embodiment of the present invention. FIG. 12 is an enlarged view around the element isolation region of FIG. The element isolation structure shown in FIGS. 11 and 12 includes a plurality of element region blocks 24 each formed of a diffusion region of the first conductivity type by selectively thermally diffusing an impurity of the first conductivity type into the semi-insulating semiconductor layer 2. Are formed, and the element isolation groove 23 is formed by etching the boundary between the adjacent element region blocks 24 so as to include all the overlapping portions of the both element region blocks 24. In the third embodiment, the width of the element isolation groove can be made smaller than before, and the depth of the element isolation groove can be made smaller than before.

As shown in FIG. 11, in the third embodiment, a substrate having a semi-insulating semiconductor layer 2 formed on a semiconductor substrate layer 1 is used as in the first embodiment. Note that the semiconductor substrate described above may be a simple semi-insulating semiconductor substrate instead of a two-layer structure of a substrate layer and a semi-insulating layer. In this case, the entire semiconductor substrate corresponds to a semi-insulating semiconductor layer.

An impurity of the first conductivity type is selectively thermally diffused into the semi-insulating semiconductor layer 2 via a diffusion mask to form a plurality of element region blocks 24 each including a diffusion region of the first conductivity type. At this time, the side diffusion portions of the adjacent element region blocks 24 may overlap. Further, the boundary region between the adjacent element region blocks 24 is etched under such a condition that all the overlapping portions of the element region blocks 24 are included, thereby forming the element isolation grooves 23.

As shown in FIG. 12, in the third embodiment, the depth dj of the element isolation groove 23 is made smaller than the junction depth Xj1 of the first conductivity type diffusion region (element region block) 24. Can be. That is, dj <Xj1 holds.

FIGS. 13 and 14 are diagrams illustrating an example of a process of forming an element isolation structure according to the third embodiment of the present invention. 13 and 14, (a) to (h) are cross-sectional views, (B) and (E) to (H) are top views,
(B) and (e) to (h) are cross-sectional views taken along line AA ′ of (B) and (E) to (H), respectively.

First, in FIG. 13A, a semi-insulating semiconductor layer 2 is epitaxially grown on a semiconductor substrate layer 1. For example, a semi-insulating AIGaAs epitaxial layer is formed on a GaAs substrate.

Next, in FIGS. 13B and 13B, a diffusion mask 15 for selectively diffusing impurities of the first conductivity type is formed on the semi-insulating semiconductor layer 2. For example, S
The iN film is used as the diffusion mask 15, and the S
The iN film is removed.

Next, in FIG. 13C, a diffusion source 6 containing an impurity of the first conductivity type is formed on the semi-insulating semiconductor layer 2 of FIG. 13B, and an annealing cap 7 is formed thereon. I do. For example, Sn-SiO ₂ film as a diffusion source 6 uses a SiO ₂ film as annealing cap 7.

Next, in FIG. 13D, annealing is performed,
In the semi-insulating semiconductor layer 2, a plurality of diffusion regions (element region blocks) 24 of the first conductivity type are formed. At this time, the side diffusion portions of the adjacent first conductivity type diffusion regions 24 may overlap to form an overlap portion 24a. For example, thermal diffusion is performed using an open tube annealing furnace,
The first conductivity type impurity of the diffusion source 6 is selectively diffused from the opening of the diffusion mask 15 into the semi-insulating semiconductor layer 2.

Next, in FIGS. 13E and 13E, the annealing cap 7, the diffusion source 6, and the diffusion mask 15 are all removed.

Next, in FIGS. 14F and 14F, an etching mask 25 for forming an element isolation groove is formed at the boundary of the element isolation block 24. For example, using photoresist as the etching mask 25, the photoresist is patterned by the photolithography method so that an opening is formed on the boundary region of the element isolation block 24.

Next, in FIGS. 14G and 14G, an element isolation groove 23 is formed in the boundary region of the first conductivity type diffusion region (element region block) 24 by wet etching. For example, using phosphoric acid peroxide as an etchant,
The above-described boundary region is etched from the opening of the etching mask 25 so as to include the entire overlap 24a of the conductivity type diffusion region 24.

Next, in FIGS. 14H and 14H, the etching mask 25 is completely removed. As described above, a plurality of element region blocks 24 each composed of a diffusion region of the first conductivity type are formed in the semi-insulating semiconductor layer 2.
4 are insulated from each other by element isolation grooves 23 to form an element isolation structure of the third embodiment.

As described above, according to the third embodiment, the first conductivity type impurity is selectively diffused into the semi-insulating semiconductor layer 2, and the plurality of element regions 2 composed of the first conductivity type diffusion region are formed.
4 is formed, the boundaries between adjacent element region blocks 24 are etched, and the element isolation grooves 23 are formed so as to include all the overlapping portions of the two element region blocks 24, thereby reducing the width of the element isolation grooves 23. And device isolation can be performed with good yield. Further, the depth of the element isolation groove 23 can be made shallower than before. Therefore, the device characteristics near the device isolation region and the reliability of wiring formation on the device isolation region are improved.

In the third embodiment, the element isolation groove is formed by isotropic wet etching. However, the element isolation groove may be formed by anisotropic dry etching. FIG. 15 is a view showing an element isolation structure of the third embodiment formed by dry etching. FIG.
FIG. 15 is an enlarged view around the element isolation region of FIG. If an element isolation groove is formed by dry etching, FIG.
As shown in FIG. 16 and FIG. 16, the side wall of the element isolation groove can be made steeper, so that the element isolation width can be further reduced. Fourth Embodiment FIGS. 17A and 17B are diagrams showing a structure of an LED array according to a fourth embodiment of the present invention, wherein FIG. 17A is an overall top view, and FIG.
3A is a cross-sectional view taken along the line AA ′ of FIG. The LED array of FIG. 17 is a multilayer wiring type LED array to which the element isolation structure of the first embodiment is applied.

In the LED array shown in FIG. 17, the first embodiment has a semi-insulating semiconductor layer 2 (here, a semi-insulating AlGaAs epitaxial layer) formed on a semiconductor substrate layer 1 (here, a GaAs substrate layer). Using the same semiconductor substrate, the element isolation structure of the first embodiment is formed in the semi-insulating semiconductor layer 2. That is, an n-type impurity is selectively diffused in the semi-insulating semiconductor layer 2 so that the element isolation region 3 composed of the semi-insulating semiconductor region remains, and a plurality of element forming blocks 4 composed of n-type diffusion regions are formed. are doing. The n-type element forming block 4 includes a p-type diffusion region (light emitting portion) 31, a second-layer wiring 32, and a p-side electrode wiring 3.
3, a p-side electrode pad 34, an n-side electrode pad 35, an interlayer insulating film 36 and the like are formed.

When the element isolation structure of the first embodiment is applied, a semiconductor element with a narrow element isolation width and a planar type can be easily isolated, and a high density LED is formed on the semiconductor layer. And a plurality of element region blocks which can improve the reliability of wiring formation.

In the semi-insulating semiconductor layer 2, M (M is a positive integer) n-type element region blocks 4 are arranged in a line (in FIG. 17, two element region blocks are shown). 4 is shown). In each of the n-type element region blocks 4, N (N is a positive integer) p-type diffusion regions (light-emitting portions) 31 are formed in a line (N = 5 in FIG. 17). Each pn junction surface between the p-type diffusion region 31 and the n-type semiconductor region of the element region block 4 constitutes an individual LED, and one element region block 4 has N LEs.
D is formed.

In the interlayer insulating film 36 composed of the first interlayer insulating film 36a and the second interlayer insulating film 36b, a light emitting opening 36c for exposing the light emitting portion 31 and an n-type element region block 4
And an n-side electrode pad opening 36d for exposing the surface of the substrate. The second interlayer insulating film 36b includes a p-side electrode pad opening 36e that exposes the p-side electrode pad,
Via hole 36f exposing a part of p-side electrode wiring 33
Are further provided.

On the first interlayer insulating film 36a, a p-side electrode wiring 33 and a p-side electrode pad 34 are formed. p
The side electrode wiring 33 is connected to the light emitting portion 3 at the light emitting opening 36c.
1 individually. p-side electrode pad 34
Are formed integrally with a predetermined p-side electrode wiring 33. n
The side electrode pad 35 is formed in the n-side electrode opening 36d, and is in contact with the n-type element region block 4. L (L is a positive integer) is formed on the second interlayer insulating film 36b.
Two second-layer wirings 32 are formed (L = L in FIG. 17).
5). The second-layer wiring 32 is formed over all the n-type element region blocks 4 and over the element isolation regions 3, and a predetermined p-side electrode wiring 3 is formed in the via hole 36f.
Contact 3 In order to make a desired LED emit light in the multilayer wiring type LED array of FIG.
A p-side electrode pad 34 connected to the anode of the ED;
A voltage is applied between the n-side electrode pads 35 in contact with the cathode of the LED.

Next, the manufacturing process will be described. FIG.
21 are diagrams illustrating an example of a manufacturing process of the multilayer wiring LED array of FIG. 18 to 21, (A) to (K) are top views, and (a) to (k) are cross-sectional views taken along AA ′ in (A) to (K), respectively.
In FIG. 17, one p-side electrode pad 34 is formed for each element region block 4, and FIGS.
Then, the p-side electrode pad 3 is provided for each element region block 4.
4 are formed two by two, but the number of the p-side electrode pads 34 for one element region block 4 is arbitrary. For example, the p-side electrode pads 3 are provided for every two element region blocks 4.
4 may be formed one by one.

(1) Semiconductor substrate [FIGS. 18A and 18A]
First, an element isolation structure of the first embodiment (an element isolation structure by the process of FIG. 3) is formed on a semiconductor substrate. That is, by using a semiconductor substrate having a semi-insulating semiconductor layer 2 formed on a semiconductor substrate layer 1 and selectively thermally diffusing an n-type impurity into the semi-insulating semiconductor layer 2, a semi-insulating semiconductor layer 2 N so that the element isolation region 3 including the region remains.
A plurality of element region blocks 4 each including a mold diffusion region are formed. For example, a GaAs substrate layer is used for the semiconductor substrate layer 1 and a semi-insulating AlGaAs epitaxial layer is used for the semi-insulating semiconductor layer 2.

(2) Formation of Diffusion Mask (First Interlayer Insulating Film) [See FIGS. 18B and 18B] Next, on the semi-insulating semiconductor layer 2 shown in FIGS. 18A and 18A. A diffusion mask (first interlayer insulating film) 36a is formed, and a light emitting opening 36c is formed in the diffusion mask 36a. The element isolation region 3 is covered with a diffusion mask 36a. For example,
A film thickness of 500 to 3000 is formed on the diffusion mask 36 by the CVD method.
Using the SiN film of [形成], a light emitting opening 36c is formed in the SiN film by photolithography and etching.

(3) Formation of diffusion source [FIG. 18 (c),
Next, a diffusion source 41 containing a p-type impurity is formed on the diffusion mask 36a and the n-type element region block 4 in FIGS. 18B and 18B. For example, the diffusion source 41 is provided with ZnO—SiO _{2 having} a thickness of 500 to 3000 [〜] by sputtering.
Use a membrane.

(4) Formation of Anneal Cap [FIG. 19]
(See (d) and (D)] Next, an annealing cap 42 is formed on the diffusion source 41 shown in FIGS. 18 (c) and 18 (C). For example, a film thickness of 500 to 3000 [Å] is formed on the annealing cap 42 by a sputtering method.
Is used.

(5) Diffusion annealing [FIG. 19 (e),
(E)] Next, the substrates shown in FIGS. 19D and 19D are annealed,
A p-type impurity is diffused from the diffusion source 41 to the n-type element region block 4 in the light-emitting opening 36c to form a p-type diffusion region (light-emitting portion) 31. For example, 650 under nitrogen atmospheric pressure
Annealed at [° C] for about 1 hour to obtain a junction depth of about 1.0 [μ
[m] is formed.

(6) Separation of Annealing Cap and Diffusion Source [See FIGS. 19 (f) and 19 (F)] Next, the annealing cap 42 and the diffusion source 41 are all stripped by a selective etching method, and the surface of the p-type diffusion region 31 is removed. To expose. The diffusion mask 36a is left and becomes the first interlayer insulating film.

(7) Formation of n-side electrode pad opening [FIG.
0 (g), (G)] Next, an n-side electrode pad opening 36d is formed in the first interlayer insulating film 36a by a photolithography method and an etching method.
The surface of the mold element region block 4 is exposed.

(8) Formation of p-side electrode wiring and p-side electrode pad [Refer to FIGS. 20 (h) and (H)] Next, on the diffusion mask 36a and the light emitting portion (FIG. 20 (g) and (G)). A conductive film to be a p-side electrode wiring 33 and a p-side electrode pad 34 is formed on the p-type diffusion region 31, and the conductive film is patterned by a lift-off method so that the p-side electrode wiring 33 and the p-side electrode pad 34 Is formed. For example, Al is used for the p-side electrode. Thereafter, the p-side electrode wiring 33 is sintered to make ohmic contact with the light emitting section 31.

(9) Formation of n-side electrode pad [FIG.
(I), (I)] Next, a conductive film to be the n-side electrode pad 35 is formed on the diffusion mask 36a and the n-type element region block 4 in FIGS. The conductive film is patterned by a lift-off method to form an n-side electrode pad 35 in the n-side electrode pad opening 36d. For example, the n-side electrode pad 15
Use an Au alloy.

(10) Formation of Second Interlayer Insulating Film [FIG.
(J), (J)] Next, a second interlayer insulating film 36b is formed on the first interlayer insulating film 36a and the p-side electrode in FIGS. 20 (i) and (I), and the second interlayer insulating film 36b is formed. A light emitting opening 36c, an n-side electrode pad opening 36d, a p-side electrode pad opening 36e, and a via hole 36f are formed in the insulating film 36b by photolithography and etching. For example, polyimide is used for the second interlayer insulating film 36b.

(11) Formation of Second Layer Wiring [FIG.
(K), (K)] Next, a conductive film to be the second-layer wiring 32 is formed on the second interlayer insulating film 36b in FIGS. 20 (j) and (J), and the conductive film is lifted off. The second layer wiring 32 by patterning by the method
To form For example, Al is used for the second-layer wiring 32. As described above, the multilayer wiring type LED array of FIG. 17 is manufactured.

As described above, according to the fourth embodiment, the width of the element isolation region 3 can be reduced and the element isolation region can be reduced by applying the element isolation structure of the first embodiment to the multilayer wiring type LED array. 3 can be made planar, so that a high-density LED array with improved light emission characteristics in the element isolation region 3 and reliability of wiring formation can be manufactured. Fifth Embodiment FIGS. 22A and 22B are diagrams showing a structure of an LED array according to a fifth embodiment of the present invention, wherein FIG. 22A is an overall top view, and FIG.
3A is a cross-sectional view taken along the line AA ′ of FIG. The LED array of FIG. 22 is a multilayer wiring type LED array to which the element isolation structure of the second embodiment is applied. In FIG. 22, the same components as those in FIG. 17 are denoted by the same reference numerals.

In the LED array shown in FIG. 22, a semi-insulating semiconductor layer 2 is formed on a semiconductor substrate layer 1, and the element isolation structure of the second embodiment is formed on the semi-insulating semiconductor layer 2. . That is, n is selectively added to the semi-insulating semiconductor layer 2.
A plurality of element forming blocks 14 each including an n-type diffusion region are formed by diffusing the n-type impurity, and a p-type impurity is thermally diffused at a boundary between adjacent element region blocks 14 to completely remove an overlap portion between the two element region blocks 14. An element isolation region 13 composed of a p-type diffusion region is formed so as to include the same. In the n-type element region block 14, a p-type diffusion region (light emitting portion) 31, a second layer wiring 32, a p-side electrode wiring 33,
A p-side electrode pad 34, an n-side electrode pad 35, an interlayer insulating film 36 and the like are formed.

When the element isolation structure of the second embodiment is applied, a semiconductor element having a narrow element isolation width and a planar type can be easily isolated, and a semiconductor layer on which an LED is formed at a high density can be formed with a light emitting characteristic. And a plurality of element region blocks which can improve the reliability of wiring formation.

In the semi-insulating semiconductor layer 2, M n-type element region blocks 14 are arranged in a line (FIG.
Two of the element region blocks 4 are illustrated).
In each of the n-type element region blocks 14, N-type p-type diffusion regions (light emitting portions) 31 are formed in one column (N = 5 in FIG. 22). Each pn junction surface between the p-type diffusion region 31 and the n-type semiconductor region of the element region block 14 constitutes an individual LED, and N LEDs are formed in one element region block 14. .

Next, the manufacturing process will be described. FIG.
26A to 26 are diagrams illustrating an example of a manufacturing process of the multilayer wiring LED array in FIG. 23 to 26, (A) to (K) are top views, and (a) to (k) are cross-sectional views taken along AA 'in (A) to (K), respectively.
23 to 26, the same components as those in FIGS. 18 to 21 are denoted by the same reference numerals. In FIG. 22, one p-side electrode pad 34 is formed for each element region block 4, and in FIGS. 25 and 26, two p-side electrode pads 34 are formed for each element region block 4. However, the number of p-side electrode pads 34 for one element region block 4 is arbitrary. For example, one p-side electrode pad 34 may be formed for every two element region blocks 4.

(1) Semiconductor substrate [FIG. 23 (a), (A)
First, an element isolation structure of the second embodiment (an element isolation structure obtained by the steps shown in FIGS. 7 and 8) is formed on a semiconductor substrate. That is, the semi-insulating semiconductor layer 2 is formed on the semiconductor substrate layer 1.
Is formed on a semi-insulating semiconductor layer 2 using a semiconductor substrate on which
A plurality of element region blocks 14 composed of n-type diffusion regions are formed by selectively thermally diffusing n-type impurities, and p-type impurities are thermally diffused at the boundaries between adjacent element region blocks 14 to thereby form both element regions. The element isolation region 13 made of a p-type diffusion region is formed so as to include all the overlap portions of the block 14.

(2) Formation of Diffusion Mask (First Interlayer Insulating Film) [See FIGS. 23 (b) and 23 (B)] Next, on the semi-insulating semiconductor layer 2 of FIGS. 23 (a) and 23 (A). A diffusion mask (first interlayer insulating film) 36a is formed, and a light emitting opening 36c is formed in the diffusion mask 36a. The element isolation region 13 is covered with a diffusion mask 36a.

(3) Formation of diffusion source [FIG.
Next, a diffusion source 41 containing a p-type impurity is formed on the diffusion mask 36a and the n-type element region block 14 in FIGS. 23 (b) and 23 (B).

(4) Formation of Annealing Cap [FIG.
(See (d) and (D).) Next, an annealing cap 42 is formed on the diffusion source 41 shown in FIGS. 23 (c) and 23 (C).

(5) Diffusion annealing [FIG. 24 (e),
(E)] Next, the substrates of FIGS. 24 (d) and (D) are annealed,
A p-type impurity is diffused from the diffusion source 41 into the n-type element region block 14 in the light-emitting opening 36c to form a p-type diffusion region (light-emitting portion) 31.

(6) Separation of Annealing Cap and Diffusion Source [Refer to FIGS. 24 (f) and (F)] Next, the annealing cap 42 and the diffusion source 41 are all stripped by the selective etching method, and the surface of the p-type diffusion region 31 is removed. To expose. The diffusion mask 36a is left and becomes the first interlayer insulating film.

(7) Formation of n-side electrode pad opening [FIG.
5 (g), (G)] Next, an n-side electrode pad opening 36d is formed in the first interlayer insulating film 36a by a photolithography method and an etching method.
The surface of the mold element region block 4 is exposed.

(8) Formation of p-side electrode wiring and p-side electrode pad [see FIGS. 25 (h) and (H)] Next, on the diffusion mask 36a and the light emitting portion (FIG. 25 (g) and (G)). A conductive film to be a p-side electrode wiring 33 and a p-side electrode pad 34 is formed on the p-type diffusion region 31, and the conductive film is patterned by a lift-off method so that the p-side electrode wiring 33 and the p-side electrode pad 34 A p-side electrode is formed, and then sintering is performed.

(9) Formation of n-side electrode pad [FIG.
(I) and (I)] Next, a conductive film to be the n-side electrode pad 35 is formed on the diffusion mask 36a and the n-type element region block 4 in FIGS. 25 (h) and 25 (H). The conductive film is patterned by a lift-off method to form an n-side electrode pad 35 in the n-side electrode pad opening 36d.

(10) Formation of Second Interlayer Insulating Film [FIG.
(J), (J)] Next, a second interlayer insulating film 36b is formed on the first interlayer insulating film 36a and the p-side electrode in FIGS. 25 (i) and 25 (I), and the second interlayer insulating film 36b is formed. A light emitting opening 36c, an n-side electrode pad opening 36d, a p-side electrode pad opening 36e, and a via hole 36f are formed in the insulating film 36b by photolithography and etching.

(11) Formation of Second Layer Wiring [FIG. 26
(K), (K)] Next, a conductive film to be the second-layer wiring 32 is formed on the second interlayer insulating film 36b in FIGS. 26J and 26J, and the conductive film is lifted off. The second layer wiring 32 by patterning by the method
To form As described above, the multilayer wiring type LE of FIG.
A D array is manufactured.

As described above, according to the fifth embodiment, the width of the element isolation region 13 can be reduced and the element isolation region can be reduced by applying the element isolation structure of the second embodiment to the multilayer wiring type LED array. 3 can be of a planar type, so that a high-density LED array with improved light emission characteristics in the element isolation region 13 and reliability of wiring formation can be manufactured. Sixth Embodiment FIGS. 27A and 27B are views showing the structure of an LED array according to a sixth embodiment of the present invention, wherein FIG. 27A is an overall top view, and FIG.
3A is a cross-sectional view taken along line AA ′, and FIG. 3C is a cross-sectional view taken along line BB ′ in FIG. The LED array of FIG. 27 is a multilayer wiring type LED array to which the element isolation structure of the second embodiment is applied. 27, the same components as those in FIG. 17 are denoted by the same reference numerals.

In the LED array of FIG. 27, similar to the LED array of the fifth embodiment, the semiconductor substrate layer 1
The semi-insulating semiconductor layer 2 is formed thereon, and the element isolation structure of the second embodiment is formed on the semi-insulating semiconductor layer 2. That is, an n-type impurity is selectively diffused into the semi-insulating semiconductor layer 2 to form a plurality of element forming blocks 14 each including an n-type diffusion region, and the p-type impurity is thermally diffused at a boundary between adjacent element region blocks 14. And both element region blocks 14
Is formed so as to include all of the overlapped portions. And this n
The p-type diffusion region (light emitting portion) 3
The first and second layer wiring 32, the p-side electrode wiring 33, the p-side electrode pad 34, the n-side electrode pad 35, the interlayer insulating film 36 and the like are formed.

The sixth embodiment is different from the fifth embodiment in that the p-type element isolation region 13 and the light-emitting portion (p-type diffusion region) 31 are simultaneously formed by the same p-type impurity doping process. This simplifies the manufacturing process. Therefore, in the sixth embodiment, the element isolation region 1
3 and the light emitting part 31 have the same junction depth.

Next, the manufacturing process will be described. FIG.
FIG. 31 to FIG. 31 are diagrams illustrating an example of a manufacturing process of the multilayer wiring LED array of FIG. 28 to 31, (A) to (K) are top views, and (a) to (k) are cross-sectional views taken along AA 'in (A) to (K), respectively.
28 to 31, the same components as those in FIGS. 23 to 26 are denoted by the same reference numerals. In FIG. 27, one p-side electrode pad 34 is formed for each element region block 4, and in FIGS. 30 and 31, two p-side electrode pads 34 are formed for each element region block 4. However, the number of p-side electrode pads 34 for one element region block 4 is arbitrary. For example, one p-side electrode pad 34 may be formed for every two element region blocks 4.

(1) Semiconductor substrate [FIGS. 28A and 28A]
First, a structure before forming the element isolation region 13 in the element isolation structure of the second embodiment is formed on a semiconductor substrate. In other words, a semi-insulating semiconductor layer 2 is formed on the semiconductor substrate layer 1, and n-type impurities are selectively thermally diffused into the semi-insulating semiconductor layer 2 to form a plurality of element region blocks each including an n-type diffusion region. 14 is formed. Side diffusion portions of adjacent element region blocks 14 may overlap.

(2) Formation of Diffusion Mask (First Interlayer Insulating Film) [See FIGS. 28 (b) and (B)] Next, on the semi-insulating semiconductor layer 2 of FIGS. 28 (a) and 28 (A). A diffusion mask (first interlayer insulating film) 36a is formed, a light emitting opening 36c is formed in the diffusion mask 36a, and the n-type element region block 14 of the diffusion mask 36a is formed.
Is formed at a position corresponding to the boundary region of FIG.

(3) Formation of diffusion source [FIG.
Next, a diffusion source 41 containing a p-type impurity is formed on the diffusion mask 36a and the n-type element region block 14 in FIGS. 28 (b) and 28 (B).

(4) Formation of Anneal Cap [FIG. 29]
(D), (D)] Next, an annealing cap 42 is formed on the diffusion source 41 shown in FIGS. 28 (c) and 28 (C).

(5) Diffusion annealing [FIG. 29 (e),
(E)] Next, the substrates of FIGS. 29D and 29D are annealed,
The p-type impurity is diffused from the diffusion source 41 into the n-type element region block 14 in the light-emitting opening 36c to form the p-type diffusion region (light-emitting portion) 31. At the same time, the n-type impurity is diffused from the diffusion source 41 in the element separation region opening 51. Element area block 1
A p-type impurity is diffused in the boundary region of No. 4 to form an element isolation region 13 made of a p-type diffusion region so as to include all the overlapped portions of both element region blocks.

(6) Separation of Annealing Cap and Diffusion Source [See FIGS. 29 (f) and 29 (F)] Next, the annealing cap 42 and the diffusion source 41 are all stripped by a selective etching method, and the surface of the p-type diffusion region 31 is removed. To expose. The diffusion mask 36a is left and becomes the first interlayer insulating film.

(7) Formation of n-side electrode pad opening [FIG.
0 (g), (G)] Next, an n-side electrode pad opening 36d is formed in the first interlayer insulating film 36a by a photolithography method and an etching method.
The surface of the mold element region block 4 is exposed.

(8) Formation of p-side electrode wiring and p-side electrode pad [see FIGS. 30 (h) and (H)] Next, on the diffusion mask 36a and the light emitting portion (FIG. 30 (g) and (G)). A conductive film to be a p-side electrode wiring 33 and a p-side electrode pad 34 is formed on the p-type diffusion region 31, and the conductive film is patterned by a lift-off method so that the p-side electrode wiring 33 and the p-side electrode pad 34 A p-side electrode is formed, and then sintering is performed.

(9) Formation of n-side electrode pad [FIG.
(I), (I)] Next, a conductive film to be the n-side electrode pad 35 is formed on the diffusion mask 36a and the n-type element region block 4 in FIGS. The conductive film is patterned by a lift-off method to form an n-side electrode pad 35 in the n-side electrode pad opening 36d.

(10) Formation of second interlayer insulating film [FIG.
(J), (J)] Next, a second interlayer insulating film 36b is formed on the first interlayer insulating film 36a and the p-side electrode in FIGS. 30 (i) and 30 (I), and the second interlayer insulating film 36b is formed. A light emitting opening 36c, an n-side electrode pad opening 36d, a p-side electrode pad opening 36e, and a via hole 36f are formed in the insulating film 36b by photolithography and etching.

(11) Formation of Second Layer Wiring [FIG.
(K), (K)] Next, a conductive film to be the second wiring 32 is formed on the second interlayer insulating film 36b in FIGS. 31 (j) and (J), and the conductive film is lifted off. The second layer wiring 32 by patterning by the method
To form As described above, the multilayer wiring type LE of FIG.
A D array is manufactured.

As described above, according to the sixth embodiment, the width of the element isolation region 13 can be reduced and the element isolation region can be narrowed by applying the element isolation structure of the second embodiment to the multilayer wiring type LED array. 3 can be of a planar type, so that a high-density LED array with improved light emission characteristics in the element isolation region 13 and reliability of wiring formation can be manufactured. Further, by simultaneously forming the p-type element isolation region 13 and the light-emitting portion (p-type diffusion region) 31 by the same p-type impurity doping process, the manufacturing process can be simplified as compared with the fifth embodiment. Seventh Embodiment FIGS. 32A and 32B are views showing the structure of an LED array according to a seventh embodiment of the present invention, wherein FIG. 32A is an overall top view, and FIG.
3A is a cross-sectional view taken along line AA ′, and FIG. 3C is a cross-sectional view taken along line BB ′ in FIG. The LED array of FIG. 32 is a multilayer wiring type LED array to which the element isolation structure of the third embodiment is applied. In FIG. 32, the same components as those in FIG. 17 are denoted by the same reference numerals.

In the LED array of FIG. 32, a semi-insulating semiconductor layer 2 is formed on a semiconductor substrate layer 1, and the element isolation structure of the third embodiment is formed on the semi-insulating semiconductor layer 2. . That is, n is selectively added to the semi-insulating semiconductor layer 2.
A plurality of element forming blocks 24 each formed of an n-type diffusion region, and etching the boundary between adjacent element region blocks 24 so as to include all the overlapping portions of both element region blocks 24. A separation groove 23 is formed. In the n-type element region block 24, a p-type diffusion region (light emitting portion) 31, a second layer wiring 32, a p-side electrode wiring 33, a p-side electrode pad 34, an n-side electrode pad 35, an interlayer insulating film 36, and the like Is formed.

If the element isolation structure of the third embodiment is applied, element isolation can be easily performed with a narrow element isolation width and a shallow element isolation groove, and a semiconductor layer on which an LED is formed at a high density can be used. The element can be separated into a plurality of element region blocks which can improve the light emission characteristics and the reliability of forming a disconnection.

In the semi-insulating semiconductor layer 2, M n-type element region blocks 14 are arranged in a line (in FIG. 32,
Two of the element region blocks 4 are illustrated).
In each of the n-type element region blocks 24, N-type p-type diffusion regions (light-emitting portions) 31 are formed in one column (N = 5 in FIG. 32). Each pn junction surface between the p-type diffusion region 31 and the n-type semiconductor region of the element region block 24 forms an individual LED, and N LEDs are formed in one element region block 24. .

Next, the manufacturing process will be described. FIG.
FIG. 36 to FIG. 36 are diagrams illustrating an example of a manufacturing process of the multilayer wiring type LED array of FIG. 32. 33 to 36, (A) to (K) are top views, and (a) to (k) are cross-sectional views taken along AA 'in (A) to (K), respectively.
33 to 36, the same components as those in FIGS. 18 to 21 are denoted by the same reference numerals. In FIG. 32, one p-side electrode pad 34 is formed for each element region block 4, and in FIGS. 35 and 36, two p-side electrode pads 34 are formed for each element region block 4. However, the number of p-side electrode pads 34 for one element region block 4 is arbitrary. For example, one p-side electrode pad 34 may be formed for every two element region blocks 4.

(1) Semiconductor substrate [FIG. 33 (a), (A)
First, an element isolation structure according to the third embodiment (an element isolation structure obtained by the steps shown in FIGS. 13 and 14) is formed on a semiconductor substrate. That is, a semiconductor substrate having a semi-insulating semiconductor layer 2 formed on a semiconductor substrate layer 1 is used.
Then, a plurality of element region blocks 24 each composed of an n-type diffusion region are formed by selectively thermally diffusing an n-type impurity, and the boundaries between adjacent element region blocks 24 are wet-etched to form both element region blocks 24. The element isolation groove 23 is formed so as to include all the overlapped portions.

(2) Formation of Diffusion Mask (First Interlayer Insulating Film) [See FIGS. 33 (b) and (B)] Next, on the semi-insulating semiconductor layer 2 of FIGS. 33 (a) and 33 (A). A diffusion mask (first interlayer insulating film) 36a is formed, and a light emitting opening 36c is formed in the diffusion mask 36a. The element isolation groove 23 is covered with a diffusion mask 36a.

(3) Formation of diffusion source [FIG. 33 (c),
Next, a diffusion source 41 containing a p-type impurity is formed on the diffusion mask 36a and the n-type element region block 24 in FIGS. 33 (b) and 33 (B).

(4) Formation of Anneal Cap [FIG. 34]
(See (d) and (D).) Next, an annealing cap 42 is formed on the diffusion source 41 shown in FIGS. 33 (c) and 33 (C).

(5) Diffusion annealing [FIG. 34 (e),
(E)] Next, the substrates of FIGS. 34 (d) and (D) are annealed,
A p-type impurity is diffused from the diffusion source 41 into the n-type element region block 24 in the light-emitting opening 36c to form a p-type diffusion region (light-emitting portion) 31.

(6) Peeling of Annealing Cap and Diffusion Source [See FIGS. 34 (f) and (F)] Next, the annealing cap 42 and the diffusion source 41 are all stripped by a selective etching method, and the surface of the p-type diffusion region 31 is removed. To expose. The diffusion mask 36a is left and becomes the first interlayer insulating film.

(7) Formation of n-side electrode pad opening [FIG.
5 (g), (G)] Next, an n-side electrode pad opening 36d is formed in the first interlayer insulating film 36a by a photolithography method and an etching method.
The surface of the mold element region block 4 is exposed.

(8) Formation of p-side electrode wiring and p-side electrode pad [see FIGS. 35 (h) and (H)] Next, on the diffusion mask 36a and the light emitting portion (FIG. 35 (g) and (G)). A conductive film to be a p-side electrode wiring 33 and a p-side electrode pad 34 is formed on the p-type diffusion region 31, and the conductive film is patterned by a lift-off method so that the p-side electrode wiring 33 and the p-side electrode pad 34 A p-side electrode is formed, and then sintering is performed.

(9) Formation of n-side electrode pad [FIG.
Next, a conductive film to be the n-side electrode pad 35 is formed on the diffusion mask 36a and the n-type element region block 4 in FIGS. The conductive film is patterned by a lift-off method to form an n-side electrode pad 35 in the n-side electrode pad opening 36d.

(10) Formation of second interlayer insulating film [FIG. 36
(J), (J)] Next, a second interlayer insulating film 36b is formed on the first interlayer insulating film 36a and the p-side electrode in FIGS. 35 (i) and (I), and the second interlayer insulating film 36b is formed. A light emitting opening 36c, an n-side electrode pad opening 36d, a p-side electrode pad opening 36e, and a via hole 36f are formed in the insulating film 36b by photolithography and etching.

(11) Formation of Second Layer Wiring [FIG. 36
(K), (K)] Next, a conductive film to be the second wiring 32 is formed on the second interlayer insulating film 36b in FIGS. 36 (j) and (J), and the conductive film is lifted off. The second layer wiring 32 by patterning by the method
To form As described above, the multilayer wiring type LE shown in FIG.
A D array is manufactured.

As described above, according to the seventh embodiment, by applying the element isolation structure of the third embodiment to a multilayer wiring type LED array, the width of the element isolation groove 23 can be reduced and the element isolation groove can be narrowed. 3 can be made shallower than before, so that a high-density LED array with improved light emission characteristics in the element isolation groove 23 and reliability of wiring formation can be manufactured.

[0118]

As described above, according to the present invention, the semi-insulating semiconductor layer is selectively doped with impurities of the first conductivity type, and a plurality of semi-insulating semiconductor layers are formed so that the semi-insulating regions remain at their boundaries. A plurality of element regions are formed by forming the element regions or selectively doping the semi-insulating semiconductor layer with a first conductivity type impurity, and forming a second conductivity type impurity at a boundary between adjacent element regions. Is selectively doped, and the second conductivity type isolation region is formed so as to include all the overlapped portions of the two device regions, or the first region is formed in the semi-insulating semiconductor layer.
By selectively doping impurities of the conductivity type, forming a plurality of element regions, and forming an isolation groove at the boundary between adjacent element regions so as to include all the overlap portions of both element regions, Size (width and depth) can be reduced. Thereby, when applied to a multilayer wiring type LED array, there is an effect that the light emission characteristics in the element isolation region and the reliability of wiring formation are improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an element isolation structure according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating junction depth and side diffusion.

FIG. 3 is a diagram illustrating an example of a process of forming an element isolation structure according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a modification of the element isolation structure according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an element isolation structure according to a second embodiment of the present invention.

FIG. 6 is an enlarged view around the element isolation region in FIG.

FIG. 7 is a diagram illustrating an example of a process of forming an element isolation structure according to a second embodiment of the present invention (part 1).

FIG. 8 is a diagram illustrating an example of a step of forming the element isolation structure according to the second embodiment of the present invention (part 2).

FIG. 9 is a diagram showing a modification of the element isolation structure according to the second embodiment of the present invention.

FIG. 10 is an enlarged view around the element isolation region of FIG.

FIG. 11 is a diagram showing an element isolation structure according to a third embodiment of the present invention.

FIG. 12 is an enlarged view around the element isolation region in FIG.

FIG. 13 is a diagram illustrating an example of a step of forming the element isolation structure according to the third embodiment of the present invention (part 1).

FIG. 14 is a diagram illustrating an example of a step of forming the element isolation structure according to the third embodiment of the present invention (part 2).

FIG. 15 is a view showing a modification of the element isolation structure according to the third embodiment of the present invention.

FIG. 16 is an enlarged view around the element isolation region of FIG.

FIG. 17 is a diagram illustrating a structure of an LED array according to a fourth embodiment of the present invention.

FIG. 18 is a diagram illustrating an example of the manufacturing process of the LED array according to the fourth embodiment of the present invention (part 1).

FIG. 19 is a diagram illustrating an example of a manufacturing process of the LED array according to the fourth embodiment of the present invention (part 2).

FIG. 20 is a view illustrating an example of a manufacturing process of the LED array according to the fourth embodiment of the present invention (part 3).

FIG. 21 is a diagram illustrating an example of a manufacturing process of the LED array according to the fourth embodiment of the present invention (part 4).

FIG. 22 is a diagram illustrating a structure of an LED array according to a fifth embodiment of the present invention.

FIG. 23 is a diagram illustrating an example of a manufacturing process of the LED array according to the fifth embodiment of the present invention (part 1).

FIG. 24 is a diagram illustrating an example of the manufacturing process of the LED array according to the fifth embodiment of the present invention (part 2).

FIG. 25 is a view illustrating an example of a manufacturing process of the LED array according to the fifth embodiment of the present invention (part 3).

FIG. 26 is a view illustrating an example of the manufacturing process of the LED array according to the fifth embodiment of the present invention (part 4).

FIG. 27 is a diagram illustrating a structure of an LED array according to a sixth embodiment of the present invention.

FIG. 28 is a diagram illustrating an example of a manufacturing process of the LED array according to the sixth embodiment of the present invention (part 1).

FIG. 29 is a view illustrating an example of the manufacturing process of the LED array according to the sixth embodiment of the present invention (part 2).

FIG. 30 is a view illustrating an example of a manufacturing step of the LED array according to the sixth embodiment of the present invention (part 3).

FIG. 31 is a diagram illustrating an example of the manufacturing process of the LED array according to the sixth embodiment of the present invention (part 4).

FIG. 32 is a diagram illustrating a structure of an LED array according to a seventh embodiment of the present invention.

FIG. 33 is a view illustrating an example of the manufacturing process of the LED array according to the seventh embodiment of the present invention (part 1).

FIG. 34 is a view illustrating an example of the manufacturing process of the LED array according to the seventh embodiment of the present invention (part 2).

FIG. 35 is a view illustrating an example of the manufacturing process of the LED array according to the seventh embodiment of the present invention (part 3).

FIG. 36 is a view illustrating an example of the manufacturing process of the LED array according to the seventh embodiment of the present invention (part 4).

FIG. 37 is a diagram showing an example of the structure of a conventional LED array.

[Explanation of symbols]

1 semi-insulating semiconductor substrate, 2 semi-insulating semiconductor layer,
3,13 device isolation region, 4,14,24 device region block, 23 device isolation groove, 31 p-type diffusion region (light emitting portion).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Hiroshi Hamano 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Takaatsu Shimizu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. F term (reference) 5F041 AA31 CA02 CA35 CA38 CA71 CA72 CA74 CA75 CB22 CB23 CB24 CB25 5F073 AB05 DA12 DA14 DA21 DA34

Claims (10)

[Claims] 1. A semiconductor device, comprising:
In the element isolation structure in which a plurality of conductive element regions are formed, the semiconductor layer is semi-insulating, and the semi-insulating semiconductor layer is selectively doped with an impurity, so that a semi-insulating material is formed at a boundary between the semiconductor layers. An element isolation structure, wherein a plurality of element regions are formed so that a conductive region remains. 2. An element isolation structure in which a plurality of element regions insulated and isolated from each other are formed in a semiconductor layer, wherein the semiconductor layer is semi-insulating, and the semi-insulating semiconductor layer has a first conductivity type. By selectively doping impurities, a plurality of element regions are formed, and a boundary of an adjacent element region is doped with an impurity of the second conductivity type so as to include all the overlapped portions of both element regions. And an element isolation structure characterized in that an isolation region of the second conductivity type is formed. 3. The element isolation structure according to claim 2, wherein said isolation region is formed by a thermal diffusion method or an ion implantation method. 4. An element isolation structure in which a plurality of element regions insulated from each other are formed in a semiconductor layer, wherein the semiconductor layer is semi-insulating, and an impurity is selectively added to the semi-insulating semiconductor layer. An element isolation structure, wherein a plurality of element regions are formed by doping, and an isolation groove is formed at a boundary between adjacent element regions so as to include all overlapping portions of both element regions. 5. The element isolation structure according to claim 4, wherein said isolation groove is formed by an isotropic or anisotropic etching method. 6. The element isolation structure according to claim 2, wherein a depth of the isolation region or the isolation trench from a surface of the semiconductor layer is equal to or less than a depth of the element region. 7. The element isolation structure according to claim 1, wherein said element region is formed by a thermal diffusion method or an ion implantation method. 8. A plurality of device regions are formed in a semi-insulating semiconductor layer of a semiconductor substrate by the device isolation structure according to claim 1, and a plurality of light emitting devices are respectively formed in the device regions. A light emitting element array characterized by being formed. 9. A plurality of device regions are formed in a semi-insulating semiconductor layer of a semiconductor substrate by the device isolation structure according to claim 2.
A light-emitting element array in which a plurality of light-emitting elements are formed in each of the element regions, wherein the light-emitting element has a second conductive type impurity doping step in which the isolation region is formed in the semiconductor layer. A light-emitting element array formed simultaneously with the isolation region by selectively doping two-conductivity-type impurities. 10. The semi-insulating semiconductor layer is a semiconductor layer provided on a first conductivity type, a second conductivity type, or a semi-insulating semiconductor substrate layer, or a semi-insulating semiconductor substrate. The light emitting element array according to claim 8 or 9, wherein