JP2006148059A - Array-type light emitting diode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a luminescence array for improving a resolution at each luminescence point of an array-type light emitting diode. <P>SOLUTION: A method of manufacturing the array-type light emitting diode comprises steps of: forming a plurality of striped light emitting diode regions by etching an n-type AlxGal-xAs cladding layer 203, an n-type AlxGal-xAs layer 204 and a p-type AlxGal-xAs cladding layer 205; covering the side wall and the front surface of the striped light emitting diode region with an insulating protective coat 210; and thereafter covering a front surface excluding the side wall of the striped light emitting diode region and a luminescence window portion with wiring concurrently with metal cladding layers 220B, 220A. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an array type light emitting diode (LED), and more particularly to a method for forming a p-type cladding layer and an ohmic contact layer of a light emitting diode.

  The basic structure of a light-emitting diode array is similar to that of a light-emitting diode. The difference between the two is that the array-type light-emitting diode is mainly used in an electronic optical print head, not as illumination. If it is 1200 points per inch (1200 DPI), the unit area of light emission is only tens of micrometers x tens of micrometers. The interval between the light emitting elements is only 20 and a few micrometers. Therefore, the light emission intensity of each light emitting element needs to be uniform, and since the light emitting elements are close to each other, insulation between the light emitting elements is very important.

As shown in FIGS. 1 to 3, a typical manufacturing method of the light emitting diode array is disclosed in US Pat. No. 6,133,588. First, an n-type GaAs semiconductor substrate 101 is provided, the n-type gallium arsenide (GaAs) substrate 101 is placed in a metal organic vapor phase epitaxy (MOVPE), silicon is used as an n-type dopant source, aluminum, gallium, and Provided is an epitaxial layer necessary for organic growth including arsenic. buffer layer 102 of n-type GaAs epitaxial layer, a lower cladding layer of n-type _{Al x Ga 1-x As (} cladding layer) 103, n -type Al _x Ga _1-x As layer 104, a semi-insulating layer Al _x Ga _1-x As 105, another semi-insulating GaAs 106, and a diffusion mask layer 109 are sequentially grown and formed on the surface of the wafer 131. In addition, the first window 133 and the second window 134 are formed by patterning the diffusion mask layer 109.

  Further, as shown in FIG. 2, a diffusion control layer 135 is formed, and patterning is performed on the diffusion control layer 135, so that the first window 133 remains uncovered. Then, a diffusion source thin film 136 containing zinc and an annealing coating layer 137 are formed. Next, the p-type diffusion region 138 is formed by annealing at a temperature of about 650 ° C. During annealing, zinc diffuses deep inside the wafer 131 and penetrates the diffusion control film 135, thereby forming a shallow current conducting diffusion area 108.

The diffusion leading edge of the light emitting diffusion area reaches the n-type Al _y Ga _1-y As layer 104, and the leading edge of the conductive diffusion region 108 reaches the semi-insulating layer Al _x Ga _1-x As105. It is necessary to appropriately control the annealing conditions. Further, when annealing the wafer, aluminum nitride (not shown) may be selectively formed in the lower portion of the wafer 131 in order to prevent the n-type dopant from disappearing from the lower portion.

  Then, as shown in FIG. 3, the coating layer 137, the diffusion source thin film 136, and the diffusion control layer 135 are removed by etching. The diffusion mask layer 109 is used as an insulating layer without being etched. Subsequently, the p-type electrode 110 is formed in the conductive diffusion region 108, and annealing is performed, so that the p-type electrode 110 and the conductive diffusion region 108 are electrically well connected. Finally, the back surface of the wafer is polished to form an n-type bottom electrode.

  As described above, in the prior art, a p-type or n-type semiconductor in the light emission range is defined by diffusion, and then necessary light-emitting elements, internal wirings, and wire bonding regions are created by the semiconductor process technology. However, in a p-type or n-type semiconductor defined by diffusion, the diffusion ratio between the depth direction and the width direction depends on the state of the chip surface, the temperature of the diffusion furnace, and the uniformity of the airflow. As a result, the carrier concentration of the p-type or n-type semiconductor is affected, causing problems such as a non-uniform light emitting region, a high reverse current of the light emitting diode, and poor insulation between the light emitting elements.

  In addition, since the distance between the light emitting elements is short, there is a problem that the resolution of the issue point is lowered due to the mutual interference of stray light emitted from the side surface.

  Accordingly, one of the objects of the present invention is to solve the above-mentioned problems of the prior art.

  The present invention relates to an array-type light emitting diode, a light emitting element formed on a substrate, a protective layer covering the light emitting element so that an upper electrode of the light emitting element is exposed, and the light emission from the upper electrode. A metal line formed on the surface of the exposed upper electrode and a surface of a protective layer on the side wall of the light emitting device so that an electrical connection with another array type light emitting diode is formed along the side wall of the device. The present invention relates to a configuration of an array type light emitting diode including at least a metal layer formed on the substrate and a lower electrode formed on a back surface of the substrate.

  The light emitting device is a light emitting diode including a DBR layer (distributed Bragg reflection layer), a buffer layer, an n-type epitaxial cladding layer, an active layer, a p-type epitaxial cladding layer, a p-type ohmic contact layer, and the p-type electrode from the substrate. In addition, the light emitting device may include at least a metal adhesive layer, a metal reflective layer, a p-type electrode, a p-type ohmic contact layer, a p-type epitaxial cladding layer, an active layer, an n-type epitaxial cladding layer, a buffer layer, and a substrate. It may be a light emitting diode including an etching stop layer.

  Since the metal cladding layer is formed on the surface of the insulating protective layer on the side wall of the light emitting device, the light emission shape of each light emitting device is improved by blocking stray light emitted from the side surface by the metal coating, and each light emitting point. Therefore, the image forming quality of the light emitting array can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  In the conventional technique, the p-type ohmic contact layer and the upper cladding in the light-emitting diode array are formed by a diffusion technique after a light emission range is defined by a lithography technique. As described above, since the depth, width, and impurity concentration are greatly related to the diffusion atmosphere control, there are problems such as a non-uniform light emitting region and a high reverse current of the light emitting diode.

  The present invention solves the non-uniformity of the light emitting region, which has been a problem in the prior art, by giving two specific embodiments.

(Embodiment 1)
In the first embodiment of the present invention, the p-type cladding layer, the p-type ohmic contact layer, and the n-type cladding layer are grown by the MOCVD epitaxial method. Is described in Taiwan Patent Application No. 093129840 by the present applicant.

First, as shown in FIG. 4, the light emitting diode array of the present invention is based on an n-type gallium arsenide (GaAs) substrate 200. An n-type gallium arsenide (GaAs) substrate 200 is placed in a metal organic vapor phase epitaxy (MOVPE), and an n-type DBR layer 201A, an n-type buffer layer 202, and an n-type Al _x Ga _1-x As lower cladding layer (cladding layer ) 203, the required epitaxial layers in the order of the n-type Al _y Ga _1-y As layer 204, the p-type Al _x Ga _1-x As upper cladding layer 205, and the p-type Al _z Ga _1-z As ohmic contact layer 206 Grow. Here, x is 0.3 to 1.0, y is 0 to 0.6, and z is 0 to 0.6. Although the n-type Al _y Ga _1-y As layer 204 is an active layer that emits light, it may be p-type or non-doped.

Subsequently, a resist (not shown) is applied to the p-type Al _z Ga _1-z As ohmic contact layer 206, a p-type electrode contact window (not shown) is formed by a lithography technique, and a p-type metal is formed by vapor deposition. (Au / Be or Ti / Pt / Au) is deposited in a resist or p-type electrode contact window and excess metal is removed by lift-off. The chip completed by lift-off is annealed at a temperature of 380 ° C. to 480 ° C. so that a good ohmic contact between the p-type metal electrode 212 and the p-type ohmic contact layer 206 is formed.

  As shown in FIG. 5 (a), the range of the light emitting element 231 is defined by a resist lithography technique, and an excess portion is removed by chemical etching to form an array type light emitting diode. A typical thickness of the p-type metal electrode 212 is about 100 to 200 angstroms. Thereafter, an insulating protective layer 210 of, for example, silicon nitride or silicon dioxide is deposited on the surface of the light emitting element 231 by plasma chemical vapor deposition, and the surface of the p-type electrode 212 is exposed by a resist lithography technique or an etching method. Thereafter, metal wiring and wire bonding regions are defined by resist lithography technology to connect the p-type electrode 212 and other light emitting elements (not shown) in the array. As shown in the cross-sectional view of FIG. 5 (a) and the plan view of FIG. 5 (b), unlike the prior art, the above-mentioned definition of the metal wiring and the wire bonding region is not only the wiring 220B but also the light emitting element by evaporation. It should be noted that the insulating protective layer 210 on the side wall of 231 and a metal clad layer 220A formed on the surface of the resist and formed by lifting off excess metal by a metal lift-off technique are included.

  Next, the substrate 200 is polished to an appropriate thickness (200-400 μm), a back metal 240 is deposited on the back surface of the substrate 200, and annealed at a temperature of about 380 ° C. to 460 ° C. to form a good ohmic contact. Thus, the n-type electrode 240 is formed.

  In addition to forming the n-type electrode 240 of the light-emitting diode on the back surface of the wafer as shown in FIG. 5 (a), the n-type electrode 240a may be formed on the surface of the wafer. Here, the silicon dioxide of FIG. 5 (a) is added to the p-type contact window to form an n-type contact window, and the n-type electrode wiring is also defined in the definition of the metal wiring and the wire bonding region. Finally, a good ohmic contact is formed by annealing at a temperature of 380 ° C. to 460 ° C. The result is shown in FIG. 5 (c).

(Embodiment 2)
As in the second embodiment of the present invention shown in FIG. 6, an example in which the four side surfaces of a light emitting element including a DBR layer are covered with a metal layer is an array type light emitting diode in which the substrate includes a metal reflective layer by a metal adhesive layer It is also possible to apply to what joined. According to the method of the present invention, each layer of the light emitting diode is the same as that of the first embodiment except that the DBR layer 201A is replaced with an etching stop layer 201B. Therefore, as described above, the n-type gallium arsenide (GaAs) substrate 200 is placed in a metal organic vapor phase epitaxy (MOVPE), and the etching stop layer 201B, the n-type buffer layer 202, and the n-type Al _x Ga _1-x As are formed. A lower cladding layer (cladding layer) 203, an n-type Al _y Ga _1-y As layer 204, a p-type Al _x Ga _1-x As upper cladding layer 205, and a p-type Al _z Ga _1-z As ohmic contact layer 206 In order, necessary epitaxial layers are grown. Here, x is 0.3 to 1.0, y is 0 to 0.6, and z is 0 to 0.6. Although the n-type Al _y Ga _1-y As layer 204 is an active layer that emits light, it may be p-type or non-doped.

Subsequently, as described in the first embodiment, the p-type electrode layer 212 is formed on the p-type ohmic contact layer 206. Then, the transparent conductor oxide layer 213, the metal reflection layer 214, and the metal bonding layer 216 are sequentially deposited on the p-type Al _z Ga _1-z As ohmic contact layer 206. The transparent conductor oxide layer 213 is made of indium oxide, for example, and can suppress a reaction that deteriorates the metal reflection layer 214 or the metal reflection layer 214 caused by the p-type ohmic contact layer 206 during annealing. According to the method of the present invention, the deposition of the transparent conductor oxide layer 213 is not a necessary condition but a process that is performed selectively.

  The material for the metal reflection layer 214 may be a metal such as gold, silver, or aluminum. In addition, the material of the metal bonding layer 216 may be, for example, PbSn, InSn, AuSn, or other metal that easily undergoes an eutectic reaction. As shown in FIG. 7, according to the method of the present invention, a support substrate 250 is further prepared and bonded to the metal bonding layer 216, and both are bonded by a low temperature annealing treatment at 180 ° C. to 250 ° C. In addition, according to the method of the present invention, another bonded metal bonding layer 216A may be formed on the support substrate 250 to strengthen the bonding between the two. Then, the n-type gallium arsenide (GaAs) substrate 200 is removed by etching up to the etching stop layer 201B by a wet etching method.

  As shown in FIG. 8, the p-type electrode layer 212 is formed on the p-type ohmic contact layer 206 as described in the first embodiment. In the second embodiment, after the n-type electrode 240 is formed on the surface of the etching stop layer 201B, the range of the light-emitting element 231 is defined as shown in FIG. As shown, the etching stop layer 201B is placed on the upper side, the support substrate 250 is placed on the lower side, and an extra portion is removed by lithography or etching technique to stop at the metal reflective layer 214 (or metal adhesive layer 216). Thereafter, an insulating protective layer 210 is formed over the entire surface so as to cover the light emitting diode element 231. Finally, the p-type electrode connection window on the n-type electrode 240 and the metal reflective layer 214 (or the metal adhesive layer 216) is exposed by patterning to form a metal layer used as the metal clad layer 220A and the wiring 220B. The metal clad layer 220A is formed on the surface of the insulating protective layer 210 on the four side surfaces of the light emitting element 231. The wiring 220B is a conductive wire from the n-type electrode 240 to the metal clad layer 220A and from the metal clad layer 220A to another light emitting element, and is connected to the p-type electrode 212. The wiring 220C of the P-type electrode 212 may be on the back surface of the support substrate 250.

  Further, according to the method of the present invention, in the first and second embodiments described above, by changing the light emission angle, the effect of total reflection is reduced and the luminous efficiency is improved. Further, surface roughening may be performed on the upper layer portion of the light emitting element. For example, in the first embodiment, the p-type ohmic contact layer 206 is roughened. FIG. 5 (d) is a diagram showing surface roughening of the p-type ohmic contact layer 206. In the second embodiment, the etching stop layer 201B is roughened. FIG. 8 (a) is a diagram showing surface roughening of the etching stopper layer 201B.

Features of the present invention:
1． Since the n-type cladding layer, active layer, p-type cladding layer, and p-type ohmic contact layer are formed simultaneously with the epitaxy growth, the number of lithography etching steps for defining the diffusion mask is reduced compared to the conventional technology. Obviously.
2． The control of the p-type impurity concentration becomes easy, and the problem of nonuniformity in diffusion control and concentration control in the vertical and horizontal depths is solved.
3． According to the method of the present invention, the material of the epitaxial layer is not limited to gallium arsenide or aluminum gallium arsenide, but may be gallium arsenide phosphorus (GaAsP) or indium gallium phosphide (InGaP).
Four. In the present invention, the n-type cladding layer, the active layer, the p-type cladding layer, and the p-type ohmic contact layer are formed by the epitaxy method, so that good interface characteristics and uniformity of concentration can be obtained, and the uniformity of light emission is greatly increased. Can be improved. Moreover, reverse current can be significantly reduced by obtaining good interface characteristics.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, in the first embodiment, an example in which the p-type electrode is on the top and the n-type electrode is on the bottom is given as an example, and those skilled in the art can replace both electrodes with appropriate modifications. This also does not depart from the inventive idea of the present application and is considered to be included in the scope of the present invention. The above-described changes can also be applied to the second embodiment.

The figure which shows the manufacture flow of the array type light emitting diode formed by the prior art The figure which shows the manufacture flow of the array type light emitting diode formed by the prior art The figure which shows the manufacture flow of the array type light emitting diode formed by the prior art The figure which shows the structure of the light emitting diode element containing the DBR layer formed by the method which concerns on the 1st Embodiment of this invention The figure which shows the structure of the light emitting diode element containing the metal wiring and metal clad layer formed by the method which concerns on the 1st Embodiment of this invention The figure which shows the state before the light emitting diode element containing the metal reflective layer formed by the method concerning the 2nd Embodiment of this invention, and a support substrate join. The figure which shows removing a GaAs substrate, after the light emitting diode element containing the metal reflection layer formed by the method concerning the 2nd Embodiment of this invention, and a support substrate are joined. After the light emitting diode including the metal reflective layer formed by the method according to the second embodiment of the present invention is defined as the light emitting diode element, the light emitting diode element is covered with the insulating layer, and further, the metal cladding layer covers the sidewall of the light emitting element. Figure showing that

Explanation of symbols

101, 201 n-type GaAs semiconductor substrate
102, 202 n-type GaAs epitaxial layer buffer layer
103, 203 n-type Al _x Ga _1-x As lower cladding layer
104, 204 n-type Al _x Ga _1-x As layer
205 Al _x Ga _1-x As upper cladding layer
105, 106 Semi-insulating layer
108 Conductive diffusion region
109 Diffusion mask layer
131, 231 wafers
133 1st window
134 Second window
135 Diffusion control layer
136 Diffusion source thin film
137 Annealing layer
138 p-type diffusion region
220 Metal wiring and bonding wires
240 n-type electrode

Claims (6)

A light emitting element formed on a substrate;
A protective layer covering the light emitting device such that the upper electrode of the light emitting device is exposed;
A metal line formed on the surface of the exposed upper electrode so as to form an electrical connection with another array type light emitting diode along the side wall of the light emitting device from the upper electrode;
A metal layer formed on the surface of the protective layer on the sidewall of the light emitting device;
A lower electrode formed on the back surface of the substrate;
An array type light emitting diode comprising at least The light emitting element is at least
DBR layer formed sequentially from the substrate, buffer layer, n-type epitaxial cladding layer, active layer, p-type epitaxial cladding layer, p-type ohmic contact layer, and the upper electrode,
2. The array type light emitting diode according to claim 1, comprising: The surface of the p-type ohmic contact layer is a roughened surface,
3. The array type light emitting diode according to claim 2. The light emitting element is at least
Metal adhesive layer, metal reflective layer, p-type electrode, p-type ohmic contact layer, p-type epitaxial clad layer, active layer, n-type epitaxial clad layer, buffer layer, and etching stop layer formed in order from the substrate,
2. The array type light emitting diode according to claim 1, comprising: A transparent conductive oxide layer formed between the metal reflective layer and the p-type ohmic contact layer and covering the p-type electrode;
5. The array type light emitting diode according to claim 4, further comprising: The surface of the etch stop layer is a roughened surface;
5. The array type light emitting diode according to claim 4.

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