JP5326957B2 - Light emitting device manufacturing method and light emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a light emitting element and the light emitting element, in which manufacturing cost can be reduced and yield can be enhanced. <P>SOLUTION: The method of manufacturing the light emitting element 1 includes the processes of: exposing a part of a surface of an n-type semiconductor layer by removing a part of a semiconductor laminate structure including the n-type semiconductor layer, a light emitting layer 25 and a p-type semiconductor layer; forming a diffusion electrode 30 on the p-type semiconductor layer; forming an n-electrode 40 made of the same material with a p-electrode 42 on the exposed n-type semiconductor layer while forming the p-electrode 42 on the diffusion electrode 30; forming an insulating layer 50; forming an opening 52 on the p-electrode 42 and on the n-electrode 40 by removing the insulating layer 50 on the p-electrode 42 and on the n-electrode 40; forming a barrier layer 70 in the opening 52 on the p-electrode 42 and on the n-electrode 40; and forming a solder layer 80 on the barrier layer 70 formed on the p-electrode 42 and on the n-electrode 40. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a light emitting device and a light emitting device in which a p electrode and an n electrode are made of the same material.

  Conventionally, a diffusion electrode comprising a diffusion electrode formed on a semiconductor layer, a passivation film that covers the surface of the diffusion electrode and having an opening in part, and a bonding electrode having a solder layer on the upper surface A semiconductor light emitting device is known in which a buffer electrode having a diameter larger than that of the opening and flatter than the surface of the diffusion electrode is formed on the bottom of the opening of the passivation film, and the bonding electrode is connected to the buffer electrode. (For example, refer to Patent Document 1).

  In the semiconductor light emitting device described in Patent Document 1, a buffer electrode is formed on the surface of the diffusion electrode, and an opening smaller than the buffer electrode is formed in the passivation film on the buffer electrode, so that the surface of the buffer electrode is flat. As a result, the adhesion between the buffer electrode and the passivation film can be secured, and the progress of the lateral etching from the interface between the buffer electrode and the passivation film can be suppressed when the opening is etched. .

JP 2008-288548 A

  However, the semiconductor light-emitting device described in Patent Document 1 has many processes for manufacturing a semiconductor light-emitting device because the p-electrode and the n-electrode are formed of different materials. Since it is necessary to prepare for each electrode a material having good compatibility such as adhesion between the electrode and the barrier layer that contacts the electrode, it is necessary to prepare each of the electrodes. There is a limit to improving the yield.

  Accordingly, an object of the present invention is to provide a method for manufacturing a light-emitting element and a light-emitting element that can reduce the manufacturing cost and improve the yield.

In order to achieve the above object, according to the present invention, a part of a semiconductor stacked structure including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer is removed from the p-type semiconductor layer side. A removal step of exposing the surface of the layer; a diffusion electrode formation step of forming a diffusion electrode on the p-type semiconductor layer; and a n-type exposed in the removal step simultaneously with forming a p-electrode on the diffusion electrode An electrode forming step of forming an n electrode made of the same material as the p electrode on the semiconductor layer; the diffusion electrode on which the p electrode is formed; and at least a part of the n-type semiconductor layer on which the n electrode is formed An insulating layer forming step for forming an insulating layer covering the first and second electrodes; and removing the insulating layer on the p electrode and the n electrode to form openings in the insulating layer on the p electrode and the n electrode, respectively. Forming an opening, and on and before the p-electrode a barrier layer forming step of simultaneously forming a barrier layer made of the same material in the opening and on the insulating layer around the opening on the n electrode, the p electrode and on the barrier layer formed on the n electrode A solder layer forming step of simultaneously forming a solder layer made of the same material , the n-type semiconductor layer is formed from n-type GaN, the diffusion electrode is formed from an oxide semiconductor, and the n-electrode is A contact layer made of Ni or Cr and in contact with the n-type semiconductor layer, and an Au layer formed on the contact layer, the p-electrode made of Ni or Cr and in contact with the diffusion electrode, And an Au layer formed on the contact layer, wherein the barrier layer includes a plurality of pair layers, with the first barrier layer made of Ti and the second barrier layer made of Ni as one pair layer, The Au layer of each of the n electrode and the p electrode is in contact with the first barrier layer of the barrier layer located thereon, and the insulating layer around the opening is the barrier layer located on the insulating layer There is provided a method for manufacturing a light emitting device in contact with the first barrier layer .

  In the method for manufacturing a light emitting device, the insulating layer forming step includes a first step of covering the diffusion electrode on which the p electrode is formed and at least a part of the n-type semiconductor layer on which the n electrode is formed. A first insulating layer forming step of forming a first insulating layer, a reflective layer forming step of forming a reflective layer on the first insulating layer excluding at least a part above the p electrode and the n electrode, A second insulating layer forming step of forming a second insulating layer covering the reflective layer, wherein the opening forming step includes the first insulating layer on the p electrode and the n electrode, and the second insulating layer. It is preferable that the two insulating layers are removed and the openings are formed in the insulating layers on the p-electrode and the n-electrode, respectively.

  In the method for manufacturing a light emitting element, the electrode forming step preferably forms a plurality of n electrodes on the surface of the n-type semiconductor layer.

  In the method for manufacturing a light emitting element, the electrode forming step preferably forms a plurality of p electrodes on the surface of the diffusion electrode.

  In the method for manufacturing a light emitting element, the p electrode and the n electrode may have an intermediate layer between the contact layer and the Au layer.

  According to the present invention, the manufacturing cost can be reduced and the yield can be improved.

FIG. 1A is a longitudinal sectional view of a light emitting device according to the first embodiment of the present invention, and FIG. 1B is a plan view of the light emitting device according to the first embodiment of the present invention. It is. FIG. 2A is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2B is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2C is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 3A is a plan view of a light emitting device according to a second embodiment of the present invention. FIG. 3B is a longitudinal sectional view of a light emitting device according to the second embodiment of the present invention. FIG. 4A is a longitudinal sectional view of a light emitting device according to the third embodiment of the present invention, and FIG. 4B is a plan view of the light emitting device according to the third embodiment of the present invention. It is.

[First Embodiment]
FIG. 1A shows an outline of a longitudinal section of the light emitting device according to the first embodiment of the present invention, and FIG. 1B shows a plane of the light emitting device according to the first embodiment of the present invention. The outline of is shown.

(Configuration of Light-Emitting Element 1)
As illustrated in FIG. 1A, the light emitting device 1 according to the first embodiment of the present invention includes, as an example, a sapphire substrate 10 having a C plane (0001) and a buffer provided on the sapphire substrate 10. A layer 20, an n-side contact layer 22 provided on the buffer layer 20, an n-side cladding layer 24 provided on the n-side contact layer 22, and a light emitting layer 25 provided on the n-side cladding layer 24 The semiconductor laminated structure includes a p-side cladding layer 26 provided on the light emitting layer 25 and a p-side contact layer 28 provided on the p-side cladding layer 26.

  The light emitting element 1 includes a diffusion electrode 30 provided on the p-side contact layer 28, a p-electrode 42 provided in a partial region on the diffusion electrode 30, and at least an n-side contact layer from the p-side contact layer 28. An n-electrode 40 provided on the n-side contact layer 22 exposed by etching to the surface of 22 and an opening 52 and an n-side contact layer for exposing a region where the p-electrode 42 on the diffusion electrode 30 is disposed 22, an insulating layer 50 as a passivation film having an opening 52 exposing a region where the n-electrode 40 is disposed, a reflective layer 60 disposed inside the insulating layer 50, and a part of the upper surface of the insulating layer 50. A barrier layer 70 that covers and is provided in each of the openings on the p-electrode 42 and the n-electrode 40 and a solder layer 80 provided on the barrier layer 70 are provided.

  In the present embodiment, the material constituting the n-electrode 40 and the material constituting the p-electrode 42 are the same. Further, when the n-electrode 40 and the p-electrode 42 are formed from multiple layers, the respective layer configurations are the same. In particular, the material constituting the n electrode 40 and the material constituting the p electrode 42 have electrical connection and adhesion between the barrier layer 70 in contact with the n electrode 40 and the barrier layer 70 in contact with the p electrode 42. Use good materials. Further, the material constituting the barrier layer 70 and the solder layer 80 provided on the n-electrode 40 can be made the same as the material constituting the barrier layer 70 and the solder layer 80 provided on the p-electrode 42. The barrier layer 70 and the solder layer 80 are collectively referred to as a bonding electrode.

Here, the buffer layer 20, the n-side contact layer 22, the n-side cladding layer 24, the light emitting layer 25, the p-side cladding layer 26, and the p-side contact layer 28 are each made of a group III nitride compound semiconductor. It is a layer. The group III nitride compound semiconductor is, for example, a quaternary group III nitride of Al _x Ga _y In _1-xy N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). A compound compound semiconductor can be used, and a binary group III nitride compound semiconductor such as AlN, GaN, or InN, Al _x Ga _1-x N, Al _x In _1-x N, or Ga _x In _A ternary group III nitride compound semiconductor of _1-xN (where 0 <x <1) can also be used.

  In the present embodiment, the buffer layer 20 is made of AlN. The n-side contact layer 22 and the n-side cladding layer 24 are each formed from n-GaN doped with a predetermined amount of n-type dopant (for example, Si). The light emitting layer 25 has a multiple quantum well structure formed of InGaN / GaN / AlGaN. Further, the p-side cladding layer 26 and the p-side contact layer 28 are each formed from p-GaN doped with a predetermined amount of p-type dopant (for example, Mg).

Further, the diffusion electrode 30 according to the present embodiment is made of an oxide semiconductor, for example, made of ITO (Indium Tin Oxide). The insulating layer 50 is mainly formed from, for example, silicon dioxide (SiO ₂ ). The reflective layer 60 is provided inside the insulating layer 50 and is made of a metal material that reflects light emitted from the light emitting layer 25, for example, Al. The total thickness of the insulating layer 50 is, for example, 0.1 μm or more and 1 μm or less, and the thickness of the reflective layer 60 provided inside the insulating layer 50 is to appropriately reflect the light incident on the reflective layer 60. The purpose is, for example, 0.05 μm or more and 0.5 μm or less.

  As shown in FIG. 1A, the n-electrode 40 is separated from the mesa portion formed of a plurality of compound semiconductor layers from the n-side cladding layer 24 to the p-side contact layer 28 on the n-side contact layer 22. In position, along the side of the mesa portion. The n-electrode 40 is in contact with the insulating layer 50 at the upper surface in contact with the barrier layer 70, with the outer edge portion 40 a that is not in contact with the barrier layer 70. In FIG. 1B, the n-electrode 40 cannot be visually confirmed because the solder layer 80 is exposed on the surface. The p-electrode 42 is formed in a rectangular shape in a top view at the central portion of the upper surface of the diffusion electrode 30 provided on the mesa portion. In addition, the p-electrode 42 is in contact with the insulating layer 50 at the upper surface in contact with the barrier layer 70, and the outer edge portion 42 a that is not in contact with the barrier layer 70. The insulating layer 50 covers the diffusion electrode 30 and the mesa portion except for the formation region of the p-electrode 42, and covers the n-side contact layer 22 except for the formation region of the n-electrode 40.

  The n electrode 40 and the p electrode 42 are made of a metal material containing Ni or Cr and Au. In particular, when the n-side contact layer 22 is formed of n-type GaN, the n-electrode 40 is formed including the Ni layer as the contact layer and the Au layer above the Ni layer from the n-side contact layer 22 side. Alternatively, it can be formed including a Cr layer as a contact layer and an Au layer above the Cr layer from the n-side contact layer 22 side. In particular, when the diffusion electrode 30 is formed of an oxide semiconductor, the p-electrode 42 can be formed including a Ni layer as a contact layer and an Au layer above the Ni layer from the diffusion electrode 30 side. Alternatively, a Cr layer as a contact layer and an Au layer above the Cr layer can be formed from the diffusion electrode 30 side. For the purpose of improving the flatness of the surfaces of the n electrode 40 and the p electrode 42 and maintaining ohmic contact (that is, obtaining good ohmic contact), the thickness of the Ni layer or Cr layer is For example, the thickness is preferably 0.01 μm or more and 0.1 μm or less, and the thickness of the Au layer is preferably 0.05 μm or more and 0.5 μm or less.

  The n-electrode 40 can also be formed including a contact layer, an intermediate layer, and an Au layer. Similarly, the p-electrode 42 can be formed including the contact layer, the intermediate layer, and the Au layer from the diffusion electrode 30 side. For the purpose of maintaining ohmic contact between the contact layer and the n-side contact layer 22 or the diffusion electrode 30, the intermediate layer diffuses upper Au into Ni or Cr of the contact layer (that is, Au and Ni Or a material capable of suppressing alloying with Cr), for example, a metal material such as Ti or Pt. The intermediate layer is preferably formed to have a thickness of, for example, 0.01 μm or more and 0.1 μm or less.

  Here, in the present embodiment, the contact portion between the p electrode 42 and the barrier layer 70 is the center side of the p electrode 42 in plan view, and the contact portion between the p electrode 42 and the insulating layer 50 is seen in plan view. The outer edge portion 42a of the p-electrode 42. Furthermore, the barrier layer 70 is in contact with the surface of the insulating layer 50 opposite to the diffusion electrode 30 (that is, the upper surface in FIG. 1A) and covers a predetermined region of the surface of the insulating layer 50. . The barrier layer 70 has a metal layer mainly composed of Ti at a contact portion with the insulating layer 50. In addition, in order to make the insulating layer 50 contact the surface of the outer edge part of the n electrode 40 and the p electrode 42, the contact layer (namely, Ni layer or Cr layer) which comprises the n electrode 40 and the p electrode 42, an intermediate | middle layer, and Au The thickness of the layer is preferably in the above range.

  As shown in FIG. 1B, the light emitting element 1 is formed in a substantially rectangular shape near the center of the light emitting element 1 in a plan view, and is in electrical contact with the p-electrode 42 through the barrier layer 70. A p-side solder layer 80 is provided. The light-emitting element 1 includes an n-side solder layer 80 that is formed in a substantially U shape in plan view and is in electrical contact with the n-electrode 40 through the barrier layer 70. That is, the n-side solder layer 80 includes a side portion 80a provided along the vicinity of one side of the light emitting element 1 in plan view, and an end portion 80b extending from both end portions of the side portion 80a in a direction perpendicular to the one side. Have. In this way, by forming the n-side solder layer 80 in a U-shape, when the light-emitting element 1 is mounted on a submount or the like, leads or wirings electrically connected to the p-side solder layer 80 are externally provided. Can be pulled out easily. The solder layer 80 can be formed from a eutectic material, such as AuSn. The solder layer 80 can be formed by, for example, a vacuum evaporation method (for example, an electron beam evaporation method or a resistance heating evaporation method), a sputtering method, a plating method, a screen printing method, or the like. The solder layer 80 can also be formed from eutectic solder made of a eutectic material other than AuSn or lead-free solder such as SnAgCu.

  Specifically, the barrier layer 70 is formed on the first barrier layer in contact with the insulating layer 50, the n-electrode 40 and the p-electrode 42, and diffuses the material constituting the solder layer 80. And a second barrier layer to be suppressed. The first barrier layer is formed of a material having an ohmic contact with the material forming the n-electrode 40 and the material forming the p-electrode 42 and having good adhesion, and is mainly formed of, for example, Ti. The second barrier layer is formed of a material capable of suppressing the material constituting the solder layer 80 from diffusing to the n electrode 40 and p electrode 42 sides, and is mainly formed of Ni, for example.

  The barrier layer 70 can also include a plurality of pair layers, with the first barrier layer and the second barrier layer as one pair layer. When barrier layer 70 includes a plurality of pair layers, diffusion of the material constituting solder layer 80 can be further suppressed. The film thickness of the first barrier layer of the barrier layer 70 is, for example, about 150 nm, and the film thickness of the second barrier layer is, for example, about 100 nm or 150 nm. Furthermore, the solder layer 80 is formed to have a thickness of 2 μm to 20 μm, for example.

  The light-emitting element 1 configured as described above is a flip-chip light-emitting diode (LED) that emits light having a wavelength in the blue region. For example, the light-emitting element 1 has a forward voltage of 2.9 V and a forward current. In the case of 20 mA, light having a peak wavelength of 455 nm is emitted. The light emitting element 1 is formed in a substantially square shape in plan view. For example, the vertical dimension and the horizontal dimension of the light emitting element 1 are approximately 350 μm, respectively.

  Each layer from the buffer layer 20 to the p-side contact layer 28 provided on the sapphire substrate 10 is, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (Molecular Beam). Epitaxy (MBE), Halide Vapor Phase Epitaxy (HVPE), etc. Here, the buffer layer 20 is formed of AlN, but the buffer layer 20 can also be formed of GaN. Further, the quantum well structure of the light emitting layer 30 may be a single quantum well structure or a strained quantum well structure instead of a multiple quantum well structure.

The insulating layer 50 is formed from a metal oxide such as titanium oxide (TiO ₂ ), alumina (Al ₂ O ₃ ), tantalum pentoxide (Ta ₂ O ₅ ), or a resin material having electrical insulation properties such as polyimide. You can also And the reflective layer 60 can also be formed from Ag, and can also be formed from the alloy which contains Al or Ag as a main component. The reflective layer 60 may be a distributed Bragg reflector (DBR) formed from a plurality of layers of two materials having different refractive indexes.

  Furthermore, the light emitting element 1 may be an LED that emits light having a peak wavelength in the ultraviolet region, the near ultraviolet region, or the green region, but the region of the peak wavelength of the light emitted by the LED is not limited thereto. In other modified examples, the planar dimension of the light emitting element 1 is not limited to this. For example, the planar dimension of the light emitting element 1 can be designed such that the vertical dimension and the horizontal dimension are each 1 mm, and the vertical dimension and the horizontal dimension can be different from each other.

(Manufacturing process of light-emitting element 1)
2A to 2C show an example of a manufacturing process of the light-emitting element according to the first embodiment. Specifically, FIG. 2A (a) is a longitudinal sectional view before etching for exposing the surface of the n-side contact layer is performed. FIG. 2B is a longitudinal sectional view after the etching for exposing the surface of the n-side contact layer is performed. Moreover, (c) of FIG. 2A is a longitudinal cross-sectional view of a state in which a mask is formed on the diffusion electrode. Furthermore, (d) of FIG. 2A is a longitudinal cross-sectional view after etching the diffusion electrode.

  First, a sapphire substrate 10 is prepared, and a semiconductor stacked structure including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer is formed on the sapphire substrate 10. Specifically, the buffer layer 20, the n-side contact layer 22, the n-side cladding layer 24, the light emitting layer 25, the p-side cladding layer 26, and the p-side contact layer 28 are formed on the sapphire substrate 10. Epitaxial growth is performed in this order to form an epitaxial growth substrate (semiconductor laminated structure forming step).

  Subsequently, a mask 200 made of a photoresist is formed on the p-side contact layer 28 of the epitaxial growth substrate by using a photolithography technique (FIG. 2A (a)). Next, after etching a part of the region excluding the portion where the mask 200 is formed from the p-side contact layer 28 to the surface of the n-side contact layer 22, the mask 200 is removed. Thereby, a mesa portion composed of a plurality of compound semiconductor layers from the n-side cladding layer 24 to the p-side contact layer 28 is formed, and a part of the surface of the n-side contact layer 22 is exposed (FIG. 2A (b)). , Removal step). In the removal step, etching is performed to a part of the n-side contact layer 22 for the purpose of completely removing the portion from the n-side cladding layer 24 to the p-side contact layer 28 where the mask 200 is not formed. You can also.

  Thereafter, the diffusion electrode 30 is formed on the entire surface of the n-side contact layer 22 and the p-side contact layer 28. That is, the diffusion electrode 30 is formed so as to cover the exposed surface of the n-side contact layer 22, the side surface of the mesa portion, and the surface of the p-side contact layer 28 (that is, the upper surface of the mesa portion). In the present embodiment, the diffusion electrode 30 is ITO, and is formed using, for example, a vacuum deposition method. The diffusion electrode 30 can also be formed by a sputtering method, a CVD method, a sol-gel method, or the like. Then, a mask 202 made of a photoresist is formed in a region where the diffusion electrode 30 is left (FIG. 2A (c)). Subsequently, the diffusion electrode 30 not covered with the mask 202 is etched. Thereby, the diffusion electrode 30 is formed in a predetermined region of the p-side contact layer 28 (FIG. 2A (d), diffusion electrode formation step). First, after the diffusion electrode 30 is formed on the entire surface of the epitaxial growth substrate, a part of the diffusion electrode 30 is removed by etching using the photolithography technique and the etching technique, and the n-side contact from the p-side contact layer 28 is removed. It is also possible to etch down to the surface of the layer 22.

  FIG. 2B (a) is a longitudinal sectional view after the n-electrode and the p-electrode are formed. FIG. 2B (b) is a longitudinal sectional view after forming the first insulating layer. Further, FIG. 2B (c) is a longitudinal sectional view after the reflective layer and the second insulating layer are formed.

  First, the n electrode 40 is formed in a predetermined partial region on the surface of the n-side contact layer 22 by using a vacuum deposition method and a photolithography technique, and at the same time, the p electrode 42 is determined in advance on the surface of the diffusion electrode 30. Then, it is formed in a part of the formed region (FIG. 2B (a), electrode forming step). In the present embodiment, the material constituting the n-electrode 40 and the material constituting the p-electrode 42 are the same material. That is, a photoresist mask having openings in each of a predetermined region of the n-side contact layer 22 forming the n-electrode 40 and a predetermined region of the diffusion electrode 30 forming the p-electrode 42 is formed. Thereafter, an electrode material is simultaneously vacuum deposited on each opening, thereby forming an n electrode 40 and a p electrode 42 made of the same material. In addition, after providing the material which comprises the n electrode 40 and the p electrode 42 on the n side contact layer 22 and the diffusion electrode 30, it is between the n side contact layer 22 and the n electrode 40, and the diffusion electrode 30 and the p electrode 42. In order to ensure ohmic contact and adhesion between the two, a heat treatment can be performed for a predetermined time at a predetermined temperature and in a predetermined atmosphere.

  Subsequently, an insulating layer 50 covering the n electrode 40 and the p electrode 42 is formed. Specifically, a first insulating layer 50a that covers the n-side contact layer 22, the n electrode 40, the mesa portion, the diffusion electrode 30, and the p electrode 42 is formed by plasma CVD (first insulating layer forming step). Insulating layer forming step). Then, a reflective layer 60 is formed on the first insulating layer 50a in a predetermined region excluding above the n-electrode 40 and the p-electrode 42 by using a vapor deposition method and a photolithography technique (FIG. 2B (b)). The reflective layer forming step in the insulating layer forming step). Next, the second insulating layer 50b is formed using the plasma CVD method on the upper side of the reflective layer 60 formed in the step of FIG. 2B (b) and on the upper side of the portion where the reflective layer 60 is not formed. (FIG. 2B (c), second insulating layer forming step in the insulating layer forming step). As a result, the reflective layer 60 is covered with the second insulating layer 50b. The first insulating layer 50a and the second insulating layer 50b constitute the insulating layer 50 according to this embodiment.

  FIG. 2C (a) is a longitudinal sectional view after an opening is formed in a part of the insulating layer. Further, FIG. 2C (b) is a longitudinal sectional view after the barrier layer and the solder layer are formed.

  Subsequently, at least a part of the upper part of the n-electrode 40 and at least a part of the upper part of the p-electrode 42 in the insulating layer 50 are removed by using a photolithography technique and an etching technique. Thereby, the opening 52 of the insulating layer 50 is formed on the p-electrode 42, and the opening 52 of the insulating layer 50 is formed on the n-electrode 40 (FIG. 2C (a), opening forming step).

  Next, a barrier layer 70 made of the same material is simultaneously formed inside each opening 52 by using a vacuum deposition method and a photolithography technique (barrier layer forming step). The barrier layer 70 formed in the opening 52 on the n-electrode 40 is electrically connected to the n-electrode 40, and the barrier layer 70 formed in the opening 52 on the p-electrode 42 is electrically connected to the p-electrode 42. . Subsequently, a solder layer 80 made of the same material is simultaneously formed on the barrier layer 70 formed on the n-electrode 40 and on the barrier layer 70 formed on the p-electrode 42 (solder layer forming step). Thereby, the light emitting element 1 shown in FIG. 2C (b) is manufactured.

  Each of the n electrode 40 and the p electrode 42 can also be formed by a sputtering method. The insulating layer 50 can also be formed by chemical vapor deposition (CVD). The light emitting element 1 formed through the above steps is mounted by flip chip bonding at a predetermined position on a substrate made of ceramic or the like in which a wiring pattern of a conductive material is formed in advance. And the light emitting element 1 mounted on the board | substrate can be packaged as a light-emitting device by sealing integrally with sealing materials, such as an epoxy resin, a silicone resin, or glass.

(Effects of the first embodiment)
In the light emitting element 1 according to the present embodiment, the n electrode 40 and the p electrode 42 are simultaneously formed of the same material. Therefore, the manufacturing cost is higher than the case where the n electrode 40 and the p electrode 42 are separately formed from different materials. Can be reduced and the yield can be improved. Since the n-electrode 40 and the p-electrode 42 are formed simultaneously from the same material, the n-electrode 40 and the p-electrode 42 are in close contact and electrical connectivity between the n-electrode 40 and the p-electrode 42 and the barrier layer 70. Therefore, the degree of freedom in selecting the material constituting the barrier layer 70 can be improved.

  In the light emitting device 1 according to the present embodiment, the contact layer of the n electrode 40 and the p electrode 42 is formed of Ni or Cr, so that the electrode made of the same material is made of an oxide semiconductor such as ITO and n-type GaN. It is possible to make ohmic contact with both. In addition, when the contact layer is formed of Ni in the light-emitting element 1, there is an effect that high adhesion to the diffusion electrode 30 and the n-side contact layer 22 is obtained. When the contact layer is formed of Cr, the diffusion electrode 30 and n There is an effect that the contact resistance between the side contact layer 22 and the contact layer can be lowered.

  In addition, since the n-electrode 40 and the p-electrode 42 and the reflective layer 60 are kept separate from each other in the light-emitting element 1 according to the present embodiment, no current flows through the reflective layer 60 and the reflective layer 60 Can prevent electromigration. Thereby, compared with the case where the electrode which combines the function of the electrode and the function of the reflective layer is provided, the electromigration of the material constituting the reflective layer 60 can be prevented. A reduction in ohmic characteristics can be prevented, and a highly reliable light-emitting element 1 can be provided.

[Second Embodiment]
FIG. 3A shows an outline of a plane of the light emitting device according to the second embodiment of the present invention, and FIG. 3B shows an outline of a longitudinal section of the light emitting device according to the second embodiment of the present invention.

  The light emitting device 2 according to the second embodiment has substantially the same configuration as the light emitting device 1 according to the first embodiment, except that the configurations of the diffusion electrode 30, the n electrode 40, and the p electrode 42 are different. And has a function. Therefore, a detailed description is omitted except for differences.

  In the second embodiment, the diffusion electrode 30 is formed in a comb shape in plan view. A plurality of p-electrodes 42 are formed at intervals on portions corresponding to the comb teeth in the diffusion electrode 30, and a joining electrode composed of a plurality of long barrier layers 70 and solder layers 80 parallel to each other is formed. It is formed. The outer diffusion electrode 30 and the solder layer 80 in the width direction are formed shorter than the other diffusion electrodes 30 and the solder layer 80.

  The n-electrode 40 is formed between the teeth of the comb-shaped diffusion electrode 30 and at two corners of the light emitting element 2 (for example, two corners that are not diagonal positions), and is provided on the n-electrode 40. The barrier layer 70 and the solder layer 80 to be formed are also formed at two corners of the light emitting element 1. The barrier layer and the solder layer 80 on the n-electrode 40 are opposed to the short-formed barrier layer 70 and the solder layer 80 of the p-electrode 42 in plan view.

(Effect of the second embodiment)
The light-emitting element 2 according to the second embodiment includes a plurality of n-electrodes 40 to disperse the flow of current supplied to the light-emitting element 2 in the light-emitting element 2, and the n-electrode 40 and n The contact area with the side contact layer 22 can be increased. Thereby, in the second embodiment, the driving voltage of the light emitting element 2 can be reduced, and a low forward voltage can be stably maintained.

[Third Embodiment]
FIG. 4A shows an outline of a longitudinal section of a light emitting device according to the third embodiment of the present invention, and FIG. 4B shows a plan view of the light emitting device according to the third embodiment of the present invention. The outline of is shown. 4A shows an outline of a cross section taken along line BB in FIG. 4B.

  The light emitting element 3 according to the third embodiment has substantially the same configuration and function except that the n electrode 40 and the p electrode 42 are different from the light emitting element 1 according to the first embodiment. Therefore, a detailed description is omitted except for differences.

  The light emitting element 3 includes a plurality of n electrodes 40 and a plurality of p electrodes 42. For example, in the light emitting element 3, a plurality of n electrodes 40 are formed on the n-side contact layer 22 at intervals in a plan view, and a plurality of p electrodes 42 are formed on the diffusion electrode 30 at intervals. ing. In other words, the plurality of n electrodes 40 are scattered on the n-side contact layer 22, and the plurality of p electrodes 42 are scattered on the diffusion electrode 30. The light emitting element 3 emits light having a peak wavelength of 455 nm when the forward voltage is 2.9 V and the forward current is 20 mA. The light emitting element 3 is formed in a substantially square shape in plan view. For example, the vertical dimension and the horizontal dimension of the light emitting element 3 are approximately 350 μm, respectively.

  In the manufacturing process of the light emitting element 3, all or some of the plurality of scattered p electrodes 40 are electrically connected by forming the solder layer 80 in the solder layer forming process. Similarly, all or some of the plurality of n electrodes 42 are electrically connected by forming the solder layer 80.

  While the embodiments of the present invention have been described above, the embodiments described above do not limit the invention according to the claims. In addition, it should be noted that not all the combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

1, 2 and 3 Light-emitting element 10 Sapphire substrate 20 Buffer layer 22 n-side contact layer 24 n-side cladding layer 25 light-emitting layer 26 p-side cladding layer 28 p-side contact layer 30 Diffusion electrode 40 n-electrode 40a end 42 p-electrode 42a end Part 50 Insulating layer 50a First insulating layer 50b Second insulating layer 52 Opening 60 Reflective layer 70 Barrier layer 80 Solder layer 80a Side 80b End part 200, 202 Mask

Claims (5)

removing a part of the semiconductor multilayer structure including the n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer from the p-type semiconductor layer side to expose the surface of the n-type semiconductor layer;
A diffusion electrode forming step of forming a diffusion electrode on the p-type semiconductor layer;
Forming an p-electrode on the diffusion electrode, and simultaneously forming an n-electrode made of the same material as the p-electrode on the n-type semiconductor layer exposed in the removing step;
An insulating layer forming step of forming an insulating layer covering the diffusion electrode on which the p electrode is formed and at least a part of the n-type semiconductor layer on which the n electrode is formed;
An opening forming step of removing the insulating layer on the p electrode and the n electrode and forming openings in the insulating layer on the p electrode and the n electrode, respectively;
A barrier layer forming step of simultaneously forming a barrier layer made of the same material on the opening on the p electrode and the n electrode and on the insulating layer around the opening ;
A solder layer forming step of simultaneously forming a solder layer made of the same material on the barrier layer formed on the p electrode and the n electrode ,
The n-type semiconductor layer is formed of n-type GaN, and the diffusion electrode is formed of an oxide semiconductor;
The n electrode includes a contact layer made of Ni or Cr and in contact with the n-type semiconductor layer, and an Au layer formed on the contact layer,
The p-electrode includes a contact layer made of Ni or Cr and in contact with the diffusion electrode, and an Au layer formed on the contact layer,
The barrier layer includes a plurality of pair layers, with the first barrier layer made of Ti and the second barrier layer made of Ni layer as one pair layer,
The Au layer of each of the n electrode and the p electrode is in contact with the first barrier layer of the barrier layer located thereon,
The method for manufacturing a light emitting device, wherein the insulating layer around the opening is in contact with a first barrier layer of the barrier layer located on the insulating layer. The insulating layer forming step includes
A first insulating layer forming step of forming a first insulating layer covering the diffusion electrode in which the p electrode is formed and at least a part of the n-type semiconductor layer in which the n electrode is formed;
A reflective layer forming step of forming a reflective layer on the first insulating layer excluding at least a portion above the p electrode and the n electrode;
A second insulating layer forming step of forming a second insulating layer covering the reflective layer,
The opening forming step includes
The first insulating layer and the second insulating layer on the p electrode and the n electrode are removed, and the openings are formed in the insulating layers on the p electrode and the n electrode, respectively. 2. A method for producing a light-emitting device according to 1 . The light emitting element manufacturing method according to claim 2 , wherein the electrode forming step forms a plurality of n electrodes on a surface of the n-type semiconductor layer. The method for manufacturing a light-emitting element according to claim 3 , wherein the electrode forming step forms a plurality of p-electrodes on a surface of the diffusion electrode. The method for manufacturing a light emitting element according to claim 4 , wherein the p electrode and the n electrode have an intermediate layer between the contact layer and the Au layer.

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