TWI253188B - Method of forming light emitting diode array - Google Patents

Abstract

A light emitting element array is disclosed. Each of the light emitting elements with characteristics of having an insulating layer and a metal layer successive enclosed sidewalls thereof. The metal layer on the sidewall of the element provides a function of screening those stray lights generated from the side walls of light emitting elements in neighbor so as to improve resolution of point to point and enhance the light emission efficiency.

Description

Ϊ 253188 1 VII. Designated representative map: . (1) The representative representative of the case is: (5A). The symbol of the symbol of this representative figure is simple: 201 η-type GaAs semi-conductive I#, your 2〇2 gate type (3^ epitaxial layer of the 203 layer η-type AlxGai_xAs under the cladding layer (c|ac|ding Layer) 204 η-type AlyGavyAs layer 205 AlxGai_xAs upper cladding layer (c|acjding layer) 231 wafer 220 metal connection and bonding wire 240 η-type electrode right chemical formula, please reveal the chemical formula that best shows the characteristics of the invention: [Description of the Invention] The present invention relates to a method for fabricating an array type LED light emitting diode (LED) array, which is a kind of light-emitting diode.

A method of forming a p-type cladding layer and an ohmic contact layer of 930902TW 1253188. [Prior Art] The basic structure of the Chen array is similar to that of the light-emitting diode. The main use for electronic body sounds is not to use lighting, but to make _, 弋, sub-heads. Take the mother 吋 1200 points (1200 DPI) and two: 1⁄2, the area of the material element is only about a dozen microns by Xuan micron. It was sent out for twenty meters. Therefore, the hairpin of each light-emitting unit Γ Γ 均 均 均 均 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于U.S. Patent No. 133,588, which is obtained by the prior art. First, the semiconductor substrate 1〇1 of the n-type GaAs is provided, and the GaAS substrate 1〇1 is fed into the organometallic vapor phase epitaxy machine D (M0VPE)' in seconds. It is an n-type doped impurity source, and a wormhole layer required for the growth of organic matter containing Shao, Lukun and Kun. The growth order is η-type GaAS stupid layer 102, the under cladding layer of n-type AlxGai_xAs

AlxGai_xAs105, another semi-essential H (semHnsulating) GaAs 106, and a diffusion mask layer are sequentially formed on the surface of the wafer 131. The diffuser mask layer is again patterned to form second and second windows 133 and 134. Referring subsequently to Figure 2, a diffusion control layer 135 is formed and patterned to leave the first window σ 133 uncovered. Subsequently, a zinc-containing source film 136 and an annealing cap layer 137 are formed. Then, annealing is performed at about 65 (rc) to form a p-type diffusion region 138. During annealing, zinc diffuses deeply into the interior of the wafer 131 and penetrates the diffusion control film 135 to form a shallower = flow conduction.

Current conducting diffusion area 108. ' 930902TW 1253188 • The above annealing conditions must be properly controlled so that the diffusion front of the emitting.

AlyGai_yAs layer 104, and the leading edge of the current conducting diffusion region 1〇8 reaches the semi-insulating layer AlxGauAs· In addition, it is also possible to form a nitride (not shown in the low portion of the wafer 131 to protect the wafer from annealing, lower Part of the impurity is lost. lb W Figure 3 ' Subsequently, the cover layer 137, the diffusion source film 136 = the control layer 1J35 is removed in a rotten manner. The diffusion mask layer _ is not used as an insulating layer. Then, Forming a p-type electrode 彳彳, region 1. 8. Re-annealing so that the P-type electrode 110 is in good contact with the ί 政, 108. Finally, the wafer ^ is ground, and then the n-type bottom electrode is formed.乂 semi-conducting surface shape often, ringing P or η-type semi-conducting (four) (four) 2 two feathers related to 'will shadow ^ first load ^ degree' so often cause problems such as poor light-emitting area. -, reverse ° current through the 'lighting The problem that the insulation between the cells is not astigmatism = the distance between the cells is small, and the interference of the spot is reduced, and the spot discrimination rate is lowered. [Invention] The purpose of the present invention is to solve the above-mentioned conventional technical problems. Array type (2) column type light-emitting diode structure, at least J : ^ Body -, front left foot board t Bu Lai layer packet the light emitting unit, but the bare GU

930902TW 1253188 an electrode; a beryllium metal wire is formed on the bare upper electrode and electrically connected to the other array type light emitting diode from the upper electrode along the sidewall of the light emitting unit; a metal layer is formed on the electrode a protective layer on the sidewall of the light emitting unit; and a lower electrode formed on the back surface of the substrate. The light-emitting unit may include a DBR layer including a substrate, a buffer layer, an n-type epitaxial cladding layer, an active layer, a p-type epitaxial package, a P-type ohmic contact layer, and The light-emitting diode of the p-type electrode. The second light-emitting unit includes at least a substrate including a metal adhesion layer, a metal reflective layer, a P-type electrode, a p-type ohmic contact layer, a p-type epitaxial cladding layer, and an active layer. The n-type insect crystal coating layer, the buffer layer, and the side stop layer of the light-emitting diode: since the metal coating layer is formed on the side wall of the light-emitting unit, the insulating protective layer is dead, and the metal coating can be used to send the side surface The stray light is shielded, thereby improving the light shape of each of the light-emitting units, and improving the clock rate of each light spot, thereby improving the image quality of the light-emitting array. [Embodiment] Conventional technology, P in a light-emitting diode array The ohmic contact layer and the upper cladding layer _ lithography technology define the illuminating range and then apply the expansion technique. As mentioned above, the depth, the width and the impurity concentration are all related to the diffusion control. Often cause uneven illumination area" The reverse current of the polar body is too high, etc. x The present invention will propose three specific preferred embodiments to solve the problem of the electro-optical area unevenness of the prior art. According to the first preferred embodiment of the present invention, the P-type cladding layer The m-contact layer and the n-type cladding layer are grown by MOCVD epitaxy. For the specific growth conditions of the above-mentioned stupid layer, please refer to another patent application of the applicant, the application number is 93129840.

930902TW 1253188 First, please refer to FIG. 4, which is based on the light-emitting diode array of the present invention = GaAs substrate 2GG. Next, the n lion: f 200 is sent to the organometallic vapor phase epitaxy machine (M〇vpE) growth station + Gu 1Η 冲 冲 layer ^ AixG:i(ia^;g 〇τΐρ ^nAf rAlyGr^As 204 small g3 6. n] type layer 2 ° 4 series as a light-emitting 匕 #匕 also 疋 P-type or undoped.

Then, a p-type AlxGalxAS is coated with a photoresist (not shown) to form a 13-type electrode contact window (not shown) i, and a P-type metal (Au/Be Ti/pt ^ 3 pole contact) is formed by a ruthenium plating method. In the window, the use of the separation technique will be redundant; i is divided. Annealing, type r., contact layer 206幵, into a good ohmic contact. = 2 Figure 5A, using photoresist lithography technology to send excess parts to chemistry _ method will be finished in Wei / Lu about A1 two, one pole. Immediately followed by 'typically 〇 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 The dichroic product accumulates the upper surface of the P-type electrode 212 by the bare light-emitting unit 23g and the etching method to define the area of the F-electrode and the bonding wire. To, , ± 桎 2 2 and other illuminating units of the array (not defined, connected: 1 Chi #, the above metal connection and fresh line mine, and a metal coated leg to steam S It is also very early? The insulating protective layer 210 on the side wall of 231 and the Mengyi technology will separate the excess metal. See the figure

A cross-sectional view of 930902TW 1253188 5A and a top view of FIG. 5B. After that, the substrate 200 is first ground to a suitable thickness (2 〇〇 to shed), and the back metal 240 is deposited on the back surface of the substrate 2 by vapor deposition, and is annealed at a temperature of about 380 to 460 ° C. The ohmic contact forms an n-type electrical 240. The n-type electrode 240a may be formed on the front surface of the wafer, except that the n-type electrode 24 of the light-emitting diode is formed on the back surface of the wafer as shown in Fig. 5A. When ' = , the cerium oxide in Fig. 5A is additionally formed with an n-type contact window in addition to the p-type contact window, and an n-type electrode connection line is also formed in the metal bond and wire bond region definition. Finally, annealing at a temperature of 380 to 46 〇〇c forms a good ohmic contact. See Figure 5C for the results. The above-described embodiment in which the light-emitting unit including the DBR layer covers the four side faces of the light-emitting unit with a metal layer may be applied to the array-type light-emitting diode in which the metal-reflective layer is bonded to the substrate by a metal adhesive layer. Referring to Figure 6, a second preferred embodiment of the present invention. In accordance with the method of the present invention, the layers of the array of light-emitting diodes are as in the first embodiment except that the etch stop layer 201B is substituted for the DBR layer 2曰01A. Therefore, as described above, the n-type gallium arsenide (GaAs) substrate 2 is fed into the organic; the epitaxial layer required for the growth of the metal vapor phase epitaxy machine (MOVPE) includes the etch stop layer 201B and the n-type buffer layer. 202, a lower cladding layer 203 of n-type AlxGai xAs, an n-type AlyGa^As 204 and a p-type AlxGal xAs upper cladding layer 205, and a p-type AlzGai-zAs ohmic contact layer 206. Here, the size of X is 0.3 to 1·0, and the size of y can be 〇 to 〇·6, and the size of z can be 0 to 〇·6. The n-type AlyGai-yAs layer 204 is used as a light-emitting active layer, which may also be p-type or undoped. Next, a p-type electrode layer 212 is formed on the p-type ohmic contact layer 206 as described in the first embodiment. Then depositing a transparent conductor oxide layer 213, one by one

930902TW 1253188 Metal reflective layer 214 and a metal bond layer 216 formed on a Type AizGai ohmic contact layer 206. The transparent conductor oxide layer 213 is, for example, indium oxide, z to reduce the reaction of the metal reflective layer 214 and the p-type ohmic contact layer 2?6 during annealing, which deteriorates the metal reflective layer 214. The deposition of the bulk oxide layer 213 in accordance with the method of the present invention is not a necessary and optional step. The material to the reflective layer 214 may be a metal such as gold, silver, or sinter. The material of the metal bonding layer 216 may be, for example, lead tin or indium tin or gold tin or other metal which is liable to cause a eutectic reaction. In accordance with the method of the present invention, reference is made to Figure 7, and subsequently, a receiving substrate 25 is placed in contact with the metal bonding layer 216 and a low temperature annealing of 180-250 ° C is applied to cause the bonding. In accordance with the method of the present invention, the receiving substrate 250 can also form another conforming metal bonding layer 216a to promote adhesion therebetween. The n-type gallium antimonide (GaAs) substrate 200 is then etched away by wet etching to stop the etch stop layer 201B. Referring to FIG. 8, a p-type electrode layer 212 is formed on the erbium-type ohmic contact layer 206 as described in the first embodiment. In the second embodiment, the θ ^ electrode 240 is formed on the etch stop layer 201, and the range of the light-emitting unit 231 is defined as shown in FIG. 5C, and the etch stop layer 2 〇 β is taken up, and the substrate 25 承 is taken down. The lithography and etching technique stops the excess portion by chemical etching on the metal reflective layer 214 (or the metal adhesion layer 216) to form the array light-emitting diode unit 231. Subsequently, an insulating type protective layer 21 is formed over the entire surface to cover the light emitting diode unit 231. Finally, patterning is performed to expose the n-type electrode 240 and the p-type electrode connection window on the metal reflective layer 214 (or the metal adhesion layer 216). Finally, a metal layer is formed as the metal cladding layer 22a and the wiring 220B. The metal clad layer 220A is formed on the insulating protective layer 210 on the four sides of the light emitting unit 231. The connection 220B is the connection of the n-type electrode 240 to the metal cladding layer 220 and the metal cladding layer 220 to other light-emitting units.

930902TW 1253188 Connect the wires. The wiring 220B is connected to the p-type electrode 212. The wiring 220C of the p-type electrode 212 may also be on the back surface of the receiving substrate 250. Further, according to the method of the present invention, in the first and second embodiments described above, the upper layer of the light-emitting unit may be further roughened. In order to change the exit angle of light, the effect of total reflection is reduced, and the luminous efficiency is improved. For example, in the first embodiment, the p-type ohmic contact layer 206 is roughened, and Fig. 5D shows a schematic view of the surface roughening. . The etching stop layer 2?1? is roughened in the second embodiment, and Fig. 8A is a schematic view showing the surface roughening of 201B. Advantages of the invention:

1. Since the n-type cladding layer, the active layer, the p-type cladding layer, and the p-type ohmic contact layer have been formed by using the epitaxial growth, the plurality of rib-defining diffusion covers are significantly reduced as compared with the previous case. The lithographic side steps of the curtain. 2 life ρ, impurity concentration control is easy, and there is no problem of diffusion control longitudinal, lateral twist, and unequal control. Gallium also, _, Kun Huaming 4.=In the invention, the η-type cladding layer is made by insect crystal method, and the living

Good interface, readable clock. Since there is a good (4) material that is better than the present invention, it is not within the scope of the patent. Example 2' should be included in the following description of the electrode below, {column, 孰D phase H'! in the middle of the P electrode is on the top, λ two electrodes are adjusted, still both '丨, right people must be able to make appropriate modifications and still Without departing from the spirit of the invention, it should

930902TW 11 1253188 Within the scope of the present invention, the above modifications are also the same in the second embodiment.

930902TW 12 1253188 [Brief Description of the Drawings] The preferred embodiment of the present invention will be explained in more detail in the following description with the following figures: Figure 1 to Figure 3 show the formation of array-type illumination according to the prior art. Schematic diagram of the manufacturing process of the diode. Fig. 4 is a schematic view showing the structure of a light-emitting diode unit formed by the method according to the first embodiment of the present invention, comprising a DBR layer therein. 5A is a schematic view showing a method of forming a protective layer to cover a light emitting diode unit and forming an n-type electrode on a back surface of a wafer according to the method of the first embodiment of the present invention, and FIG. Fig. 5C is a schematic view showing the formation of an n-type electrode on a buffer layer in such a manner that the electrodes are on the same side in accordance with the method of the first embodiment of the present invention. Figure 5D is a schematic illustration of the roughening of the surface in accordance with the method of the present invention. Figure 6 is a schematic illustration of a method of forming a light-emitting diode comprising a metal reflective layer prior to bonding to a receiving substrate in accordance with a second embodiment of the present invention. Figure 7 is a schematic view showing the method of forming a light-emitting diode unit including a metal reflective layer bonded to a receiving substrate in accordance with a second embodiment of the present invention, and then removing the GaAs substrate. 8 is a diagram showing a method according to a second embodiment of the present invention for forming a light-emitting diode including a metal reflective layer, which is defined as a light-emitting diode, and then covered with an insulating layer, and then wrapped in a metal package. A schematic view of the cladding covering the sidewalls of the light emitting unit. Figure 8A is a schematic illustration of the method of roughening a surface in accordance with the method of the present invention.

930902TW 1253188 [Description of main component symbols] 101 η-type GaAs semiconductor substrate 102, 202 η-type GaAs epitaxial layer buffer layer 103, 203 π-type AlxGai-xAs lower cladding layer (c|adding layer) 104, 204| 1 type 八31_/^ layer 105, 205 AlxGai-xAs upper cladding layer 106 semi-insulating GaAs 108 current conducting diffusion area 109 diffusion mask layer 131 231 wafers 133 and 134 first and second windows 135 diffusion control layer 136 diffusion source film 137 annealing cap layer 138 p-type diffusion region 200 n-type GaAs semiconductor substrate 201 ADBR layer 201B etch stop layer 206 ohmic contact metal layer 210 Insulation type protective layer 250 receives substrate 212 p-type electrode 213 transparent conductor oxide layer 214 metal reflective layer 216 metal bonding layer 220B metal connecting wire

930902TW 1253188 220A metal cladding. 240 η-type electrode

930902TW 15

Claims (1)

1253188 X. Patent application scope · · · · Array type light-emitting diode _ _ A light-emitting unit 戦 构 ' at least contains · · - metal gas: ΐ upper electrode = element side wall and the other array ^ On the layer; the junction of the array type light-emitting diode 3. The type electrode, the lower electrode system_electrode. The structure of the array type light-emitting diode according to the above, wherein the light-emitting unit comprises at least a bottle, and the DBR layer, the buffer layer, and the n-type silicon crystal coating layer are included in the substrate. A Ρ-type ohmic contact layer and the i-type i-pole.阵列ίί利 Range The array type of light-emitting diode according to item 3 is a rough surface from the upper surface of the ohmic contact layer. The junction of the array type light-emitting diode according to Item 1 is characterized in that the upper electrode is an n-type electrode and a lower electrode is a P-type electrode. The structure of the array type light-emitting diode according to claim 1, wherein the light-emitting unit comprises: at least a metal-containing layer, a metal anti-(four), the p-type electrode, a touch layer, and a P layer The insect crystal coating layer, the active layer, the n-type stray crystal coating layer, the buffer layer, and the etch stop layer. The 930902TW 16 1253188 structure of the array type light-emitting diode according to claim 6, further comprising a transparent conductor oxide layer formed between the metal reflective layer and the P-type ohmic contact layer and covering the P Type electrode. 8. The structure of an array type light-emitting diode according to claim 6, wherein the upper surface of the etch stop layer is a thick chain surface. 930902TW 17