JP3340626B2 - Light emitting diode array and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array (LED array) and a method for manufacturing the same.

[0002]

2. Description of the Related Art For a general structure and a manufacturing method of a light emitting diode array used as a light source of an LED print head, see, for example, Reference 1: "Design of an optical printer, supervised by Yoshisuke Takeda, Trikeps, pp 121-126, Showa. 60 years ".

The light-emitting diode array disclosed in Document 1 selectively diffuses a p-type impurity, Zn, into an n-type semiconductor substrate (eg, an n-type GaAsP substrate) to form a PN.
An array of junctions (light emitting diode array) is formed. In addition, a diffusion mask having a diffusion window in a diffusion expected region is used for selective diffusion of Zn into a semiconductor substrate.
Therefore, a diffusion mask having a diffusion window in a diffusion region is provided on the substrate. In addition, one p-type side electrode that is in contact with the diffusion region and extends to above the diffusion mask is provided for each diffusion region. An n-type side electrode is provided on the back surface of the substrate.

[0004]

However, in the above-described light emitting diode array having the conventional structure, when the dot density of the light emitting diodes (LEDs) is increased, the following problems occur.

[0005] For example, when a high dot density such as 1200 dpi is used, the dot pitch becomes about 21 µm. For this reason, the space for routing the p-side electrode (including the p-side electrode pad) becomes very narrow, and it becomes difficult to form a pattern of the p-side electrode.

Further, even if the pattern of the p-type electrode can be formed, the density of the p-type electrode pad becomes extremely high, and connection with an IC for driving each light-emitting diode constituting the light-emitting diode array is made. Wire bonding is substantially impossible.

As described above, in the light emitting diode array having the conventional structure, it is difficult to form a pattern of the p-type side electrode, and wire bonding is substantially impossible. Could not be manufactured.

Therefore, the emergence of a light-emitting diode array having a structure capable of manufacturing a high-density light-emitting diode array and a method of manufacturing the same have been desired. More desirably, the emergence of an LED array and a method of manufacturing the same, in which the light emitting diodes constituting the light emitting diode array have good light emission characteristics, has been desired.

[0009]

Therefore, according to the light emitting diode array of the present invention, a plurality of light emitting diodes each having a junction for light emission between the first conductive type semiconductor region and the second conductive type semiconductor region are provided. In the light emitting diode array having an array and having the first conductivity type side electrode and the second conductivity type side electrode for these light emitting diodes, the light emitting diodes are included in the same number of light emitting diode groups, respectively, and are electrically separated from each other. And a second conductive type side electrode common to one set of light emitting diodes selected one by one from each block in a non-overlapping manner. As wiring, for each set,
The first conductivity type side electrode is provided for each block as one first conductivity type side wiring common to the light emitting diode group in the block.

According to the light emitting diode array of the present invention described above, the light emitting diodes are electrically separated into a plurality of blocks each including the same number of light emitting diodes by using an appropriate separating means. Then, one light emitting diode is non-overlappingly selected from each block to form a set of light emitting diodes, and one common second conductive type common wiring is provided for each set. Further, for each block, one common wiring of the first conductivity type is provided for each of the light emitting diode groups in the block. If the light emitting diode array has such a structure, one second conductivity type electrode pad is provided for each second conductivity type common wiring, and the first conductivity type electrode pad is provided for each first conductivity type wiring. Since it is only necessary to provide one electrode pad, the total number of pads is smaller than in the conventional case where one electrode pad is provided for each light emitting diode. Therefore, even when the dot density of the light emitting diode is high, the density of the electrode pads can be reduced. Therefore, the electrode pattern including the electrode pad is easily formed, and the wire bonding for connecting to the IC for driving the light emitting diode is facilitated.

In addition, in the light-emitting diode array according to the present invention, the first conductive type semiconductor region is an upper layer made of the first conductive type semiconductor provided above a base made of a semi-insulating semiconductor or an insulator, and the second conductive type semiconductor region is made of a second conductive type. The type semiconductor region is an island-shaped region made of a second conductivity type semiconductor selectively formed from a top surface of the upper layer to a part of a depth in a thickness direction of the upper layer;
The separating means is a separating groove extending from the upper surface of the upper layer to the base. With such a structure, the first conductivity type semiconductor region is
It becomes easy to partition into a plurality of electrically separated blocks (hereinafter, this block may be referred to as a first conductivity type block) each including the same number of light emitting diodes as a light emitting diode group.

When the shape of the separation groove in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer is rectangular, the space for the separation groove can be saved, so that a high-density light emitting diode array is provided. Can be configured.

In the case where the shape of the separation groove in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer is a regular mesa, even if the separation groove is not embedded,
There is no risk of disconnection occurring in the second conductive type common wiring provided across the separation groove.

Further, the width of the separation groove in a direction parallel to the arrangement direction of the light emitting diodes is made sufficiently small so as not to affect the characteristics of the light emitting diode array in the region where the light emitting diodes are arranged, and in the other regions. In the case where the width is sufficiently larger than the depth of the groove, a high-density light-emitting diode array can be formed, and the second conductivity type side provided across the separation groove without embedding the separation groove can be formed. The risk of disconnection occurring in the common wiring is eliminated. Here, in the region where the light emitting diodes are arranged, in order to make the width of the separation groove in the direction parallel to the arrangement direction of the light emitting diodes sufficiently narrow so as not to affect the characteristics of the light emitting diode array, The shape of the separation groove in a cross section parallel to the arrangement direction and perpendicular to the upper surface of the upper layer may be rectangular. Further, in a region other than the region where the light emitting diodes are arranged, when the width of the separation groove in the direction parallel to the arrangement direction of the light emitting diodes is made sufficiently wider than the depth of the separation groove, the arrangement of the light emitting diodes is It is preferable that the shape of the separation groove in a cross section parallel to the direction and perpendicular to the upper surface of the upper layer be a regular mesa shape.

When the isolation groove is buried with an insulating material so that the surface of the sample is flattened, the second conductive type common wiring provided across the isolation groove is disconnected regardless of the shape and depth of the isolation groove. There is no danger of occurrence. In this case, polyimide can be used as the insulating material.

The second conductive type side individual wiring is provided, one end of which is connected to the corresponding second conductive type common wiring and the other end of which is provided in contact with the second conductive type semiconductor region of the corresponding light emitting diode. In other words, when the second conductive type individual wiring provided in contact with the second conductive type semiconductor region of the same set of light emitting diodes is connected to one second conductive type common wiring, It is easy to make the second conductive type side common wiring function as a common wiring for the set of light emitting diodes.

Here, a first interlayer insulating film is provided between the upper layer and the second conductive type common wiring, and a second interlayer insulating film is provided between the second conductive type common wiring and the second conductive type individual wiring. The connection between the second conductive type side individual wiring and the second conductive type side common wiring is
The contact is made through a via hole reaching the second conductive type common wiring through the interlayer insulating film, and the contact between the second conductive type individual wiring and the second conductive type semiconductor region passes through the first and second interlayer insulating films. In this case, the opening is formed through the opening reaching the second conductivity type semiconductor region.
The conductive type common wiring and the second conductive type individual wiring are insulated by the second interlayer insulating film, and the second conductive type side individual wiring and the upper layer are separated by the first and second interlayer insulating films in portions other than the openings. It is insulated, and the second conductive type common wiring and the upper layer are insulated by the first interlayer insulating film.

On the other hand, a first interlayer insulating film is provided between the upper layer and the second conductive type individual wiring, and a second interlayer insulating film is provided between the second conductive type individual wiring and the second conductive type common wiring. The connection between the second-conductivity-type-side individual wiring and the second-conductivity-type-side common wiring is made through a via hole penetrating the second interlayer insulating film and reaching the second-conductivity-type-side common wiring. When the contact between the wiring and the second conductivity type semiconductor region is made through an opening that penetrates the first interlayer insulating film and reaches the second conductivity type semiconductor region, the second conductivity type side individual wiring is connected to a portion other than the via hole. The second conductive type common wiring is insulated by the second interlayer insulating film, and the second conductive type individual wiring and the upper layer are insulated by a first interlayer insulating film in portions other than the openings.

Each of the first conductivity type blocks has a first conductivity type ohmic electrode provided in contact with the upper surface of the upper layer in the block and commonly provided for the light emitting diode group in the block. In this case, the first-conductivity-type-side wiring is less likely to come off.

Also, a second conductivity type electrode pad provided in connection with the second conductivity type common wiring, and a first conductivity type electrode pad provided in connection with the first conductivity type wiring, respectively. When the first and second conductive type side electrode pads are provided in one region with the arrangement of the light emitting diodes as a boundary, wire bonding for connecting to an IC for driving the light emitting diodes is provided. It will be easier. In particular, when the first and second conductivity type side electrode pads are provided in a line, the space for providing these electrode pads can be reduced, so that the size of the light emitting diode array chip can be reduced.

Each of the first conductivity type blocks has a first conductivity type ohmic electrode provided in contact with the upper surface of the upper layer in the block and provided in common to the light emitting diode group in the block. The first conductive type ohmic electrode is
When each of the conductive type blocks is provided in one region with the arrangement of the light emitting diodes as a boundary, in each first conductive type block, a junction region between the first conductive type semiconductor region and the second conductive type semiconductor region is provided. The electric field distribution can be made uniform among the light emitting diodes. Therefore, all the light emitting diodes in each first conductivity type block have the same light emitting characteristics, and the light emitting characteristics among the light emitting diodes do not vary.

A second conductive type side individual wiring, one end of which is connected to the corresponding second conductive type common wiring and the other end of which is provided in contact with the second conductive type semiconductor region of the corresponding light emitting diode; A first conductivity type ohmic electrode provided in contact with the upper surface of the upper layer in the block and commonly provided for the light emitting diode group in the block for each first conductivity type block; The mold-side ohmic electrode is provided in one region for each first-conductivity-type block with the arrangement of the light-emitting diodes as a boundary, and the second conductive-type ohmic electrode is opposite to the region in which the first-conductivity-type-side ohmic electrode is provided. When the other end of the second-conductivity-type-side individual wiring is in contact with the portion of the second-conductivity-type semiconductor region, when a voltage is applied to the junction between the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region, Current is uniform in the semiconductor region To flow. Thus the second
When the current flows uniformly in the conductive semiconductor region, the light emission characteristics are improved.

According to the method of manufacturing a light emitting diode array of the present invention, an array of a plurality of light emitting diodes each having a junction for emitting light between the first conductive type semiconductor region and the second conductive type semiconductor region is provided. In manufacturing a light emitting diode array having the first conductivity type side electrode and the second conductivity type side electrode for the light emitting diode, a first conductivity type semiconductor region provided on a base made of a semi-insulating semiconductor or insulator. The second conductive layer extends from the upper surface of the upper layer made of the first conductivity type semiconductor to a part of the depth in the thickness direction of the upper layer.
A step of forming an array of a plurality of light emitting diodes by selectively forming an island region made of a second conductive type semiconductor as a conductive type semiconductor region, and including the same number of light emitting diodes as light emitting diode groups respectively Forming a separation groove extending from the upper surface of the upper layer to the base for partitioning into a plurality of first conductivity type blocks electrically separated from each other; and forming a second conductivity type side electrode from each first conductivity type block. Forming a second conductive type side common wire common to one set of light emitting diodes selected one by one in a non-overlapping manner for each set; Forming one common first-conductivity-type wiring for each light-emitting diode group in the block for each one-conductivity-type block.

According to the above-described method of manufacturing the light emitting diode array, the light emitting diodes are electrically separated into a plurality of first conductivity type blocks each including the same number of light emitting diodes by using the separation groove extending from the upper surface of the upper layer to the base. Then, one light emitting diode is non-overlappingly selected from each first conductivity type block to form a set of light emitting diodes, and one common second conductivity type common wiring is formed for each set. Also, the first
One common first-conductivity-type wiring is formed for each light-emitting diode group in each conductive-type block. If the light emitting diode array is manufactured in this way, one second conductivity type electrode pad is formed for each second conductivity type common wiring, and one first conductivity type electrode pad is formed for each first conductivity type wiring. Since only one electrode pad needs to be formed, the total number of pads to be formed is smaller than in the conventional case in which electrode pads are formed one by one on the light emitting diode. For this reason, even when the dot density of the light emitting diode is high, the density of the electrode pads to be formed can be reduced. Therefore, it is easy to form an electrode pattern including the electrode pad.

Then, a step of forming a first interlayer insulating film on the upper layer, and forming a second conductive type common wiring on the first interlayer insulating film, and then forming the first interlayer insulating film on the first interlayer insulating film. Forming a second interlayer insulating film covering the common wiring on the two conductivity type side;
Forming a via hole penetrating through the interlayer insulating film and reaching the second conductive type common wiring and an opening reaching the island region through the first and second interlayer insulating films; Forming a second conductive type-side individual wiring by connecting one end to the mold-side common wiring and bringing the other end into contact with the corresponding island-shaped region of the light-emitting diode through the opening. Part 2
The common wiring on the second conductivity type side is formed insulated from the individual wiring on the second conductivity type side by the interlayer insulating film.
The second conductive type side individual wiring can be formed insulated from the upper layer by the second interlayer insulating film, and the second conductive type side common wiring can be formed insulated from the upper layer by the first interlayer insulating film.

In addition, a step of forming a first interlayer insulating film on the upper layer, a step of forming an opening penetrating the first interlayer insulating film and reaching the island region, and a step of forming a corresponding light emitting diode through the opening. Forming a second conductive type side individual wiring by bringing the other end into contact with the island-shaped region; and forming a second conductive type second wiring on the first interlayer insulating film.
Forming a second interlayer insulating film covering the conductive type-side individual wiring, forming a via hole through the second interlayer insulating film to reach the second conductive type-side individual wiring, and a corresponding second conductive film through the via hole. Forming the second conductive type common wiring by connecting to one end of the mold side individual wiring, the second conductive type side individual wiring is formed by the second interlayer insulating film in a portion other than the via hole. It is formed insulated from the conductive type side common wiring, and the second interlayer insulating film is formed on the portion other than the opening by the first interlayer insulating film.
The conductivity type individual wiring can be formed insulated from the upper layer.

The first interlayer insulating film may be formed by a diffusion mask having a diffusion window in a region where an island region is to be formed, a diffusion source film containing a second conductivity type impurity formed on the diffusion mask, A laminated film having a configuration in which an annealing cap film formed on the diffusion source film is laminated is formed, and the formation of the island region is performed by solid-phase diffusion to the upper layer of the second conductivity type impurity contained in the diffusion source film. In this case, since the island-shaped region can be formed shallowly, the thickness of the upper layer can be reduced. As a result, the aspect ratio of the separation groove can be reduced. Further, since the diffusion mask, the diffusion source film, and the annealing cap film used for forming the island region are used as the first interlayer insulating film, the manufacturing process of the light emitting diode array can be omitted.

Further, when the separation groove is formed so as to have a rectangular shape in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer, the space for the separation groove can be saved. Thus, a high-density light-emitting diode array can be formed.

In the case where the separation groove is formed so as to have a forward mesa shape in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer, the separation groove may not be embedded. In addition, the second conductive type common wiring can be formed by traversing the separation groove without fear of disconnection.

Further, the width of the separation groove in a direction parallel to the arrangement direction of the light emitting diodes is sufficiently small in the region where the light emitting diodes are arranged so as not to affect the characteristics of the light emitting diode array, and in other regions. If it is formed so as to be sufficiently wider than the depth, it is possible to form a high-density photodiode array, and to traverse the separation groove without fear of disconnection without embedding the separation groove. The two-conductivity-type common wiring can be formed.
Here, in the region where the light emitting diodes are arranged, in order to form the width of the separation groove in a direction parallel to the arrangement direction of the light emitting diodes so as to be sufficiently small so as not to affect the characteristics of the light emitting diode array, What is necessary is just to form so that the shape of the isolation groove in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer may be rectangular. Further, in a region other than the region where the light emitting diodes are arranged, when the width of the separation groove in the direction parallel to the arrangement direction of the light emitting diodes is formed to be sufficiently wider than the depth of the separation groove, the light emitting diode Is preferably formed so that the shape of the separation groove in a cross section parallel to the arrangement direction and perpendicular to the upper surface of the upper layer has a regular mesa shape.

In the case where the separation groove is buried with an insulating material so that the surface of the sample is flattened, regardless of the shape and depth of the separation groove, the separation groove is traversed without fear of disconnection, and the second conductivity type side is formed. A common wiring can be formed. In this case, polyimide can be used as the insulating material.

When the upper layer is formed by epitaxially growing the first conductivity type semiconductor layer to a predetermined thickness on the semi-insulating semiconductor substrate or the insulating substrate, a uniform upper layer can be formed. .

When the upper layer is formed by diffusing the first conductivity type impurity from the upper surface of the semi-insulating semiconductor substrate to a predetermined depth, an inexpensive upper layer can be formed.

Further, in the case where a first conductivity type ohmic electrode is provided for each block of the first conductivity type, which is provided in contact with the upper surface of the upper layer in the block and provided in common to the light emitting diode group in the block. In this case, the first conductivity type side wiring is easily formed.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In each of the drawings used in the following description, each component merely schematically shows its shape, size, and positional relationship so that the present invention can be understood. In the drawings used for the description, the same components are denoted by the same reference numerals, and the duplicate description thereof may be omitted. Further, the numerical conditions such as the materials used, the forming method, and the film thickness described in the following description are merely preferred examples of the present invention. Therefore, it should be understood that the invention according to this application is not limited only to these conditions.

First, FIGS. 1 and 2A to 2C show a basic configuration example of a light emitting diode array according to the present invention.
This will be described with reference to FIG. FIG. 1 is a schematic plan view showing a basic configuration example of a light emitting diode array according to the present invention, and FIG. 2A is a schematic plan view taken along a line II in FIG. FIG. 2 is a cross-sectional view (a cutaway view),
FIG. 2B is a schematic sectional view taken along the line II-II in FIG. 1 (however, a cutaway view), and FIG. 2C is a view along the line III-III in FIG. It is the schematic sectional drawing (however, the figure of a cut side) cut and taken.

As shown in FIGS. 1 and 2A to 2C, the light emitting diode array of the present invention is provided on a base 11 made of a semi-insulating semiconductor substrate. An upper layer 13 made of an n-type semiconductor, and p as a second conductivity type semiconductor region selectively formed from an upper surface of the upper layer 13 to a part of a depth in a thickness direction thereof.
(PN junction) 1 with island-shaped region 15 made of type semiconductor
L of a plurality of light emitting diodes 19 each having
It has. The light-emitting diodes 19 are arranged in a line at regular intervals.

A plurality of electrically separated n-type blocks 23 each including the same number of light emitting diodes 19, for example, four light emitting diode groups 21, respectively.
From the upper surface of the upper layer 13 to the base 1
It has a separation groove 25 reaching one. This separation groove 25
The shape of the cross section parallel to the arrangement direction of the light emitting diodes 19 and perpendicular to the upper surface of the upper layer 13 is rectangular (see FIG. 2B). Then, the separation groove 25 is buried with an insulating material 27. When polyimide is used as the insulating material 27, the isolation groove 2 having a large aspect ratio is used.
Even if it is 5, it can be completely embedded. When the cross-sectional shape of the separation groove is rectangular, it is effective to embed the separation groove with an insulating material. If it is wide enough, it is not always necessary to fill the isolation trench with an insulating material.

Further, one p-type common wiring 29 as a second conductive type common wiring common to one set of light emitting diodes 19 non-overlapping one by one from each n-type block 23 is provided. Each is provided for each set. That is, the light emitting diodes 19 are non-overlapping one by one from each n-type block 23.
Are selected to form four sets of light emitting diodes 19, and one common p-type common wiring 29 is provided for each set. Each p-type common wiring 29 is provided across all the n-type blocks 23 across the separation groove 25. Here, non-overlapping means that the light emitting diode 19 once selected is not selected again (the same applies hereinafter). For example, the first light emitting diodes 19 from the left of each n-type block 23 are selected one by one to form one set,
Similarly, the second light emitting diode 19 from the left is selected one by one to form one set, and the third light emitting diode 19 from the left is selected one by one to form one set, and the fourth light emitting diode from the left is formed. The diodes 19 are selected one by one to form one set. Here, a p-type individual wiring 31 is provided, one end of which is connected to the p-type common wiring 29 and the other end of which is in contact with the surface of the island region 15 of the light emitting diode 19. All the p-type individual wirings 31 provided in contact with the surfaces of the island regions 15 of the same set of light emitting diodes 19 are connected to the same p-type common wiring 29. Also, the upper layer 13 and p
A first interlayer insulating film 33 between the p-side common wiring 29 and a second interlayer insulating film 35 between the p-side common wiring 29 and the p-side individual wiring 31; The connection with the mold-side common wiring 29 is made through a via hole 37 that penetrates through the second interlayer insulating film 35 and reaches the p-type common wiring 29. Is performed through an opening 39 that reaches the surface of the island region 15 through the first and second interlayer insulating films 33 and 35. Each of the p-side common wirings 29 is connected to a p-side electrode pad (not shown) serving as one common second conductivity-type electrode pad.

Further, for each n-type block 23, an n-type side wiring 41 as one first conductivity type side wiring common to the light emitting diode group 21 in the n-type block 23 is provided. Here, for each n-type block 23, a first conductivity type ohmic electrode provided in contact with the upper surface of the upper layer 13 in the n-type block 23 and commonly provided for the light emitting diode group 21 in the n-type block 23. , And an n-type electrode pad 45 as a first conductivity-type electrode pad which is connected to the n-type wiring 41 and provided respectively. n-type ohmic electrode 4
Numeral 3 is provided in one region for each n-type block 23 with the array L of the light emitting diodes 19 as a boundary. n-type side wiring 4
The connection between 1 and the n-type ohmic electrode 43 is made through a via hole 47 that penetrates through the second interlayer insulating film 35 and reaches the n-type ohmic electrode 43.

Although not shown, the n-type side electrode pad 4
5 and the p-side electrode pad are provided in one region with the arrangement L of the light emitting diodes 17 as a boundary.

In order to drive the light emitting diode array having such a structure, a time division driving method may be used. The same goes for the following embodiments. For this reason, the description of the driving method is omitted in each of the following embodiments.

In the above description, the light emitting diode 1
Although the case where the shape of the separation groove 25 is rectangular in the cross section parallel to the arrangement direction 9 and perpendicular to the upper layer 13 has been described, the cross sectional shape may be a normal mesa shape. Further, the cross-sectional shape may be a rectangular shape in a region near the arrangement of the light emitting diodes and a regular mesa shape in other regions. Further, a case in which the width is different between the region near the light emitting diode array and the other region may be a normal mesa shape. Specific examples of the case where the cross-sectional shape is a rectangular shape, a normal mesa shape, a rectangular shape in a region where light emitting diodes are arranged, and a mesa shape in other regions will be described later.

In the above description, the first interlayer insulating film 33 is provided between the upper layer 13 and the p-type common wiring 29 and the second interlayer insulating film 33 is provided between the p-type common wiring 29 and the p-type individual wiring 31. An insulating film 35 is provided, and the p-type individual wiring 31 and the p-type common wiring 2
9 is made through a via hole 37 that penetrates through the second interlayer insulating film 35 and reaches the p-type common wiring 29. The contact between the p-type individual wiring 31 and the surface of the island-shaped region 15 is made by the first and the second. In the case where the process is performed through the opening 39 that reaches the surface of the island region 15 through the second interlayer insulating films 33 and 35, ie, the first interlayer insulating film
The case where the mold-side common wiring 29, the second interlayer insulating film 35, and the p-type individual wiring 31 are provided in this order has been described. However, the present invention is not limited to this case. A first interlayer insulating film, a second interlayer insulating film between the p-type individual wiring and the p-type common wiring,
The connection with the mold-side common wiring is made through a via hole that penetrates through the second interlayer insulating film and reaches the p-type individual wiring.
The contact between the p-type individual wiring and the surface of the island region is made through the opening reaching the surface of the island region through the first interlayer insulating film, that is, the first interlayer insulating film is formed on the upper layer.
The p-type individual wiring, the second interlayer insulating film, and the p-type individual wiring may be provided in this order. Specific structural examples in these two cases will be described later.

FIG. 1 shows the case where the other end of the p-type individual electrode 31 is in contact with the surface of the island-shaped region on the same side as the region where the n-type ohmic electrode 43 is provided. However, the present invention is not limited to this case. As shown in FIGS. 3 and 4, the other end of the p-type individual electrode 31 is connected to the island-shaped region 15 on the opposite side to the region where the n-type ohmic electrode 43 is provided. May be in contact with the surface portion of. These two
A specific example of the structure in the two cases will be described later.

The specific structure of the light emitting diode array according to the present invention and the method of manufacturing the same will be described below.
A description will be given as a fifth embodiment.

1. First Embodiment First, a light-emitting diode array according to this embodiment will be described with reference to FIGS. FIG. 5 (A)
FIG. 5B is a schematic plan view showing a light-emitting diode array according to this embodiment, and FIG.
FIG. 5C is a schematic sectional view taken along line I (however, a cutaway view), and FIG. 5C is a schematic sectional view taken along line II-II in FIG. FIG. 6 is a cross-sectional view (a cut-away view), and FIG. 6 is a schematic cross-sectional view (a cut-away view) taken along line III-III in FIG.

The light emitting diode array of this embodiment has an n-type GaAs layer as an upper layer 13 formed by epitaxial growth on a semi-insulating GaAs substrate as a base 11, and a thickness direction from the upper surface of the upper layer 13 to its thickness. (P-n junction) 17 with a p-type GaAs region as an island region (hereinafter referred to as a diffusion region) 15 formed by selectively diffusing Zn as a p-type impurity over a part of the depth of And an array of a plurality of light emitting diodes 19. The light-emitting diodes 19 are arranged in a line at regular intervals. FIG. 5 (A) shows a separation groove 25 to be described later among a large number of light emitting diodes 19.
3 shows a region including five light emitting diodes 19 provided continuously with the light emitting diode 19 interposed therebetween. The thickness of the upper layer 13 is, for example, 4 μm, and the diffusion depth of the diffusion region 15 is
For example, it is 1 μm. As will be described in detail later, the diffusion region 15 is formed by using a diffusion mask 51 provided on the upper layer 13 and having a diffusion window 51a in a region to be diffused, and solidifying Zn from the diffusion window 51a to the upper layer 13. Since the diffusion region 15 is formed by phase diffusion, the diffusion region 15 extends not only in a direction perpendicular to the upper surface of the upper layer 13 but also in a direction parallel to the upper surface of the upper layer 13, that is, in the lateral direction. Note that in order to avoid complicating the drawing, FIG. 5A shows the diffusion mask 5 in the region where the light emitting diode 19 is provided.
Only the position of the first diffusion window 51a is surrounded by a broken line, and the irregularities of the diffusion source film 53 and the annealing cap film 55 are not shown in the drawing (the same applies to the following manufacturing steps and other embodiments). Is.).

As described above, when the thickness of the upper layer 13 is 4 μm and the diffusion depth of the diffusion region 15 is 1 μm,
Since the distance from the PN junction 17 to the base 11 is about 3 μm and longer than the average free path (about 2 μm) of holes injected from the diffusion region 15 into the upper layer 13, the luminous efficiency of each light emitting diode 19 constituting the light emitting diode array Is not considered to be affected.

The same number of light emitting diodes 19, for example, four light emitting diode groups are included.
It has a separation groove 25 for partitioning into a plurality of n-type blocks electrically separated from each other. The separation groove 25 is formed in the upper layer 13.
Of the separation groove 25 in a cross section parallel to the arrangement direction of the light emitting diodes 19 (hereinafter sometimes referred to as an LED arrangement direction) and perpendicular to the upper surface of the upper layer 13. The shape is rectangular (see FIG. 5C). The depth of the separation groove 25 is, for example, 6 μm. The separation groove 25 is buried with an insulating material 27 made of polyimide. The separation groove 25
As described in detail later, a first layer is formed on the upper layer 13.
An interlayer insulating film 33 is provided, and a part thereof,
After removing the first interlayer insulating film 33 in the region where the fifth trench 5 is to be formed, an opening 57 for forming a separation trench is formed.
From the upper surface of the upper layer 13 exposed from this opening 57,
It is formed by etching until it reaches 1. Therefore, the opening 57 for forming the separation groove formed in the first interlayer insulating film 33 is also buried with polyimide. The depth of the separation groove 25 is larger than the thickness of the upper layer 13,
In addition, the separation groove 25 may have any suitable size that can be embedded with the insulating material 27.

The width of the separation groove 25 in the LED array direction may be any suitable size depending on the dot density of the light emitting diode 19 and the width of the upper surface 13 of the diffusion region 15 in the LED array direction. FIG. 7 is a schematic diagram showing an arrangement relationship between the diffusion region and the separation groove. For example, when the dot density of the light emitting diode 19 is 1200 dpi, the dot pitch p is about 21 μm. Therefore, as shown in FIG. 7, the width a of the diffusion window (not shown) in the LED array direction is set to 5
If the horizontal diffusion distance b of Zn is 1.5 μm, the width c in the LED array direction on the upper surface of the upper layer 13 of the diffusion region 15 is 8 μm. Therefore, L of the separation groove 25
When the width d in the ED arrangement direction is 5 μm, the distance e from the diffusion region 15 to the separation groove 25 can be secured about 4 μm. The width d of the separation groove 25 in the LED array direction is 5 μm.
In this case, as described above, the separation groove 25 has a depth of 6
Since the thickness is μm, the aspect ratio (depth / width) of the groove formed by the separation groove 25 and the opening 57 for forming the separation groove is about 1 even when the thickness of the first interlayer insulating film 33 is considered. Become. In the case of this aspect ratio, this groove can be completely filled with polyimide.

Further, one common light emitting diode 19 is selected one by one from each n-type block in a non-overlapping manner.
The p-side common wirings 29 are provided for each set. That is, the light emitting diodes 19 are selected one by one from each n-type block in a non-overlapping manner, and four sets of light emitting diodes 19 are formed, and one common p-type common wiring 29 is provided for each set. It is. Each p-type common wiring 29 is provided with
5 and across all n-type blocks. For example, the first light emitting diodes 19 from the left of each n-type block are selected one by one to form one set, and similarly, the second light emitting diodes 19 from the left are selected one by one to form one set. , The third light emitting diode 19 from the left
Are selected one by one to form one set, and the fourth light emitting diode 19 from the left is selected one by one to form one set.

Further, a p-type individual wiring 31 having one end connected to the p-type common wiring 29 and the other end in contact with the surface of the diffusion region 15 of the light emitting diode 19 is provided.
All the p-type individual wirings 31 provided in contact with the surface of the diffusion region 15 of the same set of light emitting diodes 19 have the same p-type.
Connected to the mold side common wiring 29. The p-side common wiring 29 and the p-side individual wiring 31 are made of Al. However, the surface of the p-type common wiring 29 is coated with Ni to prevent oxidation of the surface and enable connection with the p-type individual wiring 31.

A diffusion mask 51 made of AlN, a diffusion source film 53 made of a mixture of ZnO and SiO ₂ , and a SiN or A first interlayer insulating film 33 composed of a laminated film having a configuration in which an annealing cap film 55 composed of AlN is laminated is provided. An insulating film 35 is provided. That is, the p-type common wiring 29 is provided on the first interlayer insulating film 33, and the p-type individual wiring 31 is provided on the second interlayer insulating film 35. This first interlayer insulating film 33
Is also a film used to form the diffusion region 15, so that the diffusion mask 51 has a diffusion window 51 a in the diffusion region 15.
Is provided. The thickness of the diffusion mask 51 is, for example, 2
000 °, and the thickness of the diffusion source film 53 is, for example, 200
Å2000 ア ニ ー ル, and the thickness of the annealing cap film 55 is, for example, 200〜2000Å. The thickness of the second interlayer insulating film 35 is, for example, 1000 °.

The connection between the p-type individual wiring 31 and the p-type common wiring 29 is made through a via hole 37 that reaches the p-type common wiring 29 through the second interlayer insulating film 35. The contact between the individual wiring 31 and the surface of the diffusion region 15 is made through an opening 39 that passes through the first and second interlayer insulating films 33 and 35 and reaches the surface of the diffusion region 15.

Further, a p-type electrode pad (not shown) provided to be connected to the p-type common wiring 33 is provided.

Also, for each n-type block, one common n-type side wiring 41 for the light emitting diode group in the n-type block
Are provided respectively. Further, for each n-type block, n
The n-type ohmic electrode 43 provided in contact with the upper surface of the upper layer 13 in the mold block and commonly provided for the light-emitting diode group in the n-type block, And a mold-side electrode pad 45. The n-type side wiring 41 and the n-type side electrode pad 45 are
It is provided on the interlayer insulating film 35. The n-type ohmic electrode 43 is provided in one region, specifically, the light-emitting diode
Are provided in a region between the region where is arranged and the region where the p-type common wiring 33 is provided. The other end of the p-type individual wiring 31 contacts the surface of the diffusion region 15 on the same side as the region where the n-type ohmic electrode 43 is provided. The n-type ohmic electrode 43 is formed on the exposed upper layer 13 after a part of the first interlayer insulating film 33 is removed to expose the upper layer 13 as described later in detail. Therefore, the periphery of the n-type ohmic electrode 43 is surrounded by the first interlayer insulating film 33. The connection between the n-side wiring 41 and the n-side ohmic electrode 43 is made through a via hole 47 that penetrates through the second interlayer insulating film 35 and reaches the n-side ohmic electrode 43. The n-type side wiring 41 is made of Al, and the n-type ohmic electrode 43 is made of a gold alloy.

Although not shown, the n-side electrode pad 4
9 and the p-type side electrode pad are provided in one region with the arrangement of the light emitting diodes 19 as a boundary.

Next, a method of manufacturing the light emitting diode array having the above structure will be described with reference to FIGS. (A) in FIGS. 8 to 16 is a schematic plan view at a main manufacturing stage of the light emitting diode array.
(B) in FIG. 16 to FIG. 16 is a schematic view of a light-emitting diode array shown by a cross-sectional view (a cut-away view) corresponding to a cross-section taken along line II in FIG. 5 (A). It is a manufacturing process figure, and (C) in FIGS.
FIG. 2A is a schematic manufacturing process diagram of a light-emitting diode array shown by a cross-sectional view (a cutaway view) corresponding to a cross-section taken along line II-II in (A).

First, semi-insulating GaAs as the base 11
A plurality of light emitting diodes are formed by forming a p-type GaAs region as a diffusion region 15 from the upper surface of an n-type GaAs layer as an upper layer 13 on the s substrate to a part of the depth in the thickness direction of the upper layer 13. 19 sequences are formed.

In this embodiment, first, an n-type GaAs layer as the upper layer 13 is formed by epitaxial growth on a semi-insulating GaAs substrate as the base 11. The upper layer 13 is formed to a thickness of, for example, 4 μm. Thereafter, on the upper layer 13, a diffusion mask 51 having a diffusion window 51a in a diffusion expected region, a diffusion source film 53 covering the diffusion mask 51, and an annealing cap film 55 covering the diffusion source film 53 are formed. The diffusion mask 51 is made of an AlN film, and is formed to a thickness of, for example, 2000 ° by sputtering. The diffusion source film 53 is made of a mixed film of ZnO and SiO ₂ , for example, 200 to 2000 by sputtering.
It is formed to a film thickness of Å. The annealing cap film 55 is made of SiN
The SiN film is formed by plasma CVD and the AlN film is formed by sputtering.
It is formed to a thickness of 0 to 2000 °. Thereafter, for example, by performing a heat treatment at 700 ° C. for 2 hours in a nitrogen atmosphere, Zn as a p-type impurity contained in the diffusion source film 53 is solid-phase diffused from the diffusion window 51a to the upper layer 13 to form the diffusion region 15 ( 8 (A) to 8 (C)). The diffusion depth of the diffusion region 15 is, for example, 1 μm. The heat treatment at the time of diffusing Zn is performed by combining the thicknesses of the diffusion mask 51, the diffusion source film 53, and the annealing cap film 55 and the materials used,
Further, it may be performed under any suitable condition depending on the shape and size of the diffusion window 51a. Note that a laminated film having a configuration in which the diffusion mask 51, the diffusion source film 53, and the annealing cap film 55 are laminated is used as the first interlayer insulating film 33 in the subsequent steps.

Next, the same number of light emitting diodes 19, for example, four light emitting diode groups are included.
A separation groove 2 reaching the base 11 from the upper surface of the upper layer 13 for partitioning into a plurality of n-type blocks electrically separated from each other.
5 is formed.

In this embodiment, prior to the formation of the isolation groove 25, the n-type ohmic electrode 43 is formed. The n-type ohmic electrode 43 is formed for each n-type block in contact with the upper surface of the upper layer 13 in the n-type block and commonly for the light emitting diode group in the n-type block. For this reason,
First, a part of the first interlayer insulating film 33, that is, the first interlayer insulating film 33 in the region where the n-type ohmic electrode 43 is to be formed is formed.
Is removed to form an opening 59 for forming an n-type ohmic electrode in the first interlayer insulating film 33 (FIG. 9A to FIG. 9A).
(C)). In this step, the opening 5 for forming the separation groove is formed.
7 is also formed. In order to remove a part of the first interlayer insulating film 33, a known photolithography technique and an etching technique are used. Thereafter, an n-type ohmic electrode 43 made of a gold alloy is formed on the upper layer 13 exposed from the opening 59 for forming the n-type ohmic electrode (FIG. 10).
(A) to (C)). For forming the n-type side ohmic electrode 43, a known vapor deposition lift-off method is used. The n-side ohmic electrode 43 is connected to the light emitting diode 19
Is formed in one region, specifically, a region between the region where the light emitting diodes 19 are arranged and the region where the p-type common wiring 33 is to be formed.

After that, a resist having a window at the same portion as the opening 57 for forming the separation groove is provided on the surface of the sample.
Using this resist as a mask, isolation grooves 25 are formed by dry etching using a mixed gas of BCl ₃ and Cl ₂ as an etching gas (FIG. 11A to FIG. 11A).
(C)). FIG. 11 shows a state after the resist used as the mask has been removed. Dry etching is
This is performed under the condition that the shape of the separation groove 25 in a cross section parallel to the LED arrangement direction and perpendicular to the upper surface of the upper layer 13 is rectangular. The depth of the separation groove 25 is, for example, 6 μm, and the width of the separation groove 25 is, for example, 5 μm. Prior to the formation of the separation groove 25, the n-type ohmic electrode 43
When the n-type ohmic electrode 43 is formed after the formation of the separation groove 25, the separation groove 25 is preferably formed by a deposition lift-off resist used in forming the n-type ohmic electrode 43. This is because the n-type ohmic electrode 43 may not be satisfactorily formed.

Next, one common light emitting diode 19 is selected non-overlappingly from each n-type block.
The p-type common wiring 29 is formed for each group.

In this embodiment, the p-side common wiring 29
Prior to the formation, the isolation groove 25 is filled with an insulating material 31 made of polyimide. For this purpose, first, polyimide is applied on the surface of the sample to form a film 61 made of polyimide (FIGS. 12A to 12C). In this case, the separation groove 25
Is applied to such a thickness as to be able to bury the film, and then the film 61 made of the polyimide is subjected to a heat treatment (sometimes referred to as curing or baking). This film 61 is imidized by the heat treatment. Thereafter, the heat-treated film 61 is etched back until the upper surface of the first interlayer insulating film 33 is exposed (FIGS. 13A to 13C). The sample surface after the etch back is almost flattened,
The groove formed by the opening 57 for forming the separation groove is completely filled with the insulating material 31 made of polyimide.

Then, after a film made of Al is formed on the sample surface after the etch back, the film made of Al is patterned using a known photolithography technique and an etching technique to form a first interlayer insulating film 33. The p-type common wiring 29 is formed thereon (FIGS. 14A to 14C). Four p-type common wirings 29 are formed, and each of the four p-type common wirings 29 is formed across all the n-type blocks across the separation groove 25. Further, each of these four p-type side common wirings 29 is one of four sets of light emitting diodes 19 configured by non-overlapping selection of one light emitting diode 19 from each n-type block. One pair is formed as a common wiring. That is, the first light emitting diode 1 from the left of each n-type block
9 are selected one by one to form one set. Similarly, the second light emitting diode 19 from the left is selected one by one to form one set, and the third light emitting diode 19 from the left is selected one by one. When one group is selected and the fourth light emitting diode 19 from the left is selected one by one to form one group, these four groups have different p-type common wirings 29 respectively.
Are formed as a common wiring.

Next, for each n-type block, one n-type side wiring 41 common to the light emitting diode groups in the n-type block
Are formed respectively.

In this embodiment, first, a second interlayer insulating film 35 covering the p-type common wiring 29 is formed on the first interlayer insulating film 33 and the n-type ohmic electrode 43. The second interlayer insulating film 35 is made of a SiN film and is formed to a thickness of, for example, 1000 ° by a plasma CVD method. After that, the n-type ohmic electrode 43 penetrates through the second interlayer insulating film 35.
Is formed (FIG. 15A).
(C)). In this step, a via hole 37 penetrating through the second interlayer insulating film 35 and reaching the p-type common wiring 29 and an opening penetrating through the first and second interlayer insulating films 33 and 35 and reaching the surface of the diffusion region 15 39 is also formed. In order to form the via hole 37 and the opening 39, a known photolithography technique and an etching technique are used. When the via hole 37 and the opening 39 are formed at the same time, the first interlayer insulating film 3 below the p-type common wiring 29 is formed.
3 causes etching damage, the via hole 37
It is more preferable to form the opening 39 after the formation.

Then, a film made of Al is formed in the via hole 37.
And 47, and on the surface of the sample after the opening 39 is formed, the Al film is patterned using a known photolithography technique and an etching technique, and the n-type ohmic electrode is passed through the via hole 47. 4
3 to form an n-type side wiring 41.
(A) to (C)). In this step, an n-type electrode pad 45 connected via the n-type wiring 41 is also formed. Further, in this step, one end is connected to the p-type common wiring 29 through the via hole 37 and the other end is brought into contact with the surface of the diffusion region 15 of the light emitting diode 19 through the opening 39 to form the p-type individual wiring 31. . n
The mold-side wiring 41 is formed for each n-type block as one wiring common to the light emitting diode group in the n-type block. Diffusion region 1 of the same set of light emitting diodes 19
All the p-type individual wirings 31 whose other ends are in contact with the surface of 5 are formed so as to be connected to the same p-type common wiring 29.
That is, the p-type individual wirings 31 whose other ends are in contact with the surface of the diffusion region 15 of the first light-emitting diode 19 from the left of each n-type block are formed so as to be all connected to the same p-type common wiring 29. . Similarly, the p-type individual wiring 31 whose other end contacts the surface of the diffusion region 15 of the second light emitting diode 19 from the left of each n-type block is connected to the same p-type common wiring 29, The n-type individual wirings 31 whose other ends are in contact with the surface of the diffusion region 15 of the third light emitting diode 19 from the left of each n-type block are connected to the same p-type common wiring 29 so that each n-type individual wiring 31 is connected. The p-type individual wirings 31 whose other ends are in contact with the surface of the diffusion region 15 of the fourth light emitting diode 19 from the left of the block are all the same p
It is formed so as to be connected to the mold side common wiring 29. In this embodiment, the second and third from the left of each n-type block
An n-type wiring 41 is formed between the p-type individual wirings 31.

The p-side electrode pad can be formed simultaneously in the process of forming the n-side wiring 41, the n-side electrode pad 45, and the p-side individual wiring 31 described above. In this case, in the process of forming the via holes 37 and 47 and the opening 39, the second interlayer insulating film 35 for connecting the p-type electrode pad and the p-type common wiring 29 is formed.
Are formed at the same time to reach the p-side common wiring 29, and the p-side electrode pad and the p-side common wiring 29 are formed.
Should be connected. Although not shown, the n-type electrode pad 49 and the p-type electrode pad are
It is formed in one area with the 9 arrangement as a boundary. The light emitting diode array is manufactured as described above.

In the above embodiment, the case where the n-type GaAs layer as the upper layer 13 is formed by epitaxial growth on the semi-insulating GaAs substrate as the base 11 has been described. n-type GaAs
The s layer may be formed by diffusing an n-type impurity such as Si or Sn from the upper surface of the semi-insulating GaAs substrate. As a method for forming an n-type GaAs layer as the upper layer 13 by diffusing an n-type impurity from the upper surface of a semi-insulating GaAs substrate, there is the following method. For example, on a semi-insulating GaAs substrate, an oxide film containing an n-type impurity such as silicon or tin and an anneal-up film are sequentially formed. The oxide film is formed by sputtering or SOG.
For example, it is formed to a thickness of 1000 °. Then, for example, 8
By performing heat treatment at 00 ° C. for 4 hours, an n-type impurity contained in the oxide film is diffused and formed in the GaAs substrate. The same applies to the following embodiments.

2. Second Embodiment In the first embodiment, the other end of the p-side individual electrode 31 is
Although the light-emitting diode array having a structure in which the light-emitting diode array is in contact with the surface portion of the diffusion region 15 on the same side as the region where the n-type ohmic electrode 43 is provided has been described, in this embodiment, the other end of the p-type individual electrode 31 Is the n-type ohmic electrode 4
A light emitting diode array having a structure in contact with the surface portion of the diffusion region 15 on the opposite side to the region provided with 3 will be described.

In the first embodiment, the first interlayer insulating film 33 and the p-type common
A second interlayer insulating film 35 is provided between the mold-side common wiring 29 and the p-type individual wiring 31, and the connection between the p-type individual wiring 31 and the p-type common wiring 29 is performed by connecting the second interlayer insulating film 35. Penetrate p
The contact between the p-type individual wiring 31 and the diffusion region 15 reaches the surface of the diffusion region 15 through the first and second interlayer insulating films 33 and 35. A light emitting diode array having a structure formed through the opening 39, that is, a first interlayer insulating film 33, a p-type common wiring 29, a second interlayer insulating film 35, and a p-type individual wiring 31 are sequentially provided on the upper layer 13. Although the light emitting diode array having the above structure has been described, in the present embodiment, the first interlayer insulating film 33 is provided between the upper layer 13 and the p-type individual wiring 31, and the p-type individual wiring 31 and the p-type individual wiring 31 are provided. A second interlayer insulating film 35 is provided between the common wiring 29 and the p-type individual wiring 31 and the p-type common wiring 29 are connected to the p-type individual wiring 31 through the second interlayer insulating film 35. Reached via hole 6 And the contact between the p-type individual wiring 31 and the surface of the diffusion region 15 is made through the opening 65 reaching the surface of the diffusion region 15 through the first interlayer insulating film 33. That is, a light emitting diode array having a structure in which the first interlayer insulating film 33, the p-type individual wiring 31, the second interlayer insulating film 35, and the p-type common wiring 29 are sequentially provided on the upper layer 13 will be described.

In the first embodiment, the first interlayer insulating film 33 and the second interlayer insulating film 35 are formed, the p-type common wiring 29 and the p-type individual wiring 31 are formed, and the via hole 37 is formed.
And the formation of the opening 39, on the upper layer 13,
Forming a first interlayer insulating film 33, forming a p-type common wiring 29 on the first interlayer insulating film 33, and then forming a second interlayer covering the p-type common wiring 29 on the first interlayer insulating film 33; Forming an insulating film 35, forming a via hole 37 penetrating through the second interlayer insulating film 35 to reach the p-type common wiring 29, and forming a diffusion region 15 through the first and second interlayer insulating films 33 and 35; A step of forming an opening 39 reaching the surface, one end is connected to the corresponding p-type common wiring 29 through the via hole 37, and the other end is in contact with the surface of the diffusion region 15 of the corresponding light emitting diode 19 through the opening 39. Although the method for manufacturing the light emitting diode array in which the step of forming the p-type individual wiring 31 is sequentially described, in the present embodiment, the step of forming the first interlayer insulating film 33 on the upper layer 13 and the step of forming the first Between layers Forming an opening 65 reaching the surface of the diffusion region 15 through the Enmaku 33, openings 65
Forming a p-type individual wiring 31 whose other end is in contact with the surface of the diffusion region 15 of the corresponding light emitting diode 19 through the second interlayer insulating film 33 covering the p-type individual wiring 31 on the first interlayer insulating film 33 A step of forming the insulating film 35, a step of forming a via hole 63 penetrating through the second interlayer insulating film 35 and reaching the p-type individual wiring 31, and connecting to one end of the corresponding p-type individual wiring 31 through the via hole 63 A method of manufacturing a light-emitting diode array in which the steps of forming the p-side common wiring 29 are sequentially performed will be described.

Except for the above points, the structure and manufacturing method of the light emitting diode array of this embodiment are substantially the same as those of the first embodiment. Accordingly, in the following description, the same points as those in the first embodiment may not be described.

First, the light emitting diode array of this embodiment will be described with reference to FIGS.
FIG. 17A is a schematic plan view showing a light-emitting diode array according to this embodiment, and FIG. 17B is cut along a line II in FIG. 17A. 17 (C) is a schematic cross-sectional view taken along the line II-II in FIG. 17 (A) (a cut-away view). FIG. 18 shows FIG.
FIG. 3A is a schematic cross-sectional view taken along the line III-III in FIG.

The light-emitting diode array of this embodiment has an n-type GaAs layer as an upper layer 13 formed by epitaxial growth on a semi-insulating GaAs substrate as a base 11, and an upper surface of the upper layer 13 Is a p-type impurity over a part of the depth in the thickness direction of
p-type G as a diffusion region 15 formed by diffusing n
An array of a plurality of light emitting diodes 19 each having a junction (PN junction) 17 with the aAs region is provided. The light-emitting diodes 19 are arranged in a line at regular intervals.
FIG. 17A shows a light emitting diode 1 provided in a large number.
9 shows a region including five light-emitting diodes 19 provided continuously with a separation groove 25 described later interposed therebetween. The thickness of the upper layer 13 is, for example, 4 μm,
The diffusion depth of the diffusion region 15 is, for example, 1 μm.

Also, the same number of light emitting diodes 19, for example, four light emitting diode groups are included, respectively.
It has a separation groove 25 for partitioning into a plurality of n-type blocks electrically separated from each other. The separation groove 25 is formed in the upper layer 13.
The shape of the separation groove 25 in the cross section parallel to the LED arrangement direction and perpendicular to the upper surface of the upper layer 13 is rectangular (FIG. 17).
(C)). The depth of the separation groove 25 is, for example, 6 μm. The separation groove 25 is buried with an insulating material 27 made of polyimide. This separation groove 25 is
As will be described later in detail, a first interlayer insulating film 33 is provided on the upper layer 13, and a part of the first interlayer insulating film 33, that is, the first interlayer insulating film 33 in a region where the separation groove 25 is to be formed is removed. An opening 57 for formation is formed, and furthermore, it is formed by continuously etching from the upper surface of the upper layer 13 exposed from the opening 57 to the base 11. Therefore, the opening 57 for forming the separation groove formed in the first interlayer insulating film 33 is also buried with polyimide.

Further, one common light emitting diode 19 is selected non-overlappingly from each n-type block.
The p-type common wiring 29 is provided for each group.
That is, the light emitting diodes 19 are selected one by one from each n-type block non-overlappingly, and
One common p-type common wiring 29 is provided for each set. Each p-type common wiring 29 is provided across all the n-type blocks across the separation groove 25. For example, the first light emitting diodes 19 from the left of each n-type block are selected one by one to form one set, and similarly, the second light emitting diodes 19 from the left are selected one by one to form one set. , The third light emitting diode 1 from the left
9 are selected one by one to form one set, and the fourth light emitting diode 19 from the left is selected one by one to form one set.

Further, a p-type individual wiring 31 provided with one end connected to the p-type common wiring 29 and the other end in contact with the diffusion region 15 of the light emitting diode 19 is provided. All the p-type individual wirings 31 provided in contact with the surfaces of the diffusion regions 15 of the same set of light emitting diodes 19 are connected to the same p-type common wiring 29. The p-side common wiring 29 and the p-side individual wiring 31 are made of Al. However, the surface of the p-type individual wiring 31 is coated with Ni in order to prevent oxidation of the surface and enable connection with the p-type common wiring 29.

A diffusion mask 51 made of AlN and a diffusion source film 5 made of a mixture of ZnO and SiO ₂ are provided between the upper layer 13 and the p-type individual wiring 31 in this order from the upper layer 13 side.
3 and a first interlayer insulating film 33 having a configuration in which an annealing cap film 55 made of SiN is laminated, and a second interlayer insulating film made of polyimide is provided between the p-type individual wiring 31 and the p-type common wiring 29. It has 35. That is, the p-type individual wiring 31 is provided on the first interlayer insulating film 33, and the p-type common wiring 29 is provided on the second interlayer insulating film 35.
Since the first interlayer insulating film 33 is also a film used for forming the diffusion region 15, the diffusion mask 51 has a diffusion window 51 a in the diffusion region 15. The thickness of the diffusion mask 51 is, for example, 2000 °, and the diffusion source film 53 is formed.
Is, for example, 200 to 2000 degrees, and the thickness of the annealing cap film 55 is, for example, 200 to 2000 degrees. The thickness of the second interlayer insulating film 35 is, for example, 10
00 °.

The connection between the p-type individual wiring 31 and the p-type common wiring 29 is made through a via hole 63 that penetrates through the second interlayer insulating film 35 and reaches the p-type individual wiring 31. The contact between the individual wiring 31 and the surface of the diffusion region 15 is made through an opening 65 that penetrates through the first interlayer insulating film 33 and reaches the surface of the diffusion region 15.

Further, a p-type electrode pad (not shown) provided to be connected to the p-type common wiring 33 is provided.

Also, for each n-type block, one n-type side wiring 41 common to the light emitting diode group in the n-type block
Are provided respectively. Further, for each n-type block, n
An n-type ohmic electrode 43 provided in contact with the upper layer 13 in the mold block and commonly provided to the light emitting diode group in the n-type block; And an electrode pad 45. n
The mold side wiring 41 and the n type side electrode pad 45 are provided on the first interlayer insulating film 33, and except for a part on the n type side electrode pad 45, the n type side wiring 41 and the n type side electrode pad 4 are provided.
A second interlayer insulating film 35 is provided on 5. FIG.
In (A), the removed portion of the second interlayer insulating film 35 is shown by hatching. n-type ohmic electrode 43
Is located in one region for each n-type block with respect to the arrangement of the light-emitting diodes 19, specifically, in the region opposite to the region where the p-type common wiring 29 is provided with respect to the arrangement of the light-emitting diodes 19. It is provided. Then, the p-type individual wiring 3
The other end of 1 is in contact with the surface portion of diffusion region 15 opposite to the region where n-type ohmic electrode 43 is provided. This n-type side ohmic electrode 43 is formed by removing a part of the first interlayer insulating film 33 and removing the upper layer 1 as described later in detail.
3 is exposed, and is formed on the exposed upper layer 13. Therefore, the periphery of the n-type ohmic electrode 43 is surrounded by the first interlayer insulating film 33. The n-type side wiring 41 is A
1 and the n-type ohmic electrode 43 is made of a gold alloy.

Although not shown, the n-side electrode pad 4
The 5 and p-type side electrode pads are provided in a line in one region with the arrangement of the light emitting diodes 19 as a boundary.

Next, a method of manufacturing the light emitting diode array having the above structure will be described with reference to FIGS. (A) in FIGS. 19 to 23 is a schematic plan view at a main manufacturing stage of the light emitting diode array,
(B) in FIGS. 19 to 21 corresponds to II in FIG. 17 (A).
It is the schematic manufacturing process figure of the light emitting diode array shown by the sectional view (however, the figure of a cut surface) corresponding to the cross section cut | disconnected along the line, and (C) in FIGS.
FIG. 18 is a schematic manufacturing process diagram of the light-emitting diode array shown by a cross-sectional view (a cutaway view) corresponding to a cross-section taken along line II-II in FIG.

First, as in the first embodiment, the base 1
Upper layer 1 provided on a semi-insulating GaAs substrate 1
A plurality of light emitting diodes 19 are formed by forming a p-type GaAs region as the diffusion region 15 from the upper surface of the n-type GaAs layer 3 to a part of the depth of the upper layer 13 in the thickness direction.

Next, for each n-type block, one n-type side wiring 41 common to the light emitting diode group in the n-type block
Are formed respectively.

In this embodiment, prior to forming the n-type wiring 41, the n-type ohmic electrode 43 is formed.
The n-type ohmic electrode 43 is formed for each n-type block in contact with the upper surface of the upper layer 13 in the n-type block and commonly for the light emitting diode group in the n-type block. For this reason, first, a part of the first interlayer insulating film 33, that is, the first interlayer insulating film 33 in a region where the n-type ohmic electrode 43 is to be formed is removed, and the n-type ohmic electrode 33 is formed on the first interlayer insulating film 33. An opening 59 for forming an electrode is formed. In this step, the diffusion region 15 penetrates through the first interlayer insulating film 33.
The opening 65 that reaches the surface of the substrate is also formed. In order to remove a part of the first interlayer insulating film 33, a known photolithography technique and an etching technique are used. afterwards,
An n-type ohmic electrode 4 made of a gold alloy is formed on the upper layer 13 exposed from the opening 59 for forming the n-type ohmic electrode.
3 (FIGS. 19A to 19C). For forming the n-type side ohmic electrode 43, a known vapor deposition lift-off method is used. The n-type ohmic electrode 43 has one region with respect to the arrangement of the light emitting diodes 19 for each n-type block,
Specifically, it is formed in a region opposite to a region where the p-type common wiring 29 is to be formed with respect to the arrangement of the light emitting diodes 19.

After that, a film made of Al is formed on the surface of the sample after the formation of the n-type ohmic electrode 43, and the film made of Al is patterned by using a known photolithography technique and etching technique. Then, the n-type wiring 41 is formed by being connected to the n-type ohmic electrode 43 (FIGS. 20A to 20C). In this step, an n-type electrode pad 45 connected via the n-type wiring 41 is also formed. Further, in this step, the opening 65
The p-side individual wiring 31 whose other end is in contact with the surface of the diffusion region 15 of the light emitting diode 19 is also formed. n
The mold-side wiring 41 is formed for each n-type block as one wiring common to the light emitting diode group in the n-type block. Diffusion region 1 of the same set of light emitting diodes 19
The p-side individual wirings 31 whose other ends are in contact with the surface of 5 are formed such that they can all be connected to the same p-side common wiring 29 in a later step. That is, the p-type individual wirings 31 whose other ends are in contact with the first light emitting diode 19 from the left of each n-type block are all the same p-type common wiring 29.
It is formed so that it can be connected to. Similarly, each n
The p-type individual wirings 31 whose other ends are in contact with the second light-emitting diode 19 from the left of the mold block are connected to the same p-type common wiring 29 so as to be connected to the same p-type common wiring 29. The p-side individual wirings 31 whose other ends are in contact with the light-emitting diodes 19 are connected to the fourth light-emitting diodes 19 from the left of each n-type block so that they can all be connected to the same p-type common wiring 29. The other end touches
The mold-side individual wires 31 are formed so that they can all be connected to the same p-type-side common wire 29.

Next, the same number of light emitting diodes 19, for example, four light emitting diode groups are included.
A separation groove 2 reaching the base 11 from the upper surface of the upper layer 13 for partitioning into a plurality of n-type blocks electrically separated from each other.
5 is formed.

In this embodiment, first, a part of the first interlayer insulating film 33, that is, the first interlayer insulating film 33 in a region where the isolation groove 25 is to be formed is removed, and the first interlayer insulating film 33 is separated. An opening 57 for forming a groove is formed. In order to remove a part of the first interlayer insulating film 33, a known photolithography technique and an etching technique are used. afterwards,
On the sample surface, the same parts as the opening 57 for the separation groove formation, after providing a resist having a window of slightly narrower width in consideration of the same width or side etching, the resist as a mask, and BCl ₃ Separation grooves 25 are formed by dry etching using a mixed gas with Cl ₂ as an etching gas (FIGS. 21A to 21C). FIG. 21 shows a state after the resist used as the mask has been removed. The dry etching is performed under the condition that the shape of the separation groove 25 in a cross section parallel to the LED arrangement direction and perpendicular to the upper surface of the upper layer 13 is rectangular. The depth of the separation groove 25 is, for example, 6 μm, and the width of the separation groove 25 is, for example, 5 μm.

Next, one common light emitting diode 19 is selected non-overlappingly from each n-type block.
The p-type common wiring 29 is formed for each group.

In this embodiment, the p-side common wiring 29
Prior to the formation of the trench, the isolation groove 25 is buried with an insulating material 27 made of polyimide, and the p-type individual wiring 31 is formed on the first interlayer insulating film 33 and the n-type ohmic electrode 43.
A second interlayer insulating film 35 made of polyimide is formed to cover the n-type wiring 41 and the n-type ohmic electrode 43. Therefore, first, polyimide is applied on the surface of the sample to form a film made of polyimide. In this case, it is possible to fill the isolation groove 25, and further, as described later, the polyimide is formed by applying polyimide to such a thickness that the film made of polyimide can be used as the second interlayer insulating film 35. Form a film. Thereafter, the film made of the polyimide is subjected to a heat treatment. This film is imidized by the heat treatment (FIGS. 22A to 22C). The surface of the film after the heat treatment is substantially planarized, and the groove formed by the separation groove 25 and the opening 57 for forming the separation groove is completely buried with the insulating material 31 made of polyimide. In the subsequent steps, a portion of the film after the heat treatment other than the portion embedded in the groove constituted by the separation groove 25 and the opening 57 for forming the separation groove is used as the second interlayer insulating film 35. The film thickness of the portion corresponding to the second interlayer insulating film 35 is, for example, 10
00 °. Thereafter, a via hole 63 penetrating through the second interlayer insulating film 35 and reaching the p-type individual wiring 31 is formed. In this step, the second
A part of the interlayer insulating film 35 is also removed. In order to remove a part of the second interlayer insulating film 35, a known photolithography technique and an etching technique are used. FIG.
In (A), the removed portion of the second interlayer insulating film 35 on the n-type electrode pad 45 is hatched.

After that, a film made of Al is formed in the via hole 63.
Is formed on the surface of the sample after the formation of the Al.
Is patterned and connected to one end of the p-type individual wiring 31 through the via hole 63 to form the p-type common wiring 29 (FIGS. 23A to 23C). Alternatively, the p-side common wiring 29 is formed using a known lift-off technique. Four p-type common wirings 29 are formed, and each of the four p-type common wirings 29 is formed across all the n-type blocks across the separation groove 25. Further, each of these four p-type side common wirings 29 is one of four sets of light emitting diodes 19 configured by non-overlapping selection of one light emitting diode 19 from each n-type block. One pair is formed as a common wiring. That is, the first light emitting diodes 19 from the left of each n-type block are selected one by one to form one set, and similarly, the second light emitting diodes 19 from the left are selected one by one to form one set. When the third light emitting diode 19 from the left is selected one by one to form one set, and the fourth light emitting diode 19 from the left is selected one by one to form one set, Form different p-type common wires 29 as common wires.

The p-side electrode pad can be formed simultaneously in the above-described step of forming the p-side individual wiring 31. In this case, the p-type common wiring 29 is formed by connecting to the p-type electrode pad through the via hole. Although not shown, the n-type electrode pad 45 and the p-type electrode pad are formed in one region with the arrangement of the light emitting diodes 19 as a boundary. The light emitting diode array is manufactured as described above.

3. Third Embodiment In the first embodiment, the light emitting diode array having a structure in which the shape of the separation groove 25 in a cross section parallel to the LED arrangement direction and perpendicular to the upper layer 13 is rectangular is described. In this embodiment, a light-emitting diode array having a structure in which a cross-sectional shape is a regular mesa will be described.

In the first embodiment, the separation groove 25
Has been described with respect to a light emitting diode array having a structure in which is embedded with an insulating material.
A light emitting diode array having a structure in which 5 is covered with an insulating film will be described.

Except for the above points, the structure of the light emitting diode array of this embodiment is substantially the same as that of the first embodiment. Therefore, in the following description, points different from the first embodiment will be mainly described, and description of other points may be omitted.

First, the light emitting diode array of this embodiment will be described with reference to FIGS.
FIG. 24A is a schematic plan view showing a light-emitting diode array according to this embodiment, and FIG. 24B is a cross-sectional view taken along line II in FIG. FIG. 24 (C) is a schematic cross-sectional view taken along the line II-II in FIG. 24 (A) (however, a cutaway view). FIG. 25 shows FIG.
FIG. 3A is a schematic cross-sectional view taken along the line III-III in FIG.

In the light-emitting diode array of this embodiment, the separation grooves 25 that partition the light-emitting diodes 19 into a plurality of n-type blocks that are electrically separated from each other and that include the same number of light-emitting diodes 19, for example, as four light-emitting diode groups. I have it. The separation groove 25 extends from the upper surface of the upper layer 13 to the base 11, and the shape of the separation groove 25 in a cross section parallel to the LED arrangement direction and perpendicular to the upper surface of the upper layer 13 is a regular mesa shape ( FIG. 24C). The depth of the separation groove 25 is, for example, 5 μm. Then, the separation groove 25 is formed by a diffusion mask 51 made of AlN, ZnO
Source film 53 composed of a mixture of SiO ₂ and SiO ₂ , and S
A first interlayer insulating film 33 having a configuration in which an annealing cap film 55 made of iN or AlN is sequentially stacked is covered. Note that, in order to avoid complicating the drawing, FIG.
Are indicated by broken lines, and the irregularities such as the diffusion mask 51, the diffusion source film 53, and the annealing cap film 55 are not shown (not shown in the manufacturing steps and other implementations). The same applies to the embodiment.)

The width of the upper part of the separation groove 25 in the LED array direction may be any suitable size depending on the dot density of the light emitting diode 19 and the width of the upper surface of the upper layer 13 of the island region 15 in the LED array direction. . FIG. 26 is a schematic diagram showing an arrangement relationship between an island region and a separation groove. For example,
When the dot density of the light emitting diode 19 is 1200 dpi, the dot pitch p is about 21 μm. Therefore, as shown in FIG. 26, when the width a of the diffusion window (not shown) in the LED array direction is 3 μm and the diffusion distance b of Zn in the horizontal direction is 1.5 μm, the upper layer 13 of the island region 15 is formed. Has a width c in the LED array direction of 6 μm on the upper surface. Therefore,
When the inclination θ of the separation groove 25 is 51 degrees and the width d1 of the bottom of the separation groove 25 in the LED array direction is 3 μm, the width d2 of the upper part of the separation groove 25 in the LED array direction is about 11 μm. A distance e from the island region 15 to the separation groove 25 can be secured to about 2 μm.

Next, a method of manufacturing the light emitting diode array having the above structure will be described with reference to FIGS. (A) in FIGS. 27 to 30 is a schematic plan view at a main manufacturing stage of the light emitting diode array,
(B) in FIGS. 27 to 30 corresponds to II in FIG. 24 (A).
FIG. 31 is a schematic manufacturing process diagram of a light-emitting diode array shown by a cross-sectional view (a cut-away view) corresponding to a cross section taken along a line, and FIG. 27C to FIG.
24A is a schematic manufacturing process diagram of a light-emitting diode array shown by a cross-sectional view (a cutaway view) corresponding to a cross-section taken along line II-II in FIG.

First, a semi-insulating GaAs substrate serving as a base 11 for partitioning into a plurality of n-type blocks electrically separated from each other, each including a light emitting diode as the same number, for example, four light emitting diode groups. An isolation groove 25 extending from the upper surface of the n-type GaAs layer serving as the upper layer 13 to the base 11 is formed.

In this embodiment, first, an n-type GaAs layer as the upper layer 13 is formed by epitaxial growth on a semi-insulating GaAs substrate as the base 11. The upper layer 13 is formed to a thickness of, for example, 4 μm. Thereafter, a window 67 is formed on the upper layer 13 in a region where the separation groove 25 is to be formed.
After the negative resist 67 having a is provided, the separation groove 25 is formed by wet etching using the negative resist 67 as a mask and phosphoric acid-hydrogen peroxide as an etchant (FIGS. 27A to 27C). The wet etching is performed under the condition that the shape of the separation groove 25 in a cross section parallel to the LED arrangement direction and perpendicular to the upper surface of the upper layer 13 is a regular mesa shape. The depth of the separation groove 25 is, for example, 5 μm.
The inclination of the separation groove 25 is, for example, 51 degrees, and the width of the bottom of the separation groove 25 in the LED array direction is, for example, 3 μm.
m. When the inclination of the separation groove 25 is about 51 degrees,
In the subsequent steps, the first interlayer insulating film 33 is
, And a film made of Al for forming the p-type common wiring can be covered along the shape of the isolation groove 25. After the wet etching for forming the separation groove 25, the negative resist 67 is removed.

Next, a plurality of light emitting diodes 19 are formed by forming a p-type GaAs region as the island region 15 from the upper surface of the upper layer 13 to a part of the depth of the upper layer 13 in the thickness direction.

In this embodiment, first, a diffusion mask 5 having a diffusion window 51a in a region to be diffused is formed on the upper layer 13.
1. A diffusion source film 53 covering the diffusion mask 51 and an annealing cap film 55 covering the diffusion source film 53 are formed. The diffusion mask 51, the diffusion source film 53, and the annealing cap film 55 are formed so as to cover the separation groove 25. The diffusion mask 51 is made of an AlN film, and is formed to a thickness of, for example, 2000 ° by sputtering. Diffusion source film 5
Numeral 3 is made of a mixed film of ZnO and SiO ₂ and is formed to a thickness of, for example, 200 to 2000 ° by sputtering. The anneal cap film 55 is made of a SiN film or an AlN film.
To a film thickness of Thereafter, for example, 70
By performing heat treatment at 0 ° C. for 2 hours, Zn as a p-type impurity contained in the diffusion source film 53 is solid-phase diffused from the diffusion window 51a to the upper layer 13 to form the island-like region 15.
(A) to (C)). The island-shaped region 15 is formed such that four light emitting diodes 19 are included in one n-type block. The diffusion depth of the island region 15 is, for example, 1 μm. The diffusion mask 51, the diffusion source film 53 and the annealing cap film 55 are used as the first interlayer insulating film 33 in the subsequent steps.

Thereafter, the first interlayer insulating film 33 in the region where the n-type ohmic electrode 43 is to be formed is removed by using a known photolithography technique and etching technique, and the n-type ohmic electrode 33 is formed on the first interlayer insulating film 33. Opening 5 for electrode formation
9 is formed, the n-type ohmic electrode 43 made of a gold alloy is formed on the upper layer 13 exposed from the opening 59 for forming the n-type ohmic electrode using a known vapor deposition lift-off method.
Is formed (FIGS. 29A to 29C). The n-side ohmic electrode 43 is connected to the light emitting diode 19
Is formed in one region, specifically, a region between the region where the light emitting diodes 19 are arranged and the region where the p-type common wiring 33 is to be formed.

Thereafter, similarly to the first embodiment, the p-type common wiring 29, the second interlayer insulating film 35, the via holes 37 and 47, the opening 39, the n-type wiring 41, and the n-type electrode pad 45 are formed. , The p-side individual wiring 31 and the p-side electrode pad are formed (FIGS. 30A to 30C). The light emitting diode array is manufactured as described above.

4. Fourth Embodiment In this embodiment, as in the third embodiment, the upper layer 13 is parallel to the arrangement direction of the light emitting diodes 19.
A description will be given of a light emitting diode array having a structure in which the shape of the separation groove 25 in a cross section perpendicular to FIG. Therefore, in the following description, points different from the third embodiment will be mainly described, and description of other points may be omitted.

First, the light emitting diode array of this embodiment will be described with reference to FIGS.
FIG. 31A is a schematic plan view showing a light-emitting diode array according to this embodiment, and FIG. 31B is cut along the line II in FIG. FIG. 31 (C) is a schematic sectional view taken along the line II-II in FIG. 31 (A) (however, a cutaway view). FIG. 32 shows FIG.
FIG. 3A is a schematic cross-sectional view taken along the line III-III in FIG.

In the light emitting diode array of this embodiment, the separation grooves 25 for partitioning into a plurality of n-type blocks which are electrically separated from each other and which include the same number of light emitting diodes 19, for example, as four light emitting diode groups, respectively. I have it. The separation groove 25 extends from the upper surface of the upper layer 13 to the base 11, and the shape of the separation groove 25 in a section parallel to the LED arrangement direction and perpendicular to the upper surface of the upper layer 13 is a normal mesa shape ( FIG. 31 (C)). The depth of the separation groove 25 is, for example, 5 μm. Then, the separation groove 25 is covered with an insulating film 69 made of SiN. The separation groove 25 is formed on the upper layer 13 by a diffusion mask 51 made of AlN, as will be described later in detail.
A diffusion source film 53 made of a mixture of ZnO and SiO ₂ , and an annealing cap film 55 made of SiN or AlN
Is provided in order, and a negative resist having a window in a region where the separation groove 25 is to be formed is provided thereon, and then, using the negative resist as a mask, the stacked film is etched and further continuously. It is formed by etching from the upper surface of the upper layer 13 to the base 11. For this reason, the side wall portion 71 of the laminated film formed by etching the laminated film is also covered with the insulating film 69.

A diffusion mask 51 made of AlN and a diffusion source film 5 made of a mixture of ZnO and SiO ₂ are disposed between the upper layer 13 and the p-type common wiring 29 in this order from the upper layer 13 side.
3, an annealing cap film 55 made of SiN or AlN, and a first interlayer insulating film 33 having a structure in which an insulating film 69 made of SiN is laminated, between the p-type common wiring 29 and the p-type individual wiring 31. , A second interlayer insulating film 35 made of SiN. That is, the p-type common wiring 29 is provided on the first interlayer insulating film 33, and the p-type individual wiring 31 is provided on the second interlayer insulating film 35. The thickness of the diffusion mask 51 is, for example, 2000 °, the thickness of the diffusion source film 53 is, for example, 200 to 2000 °, the thickness of the annealing cap film 55 is, for example, 200 to 2000 °,
The thickness of the insulating film 69 is, for example, 1000 °. Also,
The thickness of the second interlayer insulating film 35 is, for example, 1000 °.

Next, a method of manufacturing the light emitting diode array having the above structure will be described with reference to FIGS. (A) in FIGS. 33 to 37 is a schematic plan view at a main manufacturing stage of the light emitting diode array,
(B) in FIG. 33 to FIG. 37 are I-I in FIG.
FIG. 38 is a schematic manufacturing process diagram of a light-emitting diode array shown by a cross-sectional view (a cut-away view) corresponding to a cross section taken along a line, and FIG. 33C to FIG.
31 is a schematic manufacturing process diagram of a light-emitting diode array shown by a cross-sectional view (a cutaway view) corresponding to a cross-section taken along line II-II in FIG.

First, as in the first embodiment, the base 1
Upper layer 1 provided on a semi-insulating GaAs substrate 1
A plurality of light emitting diodes 19 are formed by forming a p-type GaAs region as the island region 15 from the upper surface of the n-type GaAs layer 3 as a part of the depth of the upper layer 13 in the thickness direction.

Next, the same number of light emitting diodes 19, for example, four light emitting diode groups are included, respectively.
A separation groove 2 reaching the base 11 from the upper surface of the upper layer 13 for partitioning into a plurality of n-type blocks electrically separated from each other.
5 is formed.

In this embodiment, prior to the formation of the isolation groove 25, the n-type ohmic electrode 43 is formed. The n-type ohmic electrode 43 is formed for each n-type block in contact with the upper surface of the upper layer 13 in the n-type block and commonly for the light emitting diode group in the n-type block. For this reason,
First, a diffusion mask 51 made of AlN, ZnO and Si
A part of a laminated film 73 having a structure in which a diffusion source film 53 made of a mixture of O _{2 and} an annealing cap film 55 made of SiN or AlN are sequentially laminated, that is, a laminated film 73 in a region where an n-type ohmic electrode 43 is to be formed is removed. Then, an opening 59 for forming an n-type ohmic electrode is formed in the laminated film 73.
To form In order to remove a part of the laminated film 73,
A known photolithography technique and an etching technique are used. Thereafter, an opening 59 for forming an n-type ohmic electrode is formed.
An n-type ohmic electrode 43 made of a gold alloy is formed on the upper layer 13 exposed from the substrate (FIGS. 33A to 33C).
For forming the n-type side ohmic electrode 43, a known vapor deposition lift-off method is used. The n-type ohmic electrode 43 is supposed to form one region, specifically, the region where the light-emitting diodes 19 are arranged, and the p-type common wiring 33 with respect to the arrangement of the light-emitting diodes 19 for each n-type block. Is formed in the region between the regions.

Thereafter, a negative resist 67 having a window 67a is provided on the surface of the sample in a region where the separation groove 25 is to be formed. The separation groove 25 is formed by etching (FIG. 34A).
(C)). The wet etching is performed under the condition that the shape of the separation groove 25 in a cross section parallel to the LED arrangement direction and perpendicular to the upper surface of the upper layer 13 is a regular mesa shape. The depth of the separation groove 25 is, for example, 5 μm, and the inclination of the separation groove 25 is, for example, 51 degrees.
The width in the arrangement direction is, for example, 3 μm. However, after this wet etching, since the portion of the laminated film 73 covered with the negative resist 67 partially remains as the eaves portion 73a, thereafter, wet etching using buffered hydrofluoric acid as an etching solution, Wet etching using acid as an etchant is continuously performed to remove the eaves 73a. Then, the negative resist 67
Is removed (FIGS. 35A to 35C).

Thereafter, an insulating film 69 is formed on the sample surface (FIGS. 36A to 36C). The insulating film 69 has the separation groove 2
5 so as to cover it. The insulating film 69 is made of SiN, and has a thickness of 1000
To a film thickness of The diffusion mask 51 and the diffusion source film 5
3. The annealing cap film 55 and the insulating film 69 are used as the first interlayer insulating film 33 in the subsequent steps.

Thereafter, as in the first embodiment, the p-type common wiring 29, the second interlayer insulating film 35, the via holes 37 and 47, the opening 39, the n-type wiring 41, and the n-type electrode pad 45 are formed. , The p-side individual wiring 31 and the p-side electrode pad are formed (FIGS. 37A to 37C). The light emitting diode array is manufactured as described above.

5. Fifth Embodiment In the first embodiment, a light emitting diode array having a structure in which the shape of the separation groove 25 in a cross section parallel to the LED arrangement direction and perpendicular to the upper layer 13 is rectangular will be described. In the second embodiment, the light-emitting diode array having a structure in which the cross-sectional shape is a regular mesa is described. In this embodiment, the cross-sectional shape is rectangular in a region where the light-emitting diodes are arranged, and other regions Now, a light emitting diode array having a forward mesa structure will be described.

The structure of the light emitting diode array of this embodiment is substantially the same as that of the second embodiment, except that the sectional shape of the separation groove 25 is rectangular in the region where the light emitting diodes are arranged. Is the same as Therefore, in the following description, points different from the second embodiment will be mainly described, and description of other points may be omitted.

First, the light emitting diode array of this embodiment will be described with reference to FIG. FIG.
FIG. 38A is a schematic plan view showing a light emitting diode array according to this embodiment, and FIG.
38A is a schematic cross-sectional view taken along the line II in (A) (however, a cutaway view), and FIG.
FIG. 2A is a schematic sectional view taken along line II-II in FIG.

The light-emitting diode array of this embodiment includes a separation groove for partitioning into a plurality of n-type blocks electrically separated from each other, each of which includes the same number of light-emitting diodes 19, for example, as a group of four light-emitting diodes. I have. The separation groove extends from the upper surface of the upper layer 13 to the base 11, and the shape of the separation groove in a cross section parallel to the LED arrangement direction and perpendicular to the upper surface of the upper layer 13 depends on the region where the light emitting diodes are arranged ( Hereafter, the region 75 is rectangular (see FIG. 38C), and the other region, that is, the region where the p-type common wiring 29 is provided (hereinafter, referred to as a second region). ) 77 has a forward mesa shape (see FIG. 38B). In FIG. 38, 2
Reference numeral 5a denotes a separation groove provided in the first region 75.
Reference numeral 5b denotes a separation groove provided in the second region 77. The depth of each of the separation groove 25a provided in the first region 75 and the separation groove 25b provided in the second region 77 is, for example, 6 μm. The separation groove 25b provided in the second region is formed by a diffusion mask 5 made of AlN.
1. Diffusion source film 5 composed of a mixture of ZnO and SiO ₂
3 and a first interlayer insulating film 33 having a configuration in which an annealing cap film 55 made of SiN or AlN is sequentially stacked. Separation groove 25a provided in first region
Is not buried with an insulating material. However, from the viewpoint of the reliability of the light emitting diode array, it is desirable that the isolation groove 25a be buried with an insulating material.

The separation groove 25 provided in the first region 75
The width a in the LED array direction depends on the dot density of the light emitting diode 19 and the LE on the upper surface 13 of the upper layer 13 of the island region 15.
Any suitable size depending on the width in the D array direction may be used. For example, if the dot density of the light emitting diode 19 is 120
In the case of 0 dpi, the dot pitch is about 21 μm. For this reason, the width of the diffusion window in the LED array direction is set to 5 μm, and Z
Assuming that the lateral diffusion distance of n is 1.5 μm, the width in the LED array direction on the upper surface of the upper layer 13 of the island region 15 is 8 μm.
μm. Therefore, when the width d of the separation groove 25 in the LED array direction is 5 μm, the separation groove 2
A distance e of about 5 μm can be secured to about 4 μm.

On the other hand, the width of the separation groove 25b provided in the second region 77 in the LED array direction is
, And the width in the LED array direction on the upper surface of the upper layer 13 of the island region 15 can be determined. For example, the inclination of the separation groove 25b is 51 degrees, and the width of the bottom of the separation groove 25b in the LED array direction is 10 μm.
When m is set, the width of the upper part of the separation groove 25b in the LED array direction is about 20 μm.

In the case of manufacturing a light emitting diode array having the above structure, first, the same steps as those described in the third embodiment are performed to provide the isolation groove 25b only in the second region 77. An element is formed. However, the separation groove 25b
Is, for example, 6 μm, and the inclination of the separation groove 25 is
For example, it is 51 degrees, and the width of the bottom of the separation groove 25 in the LED array direction is, for example, 10 μm.

Next, the light emitting diodes 19 are included in the same number, for example, as four light emitting diode groups.
A separation groove 2 reaching the base 11 from the upper surface of the upper layer 13 for partitioning into a plurality of n-type blocks electrically separated from each other.
5 a is formed in the first region 75.

In this embodiment, first, the first and second
Of the interlayer insulating films 33 and 35, ie, the isolation trench 2
First and second interlayer insulating films 3 in regions where 5a is to be formed
3 and 35 are removed, and an opening for forming a separation groove is formed in the first and second interlayer insulating films 33 and 35. In order to remove a part of the first and second interlayer insulating films 33 and 35, a known lithography technique and etching technique are used. Then, on the sample surface, the same parts as the opening of the separation grooves formed after, providing the resist having a window of slightly narrower width in consideration of the same width or side etching, the resist as a mask, BCl ₃ Trench 25a is formed by dry etching using a mixed gas of Al and Cl ₂ as an etching gas. Dry etching is LE
This is performed under the condition that the shape of the separation groove 25a in the cross section perpendicular to the D arrangement direction and perpendicular to the upper surface of the upper layer 13 is rectangular. The depth of the separation groove 25a is, for example, 6 μm,
The width of the separation groove 25a is, for example, 5 μm. The light emitting diode array is manufactured as described above.

It is apparent that the present invention is not limited to the above embodiments. For example, in each of the above-described embodiments, a case is described in which a diffusion mask having a diffusion window in a diffusion scheduled region is used, and Zn is solid-phase diffused from the diffusion window to an upper layer to form an island region. The case where the island-shaped region is formed by solid-phase diffusion of Zn from the island-shaped diffusion source film to the upper layer may be adopted. Further, when the dot density is low, an island-shaped region may be formed by vapor phase diffusion.

Further, in each of the above embodiments, the case where the upper GaAs layer is formed by epitaxial growth on the GaAs substrate as the base has been described. However, the layer to be epitaxially grown is not limited to the GaAs layer. It may be a GaAlAs layer.

Further, in each of the above embodiments, the case where the n-type ohmic electrode is made of a gold alloy is described, but it may be made of another material.

In the above-described embodiment, a case is described in which the first interlayer insulating film includes a stacked film having a structure in which a diffusion mask, a diffusion source film, and an annealing cap film are stacked. After the removal, a new film may be used to form the first interlayer insulating film.

In the above third to fifth embodiments,
The case where the isolation groove having a cross section parallel to the LED array direction and perpendicular to the upper layer and having a shape of a forward mesa is covered with an insulating material is described. Is also good.

In the above third to fifth embodiments,
Although the description has been given of the case where the normally-mesa-shaped separation groove is formed by wet etching, the case may be formed by dry etching. Further, the inclination of the forward mesa-shaped separation groove is not limited to the above-described embodiment.

Also, the shape of the p-type individual wiring is not limited to the above embodiments.

Further, a case where a buffer layer is provided between the base 11 and the upper layer 13 may be employed.

[0139]

As is apparent from the above description, according to the light emitting diode array of the present invention, the light emitting diodes are electrically separated into a plurality of blocks each including the same number by using an appropriate separating means. . Then, one light emitting diode is non-overlappingly selected from each block to form a set of light emitting diodes, and one common second conductive type common wiring is provided for each set. Also, for each block, a common one for the light emitting diode group in the block.
Each of the first conductive type side wirings is provided. If the light emitting diode array has such a structure, one second conductivity type electrode pad is provided for each second conductivity type common wiring, and the first conductivity type electrode pad is provided for each first conductivity type wiring. Since it is only necessary to provide one electrode pad, the total number of pads is smaller than in the conventional case where one electrode pad is provided for each light emitting diode. Therefore, even when the dot density of the light emitting diode is high, the density of the electrode pads can be reduced. Therefore, the electrode pattern including the electrode pad is easily formed, and the wire bonding for connecting to the IC for driving the light emitting diode is facilitated.

Further, in the light emitting diode array of the present invention, the first conductivity type semiconductor region is an upper layer made of the first conductivity type semiconductor provided above the base made of a semi-insulating semiconductor or an insulator. In the case where the semiconductor region is an island-shaped region made of the second conductivity type semiconductor formed over a part of the depth in the thickness direction of the upper layer from the upper surface of the upper layer, and the separation means is a separation groove reaching the base from the upper surface of the upper layer, It becomes easy to partition the first conductivity type semiconductor region into a plurality of first conductivity type blocks that are electrically separated from each other and include the same number of light emitting diodes as light emitting diode groups. When the shape of the separation groove in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer is rectangular, a high density light emitting diode array can be formed. Further, when the shape of the separation groove in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer is a regular mesa shape, even if the separation groove is not embedded, the separation groove is provided across the separation groove. There is no danger of disconnection occurring in the two-conductivity-type common wiring. Further, when the shape of the separation groove in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer is rectangular in a region where the light emitting diodes are arranged, and is a regular mesa shape in other regions, A high-density light-emitting diode array can be formed, and even if the separation groove is not buried, there is no possibility that the second conductive type common wiring provided across the separation groove will be disconnected. Further, when the separation groove is buried with an insulating material so that the sample surface is flattened, disconnection may occur in the second-conductivity-type-side common wiring provided across the separation groove regardless of the shape and depth of the separation groove. Disappears.

In the light emitting diode array according to the present invention, one end is connected to the corresponding second conductive type common wire and the other end is provided in contact with the second conductive type semiconductor region of the corresponding light emitting diode. A second conductive type individual wiring, and a first interlayer insulating film between the upper layer and the second conductive type common wiring, and a first interlayer insulating film between the second conductive type common wiring and the second conductive type individual wiring. A second conductive type side individual wiring and a second conductive type common wiring are connected through a via hole that penetrates through the second interlayer insulating film and reaches the second conductive type common wiring; When the contact between the second conductive type individual wiring and the second conductive type semiconductor region is made through an opening reaching the second conductive type semiconductor region through the first and second interlayer insulating films, a portion other than the via hole is provided. And the second conductive type side common wiring and the second conductive type side The wiring is insulated by the second interlayer insulating film, the second conductive type-side individual wiring and the upper layer are insulated by the first and second interlayer insulating films at portions other than the openings, and furthermore, by the second conductive type-side common wiring. The upper layer is insulated by the first interlayer insulating film. A first interlayer insulating film between the upper layer and the second conductive type-side individual wiring and a second interlayer insulating film between the second conductive type-side individual wiring and the second conductive type-side common wiring; The connection between the conductive type-side individual wiring and the second conductive type-side common wiring is made through a via hole that penetrates through the second interlayer insulating film and reaches the second conductive type-side common wiring. When the contact with the two-conductivity-type semiconductor region is made through the opening reaching the second-conductivity-type semiconductor region through the first interlayer insulating film, the second-conductivity-type-side individual wiring and the second conductor are formed in portions other than the via holes. The mold-side common wiring is insulated by the second interlayer insulating film, and the second conductive type-side individual wiring and the upper layer are insulated by the first interlayer insulating film in portions other than the openings.

As is clear from the above description,
According to the method for manufacturing a light emitting diode array of the present invention,
The light emitting diodes are electrically separated into a plurality of first conductivity type blocks each including the same number of light emitting diodes by using a separation groove extending from the upper surface of the upper layer to the base. Then, one light emitting diode is non-overlappingly selected from each first conductivity type block to form a set of light emitting diodes, and one common second conductivity type common wiring is formed for each set. In addition, one first conductivity type side wiring common to the light emitting diode group in the block is formed for each first conductivity type block. If the light emitting diode array is manufactured in this manner, one second conductivity type electrode pad is formed for each second conductivity type common wiring,
Also, the first conductivity type side electrode pad is set to one for each first conductivity type side wiring.
Since it is only necessary to form the individual pads, the total number of pads to be formed is smaller than in the conventional case in which electrode pads are formed one by one on the light emitting diode. For this reason, even when the dot density of the light emitting diode is high, the density of the electrode pads to be formed can be reduced. Therefore, it is easy to form an electrode pattern including the electrode pad.

Then, a step of forming a first interlayer insulating film on the upper layer, and forming a second conductive type common wiring on the first interlayer insulating film, and then forming the first interlayer insulating film on the first interlayer insulating film. Forming a second interlayer insulating film covering the two-conductivity-type-side common wiring;
Forming a via hole penetrating through the interlayer insulating film and reaching the second conductive type common wiring and an opening reaching the island region through the first and second interlayer insulating films; Forming a second conductive type-side individual wiring by connecting one end to the mold-side common wiring and making the other end contact the corresponding island-shaped region of the light-emitting diode through the opening. The second conductive type side common wiring and the second conductive type side individual wiring are formed insulated by the second interlayer insulating film in the portion, and the second conductive type side individual wiring and the upper layer are formed in the first layer in the portion other than the opening. And the second conductive type common wiring and the upper layer can be formed insulated by the first interlayer insulating film. A step of forming a first interlayer insulating film on the upper layer; a step of forming an opening penetrating the first interlayer insulating film to reach the island region; and a step of forming the corresponding island region of the light emitting diode through the opening. Forming a second-conductivity-type-side individual wiring contacting the other end with the second conductive-type individual wiring; forming a second interlayer-insulation film covering the second-conductivity-type-side individual wiring on the first interlayer insulating film;
Forming a via hole that penetrates the interlayer insulating film and reaches the second conductive type individual wiring; and forming the second conductive type side common wiring by connecting the via hole to one end of the corresponding second conductive type individual wiring. When the method further includes a step, the second conductive type side individual wiring and the second conductive type side common wiring are formed insulated by the second interlayer insulating film in a portion other than the via hole, and the second conductive type side common wiring is formed in a portion other than the opening. The two-conductivity-type individual wiring and the upper layer can be formed insulated by the first interlayer insulating film.

Further, the first interlayer insulating film is formed by a diffusion mask having a diffusion window in a region where an island region is to be formed, a diffusion source film containing a second conductivity type impurity formed on the diffusion mask, A laminated film having a configuration in which an annealing cap film formed on the diffusion source film is laminated is formed, and the formation of the island region is performed by solid-phase diffusion to the upper layer of the second conductivity type impurity contained in the diffusion source film. In this case, since the island-shaped region can be formed shallowly, the thickness of the upper layer can be reduced. As a result, the aspect ratio of the separation groove can be reduced. Further, since the diffusion mask, the diffusion source film, and the annealing cap film used for forming the island region are used as the first interlayer insulating film, the manufacturing process of the light emitting diode array can be omitted.

When the separation groove is formed so as to have a rectangular cross section in a section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer, the space for the separation groove can be saved. Thus, a high-density light-emitting diode array can be formed.

In the case where the separation groove is formed so as to have a normal mesa shape in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer, the separation groove may not be embedded. In addition, the second conductive type common wiring can be formed by traversing the separation groove without fear of disconnection.

The shape of the separation groove in a section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer is rectangular in a region where the light emitting diodes are arranged, and is a regular mesa shape in other regions. In this case, a high-density light-emitting diode array can be formed, and the second conductive type common wiring can be formed by traversing the separation groove without fear of disconnection without embedding the separation groove. Can be formed.

In the case where the separation groove is buried with an insulating material so that the sample surface is flattened, regardless of the shape and depth of the separation groove, the separation groove is traversed without fear of disconnection, and the second conductivity type side is cut. A common wiring can be formed.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a basic configuration example of a light emitting diode array.

FIG. 2 is a schematic cross-sectional view showing a basic configuration example of a light-emitting diode array, where (A) is a schematic cross-sectional view taken along the line II in FIG. (B) is a schematic sectional view taken along the line II-II in FIG. 1, and (C) is a schematic sectional view taken along the line III-III in FIG. It is sectional drawing.

FIG. 3 is a schematic plan view (part 1) illustrating a modification of the basic configuration example of the light emitting diode array.

FIG. 4 is a schematic plan view (part 2) showing a modification of the basic configuration example of the light emitting diode array.

FIGS. 5A and 5B are schematic diagrams showing a basic configuration example of the light emitting diode array according to the first embodiment, wherein FIG. 5A is a plan view thereof, and FIG. It is the schematic sectional drawing cut | disconnected along the line, (C) is II- in (A).
FIG. 2 is a schematic cross-sectional view taken along line II.

FIG. 6 is a schematic diagram showing a basic configuration example of the light-emitting diode array according to the first embodiment, and is an II in FIG.
FIG. 3 is a schematic sectional view taken along line I-III.

FIG. 7 is a schematic diagram illustrating an arrangement relationship between an island region and a separation groove for explanation of the first embodiment;

8A to 8C are manufacturing process diagrams of the light emitting diode array according to the first embodiment, FIG. 8A is a plan view thereof, and FIG. 8B is a sectional view taken along line II in FIG. FIG. 5C is a cross-sectional view corresponding to a cross section taken along line II-II in FIG. 5A.

FIG. 9 is a manufacturing step diagram of the light-emitting diode array of the first embodiment, following FIG. 8, (A) is a plan view thereof, and (B) is a II line in FIG. 5 (A). FIG. 5C is a sectional view corresponding to a section taken along a line, and FIG.
FIG. 2A is a cross-sectional view corresponding to a cross-section taken along line II-II in FIG.

FIG. 10 is a manufacturing process diagram of the light-emitting diode array according to the first embodiment, following FIG. 9, (A) is a plan view thereof, and (B) is a II line in FIG. 5 (A). FIG. 5C is a sectional view corresponding to a section taken along a line, and FIG.
FIG. 2A is a cross-sectional view corresponding to a cross-section taken along line II-II in FIG.

FIG. 11 is a manufacturing process diagram of the light-emitting diode array according to the first embodiment, following FIG. 10, (A) is a plan view thereof, and (B) is a II line in FIG. 5 (A). FIG. 5C is a sectional view corresponding to a section taken along a line, and FIG.
FIG. 2A is a cross-sectional view corresponding to a cross-section taken along line II-II in FIG.

12 is a manufacturing process diagram of the light-emitting diode array of the first embodiment, following FIG. 11, (A) is a plan view thereof, and (B) is a II line in FIG. 5 (A). FIG. 5C is a sectional view corresponding to a section taken along a line, and FIG.
FIG. 2A is a cross-sectional view corresponding to a cross-section taken along line II-II in FIG.

13 is a manufacturing process diagram of the light-emitting diode array of the first embodiment, following FIG. 12, (A) is a plan view thereof, and (B) is a II line in FIG. 5 (A). FIG. 5C is a sectional view corresponding to a section taken along a line, and FIG.
FIG. 2A is a cross-sectional view corresponding to a cross-section taken along line II-II in FIG.

FIG. 14 is a manufacturing step diagram of the light-emitting diode array according to the first embodiment, following FIG. 13, (A) is a plan view thereof, and (B) is a II line in FIG. 5 (A). FIG. 5C is a sectional view corresponding to a section taken along a line, and FIG.
FIG. 2A is a cross-sectional view corresponding to a cross-section taken along line II-II in FIG.

FIG. 15 is a manufacturing process diagram of the light-emitting diode array according to the first embodiment, following FIG. 14, (A) is a plan view thereof, and (B) is a II line in FIG. 5 (A). FIG. 5C is a sectional view corresponding to a section taken along a line, and FIG.
FIG. 2A is a cross-sectional view corresponding to a cross-section taken along line II-II in FIG.

FIG. 16 is a manufacturing process diagram of the light-emitting diode array according to the first embodiment, following FIG. 15, (A) is a plan view thereof, and (B) is a II line in FIG. 5 (A). FIG. 5C is a sectional view corresponding to a section taken along a line, and FIG.
FIG. 2A is a cross-sectional view corresponding to a cross-section taken along line II-II in FIG.

17A and 17B are schematic diagrams illustrating a basic configuration example of a light emitting diode array according to a second embodiment, in which FIG. 17A is a plan view thereof, and FIG. 17B is a sectional view taken along line II in FIG. It is the schematic sectional drawing cut | disconnected along the line, (C) is II in (A).
FIG. 2 is a schematic sectional view taken along the line II.

FIG. 18 is a schematic diagram illustrating a basic configuration example of a light emitting diode array according to a second embodiment, and is a schematic cross section taken along line III-III in FIG. FIG.

19A and 19B are manufacturing process diagrams of the light-emitting diode array according to the second embodiment, FIG. 19A is a plan view thereof, and FIG.
17A is a sectional view corresponding to a section taken along line II in FIG. 17A, and FIG. 17C is a sectional view taken along the line II in FIG.
FIG. 2 is a sectional view corresponding to a section taken along line II.

20 is a manufacturing process diagram of the light-emitting diode array according to the second embodiment, following FIG. 19, (A) is a plan view thereof, and (B) is a II line in FIG. 17 (A). FIG. 17C is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 17C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIG. 21 is a manufacturing step view of the light-emitting diode array according to the second embodiment, following FIG. 20, (A) is a plan view thereof, and (B) is a II line in FIG. 17 (A). FIG. 17C is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 17C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIG. 22 is a manufacturing step diagram of the light-emitting diode array according to the second embodiment, following FIG. 21, (A) is a plan view thereof, and (B) is a II line in FIG. 17 (A). FIG. 17C is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 17C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIG. 23 is a manufacturing process diagram of the light-emitting diode array according to the second embodiment, following FIG. 22, (A) is a plan view thereof, and (B) is a II line in FIG. 17 (A). FIG. 17C is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 17C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

24A and 24B are schematic diagrams illustrating a basic configuration example of a light emitting diode array according to a third embodiment, in which FIG. 24A is a plan view thereof, and FIG. It is the schematic sectional drawing cut | disconnected along the line, (C) is II in (A).
FIG. 2 is a schematic sectional view taken along the line II.

FIG. 25 is a schematic view showing a basic configuration example of a light emitting diode array according to the third embodiment, and is a schematic cross section taken along line III-III in FIG. FIG.

FIG. 26 is a schematic diagram illustrating an arrangement relationship between an island region and a separation groove for explanation of a third embodiment;

27A and 27B are manufacturing process diagrams of the light-emitting diode array according to the third embodiment, FIG. 27A is a plan view thereof, and FIG.
24A is a sectional view corresponding to a section taken along line II in FIG. 24A, and FIG. 24C is a sectional view taken along line II in FIG.
FIG. 2 is a sectional view corresponding to a section taken along line II.

FIG. 28 is a manufacturing process diagram of the light-emitting diode array according to the third embodiment, following FIG. 27, (A) is a plan view thereof, and (B) is a II line in FIG. 24A is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 24C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIG. 29 is a manufacturing step diagram of the light-emitting diode array according to the third embodiment, following FIG. 28, (A) is a plan view thereof, and (B) is a II line in FIG. 24A is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 24C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIG. 30 is a manufacturing step diagram of the light-emitting diode array according to the third embodiment, following FIG. 29, (A) is a plan view thereof, and (B) is a II line in FIG. 24A is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 24C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIGS. 31A and 31B are schematic diagrams illustrating a basic configuration example of a light emitting diode array according to a fourth embodiment, wherein FIG. 31A is a plan view thereof, and FIG. It is the schematic sectional drawing cut | disconnected along the line, (C) is II in (A).
FIG. 2 is a schematic sectional view taken along the line II.

FIG. 32 is a schematic diagram showing a basic configuration example of a light emitting diode array according to a fourth embodiment, and is a schematic cross section taken along line III-III in FIG. FIG.

FIG. 33 is a manufacturing step diagram of the light-emitting diode array according to the fourth embodiment, (A) is a plan view thereof, and (B).
31A is a cross-sectional view corresponding to a cross section taken along line II in FIG. 31A, and FIG. 31C is a cross-sectional view taken along a line II in FIG.
FIG. 2 is a sectional view corresponding to a section taken along line II.

FIG. 34 is a manufacturing step view of the light-emitting diode array according to the fourth embodiment, following FIG. 33, (A) is a plan view thereof, and (B) is a II line in FIG. 31 (A). 31A is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 31C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIG. 35 is a manufacturing step diagram of the light-emitting diode array according to the fourth embodiment, following FIG. 34, (A) is a plan view thereof, and (B) is a II line in FIG. 31 (A). 31A is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 31C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIG. 36 is a manufacturing step diagram of the light-emitting diode array according to the fourth embodiment, following FIG. 35, (A) is a plan view thereof, and (B) is a II line in FIG. 31 (A). 31A is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 31C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIG. 37 is a manufacturing step view of the light-emitting diode array according to the fourth embodiment, following FIG. 36, (A) is a plan view thereof, and (B) is a II of FIG. 31 (A). 31A is a cross-sectional view corresponding to a cross section taken along a line, and FIG. 31C is a cross-sectional view corresponding to a cross section taken along a II-II line in FIG.

FIGS. 38A and 38B are schematic diagrams illustrating a basic configuration example of a light emitting diode array according to a fifth embodiment, wherein FIG. 38A is a plan view thereof, and FIG. It is the schematic sectional drawing cut | disconnected along the line, (C) is II in (A).
FIG. 2 is a schematic sectional view taken along the line II.

[Explanation of symbols]

 11: base 13: upper layer 15: island region (diffusion region) 17: PN junction 19: light emitting diode 21: light emitting diode group 23: n-type block 25, 25a, 25b: isolation groove 27: insulating material 29: p-type side Common wiring 31: p-type individual wiring 33: first interlayer insulating film 35: second interlayer insulating film 37: via hole 39: opening 41: n-type wiring 43: n-type ohmic electrode 45: n-type electrode pad 47: Via hole 51: Diffusion mask 51a: Diffusion window 53: Diffusion source film 55: Annealing cap film 57: Opening for forming isolation trench 59: Opening for forming n-type ohmic electrode 61: Film made of polyimide 63: Via hole 65: Opening 67: Negative resist 67a: Window 69: Insulating film 71: Side wall portion of laminated film 73: Laminated film 73a: Eave portion 75: First region 77 The second area

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Takaatsu Shimizu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References Japanese Utility Model 63-170142 (JP, U) ( 58) Surveyed field (Int.Cl. ⁷ , DB name) B41J 2/44 B41J 2/45 B41J 2/455 H01L 33/00

Claims (26)

(57) [Claims] An array of a plurality of light emitting diodes each having a junction for light emission between a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type is provided. A light-emitting diode array having two-conductivity-type side electrodes, comprising: a light-emitting diode group including the same number of light-emitting diodes as a light-emitting diode group; The side electrode is one second conductivity type common wiring common to one set of the light emitting diodes selected one by one from each of the blocks in a non-overlapping manner, and for each set,
The first conductivity type side electrode is provided for each of the blocks as one first conductivity type side wiring common to the light emitting diode group in the block. The conductive type semiconductor region is an upper layer made of a first conductive type semiconductor provided above a base made of a semi-insulating semiconductor or an insulator, and the second conductive type semiconductor region is formed from an upper surface of the upper layer in a thickness direction of the upper layer. A light emitting diode array, wherein the light emitting diode array is an island-shaped region selectively formed over a part of the depth of the second conductive type semiconductor, and the separation means is a separation groove extending from the upper surface of the upper layer to the base. . 2. The light emitting diode array according to claim 1, wherein the shape of the separation groove in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer is rectangular. LED array. 3. The light emitting diode array according to claim 1, wherein the shape of the separation groove in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer is a forward mesa shape. Characteristic light emitting diode array. 4. The light emitting diode array according to claim 1, wherein the shape of the separation groove in a cross section parallel to the arrangement direction of the light emitting diodes and perpendicular to the upper surface of the upper layer is such that the light emitting diodes are arranged. A light-emitting diode array having a rectangular shape in a region and a forward mesa shape in other regions. 5. The light emitting diode array according to claim 1, wherein said separation groove is buried with an insulating material. 6. The light emitting diode array according to claim 5, wherein said insulating material is polyimide. 7. The light emitting diode array according to claim 1, wherein one end is connected to the corresponding second conductive type common wiring, and the other end contacts the second conductive type semiconductor region of the corresponding light emitting diode. A light-emitting diode array comprising a second conductivity type side individual wiring provided as follows. 8. The light emitting diode array according to claim 7, wherein a first interlayer insulating film, a second conductive type common wire, and the second conductive film are provided between the upper layer and the second conductive type common wire. A second interlayer insulating film between the second conductive type side individual wiring and the second conductive type side common wiring, the connection between the second conductive type side individual wiring and the second conductive type side common wiring is provided through the second interlayer insulating film; The contact between the second conductive type individual wiring and the second conductive type semiconductor region penetrates through the first and second interlayer insulating films to form the second conductive type through the via hole reaching the conductive type common wiring. A light-emitting diode array, which is formed through an opening reaching a semiconductor region. 9. The light emitting diode array according to claim 7, wherein a first interlayer insulating film, a second conductive type individual wiring, and the second conductive film are provided between the upper layer and the second conductive type individual wiring. A second interlayer insulating film between the second conductive type side common wiring and the second conductive type side individual wiring; and a connection between the second conductive type side common wiring and the second conductive type side common wiring. The contact between the second conductive type individual wiring and the second conductive type semiconductor region penetrates through the first interlayer insulating film and the second conductive type semiconductor region. A light-emitting diode array, wherein the light-emitting diode array is formed through an opening reaching the upper surface. 10. The light-emitting diode array according to claim 1, wherein each of the blocks is provided in contact with the upper surface of the upper layer in the block and commonly provided for the light-emitting diode group in the block. A light-emitting diode array comprising a one-conductivity-type ohmic electrode. 11. The light emitting diode array according to claim 1, wherein a second conductive type side electrode pad provided to be connected to the second conductive type side common wiring is connected to the first conductive type side wiring. And the first and second conductive type electrode pads are provided in one region with the arrangement of the light emitting diodes as a boundary. LED array. 12. The light emitting diode array according to claim 11, wherein said first and second conductivity type electrode pads are provided in a line. 13. The light-emitting diode array according to claim 1, wherein each of the blocks is provided in contact with the upper surface of the upper layer in the block and commonly provided for the light-emitting diode group in the block. A light emitting diode array, comprising: a first conductivity type ohmic electrode; and wherein the first conductivity type ohmic electrode is provided in one region for each of the blocks with respect to the arrangement of the light emitting diodes. 14. The light emitting diode array according to claim 1, wherein one end is connected to the corresponding second conductivity type common wiring, and the other end contacts the second conductivity type semiconductor region of the corresponding light emitting diode. A second conductive type side individual wiring provided for each of the blocks; and a first conductive line provided in contact with the upper surface of the upper layer in the block for each of the blocks and commonly provided for the light emitting diode group in the block. A mold-side ohmic electrode, wherein the first-conductivity-type-side ohmic electrode is provided in one region with respect to the arrangement of the light-emitting diodes for each of the blocks, and the first-conductivity-type-side ohmic electrode is further provided. A light emitting diode array, wherein the other end of the second conductivity type individual wiring is in contact with a portion of the second conductivity type semiconductor region on the opposite side of the region provided with. 15. An array of a plurality of light emitting diodes each having a junction for light emission between a first conductivity type semiconductor region and a second conductivity type semiconductor region, wherein the first conductivity type side electrode for the light emitting diode and the second light emitting diode are arranged. In manufacturing a light-emitting diode array having a two-conductivity-type side electrode, an upper surface of an upper layer made of a first-conductivity-type semiconductor as the first-conductivity-type semiconductor region provided above a base made of a semi-insulating semiconductor or an insulator Forming an array of the plurality of light emitting diodes by selectively forming an island-shaped region made of the second conductivity type semiconductor as the second conductivity type semiconductor region over a part of the depth in the thickness direction of the upper layer. And including the same number of light emitting diodes as light emitting diode groups, respectively, for partitioning into a plurality of blocks electrically separated from each other. Forming a separation groove extending from the upper surface of the upper layer to the base; and forming the second conductive type side electrode common to a set of the light emitting diodes selected one by one from each of the blocks in a non-overlapping manner. As the second conductive type side common wiring of each of the sets,
Forming each of the first-conductivity-type-side electrodes for each block as one first-conductivity-type-side wiring common to the light-emitting diode group in the block. A method for manufacturing a light emitting diode array, comprising: 16. The method for manufacturing a light emitting diode array according to claim 15, further comprising: forming a first interlayer insulating film on the upper layer; and forming the second conductive type on the first interlayer insulating film. Forming a second interlayer insulating film covering the second conductive type common wiring on the first interlayer insulating film after forming the side common wiring; and forming the second interlayer insulating film through the second interlayer insulating film. Forming a via hole reaching the two-conductivity-type common wiring and an opening penetrating the first and second interlayer insulating films to reach the island-shaped region; and a corresponding second-conductivity-type common wiring through the via hole. Forming a second conductivity type individual wiring by connecting one end of the light emitting diode to the island-shaped region of the corresponding light emitting diode through the opening. Production method 17. The method for manufacturing a light emitting diode array according to claim 15, further comprising: forming a first interlayer insulating film on the upper layer; and forming the island shape through the first interlayer insulating film. Forming an opening reaching a region, forming the second conductive type side individual wiring by contacting the other end to the corresponding island-shaped region of the light emitting diode through the opening, and forming the first interlayer insulation Forming a second interlayer insulating film covering the second conductive type side individual wiring on the film, and forming a via hole penetrating the second interlayer insulating film and reaching the second conductive type side individual wiring; And a step of forming the second conductive type common wiring by connecting to one end of the corresponding second conductive type individual wiring through the via hole. 18. The method for manufacturing a light-emitting diode array according to claim 16, wherein the first interlayer insulating film is formed on a diffusion mask having a diffusion window in a region where the island region is to be formed, and on the diffusion mask. And a diffusion source film containing an impurity of the second conductivity type formed on the diffusion source film and an annealing cap film formed on the diffusion source film. A method of manufacturing a light-emitting diode array, wherein solid-state diffusion of a second conductivity type impurity contained in the diffusion source film into the upper layer is performed. 19. The method for manufacturing a light-emitting diode array according to claim 15, wherein the separation groove has a rectangular shape in a cross-section parallel to the arrangement direction of the light-emitting diodes and perpendicular to the upper surface of the upper layer. A method for manufacturing a light-emitting diode array, comprising: 20. The method of manufacturing a light-emitting diode array according to claim 15, wherein the shape of the separation groove in a cross section parallel to the arrangement direction of the light-emitting diodes and perpendicular to the upper surface of the upper layer is a regular mesa shape. A method for manufacturing a light-emitting diode array, characterized in that the light-emitting diode array is formed so that 21. The method of manufacturing a light emitting diode array according to claim 15, wherein the shape of the separation groove in a cross section parallel to a direction in which the light emitting diodes are arranged and perpendicular to an upper surface of the upper layer is the light emitting diode. A method of manufacturing a light-emitting diode array, wherein the light-emitting diode array is formed so as to have a rectangular shape in a region where the diodes are arranged and a forward mesa shape in other regions. 22. The method of manufacturing a light emitting diode array according to claim 15, further comprising a step of burying the isolation groove with an insulating material. 23. The method of manufacturing a light emitting diode array according to claim 22, wherein the insulating material is polyimide. 24. The method of manufacturing a light-emitting diode array according to claim 15, wherein the upper layer is formed by epitaxially growing a first conductivity type semiconductor layer to a predetermined thickness above a semi-insulating semiconductor substrate or an insulating substrate. A method for manufacturing a light emitting diode array, comprising: forming a light emitting diode array; 25. The method of manufacturing a light emitting diode array according to claim 15, wherein the upper layer is formed by diffusing an impurity of a first conductivity type from an upper surface of a semi-insulating semiconductor substrate to a predetermined depth. A method of manufacturing a light emitting diode array. 26. The method of manufacturing a light emitting diode array according to claim 15, further comprising:
Forming a first conductivity type ohmic electrode provided in contact with the upper surface of the upper layer in the block and commonly provided to the light emitting diode group in the block. Production method.