JP2000294830A - Light emitting element array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the manufacturing yield of a light emitting element array by increasing flexibility for arranging electrode pads. SOLUTION: A light emitting element array is provided with n-type diffusion areas 10 which are respectively formed in the plurality of blocks 4 of a semiconductor layer 2 constituting a semiconductor substrate, a separating groove 3 which insulates and separates the areas 10 from each other, and p-type diffusion areas 11 which are formed a plurality of areas by a plurality of areas in each block 4 so that the areas 11 may individually form p-n junctions with the n-type areas 10. The array is also provided with n-electrode pads which are individually connected to the n-type areas 10, n-electrodes 13 which are individually brought into contact with the p-type areas 11, and inter-block wiring 12 which connects the plurality of p-electrodes 4 in different blocks to each other. In addition, the array is also provided with p-type electrode pads 14 which are connected to the plurality of p-electrodes 13. The semiconductor layer 2 is composed of a semi-insulating semiconductor layer and the n-type diffusion areas 10 are partially formed in the blocks 4 except block boundary areas 5 in the area 6 of the inter-block wiring 12 and the areas 7 of the p-electrode pads 7. In addition, the separating groove 3 is formed in part of the block boundary areas 5 except the insides of the areas 6 and 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides a semiconductor layer of a semiconductor substrate into a plurality of blocks which are insulated and separated from each other.
The present invention relates to a light emitting element array in which a plurality of light emitting elements are formed in each of the blocks, and a plurality of light emitting elements are formed in a line in the semiconductor layer.

[0002]

2. Description of the Related Art A light emitting element array has a plurality of light emitting elements linearly arranged at regular intervals.
A light emitting element array using an ED (light emitting diode)
It is called an ED array.

FIG. 14 is a diagram showing the basic structure of an LED array. The LED array shown in FIG.
An n-type GaAsP epitaxial layer 102 is formed thereon, and a plurality of p-type diffusion regions 11 are formed on the GaAsP layer 102.
3, a plurality of light emitting portions (pn junctions) are arranged at equal intervals, and the p-side electrode 114 and the n-side electrode 115 are formed.
Is provided. Such an LED array is used as a light source of an optical printer.

Further, there is an LED array having a multilayer wiring structure for the purpose of reducing the number of electrode pads.

[0005] A multilayer wiring type LED array uses a semiconductor substrate in which, for example, an n-type semiconductor layer is formed on a high-resistance substrate layer and forms an isolation groove in the n-type semiconductor layer to form M element region blocks. By electrically diffusing a p-type impurity selectively through a diffusion mask.
N p-type diffusion regions of the ED are formed in each block, and N p-side electrode wires individually connected to the p-type diffusion regions are formed in each block. A p-side electrode pad is integrally formed at an end, an n-side electrode connected to an n-type semiconductor layer is formed in each of M blocks, an interlayer insulating film for forming a multilayer wiring structure is formed, and a different block is formed. A second-layer wiring connecting the formed p-side electrode wirings is formed on the above-mentioned interlayer insulating film.

[0006]

The pitch of the light emitting portion of the LED array is currently 600 [dpi] or 1200 [dpi].
[Dpi], but it is expected that the density will be further increased in the future. If the pitch of the light emitting portion is further increased in the future, it is necessary to arrange the electrode pads at a high density. However, in the above-described conventional element isolation structure, an isolation groove is formed over the entire area of the block boundary. Since the separation groove is also formed in the formation region of the electrode pad, the installation position of the electrode pad is limited by the separation groove. Further, if the light emitting unit pitch is further increased in the future, the width of the element isolation region must be reduced. However, in the above-described conventional element isolation structure, the isolation groove is formed over the entire area of the block boundary. If the opening of the etching mask for forming the separation groove is not formed partially or particles are placed on the opening, a part where the separation groove is not formed is formed, and the element cannot be separated, thereby lowering the manufacturing yield. May be caused. For this reason, it is desired to develop an element isolation structure that can cope with a higher density of the light emitting unit pitch.

The present invention has been made to solve such a conventional problem, and provides a light emitting element array capable of increasing the degree of freedom in arranging electrode pads and improving the manufacturing yield. With the goal.

[0008]

In order to achieve the above object, a light emitting element array according to the present invention comprises a semiconductor substrate having a semiconductor layer divided into a plurality of blocks, and a single semiconductor substrate formed in each of the blocks. A first conductivity type region, an isolation groove formed in a block boundary region to insulate and isolate the first conductivity type region from each other, and the block so as to form a pn junction individually with the first conductivity type region. A second conductive type region formed in a row in the semiconductor layer, a first conductive side electrode pad individually connected to the first conductive type region, and a second conductive type region separately formed in the second conductive type region. A second-layer wiring that connects between a plurality of second conductive-side electrodes that contact second conductive-type regions of different blocks from each other; Do And a second conductive side electrode pad, wherein the semiconductor layer is a semi-insulating, the first conductivity type region,
A block boundary formed in a part of the block not included in the block boundary region in the arrangement region of the second-layer wiring and the second conductive side electrode pad, and wherein the isolation groove is not included in the arrangement region It is characterized in that it is formed in a part of the region.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a view showing a structure of a multilayer wiring type LED array according to a first embodiment of the present invention, wherein FIG.
Is a cross-sectional view taken along the line AA ′ in (a), and FIG.
It is sectional drawing.

The LED array shown in FIG. 1 uses a semiconductor substrate in which a semi-insulating semiconductor layer 2 is formed on a semiconductor substrate layer 1, and has an isolation groove 3 and an n-type diffusion region 10 in the semi-insulating semiconductor layer 2.
, P-type diffusion region 11, second-layer wiring 12, p-side electrode 13, p-side electrode pad 14, and n-side electrode pad 15
And an interlayer insulating film 16.

The semiconductor substrate layer 1 is, for example, a GaAs substrate layer, and the semi-insulating semiconductor layer 2 is, for example, a semi-insulating Al.
It is a GaAs epitaxial layer. The semiconductor substrate layer 1 may be semi-insulating, n-type, or p-type. Also,
The semi-insulating semiconductor layer 2 may be a semi-insulating GaAs layer according to a desired emission wavelength, or a semi-insulating GaAs layer having a laminated structure of a cladding layer, an active layer, and a cladding layer in order to increase the emission intensity.
An lGaAs layer may be used. Further, the semiconductor substrate described above may be a simple semi-insulating semiconductor substrate instead of the two-layer structure of the substrate layer and the semi-insulating layer. In this case, the entire semiconductor substrate corresponds to a semi-insulating semiconductor layer.

The block 4 is a divided region of the semi-insulating semiconductor layer 2, and the semi-insulating semiconductor layer 2 is composed of M (M is an integer of 2 or more) blocks 4 (FIG. Are shown in two blocks 4). Further, the region 6 is a layout region of the second-layer wiring 12, the region 7 is a layout region of the p-side electrode pad 14, and the region 8 is a layout region of the n-type diffusion region 10. The regions 6, 7, and 8 are partial regions extending in the longitudinal direction of the semi-insulating semiconductor layer 2, and therefore include a part of the block boundary region 5.

The n-type diffusion regions 10 are formed one by one in each block 4 by selectively diffusing n-type impurities into the blocks 4. The n-type diffusion region 10 is located within the layout region 6 of the
It is not formed in the layout area 7 of the side electrode pad 13. Therefore, the n-type diffusion region 10 includes the regions 6 and 7
It is not formed in the block boundary area 5 in FIG.

The separation groove 3 is formed in a part of the block boundary region 5 by etching. This separation groove 3 has n
It is formed only in the block boundary region 5 in the layout region 8 of the mold diffusion region 10 and the layout regions 6 and 7
It is not formed in the block boundary area 5 in FIG. The n-type diffusion region 10 is formed in or near the block boundary region 5 in the layout region 8 which is a part of the block 4, and the isolation trench 3 is formed in each block 4.
Are isolated from each other. Separation groove 3
When the side diffusion portions of the n-type diffusion region 10 overlap, they are formed so as to include all the overlap portions. The depth of the isolation groove 3 is smaller than the junction depth of the n-type diffusion region 10 as shown in FIG.

The p-type diffusion region 11 is formed by selectively diffusing a p-type impurity into the block 4 so that each block 4 has an N-type diffusion region so as to form an individual pn junction with the n-type diffusion region 10.
(N is an integer of 2 or more) (N = 5 in FIG. 1), and M × N pieces are formed on the semiconductor layer 2 in a line. The p-type diffusion regions 11 are all n-type diffusion regions 1
0. A pn junction between the p-type diffusion region 11 and the n-type diffusion region 10 constitutes a light-emitting portion of each individual LED, and one block 4 includes N LEDs.

The p-type diffusion region 1 is provided in the interlayer insulating film 36 comprising the first interlayer insulating film 16a and the second interlayer insulating film 16b.
Light-emitting opening 16c for exposing 1 and n-type diffusion region 10
And an n-side electrode pad opening 16d that exposes the surface of the substrate. Also, the second interlayer insulating film 16b
The p-side electrode pad opening 16e for exposing the p-side electrode pad 14 and the via hole 16f for exposing a part of the p-side electrode 13 are further patterned. A p-side electrode 1 is formed on the patterned first interlayer insulating film 16a.
3. A p-side electrode pad 14 and an n-side electrode pad 15 are formed, a patterned second interlayer insulating film 16b is formed thereon, and a second-layer wiring 12 is formed thereon.

The p-side electrode 13 is individually in contact with the p-type diffusion region 11 at the light emitting opening 16c.

The second-layer wirings 12 are formed in the second-layer wiring layout region 7 of the semiconductor layer 2 in L (L is an integer equal to or greater than N) (L = 5 in FIG. 1). Each of the second-layer wirings 12 is in contact with the M p-side electrodes 13 that are in contact with the p-type diffusion regions 11 of the blocks 4 different from each other at via holes 16f.

The p-side electrode pad 14 is connected to the p-side electrode opening 1.
6d, is formed on the first interlayer insulating film 16a and is integrally formed with a predetermined p-side electrode 13. The p-side electrode pads 14 are arranged in a line in the p-side electrode pad layout region 7 of the semiconductor layer 2. The p-side electrode pad 14 is connected to the M p-side electrodes 13 via the second-layer wiring 12.

The n-side electrode pad 15 is connected to the n-side electrode opening 1.
6d, is formed on the n-type diffusion region 10 and is in contact with the n-type diffusion region 10.

In the multilayer wiring type LED array shown in FIG.
To make a desired LED emit light, a voltage is applied between the p-side electrode pad 14 connected to the anode of the LED and the n-side electrode pad 15 contacting the cathode of the LED.

FIG. 2 is a sectional structural view of a light emitting section in the LED array of FIG. In the first embodiment, all the p-type diffusion regions 11 are formed in the n-type diffusion region 10,
The junction depth of the n-type diffusion region 11 is smaller than that of the n-type diffusion region 10. Therefore, all the junction surfaces of the p-type diffusion region 11 form a pn junction (light emitting portion). When a voltage is applied between the p-side electrode pad 14 and the n-side electrode pad 15, a current flows through the pn junction to emit light. In the first embodiment,
A pn junction is also formed immediately below the p-side electrode 13 to emit light. The light from the light emitting section is transmitted to the interlayer insulating film 1
6 is transmitted, but is shielded from light by the p-side electrode 13. Therefore, light generated immediately below the p-side electrode 13 does not exit to the outside,
Only light generated outside the area immediately below the p-side electrode 13 is emitted to the outside.

In the first embodiment, the n-type diffusion region 10 is formed in a part of the semi-insulating block 4 and the isolation groove 3 is formed only in a part of the block boundary region 5.
There is no separation groove 3 in the layout region 6 of the layer wiring 12 and in the layout region 7 of the p-side electrode pad 14, so that the block boundary region 5 in the layout region 6 and the layout region 7 has a flat structure. it can. This eliminates the necessity of forming the second-layer wiring 12 on the separation groove 3, so that the reliability of wiring formation can be improved. Further, since the p-side electrode pad 14 can be arranged on the block boundary region 5, the p-side electrode pad 14
, And the p-side electrode pads can be laid out with high density. Also,
Since the length of the opening of the etching mask for forming the separation groove 3 is shortened, the probability that the opening is not formed partially or particles are placed in the opening can be reduced, and as a result, The manufacturing yield can be improved. Since the degree of freedom of arrangement of the electrode pads can be increased and the production yield can be improved, it is possible to cope with a high-density LED array.

Next, the manufacturing process will be described. FIG. 3-
FIG. 7 is a diagram illustrating an example of a manufacturing process of the multilayer wiring LED array of FIG. 3A to FIG.
(N) is a top view, and (a) to (n) are (A) to (N) respectively.
It is sectional drawing between AA 'in (N).

(1) Diffusion mask formation [FIG.
(A) First, an n-type diffusion region 10 is formed on a semi-insulating semiconductor layer 2 by selective diffusion of an n-type impurity using a semiconductor substrate having a semi-insulating semiconductor layer 2 formed on a semiconductor substrate layer 1. A diffusion mask 21 is formed, and an opening 21a is formed in the diffusion mask 21 by a photolithography method and an etching method, so that a part of the semi-insulating semiconductor layer 2 that becomes the n-type diffusion region 10 is exposed. As the semiconductor substrate layer 1, for example, a GaAs substrate layer is used, and as the semi-insulating semiconductor layer 2, for example, a semi-insulating AIGaAs epitaxial layer is used. Also,
As the diffusion mask 21, for example, a SiN film is used.

(2) Formation of Diffusion Source and Annealing Cap [See FIGS. 3B and 3B] Next, a diffusion source containing an n-type impurity is formed on the diffusion mask 21 shown in FIGS. 3A and 3A. Then, an annealing cap 23 is formed on the diffusion source 22. As the diffusion source 22, for example, an Sn—SiO ₂ film is used, and an annealing cap 23 is used.
For example, an SiO ₂ film is used.

(3) Formation of element region block [FIG.
(C) and (C)] Next, diffusion annealing is performed on the substrate shown in FIGS. 3B and 3B to diffuse an n-type impurity from the diffusion source 22 into the semi-insulating semiconductor layer 2 in the opening 21a. , An n-type diffusion region 10 is formed. At this time, the side diffusion portions of the adjacent n-type diffusion regions 10 may overlap. For example, an open tube annealing furnace is used for the diffusion annealing. After forming the n-type diffusion region 10, the annealing cap 23,
The diffusion source 22 and the diffusion mask 21 are all removed.

(4) Formation of separation groove [FIGS. 4D and 4D]
Next, an etching mask 24 for forming the separation groove 3 is formed on the semiconductor layer 2 from which the diffusion mask 21 has been peeled off.
An opening 24a is formed in the etching mask 8, exposing a part of the block boundary region. Then, a part of the block boundary region is wet-etched to form the isolation groove 3 so as to include the entire overlapping portion of the n-type diffusion region 10. As the etching mask 24, for example, a photoresist is used. In addition, a part of the above-described block boundary region is etched from the opening 24a using, for example, a phosphoric acid peroxide as an etchant. After forming the separation groove 3, the etching mask 24 is entirely removed.

(5) Formation of Diffusion Mask (First Interlayer Insulating Film) [See FIGS. 4E and 4E] Next, a diffusion mask (first interlayer insulating film) is formed on the semiconductor layer 2 from which the etching mask 24 has been removed. A film 16a is formed, and a light emitting opening 16c is formed in the diffusion mask 16a. The separation groove 3 is covered with a diffusion mask 16a. Diffusion mask 16
a is, for example, a film thickness of 500 to 3000 by a CVD method.
Using the SiN film of [Å], a light emitting opening 16c is formed in the SiN film by photolithography and etching.

(6) Formation of diffusion source [FIGS. 4 (f) and 4 (F)]
Next, p is placed on the diffusion mask 16a in FIGS.
A diffusion source 31 containing a type impurity is formed. The diffusion source 31 has a thickness of, for example, 500 to 3000 by sputtering.
The ZnO—SiO ₂ film of [膜] is used.

(7) Formation of Annealing Cap [FIG.
(See (g) and (G)] Next, an annealing cap 32 is formed on the diffusion source 31 shown in FIGS. 4 (f) and 4 (F). In the annealing cap 32,
For example, an AlN film having a thickness of 500 to 3000 [Å] by a sputtering method is used.

(8) Formation of p-type diffusion region [FIG.
(H)] Next, the substrate shown in FIGS. 5 (g) and 5 (G) is annealed to diffuse n from the diffusion source 31 into the semiconductor layer 2 at the light emitting opening 16c.
A p-type impurity is diffused into the p-type diffusion region 10 to form a p-type diffusion region 11. For example, annealing is performed at 650 [° C.] under nitrogen atmosphere for about 1 hour to form the p-type diffusion region 11 having a junction depth of about 1.0 [μm].

(9) Separation of Annealing Cap and Diffusion Source [See FIGS. 5 (i) and 5 (I)] Next, the annealing cap 32 and the diffusion source 31 are all stripped by a selective etching method, and the surface of the p-type diffusion region 11 is removed. To expose. The diffusion mask 16a is left and becomes the first interlayer insulating film.

(10) Formation of n-side electrode pad opening [Refer to FIGS. 6 (j) and 6 (J)] Next, an n-side electrode pad opening 16d is formed in the first interlayer insulating film 16a by photolithography and etching. Form n
The surface of the mold diffusion region 10 is exposed.

(11) Formation of p-side electrode and p-side electrode pad [Refer to FIGS. 6 (k) and 6 (K)] Next, the p-side electrode and p-side electrode pad are formed on the first interlayer insulating film 16a of FIGS. 6 (j) and 6 (J). A conductive film serving as the side electrode 13 and the p-side electrode pad 14 is formed, and the conductive film is patterned by a lift-off method to form the p-side electrode 13 and the p-side electrode pad 14. For the p-side electrode 13, for example, Al is used. Thereafter, sintering is performed so that the p-side electrode 13 makes ohmic contact with the p-type diffusion region 11.

(12) Formation of n-side electrode pad [FIG.
(L) and (L)] Next, a conductive film to be the n-side electrode pad 15 is formed on the first interlayer insulating film 16a in FIGS. 6 (k) and 6 (K), and this conductive film is lifted off. The n-side electrode pad 15 is formed in the n-side electrode pad opening 16d. For the n-side electrode pad 15, for example, an Au alloy is used.

(13) Formation of second interlayer insulating film [FIG.
(M), (M)] Next, a second interlayer insulating film 16b is formed on the p-side electrode 13 and the p-side electrode pad 14 and the first interlayer insulating film 16a in FIGS. 6 (l) and 6 (L). The second interlayer insulating film 16 is formed.
b, a light emitting opening 16c, an n-side electrode pad opening 16d, a p-side electrode pad opening 16e, and a via hole 16f are formed by photolithography and etching.
For example, polyimide is used for the second interlayer insulating film 16b.

(14) Formation of Second Layer Wiring [FIG. 7 (n),
(N)] Next, a conductive film to be the second-layer wiring 32 is formed on the second interlayer insulating film 16b in FIGS. 7M and 7M, and the conductive film is patterned by a lift-off method. Second layer wiring 12
To form For the second layer wiring 12, for example, Al is used. As described above, the multilayer wiring type LED array of FIG. 1 is manufactured.

As described above, according to the first embodiment, the n-type diffusion region 10 is formed in a part of the semi-insulating block 4,
The separation groove 3 is formed only in a part of the block boundary region 5, and 2
By not forming the separation groove 3 in the layout area 6 of the layer wiring 12 and the layout area 7 of the p-side electrode pad 14, the reliability of wiring formation can be improved, and the arrangement of electrode pads can be freely performed. The degree can be increased, and the production yield can be improved. Thereby, it is possible to correspond to a high-density LED array.

As described in the first embodiment, the p-side electrode pad 14 may be arranged on the block boundary region 5. FIG. 8 is a diagram showing the structure of the LED array of the first embodiment in which the p-side electrode pads are arranged on the block boundary region. As shown in FIG. 8A, the p-side electrode pad 14
Are also arranged on the block boundary region 5 having a flat structure in which the separation groove 3 is not formed. As a result, a high-density p-side electrode pad arrangement can be achieved. Second Embodiment FIGS. 9A and 9B are diagrams showing the structure of a multilayer wiring type LED array according to a second embodiment of the present invention, wherein FIG.
Is a cross-sectional view taken along the line AA ′ of (a), and (c) is a BB ′ of (a).
It is sectional drawing. In FIG. 9, the same components as those in FIG. 1 are denoted by the same reference numerals. Also, the LE of the second embodiment
The manufacturing process of the D array is the same as that of the LED array of the first embodiment.

The LED array shown in FIG. 9 uses the same semiconductor substrate as the first embodiment in which the semi-insulating semiconductor layer 2 is formed on the semiconductor substrate layer 1. , N-type diffusion region 40, p-type diffusion region 41, 2
Layer wiring 12, p-side electrode 13, p-side electrode pad 14
And an n-side electrode pad 15 and an interlayer insulating film 16.

The n-type diffusion regions 40 are formed one by one in each of the blocks 4 by selectively diffusing n-type impurities into the blocks 4. The n-type diffusion region 40 is located within the layout region 6 of the
It is not formed in the layout area 7 of the side electrode pad 13. Therefore, n-type diffusion region 40 is not formed in block boundary region 5 in layout regions 6 and 7. Further, the width of the layout region 8 of the n-type diffusion region 40 is smaller than in the first embodiment.

The separation groove 33 is formed in a part of the block boundary region 5 by etching. This separation groove 33
Are formed only in the block boundary region 5 in the layout region 8 of the n-type diffusion region 40, and are not formed in the block boundary region 5 in the layout regions 6 and 7.
The n-type diffusion region 40 is formed in or near the block boundary region 5 in the layout region 8 which is a part of the block 4, and the isolation groove 33 is formed in the n-type diffusion region 40 of each block 4. Are insulated from each other. The depth of the isolation groove 33 is smaller than the junction depth of the n-type diffusion region 40 as shown in FIG.

The p-type diffusion regions 41 are formed by selectively diffusing a p-type impurity into the blocks 4 so that each block 4 has an N-type diffusion region 40 so as to form an individual pn junction with the n-type diffusion region 40.
M × N pieces are formed in a row on the semiconductor layer 2. Each p-type diffusion region 41 is formed so as to straddle the n-type diffusion region 40 and the semi-insulating region, unlike the p-type diffusion region 11 of the first embodiment. p
The pn junction between the type diffusion region 41 and the n-type diffusion region 40 constitutes a light emitting portion of each individual LED.

FIG. 10 is a sectional structural view of a light emitting section in the LED array of FIG. In the second embodiment, each p-type diffusion region 41 is formed so as to straddle the n-type diffusion region 40 and the semi-insulating region, and the junction depth of the p-type diffusion region 41 is Shallower than. Also, the p-side electrode 1
3 is not formed on the n-type diffusion region 40. Therefore, of the bonding surfaces of the p-type diffusion region 41, the bonding surface formed other than immediately below the p-side electrode 13 partially forms a pn junction (light emitting portion). That is, in the second embodiment, the pn junction (light emitting portion) is formed only in a region other than immediately below the p-side electrode 13.
Is formed. p-side electrode pad 14 and n-side electrode pad 1
When a voltage is applied between 5 and 5, a current flows through the pn junction to emit light. In the second embodiment, the p-side electrode 1
Light emission occurs only in a region other than immediately below the region 3. Accordingly, since all the generated light is emitted to the outside, there is no light loss due to the light blocking of the p-side electrode 13, and the emission efficiency of the light generated in the light emitting unit can be higher than that of the first embodiment.

In the second embodiment, as in the first embodiment, an n-type diffusion region 40 is formed in a part of the semi-insulating block 4 and separated only in a part of the block boundary region 5. Since the groove 33 is formed, there is no separation groove 33 in the layout region 6 of the second-layer wiring 12 and the layout region 7 of the p-side electrode pad 14, and the block boundary region 5 in the layout regions 6 and 7 is formed. It can have a flat structure. This eliminates the necessity of forming the second-layer wiring 12 on the separation groove 33, so that the reliability of wiring formation can be improved. In addition, since the p-side electrode pad 14 can be arranged on the block boundary region 5,
The degree of freedom of arrangement of the p-side electrode pads 14 can be increased, so that the p-side electrode pads can be laid out with high density. Further, since the length of the opening of the etching mask for forming the separation groove 33 is reduced, the probability that the opening is not formed partially or particles are placed in the opening can be reduced. As a result, the production yield can be improved. Since the degree of freedom of arrangement of the electrode pads can be increased and the production yield can be improved, it is possible to cope with a high-density LED array.

As described above, according to the second embodiment, the n-type diffusion region 40 is formed in a part of the semi-insulating block 4,
The separation groove 33 is formed only in a part of the block boundary region 5,
Since the separation groove 33 is not formed in the layout area 6 of the second-layer wiring 12 and the layout area 7 of the p-side electrode pad 14, the reliability of the wiring formation can be improved as in the first embodiment. Thus, the degree of freedom in arranging the electrode pads can be increased, and the manufacturing yield can be improved. Thereby, the high density L
It can correspond to an ED array.

Further, by forming the p-type diffusion region 41 over the n-type diffusion region 40 and the semi-insulating region,
Since the n-junction (light-emitting portion) can be formed only in a region other than immediately below the p-side electrode 13, the emission efficiency of light generated in the light-emitting portion can be higher than in the first embodiment. Third Embodiment FIG. 11 is a view showing a structure of a multilayer wiring type LED array according to a third embodiment of the present invention, wherein FIG.
(B) is an AA ′ sectional view of (a), and (c) is B of (a).
FIG. 14 is a sectional view taken along the line B-B '. In FIG. 11, the same components as those in FIG. 1 are denoted by the same reference numerals. The manufacturing process of the LED array according to the third embodiment is the same as that of the LED array according to the first embodiment.

The LED array of FIG. 1 uses the same semiconductor substrate as in the first embodiment in which the semi-insulating semiconductor layer 2 is formed on the semiconductor substrate layer 1. , N-type diffusion region 60, p-type diffusion region 61, 2
Layer wiring 12, p-side electrode 13, p-side electrode pad 14
And an n-side electrode pad 15 and an interlayer insulating film 16.

The n-type diffusion regions 60 are formed one by one in each block 4 by selectively diffusing n-type impurities into the blocks 4. The n-type diffusion region 60 is located within the layout region 6 of the
It is not formed in the layout area 7 of the side electrode pad 13. Therefore, n-type diffusion region 60 is not formed in block boundary region 5 in layout regions 6 and 7. Further, the width of the layout region 8 of the n-type diffusion region 60 is smaller than in the second embodiment.

The separation groove 53 is formed in a part of the block boundary region 5 by etching. This separation groove 53
Are formed only in the block boundary region 5 in the layout region 8 of the n-type diffusion region 60, and are not formed in the block boundary region 5 in the layout regions 6 and 7.
The n-type diffusion region 60 is formed in or near the block boundary region 5 in the layout region 8 which is a part of the block 4, and the isolation groove 53 is formed in the n-type diffusion region 60 of each block 4. Are insulated from each other. The depth of isolation groove 53 is smaller than the junction depth of n-type diffusion region 40.

The p-type diffusion region 61 is formed by selectively diffusing a p-type impurity into the block 4, so that each block 4 has an N-type diffusion region 60 so as to form an individual pn junction with the n-type diffusion region 60.
M × N pieces are formed in a row in the semiconductor layer 2. Each of the p-type diffusion regions 61 is different from the p-type diffusion region 11 of the first embodiment and the p-type diffusion region 41 of the second embodiment, and is different from the n-type diffusion region 60 of the second embodiment.
Is formed in a semi-insulating region adjacent to the P-type diffusion region 61, and a pn junction with a side end of the n-type diffusion region 60 is formed at a side end of the p-type diffusion region 61. The pn junction between the p-type diffusion region 61 and the n-type diffusion region 60 constitutes a light emitting unit of each individual LED.

FIG. 12 is a sectional structural view of a light emitting portion in the LED array of FIG. In the third embodiment, each p-type diffusion region 61 is formed in a semi-insulating region adjacent to the n-type diffusion region 60, and only the side end portions of the p-type diffusion region 61 and the n-type diffusion region 60 are formed. A pn junction (light emitting portion) is formed at the bottom. Therefore, a pn junction is not formed immediately below the p-side electrode 13. That is, also in the third embodiment, the pn junction (light emitting portion) is formed only in a region other than immediately below the p-side electrode 13 as in the second embodiment. When a voltage is applied between the p-side electrode pad 14 and the n-side electrode pad 15, a current flows through the pn junction to emit light. In the third embodiment, light emission occurs only in a region other than immediately below the p-side electrode 13. Accordingly, since all the generated light is emitted to the outside, there is no light loss due to the light blocking of the p-side electrode 13, and the emission efficiency of the light generated in the light emitting unit can be higher than that of the first embodiment.

In the third embodiment, similarly to the first and second embodiments, an n-type diffusion region 60 is formed in a part of the semi-insulating block 4 and a part of the block boundary region 5 is formed. Since the separation groove 53 is formed only in the second layer wiring 1
There is no separation groove 53 in the layout region 6 and the layout region 7 of the p-side electrode pad 14, so that the block boundary region 5 in the layout regions 6 and 7 can have a flat structure. This eliminates the need to form the second-layer wiring 12 on the separation groove 53, so that the reliability of wiring formation can be improved. Further, since the p-side electrode pad 14 can be arranged on the block boundary region 5, the degree of freedom of arrangement of the p-side electrode pad 14 can be increased, and therefore the p-side electrode pad is laid out with high density. be able to. Further, since the length of the opening of the etching mask for forming the separation groove 53 is reduced,
It is possible to reduce the probability that the opening is not formed partially or that particles are placed on the opening, thereby improving the manufacturing yield. Since the degree of freedom of arrangement of the electrode pads can be increased and the production yield can be improved, high-density LE
Compatible with D array.

As described above, according to the third embodiment, the n-type diffusion region 60 is formed in a part of the semi-insulating block 4,
The separation groove 53 is formed only in a part of the block boundary region 5,
Since the separation groove 53 is not formed in the layout area 6 of the second-layer wiring 12 and the layout area 7 of the p-side electrode pad 14, the wiring is formed in the same manner as in the first and second embodiments. The reliability can be improved, the degree of freedom in the arrangement of the electrode pads can be increased,
The manufacturing yield can be improved. This allows
It can correspond to a high-density LED array.

Further, a p-type diffusion region 61 is formed in the semi-insulating region adjacent to the n-type diffusion region 60, and the n-type diffusion region 6 is formed.
Since the pn junction (light-emitting portion) is formed only at the side edge of the p-type diffusion region 61 and 0, the pn junction (light-emitting portion) can be formed only in a region other than immediately below the p-side electrode 13. The emission efficiency of light generated in the light emitting unit can be higher than in the first embodiment. Fourth Embodiment FIG. 13 is a view showing a structure of a multilayer wiring type LED array according to a fourth embodiment of the present invention, wherein FIG.
(B) is an AA ′ sectional view of (a), and (c) is B of (a).
FIG. 14 is a sectional view taken along the line B-B '. In FIG. 13, the same components as those in FIG. 1 are denoted by the same reference numerals. The manufacturing process of the LED array of the fourth embodiment is the same as that of the LED array of the first embodiment.

The LED array of FIG. 13 is different from the LED array of the first embodiment (see FIG. 1) in that the n-side electrode pad 15 is formed in the layout region 7 of the p-side electrode pad 14. 14 and n-side electrode pad 15
Are formed in a line on one side of the semiconductor layer 2. The LED array of FIG. 13 uses the same semiconductor substrate as in the first embodiment in which the semi-insulating semiconductor layer 2 is formed on the semiconductor substrate layer 1, and the semi-insulating semiconductor layer 2 is provided with an isolation groove 73.
, N-type diffusion region 80, p-type diffusion region 11, second-layer wiring 12, p-side electrode 13, p-side electrode pad 14,
The n-side electrode pad 15 and the interlayer insulating film 16 are formed.

The n-type diffusion regions 80 are formed one by one in each of the blocks 4 by selectively diffusing n-type impurities into the blocks 4. In the fourth embodiment, since the n-side electrode pad 15 is laid out in the layout region 7 of the p-side electrode pad 14, the n-type diffusion region 80 is
It is also formed in the layout area 7 of the side electrode pad 13. However, the n-type diffusion region 80 is
And 7 are not formed in the block boundary region 5.

The separation groove 73 is formed in a part of the block boundary region 5 by etching. This separation groove 73
Is formed only in the block boundary region 5 in the layout region 9 of the p-type diffusion region 11, and is not formed in the block boundary region 5 in the layout regions 6 and 7.
Further, in the fourth embodiment, since the n-side electrode pads 15 are not laid out along the columns of the p-type diffusion regions 11, the length of the separation groove 73 is smaller than that of the first to third embodiments. Shorter than the groove. The n-type diffusion region 80 is formed in or near the block boundary region 5 in the layout region 9 which is a part of the block 4, and the isolation groove 73 is formed in the n-type diffusion region 80 of each block 4. Are insulated from each other. The depth of the isolation groove 73 is smaller than the junction depth of the n-type diffusion region 80.

The n-side electrode pad 15 is
N type diffusion region 80 formed in layout region 6 of FIG.
And is in contact with the n-type diffusion region 80. n-side electrode pad 15 and p-side electrode pad 14
Are formed in a line in the layout area 6 as shown in FIG.

In the fourth embodiment, as in the first embodiment, an n-type diffusion region 80 is formed in a part of the semi-insulating block 4 and separated only in a part of the block boundary region 5. Since the groove 73 is formed, there is no separation groove 73 in the layout region 6 of the second-layer wiring 12 and in the layout region 7 of the p-side electrode pad 14, and the block boundary region 5 in the layout regions 6 and 7 is formed. It can have a flat structure. This eliminates the need to form the second-layer wiring 12 on the separation groove 73, so that the reliability of wiring formation can be improved. Further, since the p-side electrode pad 14 can be arranged on the block boundary region 5,
The degree of freedom of arrangement of the p-side electrode pads 14 can be increased, so that the p-side electrode pads can be laid out with high density. Further, since the length of the opening of the etching mask for forming the separation groove 73 is reduced, the probability that the opening is not formed partially or particles are placed in the opening can be reduced, As a result, the production yield can be improved. Since the degree of freedom in arranging the electrode pads can be increased and the manufacturing yield can be improved, it is possible to cope with a high-density LED array.

Further, in the fourth embodiment, the n-side electrode pad 15 is formed between the rows of the p-side electrode pads 14 in the layout region 7, and the p-side electrode pad 14 and the n-side electrode pad 15 are formed in the semiconductor layer. 2 was formed in a line on one side,
The width of the ED array can be reduced.

As described above, according to the fourth embodiment, the n-type diffusion region 80 is formed in a part of the semi-insulating block 4,
The separation groove 73 is formed only in a part of the block boundary region 5,
Since the separation groove 73 is not formed in the layout area 6 of the second-layer wiring 12 and the layout area 7 of the p-side electrode pad 14, the reliability of the wiring formation is improved as in the first embodiment. Thus, the degree of freedom in arranging the electrode pads can be increased, and the manufacturing yield can be improved. Thereby, the high density L
It can correspond to an ED array.

Further, n is provided between the rows of the p-side electrode pads 14.
By forming the side electrode pad 15 and forming the p-side electrode pad 14 and the n-side electrode pad 15 in a row, LE
The width of the D array can be reduced.

The LED array according to the fourth embodiment differs from the LED array according to the first embodiment in that the n-side electrode pad 15 is formed in the layout region 7 of the p-side electrode pad 14. This layout can be applied to the LED array of the second or third embodiment.

[0066]

As described above, according to the present invention, a first conductivity type region is formed in a part of a semi-insulating block, and a separation groove is formed only in a part of a block boundary region. By not forming the separation groove in the arrangement area of the eye wiring and the second conductive side electrode pad, the block boundary area in the above-mentioned arrangement area can be made a flat structure. There is an effect that it can be improved. In addition, since the second conductive side electrode pad can be arranged on the block boundary region, there is an effect that the degree of freedom of arrangement of the electrode pad can be increased. Further, since the length of the separation groove is reduced, there is an effect that the yield of forming the separation groove can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of an LED array according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating light emission according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 1).

FIG. 4 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 2).

FIG. 5 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 3).

FIG. 6 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 4).

FIG. 7 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 5).

FIG. 8 is a diagram showing a modification of the LED array according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a structure of an LED array according to a second embodiment of the present invention.

FIG. 10 is a diagram illustrating light emission according to the second embodiment of the present invention.

FIG. 11 is a diagram illustrating a structure of an LED array according to a third embodiment of the present invention.

FIG. 12 is a diagram illustrating light emission according to a third embodiment of the present invention.

FIG. 13 is a diagram illustrating a structure of an LED array according to a fourth embodiment of the present invention.

FIG. 14 is a diagram showing a basic structure of an LED array.

[Explanation of symbols]

1 semiconductor substrate layer, 2 semi-insulating semiconductor layer, 3,3
3, 53, 73 separation groove, 4 block, 5 block boundary area, 6 layout area of second layer wiring,
7 p-side electrode pad layout region, 8 n-type diffusion region layout region, 9 p-type diffusion region layout region, 10, 40, 60, 80 n-type diffusion region
11, 41, 61 p-type diffusion region, 12 second layer wiring, 13p-side electrode, 14p-side electrode pad, 15
n-side electrode pad.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Hiroshi Hamano 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Takaatsu Shimizu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. F-term (reference) 5F041 CA93 CB24 CB25 FF13

Claims (7)

[Claims] A semiconductor substrate having a semiconductor layer divided into a plurality of blocks; a first conductivity type region formed one by one in the block; and a first conductivity type region insulated from each other. An isolation groove formed in each of the block boundary regions; a second conductivity type formed in the block so as to form a pn junction individually with the first conductivity type region; A region, a first conductive side electrode pad individually connected to the first conductive type region, a second conductive side electrode individually contacted with the second conductive type region, and a second conductive type region of a different block. A second-layer wiring connecting between the plurality of second conductive electrodes to be contacted; and a second conductive electrode pad connected to the plurality of second conductive electrodes, wherein the semiconductor layer is semi-insulating. Yes, The first conductivity type region includes the second layer wiring and the second layer wiring.
The separation groove is formed in a part of the block boundary region not included in the arrangement region, and is formed in a part of the block that is not included in the block boundary region in the arrangement region of the conductive-side electrode pad. A light-emitting element array, characterized in that: 2. The semiconductor device according to claim 1, wherein the second conductivity type region is entirely formed in the first conductivity type region.
The light-emitting element array according to claim 1. 3. The light emitting element array according to claim 1, wherein the second conductivity type region is formed so as to extend over the first conductivity type region and the semi-insulating region. 4. The method according to claim 1, wherein the second conductivity type region is formed adjacent to the first conductivity type region, and the pn junction is formed at a side end of the second conductivity type region. The light emitting element array according to claim 1, wherein 5. The light emitting element array according to claim 3, wherein the pn junction is formed only in a region other than immediately below the second conductive side electrode. 6. The first conductive side pads and the second conductive side electrode pads are formed in a line by forming the first conductive side pads between the rows of the second conductive side electrode pads. The light emitting element array according to claim 1, wherein: 7. The light emitting device according to claim 1, wherein the first conductive side electrode pad is formed on a first conductive type region and is in contact with the first conductive type region. array.