JP4036800B2 - Light emitting element array - Google Patents

Description

  The present invention relates to a light emitting element array, and more particularly to a light emitting element array having a plurality of common electrodes for an optical print head in a non-impact printer using an electrophotographic method.

    Light emitting diodes (LEDs) are light emitting diodes that emit light vividly, have low driving voltage, and facilitate peripheral circuits. For this reason, they have adopted not only display devices but also electrophotographic methods. For the purpose of application to a light source such as an optical printer, an optical print head using a light emitting diode array (hereinafter referred to as a “light emitting element array”) has been actively studied.

  An optical printer that uses a self-luminous light emitting element array as a light source emits each dot of the light emitting element array in accordance with an image signal, and exposes it on a photosensitive drum by an equal magnification imaging element such as a distributed refractive index lens. Then, an electrostatic latent image is formed, toner is selectively attached by a developing device, and then printing is performed by transferring the toner attached to plain paper or the like.

An optical print head using this light emitting element array is
(1) Since there are no moving parts and there are few components, miniaturization is possible.
(2) It is easy to increase the length by connecting a plurality of light emitting element array chips.
It has the features such as.

  Conventionally, light emitting element arrays having various structures have been developed. For reference, the structure of the light emitting element array disclosed in the following Patent Document 1 is described with reference to FIGS. explain. 4 is a plan view of a main part with the insulating layer of the light emitting element array 50 removed, and FIG. 5 is a cross-sectional view taken along the line AA of FIG.

In FIG. 4, the light emitting element array 50 is formed of a compound semiconductor 51 made of GaP, GaAsP, GaAlAs, GaAs or the like, and a plurality of light emitting regions 57 arranged in a row or staggered pattern are selectively diffused on the surface thereof. Is formed by. Insulating films 52, 53, and 54 made of Si ₃ N ₄ , SiO ₂ , Al ₂ O _{3 and the} like are sequentially provided on the surface of the compound semiconductor 51. These insulating films 52, 53, and 54 are used to select a light emitting region. A plurality of layers are provided for the purpose of a diffusion film, a protective film on the surface of the compound semiconductor, a pinhole countermeasure film, a wiring reinforcement base film, a light extraction / brightness adjustment film, and the like. On the insulating films 52 and 53, an individual electrode layer 55 made of Al, Cr, or the like in ohmic contact with the light emitting region 57 is provided. An electrode connected to each light emitting region, an electrode for bonding, and these are connected. It becomes an electrode for wiring. A common electrode 56 made of Au or the like is provided on the back surface of the compound semiconductor 51.

  In such a light emitting element array 50, since the electrode layers 55 are individually provided in the respective light emitting regions 57, when a larger number of light emitting regions 57 are formed at a higher density, the respective light emitting regions 57 are formed accordingly. Since the number of electrodes connected to the light emitting region 57, bonding electrode pads, wiring electrodes connecting these, etc. and the total area occupied by them increase, there is a problem that the density cannot be physically increased.

  Therefore, in order to solve the problems of the conventional light emitting element array as described above, individual electrodes are shared by a plurality of light emitting elements, and the number of electrode wirings and electrode pads and the total area occupied by them are reduced. A light emitting device array has been developed.

  Therefore, a light emitting element array disclosed in Patent Document 2 below will be described below with reference to FIGS. 6 and 7 in order to understand the present invention. 6 is a plan view schematically showing the light-emitting element array, and FIG. 7 is a partial plan view (FIG. 6A) and a partial cross-sectional view around the element isolation region of the light-emitting element array shown in FIG. 6 (b)).

  As shown in FIG. 7B, the light emitting element array 60 is epitaxially formed on the high resistance substrate 61 made of, for example, GaAs and functioning as a semi-insulating substrate, and on the high resistance substrate 61, made of, for example, AlGaAs. and an n-type semiconductor layer 62. In the light emitting element array 60, the n-type semiconductor layer 62 is divided into four blocks 64 by forming 4-1 = 3 element isolation regions 63 (see FIG. 6). Here, the element isolation region 63 is a diffusion region of a p-type impurity having a depth reaching the high resistance substrate 61, and is formed between adjacent blocks 64. The element isolation region 63 is an n-type in the vicinity thereof. The n-type semiconductor layer 62 is separated into blocks 64 by the pn junction formed with the semiconductor layer 62.

  Further, as shown in FIG. 6, in each block 64 of the light-emitting element array 60, four light-emitting regions 65 are formed so as to form a one-dimensional column at substantially equal intervals throughout the light-emitting element array 60. In the entire light emitting element array 60, 4 × 4 = 16 light emitting regions 65 are formed.

  As shown in FIG. 7B, the light emitting region 65 is a p-type impurity diffusion region formed by selective diffusion in the n-type semiconductor layer 62, and does not reach the high resistance substrate 61, that is, element isolation. The diffusion depth is smaller than the diffusion depth of the region 63, and the boundary between the light emitting region 65 and the n-type semiconductor layer 62 around the light emitting region 65 is a pn junction that generates a light emission phenomenon.

  In the n-type semiconductor layer 62, one p-side contact electrode 66 is formed on each light emitting region 65, and one n side is formed on a region other than the light emitting region 65 of each block 64. A contact electrode 67 is formed.

  In the light emitting element array 60, a multilayer wiring 70 for supplying a current to the light emitting region 65 through the p side contact electrode 66 and the n side contact electrode 67 is formed. The multilayer wiring 70 includes an individual wiring 71 formed on the first interlayer insulating film 80, an n-side electrode pad 75 that is an exposed portion of the n-side contact electrode 67, and a second interlayer insulating film. 85 and common wiring 73 formed on 85. The multilayer wiring 70 is a kind of so-called matrix wiring structure, and has a network structure of individual wirings 71 and common wirings 73.

  In the multilayer wiring 70, the first interlayer insulating film 80 is provided on the n-type semiconductor layer 62 of the block 64, and the first light emitting opening 81 and the n side contact electrode exposing the light emitting region 65 and the p side contact electrode 66. 67 (n-side electrode pad 75) is formed, and the individual wiring 71 is connected to the p-side contact electrode 66 exposed in the first light-emitting opening 81 on a one-to-one basis. Has been. One p-side electrode pad 74 is provided for each block 64, and is connected to one individual wiring 71 of the block 64.

  In the multilayer wiring 70, the second interlayer insulating film 85 is provided on the first interlayer insulating film 80 so as to cover the individual wiring 71, and the first light emitting opening 81 of the first interlayer insulating film 80 is exposed. A second opening 87 is formed which communicates with the second light emitting opening 86 and the first opening 82 of the first interlayer insulating film 80 and exposes the n-side electrode pad 75 (n-side contact electrode 67). A first via hole 88 exposing the p-side electrode pad 74 and a second via hole 89 exposing a part of the individual wiring 71 are also formed.

  In this multilayer wiring 70, the common wiring 73 is formed across all the blocks 64 through the element isolation region 63, and is formed integrally with the p-side electrode pad 74 through the second via hole 89 in each block 64. It is connected to the individual wiring 71.

  An n-side electrode pad 75 which is an n-side wire bonding pad is also formed in each block 64, and an exposed portion of the n-side contact electrode 67 connected to the semiconductor layer 62 through the first opening 82. It is formed as.

  In the light emitting element array 60 configured as described above, by applying a current to the p-side electrode pad 74 and the n-side electrode pad 75, a pn junction of a predetermined light emitting region 65 can emit light. Thus, the light emitting region 65 that emits light is selected and turned on by a combination of the p-side electrode pad 74 and the n-side electrode pad 75 to which current is applied.

As described above, the conventional light emitting element array described above can reduce the number of electrodes and electrode pads connected to each light emitting region, the number of individual wires and common wires, and the total area occupied by them. Thus, an excellent effect that a large number of light emitting regions can be arranged with high density can be obtained.
No. 07-036754 JP 2001-07386 A

    However, since the light emitting element array of the above-described conventional example uses multi-layer wiring for the individual wiring and the common wiring, a short circuit is likely to occur between the wirings, and there is a possibility that the yield in manufacturing the light emitting element array may be reduced. In addition, since a current sufficient to light all the light emitting regions of the light emitting element array flows through the common wiring, the width and thickness are designed according to the current value, which affects the dimensions of the light emitting element array. In addition, due to the breakdown of the insulating film under the electrode in the wire bond, a short circuit with the semiconductor layer directly under the electrode may cause a problem such as unlighting or multiple lighting.

  Therefore, the present inventor has made various studies on the configuration of the light emitting element array so that the individual wiring and the common wiring do not become a multilayer wiring. As a result, the light emitting element array having a plurality of individual blocks divided into two light emitting regions. In this case, Zn, which is a p-type carrier, can be easily diffused. Therefore, a semiconductor layer that is insulated and provided on a semiconductor substrate is a p-type semiconductor layer on the substrate side and an n-type semiconductor layer on the surface side. When the provided p-type diffusion conducting layer is brought into electrical contact with the underlying p-type semiconductor layer and this portion is used as one of the wiring electrodes, the other electrode wiring is formed on the surface of the semiconductor layer via an insulating film. Since it can be formed as a single-layer metal wiring, it has been found that the individual wiring and the common wiring can be prevented from becoming a multilayer wiring, and the present invention has been completed.

  That is, an object of the present invention is to provide a light emitting element array having a plurality of individual blocks divided into at least two light emitting regions, in which the individual wiring and the common wiring are not multilayer wiring.

The object of the present invention can be achieved by the following configurations. That is, according to the first aspect of the present invention, the p-type semiconductor layer and the n-type semiconductor are formed on the semiconductor substrate in a state where the plurality of individual blocks divided for each of the two light emitting regions are insulated from the semiconductor substrate. Having a semiconductor layer in which the layers are sequentially epitaxially grown and an active layer is formed at the interface between the two,
For each individual block, one p-side common electrode is formed by a p-type diffusion conduction region that reaches the p-type semiconductor layer from the surface of the semiconductor layer, and 1: 1 in the n-type semiconductor layers of the two light emitting regions. A light emitting element array in which two connected individual wires are formed,
The light emitting element array further includes at least one other block electrically insulated from the individual block, and the other block is connected to one individual wiring of each individual block. and a first n-side common electrode and the first n-side common electrode is electrically insulated, and a second n-side common electrode to which the other individual wiring of each individual block is connected Have
The first and second n-side common electrodes are each formed of a first n-side common wiring using the semiconductor layer of the other block and a metal wiring on the surface of the semiconductor layer via an insulating film. And a second n-side common wiring .

  In the light emitting element array of this mode, the p-side common electrode formed for each individual block communicates with the lower p-type semiconductor layer through the p-type diffusion conduction layer, and the p-type semiconductor layer has two light emitting elements. Since the entire p-type semiconductor layer can be used as a wiring because it is electrically connected to the region, the wiring resistance can be kept low and a considerably large current can flow. Further, since the p-type semiconductor layer is not exposed on the surface of the semiconductor layer except for the p-side common electrode portion, there is no multilayer wiring relationship with the individual wiring connected to the n-type semiconductor layer in the light emitting region. The degree of freedom when providing individual wiring is increased.

  In the light emitting element array having such a configuration, one individual wiring for each individual block is connected to one n-side common electrode formed in the other block, and the individual block is similarly connected to the other n-side common electrode. The other individual wiring is connected to each other, and the individual block and this other block are electrically insulated, so that the individual wiring does not become a multi-layer wiring relationship with the common wiring, and the short circuit between the wirings. In addition, the yield in manufacturing the light emitting element array is improved. In addition, the number of n-side common electrodes can be reduced to at least one, and a light-emitting region that can emit light arbitrarily can be selected by a combination of the n-side common electrode and the p-side common electrode. The area occupied by the portion can be reduced.

  In the light emitting element array having such a configuration, the first n-side common wiring is formed in the semiconductor layer, and the second n-side common wiring is formed by metal wiring on the surface of the semiconductor layer via the insulating layer. Therefore, the wiring width of both wirings can be formed as wide as possible, so that the wiring resistance can be kept low, a considerable current can be passed, and even if there is only one other block. The light emitting areas can be connected to emit light.

  In the light-emitting element array according to this aspect, the another block is a semiconductor layer in which a p-type semiconductor layer and an n-type semiconductor layer are sequentially epitaxially grown on at least a semiconductor substrate while being electrically insulated from the semiconductor substrate. The first common wiring is preferably formed by a p-type diffusion wiring region reaching the p-type semiconductor layer from the surface of the semiconductor layer and the p-type semiconductor layer. With such a configuration, since the semiconductor layer of another block can be formed simultaneously with the formation of the semiconductor layer of the individual block, the manufacturing process is simplified.

  Furthermore, the light emitting element array according to this aspect is connected to the respective surfaces of the p-side common electrode, the first n-side common wiring, and the second n-side common electrode either directly or via an insulating film. The electrode pad is preferably formed. In such a configuration, the lower portion of the p-side common electrode pad is a p-type diffusion conduction region, the lower portion of the first n-side common electrode pad is a p-type diffusion wiring region, and further the second n-side common electrode pad. Since the lower part of the electrode pad is an n-type semiconductor layer, even if a dielectric breakdown of the insulating layer occurs during wire bonding to each electrode pad, there is no short-circuit relationship. However, short-circuiting hardly occurs and the assembly yield of the optical print head is improved.

  As described above, according to the present invention, the individual wiring and the common wiring as in the conventional light emitting element array are not multi-layered wiring, so there is no risk of short circuit between the wirings, and the manufacturing yield of the light emitting element array is reduced. In addition, since a short circuit does not occur even when the insulating film under the electrode breaks in the wire bond, the print head assembly yield can be improved.

    Hereinafter, specific examples of the present invention will be described with reference to the drawings.

  1 to 3 are diagrams for explaining the manufacturing process of the light-emitting element array according to the present invention in order. FIGS. 1 (a) to 3 (a) are plan views and FIGS. 1 (b) to 3 (b), respectively. 3 (b) is a cross-sectional view of one light emitting element portion taken along line AA in FIGS. 1 (a) to 3 (a), and FIGS. 1 (c) to 3 (c) are FIG. It is sectional drawing of the one light emitting element part along the BB line of a)-Fig.3 (a).

  In the light emitting element array 10, as shown in the plan view of FIG. 3A, the light emitting element portions form two individual blocks, and the four blocks form one individual group. In this example, two groups are arranged in series.

  This light emitting element array is manufactured by the following process. First, as is apparent from the cross-sectional view of one light emitting element portion in FIG. 1B, for example, a p-type semiconductor layer 12 made of a p-type AlGaAs compound semiconductor and an n-type AlGaAs compound are sequentially formed on a semiconductor substrate 11 made of a GaAs compound semiconductor. An n-type semiconductor layer 13 made of a semiconductor is epitaxially grown, a pn junction layer 14 serving as an active layer is formed at the interface between the two layers, and an n-type GaAs compound semiconductor layer 15 is further epitaxially grown on the surface of the n-type semiconductor layer 13. The total film thickness of these epitaxial growth layers is, for example, 5 μm.

In this case, the GaAs semiconductor substrate 11 and the p-type semiconductor layer 12 are electrically insulated. As a means for this electrical insulation,
(1) A high-resistance GaAs semiconductor substrate or an n-type GaAs semiconductor substrate is used as the GaAs semiconductor substrate 11, or
(2) An insulating layer or an n-type semiconductor layer is disposed between the GaAs semiconductor substrate 11 and the p-type semiconductor layer 12;
This can be implemented as appropriate.

  Next, a diffusion mask is formed on the surface of the n-type GaAs compound semiconductor layer 15, the diffusion separation portion and the diffusion conduction portion are opened by a photolithography method and an etching method, and Zn is formed so that the pattern shown in FIG. 1 is obtained. Diffusion or ion implantation is performed to a thickness of about 3 μm until reaching the p-type semiconductor layer 12 to form a p-type element isolation region 17 around the light-emitting region 16. The electrode 18 and the n1 side common electrode wiring 19 and the n1 side common electrode 20 are formed by the p-type diffusion wiring region, respectively.

  Then, the p-side common electrode 18 and the p-type semiconductor layer 12 are electrically connected, and the n1-side common electrode wiring 19 and the n1-side common electrode 20 are also electrically connected to the p-type semiconductor layer 12. .

  In this case, the light emitting regions 16 are arranged in a line or alternately arranged in a plurality of rows, the p-side common electrode 18 is formed for each of the two light emitting regions, and the n1 side common electrode is formed. The wiring 19 and the n1-side common electrode 20 are provided at least one, preferably one for each of the two light emitting regions. FIG. 1 shows an example in which an n1 side common electrode wiring 19 and an n1 side common electrode 20 are provided one by one for two light emitting regions.

Then mesa etching down to the part where the sign 21 is shown in FIGS. 2 (a) in the semiconductor substrate 11, the light emitting region is two pair individual blocks 22 _1, 22 _2, a ... 22 ₈ In addition, the individual blocks are mesa-separated so as to form a group of four individual groups 23 ₁ and 23 ₂ and further separate blocks 24 ₁ and 24 ₂ . Then, the individual blocks 22 ₁ , 22 ₂ ,... 22 ₈ , the individual groups 23 ₁ , 23 ₂ and the other blocks 24 ₁ , 24 ₂ are electrically insulated from each other, resulting in the p-side common electrode. 18 is also electrically insulated from the n1 side common electrode wiring 19 and the n1 side common electrode 20.

Here, _two blocks 24 ₁ and 24 ₂ provided with the n1 side common electrode wiring 19 and the n1 side common electrode 20 are provided in a state of being electrically insulated from each other. It may be provided, or only one may be provided. In addition, although the individual groups 23 ₁ and 23 ₂ are formed by a set of four individual blocks, the number of the individual groups is not limited to this and may be more or less.

  Next, after the insulating film 25 is provided on the entire surface, the two contact portions 26 of the light emitting region 16, the contact portion 27 of the n1 side individual wiring 29, the contact portion of the p side common electrode 18, and the first n side common electrode 20. The insulating film 25 covering the contact portion is removed by etching and opened, and the p-side common electrode pad 28, the n1-side individual wiring 29, and the n1-side common electrode pad are lifted off as shown in FIG. 30, n2 side individual wiring 31, n2 side common wiring 32, and n2 side common electrode pad 33 are formed.

  These wirings or electrode pads can be appropriately used as long as they can be ohmic-connected to the underlying semiconductor. For example, Ti 200 Å / Au 50 Å / Ni / Ge / Au 1.2 μm is sequentially stacked as the n-side electrode material, and Ti 200 Å / Au 1.2 μm is sequentially stacked as the p-side electrode material. Note that the n-side electrode and the wiring are formed by forming the n1-side individual wiring 29, the n2-side individual wiring 31, the n2-side common wiring 32, the n1-side common electrode pad 30, and the n2-side common electrode pad 33 at one time, and the light emitting region. Only the individual electrodes that are ohmic to the 16 contact portions 26 may be formed of the n-side electrode material, and the other portions may be formed simultaneously with the common p-side electrode pad 28.

  Next, in order to make ohmic contact between each electrode and the semiconductor, a sintering process (heat treatment) is performed, and if necessary, the back side of the semiconductor substrate 11 is polished, whereby the light emitting element array as shown in FIG. 10 is completed.

According to the light emitting element array 10 obtained in this manner, the individual blocks 22 _1, 22 _2, ... 22 ₈ each p-side common electrode 18 formed on the lower layer of the p-type p-type diffusion conductive layer Since the p-type semiconductor layer 12 communicates with the semiconductor layer 12 and is electrically connected to the two light emitting regions 16 for each individual block, the entire p-type semiconductor layer can be used as a wiring. As a result, the wiring resistance can be kept low and a considerably large current can flow. Further, since the p-type semiconductor layer 12 is not exposed on the surface except for the p-side common electrode 18, the individual wirings 29 and 31 connected to the n-type semiconductor layer of the light emitting region 16 are connected to the p-type semiconductor layer 12 and the multilayer wiring. Since there is no relationship, there is no possibility of short-circuiting between the wirings due to the multi-layered wiring of the individual wiring and the common wiring as in the conventional example.

  Further, the lower portion of the p-side common electrode pad 28 is a p-type diffusion conduction region, the lower portion of the n1-side common electrode pad 30 is a p-type diffusion wiring region, and the lower portion of the n2-side common electrode pad 33 is an n-type semiconductor layer. Therefore, even if dielectric breakdown of the insulating layer occurs during wire bonding to each electrode pad, there is no short-circuit relationship.

  In this embodiment, the light emitting areas 16 are arranged so as to be linearly arranged in a line. However, the light emitting areas 16 can be alternately arranged in order to obtain a higher density light emitting element array. . In this embodiment, an example in which a GaAs semiconductor substrate is used as the insulating substrate 11 is shown, but a Si substrate can also be used. Further, although an embodiment using an AlGaAs compound semiconductor as a light emitting element has been described, it is obvious to those skilled in the art that the present invention is not limited to this and can be applied to a well-known GaP-based, AlGaInP-based, GaAsP-based compound semiconductor, and the like. Will. Useful as a light source for LED print heads.

It is a figure explaining the state at the time of forming the element isolation area | region, p type diffused conduction area | region, and p type diffused wiring area | region in the light emitting element array manufacturing process of this invention, Fig.1 (a) is a top view, FIG.1 (b) ) Is a cross-sectional view taken along line AA in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line BB in FIG. It is a figure explaining the state at the time of forming the mesa isolation | separation part in the light emitting element array manufacturing process of this invention, Fig.2 (a) is a top view, FIG.2 (b) is the AA line of Fig.2 (a). FIG. 2C is a cross-sectional view taken along the line BB of FIG. 2A. 3A and 3B are diagrams illustrating a completed light-emitting element array according to the present invention, in which FIG. 3A is a plan view, FIG. 3B is a cross-sectional view taken along the line AA in FIG. ) Is a cross-sectional view taken along line BB in FIG. FIG. 4 is a plan view of a main part in a state where an insulating layer of a conventional light emitting element array is removed. FIG. 5 is a cross-sectional view taken along line AA in FIG. FIG. 6 is a plan view showing an outline of another conventional light emitting element array. 7 is a partial plan view (FIG. 6A) and a partial cross-sectional view (FIG. 6B) around the element isolation region of the light-emitting element array shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Light emitting element array 11 Semiconductor substrate 12 P-type semiconductor layer 13 N-type semiconductor layer 14 Active layer 16 Light emitting area 17 Element isolation area 18 P side common electrode 19 n1 side common electrode wiring 20 n1 side common electrodes 22 ₁ , 22 ₂ ,. .. 22 ₈ Individual blocks 23 ₁ , 23 ₂ Individual groups 24 ₁ , 24 ₂ Separate blocks 26, 27 Contact part 28 p side electrode pad 29 n1 side individual wiring 30 n1 side electrode pad 31 n2 side individual wiring 32 n2 side common Wiring 33 n2 side electrode pad

Claims (3)

A plurality of individual blocks divided into two light-emitting regions are formed by sequentially epitaxially growing a p-type semiconductor layer and an n-type semiconductor layer on the semiconductor substrate while being insulated from the semiconductor substrate, and an active layer is formed at the interface between the two. Having a formed semiconductor layer;
For each individual block, one p-side common electrode is formed by a p-type diffusion conduction region that reaches the p-type semiconductor layer from the surface of the semiconductor layer, and 1: 1 in the n-type semiconductor layers of the two light emitting regions. A light emitting element array in which two connected individual wires are formed,
The light emitting element array further includes at least one other block electrically insulated from the individual block, and the other block is connected to one individual wiring of each individual block. and a first n-side common electrode and the first n-side common electrode is electrically insulated, and a second n-side common electrode to which the other individual wiring of each individual block is connected Have
The first and second n-side common electrodes are each formed of a first n-side common wiring using the semiconductor layer of the other block and a metal wiring on the surface of the semiconductor layer via an insulating film. And a second n-side common wiring .   The another block has a semiconductor layer formed by sequentially epitaxially growing a p-type semiconductor layer and an n-type semiconductor layer on at least a semiconductor substrate while being electrically insulated from the semiconductor substrate. The light emitting element array according to claim 1, wherein the wiring is formed by a p-type diffusion wiring region reaching the p-type semiconductor layer from the surface of the semiconductor layer and the p-type semiconductor layer.   Electrode pads for external connection are formed on the respective surfaces of the p-side common electrode, the first n-side common wiring, and the second n-side common electrode either directly or through an insulating film. The light-emitting element array according to claim 2.

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