JP2002043622A - Light emitting element array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce variation of the quantity of light in a chip of a light emitting element array and to reduce the difference between the quantity of light from a light emitting part located at the end of the chip and the quantity of light from the light emitting part located at other parts. SOLUTION: A plurality of second conductivity type semiconductor regions of specified depth are formed as a plurality of light emitting parts 21 in a first conductivity type semiconductor layer 12 and members 32, 68, 69 for regulating the quantity of light emitted from the light emitting parts 21 are provided contiguously to one or more light emitting parts 21. At least one of the regulating members is formed of a film 68, 69 for shielding light generated from the surface of the first conductivity type semiconductor layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array of light-emitting elements, and more particularly, to an array having a structure in which the amount of light emitted from all light-emitting elements is changed so as to be the same.

[0002]

2. Description of the Related Art A light emitting element array has a plurality of light emitting elements arranged linearly, and a light emitting element array using light emitting diodes (hereinafter, referred to as LEDs) as light emitting elements is called an LED array.

FIG. 24 shows a conventional LED described in “Design of LED Printer”, Trikeps, page 63.
FIG. 24A is a diagram showing the structure of the array, FIG. 24A is a sectional view, and FIG. 24B is a top view. The LED array shown in FIG. 24 is an n-type GaAs substrate on an n-type GaAs substrate 71.
Light emitting portions 73 are formed in an array by selective diffusion of a p-type impurity such as Zn in the s _0.6 P _0.4 layer 72, and an Al electrode 74 electrically connected to each light emitting portion 73 is n-type with an insulating layer 76 interposed therebetween. An Au-Ge-Ni electrode 75 formed on the GaAs _0.6 P _0.4 layer 72 and connected to the wire bond electrode part 82 and electrically connected to the n-type GaAs substrate 71 is formed on the lower part. The LED array thus formed is
It is used as a light source for electrophotographic optical printers.

In recent years, the present inventors have proposed a multilayer wiring type LED array having a multilayer wiring for the purpose of reducing the number of electrode pads as an LED array. In the multilayer wiring type LED array, an individual wiring connected to each light emitting unit and a common wiring connected to the p-side electrode pad are separated by an interlayer insulating film, and extend in directions substantially perpendicular to each other. A semiconductor layer forming a portion is divided into a plurality of blocks which are separated (isolated) from each other.

A multilayer wiring type LED array can be manufactured, for example, by the following method. First, an n-type semiconductor layer is formed on a high resistance substrate. Next, the semiconductor layer is separated into a plurality of blocks by forming element isolation regions. Next, a p-type impurity is selectively diffused through a diffusion mask to form a plurality of p-side semiconductor regions for each block.
That is, a light emitting section is formed. Next, one-to-one for a plurality of light emitting units
To form a plurality of individual p-side electrodes connected to each other and a p-side electrode pad connected to an individual wiring selected one by one for each block. Next, a part of the diffusion mask is peeled off, and an n-side electrode pad connected one-to-one to the n-type semiconductor layer of each block is formed. Next, an interlayer insulating film is formed on the individual wiring. Next, an opening for exposing a predetermined position of each individual wiring is formed in the interlayer insulating film. Next, on the interlayer insulating film, a plurality of common wires connected to the individual wires selected one by one for each block are formed over the plurality of blocks.

[0006]

The high definition of the optical printer is strongly desired.
It is necessary to increase the density of the D array. But,
When the interval between the light emitting units in the LED array is reduced in order to increase the density, the interval between the light emitting unit located at the end of the LED array and the chip end is reduced, and the light emitting unit located at the end of the array is reduced. The amount of effective light emitted from the chip (the amount of light emitted from the chip surface in a substantially vertical direction) is reduced. this is,
This is because light reaching the chip end face before reaching the chip surface is not effective light out of the light emitted from the light emitting portion with a slight inclination.

FIG. 25 is a diagram for explaining the problems of the LED array in the conventional example, in which electrodes, wiring, and the like are omitted. As shown in FIG. 25, when the chip end (dicing position) is changed from 56a to 56b, a region where light is emitted from the light emitting unit 21 at the chip end is a region corresponding to the difference in distance between 56a and 56b. And the light intensity radiated from the light emitting portion 21 at the chip end is reduced. Hereinafter, this point will be described in more detail.

FIG. 26 is a cross-sectional view of a conventional array, in which the same reference numerals as in FIG. 24 are assigned to the semiconductor layer 72, the light emitting section 73, and the insulating layer 76. A curve 70 indicates a light intensity distribution indicating the amount of light generated from each light emitting unit 73 and the surrounding surface. If the distance E from the outermost (closer to the end of the chip) light emitting portion 73 to the end of the chip is sufficiently large, the light intensity distributions 70 of all the light emitting portions 73 have the same shape as shown in the figure. As the density of the array increases, the distance E is shortened, and the light intensity distribution of the light emitting section 73 closest to the chip end is cut off as shown in FIG. That is, the portion 79 shown by hatching in FIG. 28 is removed. Therefore, the amount of light from the two (outermost) light emitting units 73 at both ends of the array is smaller than the amount of light from the light emitting units 73 inside the array.

Further, in order to further reduce the power consumption in the current multilayer wiring type LED array, it is necessary to lower the value of the forward voltage of the device characteristics. As one of the methods, there is a method of forming an n-side electrode close to a light emitting portion (p-type impurity diffusion region). That is, the distance between the n-side electrode and the light emitting section is reduced so that the influence of the resistance component of the substrate material itself is reduced as much as possible, and the influence of the voltage drop of the substrate itself is reduced.

Further, in order to further reduce the cost in the multilayer wiring type LED array, it is necessary to reduce the chip size. As one of the methods, there is a method of extracting an electrode pad for wire bonding from one side of a chip. Also in such a multilayer wiring type LED array, if the light emitting portion is further densified, the light intensity from the light emitting portion adjacent to the end of the n chip is reduced, so that a light amount variation occurs.

In view of the above, an object of the present invention is to reduce the variation in the amount of light in a chip of a light emitting element array.

Another object of the present invention is to reduce the difference between the amount of light from the light emitting unit located at the end of the chip and the amount of light from the light emitting unit located at another part.

[0013]

According to a first aspect of the present invention, there is provided a light emitting element array, wherein a plurality of second conductive type semiconductor regions having a predetermined depth are formed as a plurality of light emitting portions in a first conductive type semiconductor layer. An adjusting unit is provided adjacent to the light emitting unit and adjusts an amount of light emitted from the light emitting unit, and at least one of the adjusting units is generated from a surface of the first conductive semiconductor layer. It is formed of a light shielding film that blocks light.

According to a second aspect of the present invention, in the light emitting element array, the adjusting section is not in contact with any of the light emitting sections.

According to a third aspect of the present invention, in the light-emitting element array, the light-shielding film is disposed between two light-emitting portions adjacent to each other.

According to a fourth aspect of the present invention, in the light emitting element array, the light shielding film is electrically separated from other members.

According to a fifth aspect of the present invention, in the light-emitting element array, the light-shielding film is formed of an electrode lead-out line connected to the second conductivity type semiconductor region.

According to a sixth aspect of the present invention, in the light emitting element array, the light shielding film is constituted by a part of an electrode connected to the second conductive type semiconductor region.

According to a seventh aspect of the present invention, in the light emitting element array, at least one of the light quantity adjusting sections is formed of a light quantity adjusting groove or an element isolation region formed in the first conductivity type semiconductor layer. I do.

[0020] The light emitting element array according to the present invention is characterized in that the light amount adjusting section is formed only on one side of each of the light emitting sections.

According to a ninth aspect of the present invention, in the light emitting element array, the light amount adjusting section is arranged such that a light emitting section closest to one end of the chip in a row of the light emitting sections included in the light emitting element array has a direction in the column direction. It is not formed on either side, and among the odd-numbered light-emitting portions counted from the one end of the chip, those other than those closest to the one end, the one end of the chip The light amount adjusting portion is formed on the side of the end of the chip, and for an even-numbered light emitting portion counted from the one end of the chip, on the side opposite to the one end of the chip. The light amount adjusting section is formed.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. A case where the first conductivity type is n-type and the second conductivity type is p-type will be described with respect to each of the following embodiments, but the first conductivity type may be p-type and the second conductivity type may be n-type. . In each embodiment, a case where an LED array is used as a light emitting element array will be described. However, the light emitting element array is not limited to this, and another element such as a light emitting laser can be used.

First Embodiment A first embodiment is an LED having a multilayer wiring matrix.
An array. 1 to 3 show the structure of a multilayer wiring type LED array according to the first embodiment. FIG. 1 shows L
2 shows the entire ED array, FIG. 2 is an enlarged cross-sectional view of a region A in FIG. 1, and FIGS. 3 (a) and 3 (b) show a region B in FIG.
And the relationship between each area and the light intensity.

The multilayer wiring type LED array shown in FIGS. 1 to 3 has a high resistance substrate 13, a first conductivity type semiconductor layer 12 formed on the high resistance substrate 13, and a first conductivity type semiconductor layer 1.
2, the first conductive type semiconductor layer 12 is electrically separated by element isolation grooves 32 forming an element isolation region to form a plurality of blocks BL.

A predetermined region in the first conductivity type semiconductor layer 12 reaches a certain depth in the first conductivity type semiconductor layer 12,
The light emitting section 21 is formed by a second conductivity type semiconductor region forming a pn junction with the first conductivity type semiconductor layer 12. The light emitting units 21 are aligned and arranged at regular intervals so as to form a row extending in the longitudinal direction of the chip.

In the example shown in FIG. 1, for simplicity, the array has four blocks, and each block has four light emitting portions 21.
Are shown. Normally, the light emitting unit 2
The number of 1s and blocks BL is much larger.

The element isolation groove 32 penetrates through the diffusion mask 22 and the first conductivity type semiconductor layer 12 and reaches the high resistance substrate 13. (Note that the separation groove 32 may penetrate a part of the high-resistance substrate 13 as well.)

A p-side electrode 26 is formed on each light-emitting portion 21, a lead-out line 61 and a p-side electrode pad 28 are formed integrally with the p-side electrode 26, and one n-side electrode 67 is provided for each block. Is formed. Further, an n-side electrode 67 is formed in common for all the light emitting units 21 of each block BL, and a lead-out wiring 68 and an n-side electrode pad 29 are formed integrally with the n-side electrode 67. Further, the same number of common wirings 62 as the number of light-emitting portions 21 in each block are extended in the longitudinal direction of the chip, one p-side electrode pad 28 is formed for each common wiring 62, and each light-emitting portion 21 is connected to the p-side. A common wiring 62 corresponding via the electrode 26 and the p-side electrode lead-out wiring 61
Are connected by a contact portion 65.

The p-side electrode 26 and the p-side electrode pad 28
Although the p-side electrode lead-out wiring 61 is formed integrally, only the p-side electrode pad 28 may be formed separately. The n-side electrode 67 and the n-side electrode pad 2
9 and the n-side electrode lead-out wiring 62 are formed integrally, but only the n-side electrode pad 29 may be formed separately.

The p-side electrode lead-out wiring 68 and the light shielding film 69
Are formed in the first wiring layer together with the p-side electrode 26, the p-side electrode lead-out wiring 61 and the p-side electrode bonding pad 68. On the other hand, the common wiring 62 is formed in the second wiring layer. Between the first wiring layer and the second wiring layer, for example, an interlayer insulating film 63 made of polyimide is formed. Openings are provided in the interlayer insulating film 63 at the portion where the light emitting portion 21 is formed, the portion where the p-side electrode pad 28 and the n-side electrode pad 29 are formed, and the contact portion 65.

The p-side electrode 26, the p-side electrode lead-out wiring 61,
The n-side electrode lead wire 68 and the light shielding film 69 are made of an opaque conductive material, for example, gold. P-side electrode bonding pad 28 and n-side electrode bonding pad 29
Can also be formed of gold.

The diffusion mask 22 is formed of the first conductive type semiconductor layer 1.
2, light-emitting portion 21, element isolation region 32, n-side electrode 2
6 is formed so as to cover an area where no 6 is formed.

Further, between the adjacent light emitting portions 21,
A light amount adjusting portion made of a light shielding film 69, an n-side electrode lead-out wiring 68, and an element isolation groove 32 are formed so as not to come into contact with each light emitting portion 21.

In the illustrated example, an n-side electrode lead-out line 68 passes between two inner light emitting portions 21 of each of the four light emitting portions 21 and is connected to an end of a block adjacent to each other. An element isolation groove 32 is provided between the located light emitting units 21, and a light shielding film 69 is provided between the other light emitting units 21. Neither the light-shielding film 69 nor the n-side electrode lead-out line 68 (and, of course, the element isolation groove 32) is provided between the light emitting portion 21 located at the end of the chip and the end of the chip. The light-shielding film 69, the n-side electrode lead-out wiring 68, and the element isolation groove 32 have a light amount adjusting function. In the illustrated embodiment, the light-shielding film 69 is not connected to any of the electrodes.
Since it has the same function as that of No. 9, it can be said that it also serves as a light shielding film. In the claims, it should be understood that the light-shielding film includes one having another role such as the n-side electrode lead-out line 68.

In operation, the LED array has a corresponding p
When a forward voltage is applied to the side electrode 26 and the n-side electrode 67, each light emitting unit 21 emits light by carrier recombination. The amount of light emitted from the light emitting unit 21 at the end of the array decreases because it is close to the end of the chip. However, in the above configuration, the amount of light from the other light emitting units 21 is reduced by substantially the same amount by the light shielding film 69, the n-side electrode lead-out wiring 68, and the element isolation groove 32, and the light emission amounts of all the light emitting units 21 in the array are reduced. Are approximately the same.

As described with reference to FIGS. 26, 27 and 28, in a conventional LED array having no light amount adjusting means, when the density of the array increases, the light emitting portion 73 closest to the end of the chip starts to emit light. The distance E to the end of the chip becomes shorter, and the light intensity distribution of the light emitting unit 73 closest to the chip end is cut off as shown in FIG. Is smaller than the amount of light from the light emitting section 21 inside the array. This problem has been solved in the first embodiment of the present invention as follows.

FIG. 3A is an enlarged plan view of the region B in FIG. 1 (however, the interlayer insulating film 63 is omitted). FIG.
(B) shows the corresponding light intensity distribution 77.

Light shielding film 69 and n-side electrode lead-out wiring 68
(Reflects light into the chip), and element isolation grooves 32
The light intensity distribution of each light emitting unit 21 is cut off on both sides (for causing internal reflection and column reflection),
Thereby, the effective light emission amount from each light emitting unit 21 is reduced. This is because the light emitted from the light emitting section 21 with a slight inclination hits the light shielding film 69, the n-side electrode lead-out wiring 68, and the element isolation groove 32 before reaching the surface of the chip.

The dimensions of the light-shielding film 69, the n-side electrode lead-out wiring 68, and the element isolation groove 32 are set so that the amount of light emitted from all the light-emitting portions 21 is substantially the same. It is determined so that the difference in the amount of light emission from the other light emitting units 21 is small.

Incidentally, in order to prevent an electric short circuit, the light shielding film 69 is formed.
In addition, the width of the n-side electrode lead-out wiring 68 must be smaller than the width of the space between the light emitting units 21.

FIGS. 4 to 14 are views showing a manufacturing process of the multilayer wiring type LED array according to the first embodiment, FIGS. 4 to 9 are sectional views, and FIGS.
4 is a top view.

As shown in FIG. 4, a first conductive type semiconductor layer 12 is formed on a high resistance substrate 13 and the first conductive type semiconductor layer 1 is formed.
An opening 51 is formed in a region where a light emitting unit is to be formed by forming a diffusion mask 22 on the second mask 2. As the high resistance substrate 13, for example, a semi-insulating GaAs substrate is used, and the first conductivity type semiconductor layer 12 is used.
For example, n-type AlGaAs epitaxially grown
An s layer can be used. Further, as the diffusion mask 22, for example, a SiN film can be used. The SiN film can be formed by, for example, a CVD method, and the opening 51 in the light emitting portion formation scheduled region can be formed by, for example, a photolithography method and an etching method.

Next, as shown in FIG. 5, a diffusion source film 23 is formed on a diffusion mask including a region where a light emitting section is to be formed. As the diffusion source film 23, for example, a ZnO-SiO2 film can be used, and the ZnO-SiO2 film can be formed by, for example, a sputtering method.

Next, as shown in FIG. 6, an annealing cap 24 is formed on the diffusion source film 23. As the annealing cap 24, for example, an AlN film can be used.
The N film can be formed by, for example, a sputtering method.

Next, as shown in FIG. 7, annealing for forming a diffusion region 55 of the second conductivity type impurity in the first conductivity type semiconductor layer 12 by selective diffusion is performed. As the second conductivity type impurity, for example, Zn can be used.
By performing annealing at 50 ° C. for about 3 hours, the diffusion region 55 can be formed in the region where the light emitting section is to be formed. The formed diffusion region 55 becomes the light emitting portion 21 and has a depth of about 1 μm, for example.

Next, as shown in FIG. 8, the annealing cap 24 and the diffusion source film 23 are peeled off. The peeling of the annealing cap 24 and the diffusion source film 23 can be performed by selective etching.

Next, as shown in FIG. 9, element isolation grooves 32 are formed between the blocks. The element isolation groove 32 is formed by etching the first conductivity type semiconductor layer 1 using phosphoric acid peroxide as an etchant, for example.
2 can be selectively etched. The element isolation groove 32 constitutes an element isolation region, and extends from one side (an edge extending in the longitudinal direction) of the chip to the other side thereof, and has a depth of It is formed so as to reach the high resistance substrate 13.

Next, as shown in FIG. 10, in order to make contact between the n-side electrode lead-out wiring 68 to be formed later and the first conductive type semiconductor layer 12, the diffusion mask in the region 57 where the n-side electrode is to be formed is peeled off. I do. The peeling of the diffusion mask can be performed by a photolithography method and an etching method.

Next, as shown in FIG. 11, an n-side electrode 67 is formed by forming a pattern by, for example, a lift-off method. As the n-side electrode 67, for example, an Au alloy film can be used.

Next, as shown in FIG. 12, a pattern is formed by, for example, a lift-off method, and the integrated p-side electrode 2 is formed.
6, p-side electrode lead-out wiring 61, p-side electrode pad 28,
The integrated n-side electrode lead-out wiring 68 and the n-side electrode pad 29 are formed by film formation. As the integrated p-side electrode 26, the p-side electrode lead-out wiring 61, the n-side electrode lead-out wiring 68 and the n-side electrode pad 29 integrated with the p-side electrode pad 28, for example, an Au laminated film can be used. At this time, the p-side electrode pad 2
The patterns of the electrode lead-out wires 61 and 68 are determined so that the electrode pads 8 and the n-side electrode pad 29 are arranged symmetrically from the center of one cell.

The p-side electrode 26, the p-side electrode lead-out wiring 61, and the p-side electrode pad 2 described with reference to FIGS.
8 and n-side electrode lead-out wiring 68, n-side electrode pad 2
9 is not limited to this, and the diffusion mask 22 in the n-side electrode formation expected area 57 is
The n-side electrode lead-out wiring 68 and the n-side electrode pad 29 may be formed before the formation of the p-side electrode 26, the p-side electrode lead-out wiring 61, and the p-side electrode pad 29, for example. After the formation of the side electrode 26, the p-side electrode lead-out wiring 61, and the p-side electrode pad 28, the opening 57 in the region where the n-side electrode is to be formed may be formed.

As shown in FIG. 13, for example, the interlayer insulating film 6 is formed by photolithography and etching.
Form 3 At this time, a portion where the light emitting portion 21 is formed, a portion where the p-side electrode pad 28 is formed, a portion where the n-side electrode pad 29 is formed, and a contact portion (66) with a common wiring (62) formed later. ) Are formed so as to provide openings. As the interlayer insulating film 63, for example, polyimide can be used.

As shown in FIG. 14, a pattern is formed by, for example, a lift-off method, and the common wiring 62 is formed by film formation. The common wiring 62 extends in the chip longitudinal direction to connect predetermined p-side electrodes of each block to each other,
The contact portion 65 is connected to the p-side electrode lead wire 61.

As described above, between the adjacent light emitting portions 21, the light amount adjusting portion made of the light shielding film 69, the n-side electrode lead-out wiring 68, and the element isolation groove are formed so that the light intensity of the light emitting portion 21 at the chip end becomes the same. By forming 32, it is possible to reduce the effect of a decrease in the amount of light at the chip end, and to reduce the difference in the amount of light between the light emitting unit 21 at the chip end and the light emitting unit 21 in the chip.

Second Embodiment FIGS. 15 to 17 are views showing the structure of a multilayer wiring type LED array according to a second embodiment of the present invention. FIG. 15 shows the entire LED array. 16 is an enlarged sectional view of a region A in FIG.
(B) shows an enlarged view of the region B in FIG. 15 and the relationship between each region and the light intensity.

As shown in FIG. 15, in the second embodiment, an extension of the n-side electrode 67 is used in place of the light shielding film 69 of the first embodiment. The n-side electrode 67 is also n
Side electrode lead-out wiring 68 (shorter than in the first embodiment)
It also extends to be connected. In other respects, the second embodiment is the same as the first embodiment. As shown in FIG. 16, separation grooves 32 are used to separate blocks.

FIG. 16 is an enlarged view of a region B of FIG. 15, showing a part of the leftmost block with the interlayer insulating film 63 removed.
7A, an n-side electrode 67 and an n-side electrode lead-out line 68 are provided.
Is better shown. The n-side electrode 67 has an extension disposed between the light emitting units 21 adjacent to each other in the block. An extension of the n-side electrode 67 located between the inner light emitting portions 21 is connected to an n-side electrode lead-out line 68. The width and length of these extensions are determined so that the light intensity distribution 77 (FIG. 17B) of the light emitting portions 21 is cut off, and all the light emitting portions 21 emit the same amount of light.
In order to avoid a short circuit, the width of the extension of the n-side electrode lead-out wiring 68 and the n-side electrode 67 needs to be smaller than the distance between the light-emitting portions so as not to make contact with the light-emitting portions 21.

The second embodiment is manufactured in the same manner as the first embodiment. However, it is necessary to change the shape of the opening 57 formed in the diffusion mask 22, the shape of the n-side electrode 67, and the shape of the first wiring layer.

The second embodiment has the same effect as the first embodiment, and also has a shorter distance from the light emitting section 21 to the n-side electrode 67 through the first conductivity type semiconductor layer 12. Therefore, the effect of reducing the electric resistance is obtained. This is because the n-side electrode 67 surrounds each light emitting unit 21 on at least two sides.

Third Embodiment FIGS. 18 to 20 are views showing the structure of a multilayer wiring type LED array according to a third embodiment of the present invention. FIG. 18 shows the entire LED array. FIG. 19 is an enlarged sectional view of a region A in FIG.
(B) shows an enlarged view of the region B in FIG. 18 and the relationship between each region and the light intensity.

As shown in FIGS. 18 and 19, the third embodiment has the same configuration as the first embodiment. However, they differ in the following points. That is, the n-side electrode extraction wiring 68
Is out of the center of each block, and the light amount adjusting groove 31 is inserted at the empty center position.

These values are shown in the enlarged view of FIG.
This can be better understood from an enlarged view of the figure (with the interlayer insulating film 63 removed). The light amount adjusting groove 31 is provided in each block.
It is arranged between the two inner light emitting parts 21. The n-side electrode lead-out line 68 is arranged between the two light emitting units 21 near one side of the center. The light-shielding film 69 is disposed between the two light emitting units 21 from the other side of the center. In this way, the light amount adjusting groove 31 or the separation groove 32 is arranged between the light emitting units 21 that constitute every other light emitting unit 21, and the n-side electrode lead-out wiring 68 or the light shielding film 69 is
The light-emitting portions 21 (other than every other one) are disposed between the pairs.

Here, a modification of the third embodiment will be described. In an example of the modified example, the light amount adjusting unit is formed only on one side of each of the light emitting units. More specifically, the light amount adjustment unit is not formed on any side in the column direction of the light emitting unit closest to one end of the chip among the columns of the light emitting units included in the light emitting element array,

In the odd-numbered light emitting portions counted from the one end of the chip, those other than those closest to the one end are provided with the light amount at the one end side of the chip. An adjusting portion is formed, and the even-numbered light emitting portion counted from the one end of the chip has the light amount adjusting portion formed on a side opposite to the one end of the chip.

With this configuration, compared to the case where the light amount adjusting section is formed between all the light emitting sections, the effect of the decrease in the light amount at the chip end is reduced, and the light emitting amounts of all the light emitting sections are reduced. Adjustments can be made to be substantially the same, and furthermore, there is an effect that a decrease in the amount of light inside the chip can be suppressed to about ２.

The lengths of the light shielding film 69 and the light amount adjusting groove 31 are as follows.
The light intensity distribution 77 (FIG. 20B) can be determined according to the desired degree of cutting off. The light amount adjusting groove 31, the n-side electrode lead-out wiring 68, and the light shielding film 69 must all have sufficiently narrow widths to avoid contact with the light emitting section 21.

In the third embodiment, the same method as in the first embodiment can be manufactured. The light amount adjusting groove 31 is
It is formed in the same step as.

The third embodiment has substantially the same effect as the first embodiment. However, each light emitting unit 21 is adjacent to the n-side electrode lead-out wiring 68 or the light shielding film 69 on one side, and is adjacent to the light amount adjusting groove 31 or the separation groove 32 or the end of the chip on the other side. . Therefore, the surroundings of each light emitting unit 21 are substantially the same, and therefore, all the light emitting units 21
(The widths and lengths of the light amount adjusting groove 31 and the light shielding film 69, and the widths of the n-side electrode lead-out wiring 68 and the separating groove 32) for equalizing the amount of light from the light source. Becomes

As a modification of the third embodiment, the number of light emitting units 21 per block can be increased. However, the light-amount adjusting groove 31 or the separation groove 32 is located between every other pair of the light-emitting portions 21, and the n-side electrode lead-out wiring 68 and the light-shielding film 69 are used for other (other than the above-mentioned alternate light-emitting). It is necessary to be located between the pair of parts 21.

Fourth Embodiment FIGS. 21 to 23 are views showing the structure of a multilayer wiring type LED array according to a fourth embodiment of the present invention. FIG. 21 shows the entire LED array. 22 is an enlarged cross-sectional view of a region A in FIG.
(B) shows an enlarged view of the area B in FIG. 21 and the relationship between each area and the light intensity.

In FIGS. 21 and 22, the fourth embodiment has the same configuration as the first embodiment. However,
The light shielding film 69 does not exist.

As shown in FIG. 23A, each light emitting section 21
Is adjacent to the separation groove 32, the n-side electrode lead-out wiring 68 or the end of the chip on one side. There is no light amount changing element on the other side of the light emitting unit 21. Therefore, FIG.
As shown in (b), the light intensity distribution 78 of each light emitting unit 21
Is cut off on only one side. Thus, all the light emitting units 21 emit substantially the same amount of light.

The fourth embodiment is manufactured by the same method as that of the first embodiment. However, it is necessary to omit the light shielding film 69 from the pattern formed on the first wiring layer.

The fourth embodiment has substantially the same effect as the first embodiment. However, the amount of light emitted from each light emitting unit 21 increases. This is because the light intensity distribution 78 is cut off only on one side.

As described above, the present invention has been described as compensating for the decrease in the amount of light emission at the end of the array. However, in order to compensate for the difference in the amount of light emission due to other reasons in various other arrays. Also applicable to

The present invention can also be applied to devices other than arrays of light emitting elements used in electrophotographic printers.

Although several modifications have been described, other modifications will occur to those skilled in the art. For example, substrates, electrodes,
The material and composition of impurities and the like are not limited to those of the embodiments, and other materials can be selected.

[0078]

As described above, according to the first aspect of the present invention, the light emission amount can be adjusted by providing the light shielding film constituting the light amount adjustment unit adjacent to at least one light emitting unit. Variations in the amount of light emission can be eliminated.

According to the eighth aspect of the present invention, the reduction in the amount of light inside the chip and the reduction in the amount of light inside the chip can be reduced by about 1 in comparison with the case where a light amount adjustment section is formed between all the light emitting sections.
/ 2.

According to the ninth aspect of the present invention, it is possible to prevent the light amount of the light emitting portion closest to the chip end from being reduced and adjust the light emitting amounts of all the light emitting portions to be substantially the same.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a structure of an LED array according to a first embodiment.

FIG. 2 is an enlarged sectional view of a region A of FIG.

FIGS. 3A and 3B are an enlarged view of a region B in FIG. 1 and a diagram showing a relationship between each region and light intensity.

FIG. 4 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 5 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 6 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 7 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 8 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 9 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 10 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 11 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 12 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 13 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 14 is a diagram illustrating a manufacturing process of the LED array according to the first embodiment.

FIG. 15 is a diagram showing a structure of an LED array according to the second embodiment.

16 is an enlarged sectional view of a region A in FIG.

17A and 17B are an enlarged view of a region B in FIG. 15 and a diagram showing a relationship between each region and light intensity.

FIG. 18 is a diagram illustrating a structure of an LED array according to a third embodiment.

FIG. 19 is an enlarged sectional view of a region A in FIG. 18;

20A and 20B are an enlarged view of a region B in FIG. 18 and a diagram showing a relationship between each region and light intensity.

FIG. 21 is a diagram illustrating a structure of an LED array according to a fourth embodiment.

22 is an enlarged sectional view of a region A in FIG.

23A and 23B are an enlarged view of a region B in FIG. 21 and a diagram showing a relationship between each region and light intensity.

FIG. 24 is a diagram showing a structure of an LED array in a conventional example.

FIG. 25 is a diagram for explaining a problem of the LED array in the conventional example.

FIG. 26 is a diagram showing a light intensity distribution in a conventional structure.

FIG. 27 is a diagram showing a light intensity distribution in a conventional structure.

FIG. 28 is a diagram showing a light intensity distribution at a chip end in a conventional structure.

[Explanation of symbols]

12 first conductivity type semiconductor layer, 13 high resistance substrate, 2
1 light emitting portion, 22 diffusion mask, 23 diffusion source film,
24 Annealing cap, 26 p-side electrode, 27
n-side electrode, 28 p-side electrode pad, 29 n-side electrode pad, 31 light intensity adjustment groove, 32 element separation groove,
51 light emitting section formation planned area, 52 light quantity adjustment section formation planned area, 53 element isolation area formation planned area, 54 n
Area for forming side electrode, 55 Diffusion area for second conductivity type impurity, 56a, 56b Dicing position, 61p
Side electrode wiring, 62 common wiring, 63 interlayer insulating film,
65 contact part, 66 opening part, 71 n-type GaAs substrate, 72 n-type GaAs0.6P0.4 layer, 73
Light emitting unit, 74 Al electrode, 75 Au-Ge-N
i electrode, 76 insulating layer, 82 wire bond electrode part.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuhiko Ogihara One offshore digital imaging company at 550 Higashi-Asakawa-cho, Hachioji-shi, Tokyo (72) Inventor Hiroshi Hamano One-stockholder at 550 Higashi-Asakawa-cho, Hachioji-shi, Tokyo Digital Imaging Inc. (72) Inventor Masaharu Noboru 550 Higashi-Asakawacho, Hachioji-shi, Tokyo F-term (reference) 5F041 AA05 CA93 CA94 CB16 CB22 EE24 FF13

Claims (9)

[Claims] 1. A plurality of second conductivity type semiconductor regions having a predetermined depth are formed as a plurality of light emitting portions in a first conductivity type semiconductor layer, and are provided adjacent to one or more light emitting portions. A light-emitting element array having an adjustment unit for adjusting the amount of light emitted from the light-emitting unit, wherein at least one of the adjustment units is formed of a light-shielding film that blocks light generated from the surface of the first conductive semiconductor layer . 2. The light emitting device array according to claim 1, wherein the adjustment unit does not contact any of the light emitting units. 3. The light-emitting element array according to claim 1, wherein the light-shielding film is provided between two light-emitting portions adjacent to each other. 4. The light emitting element array according to claim 1, wherein the light shielding film is electrically separated from other members. 5. The light-emitting element array according to claim 1, wherein the light-shielding film is constituted by an electrode lead-out line connected to the second conductivity type semiconductor region. 6. The light emitting element array according to claim 1, wherein the light shielding film is constituted by a part of an electrode connected to the second conductivity type semiconductor region. 7. The light-emitting device according to claim 1, wherein at least one of the light-amount adjusting units is formed by a light-amount adjusting groove or an element isolation region formed in the first conductive semiconductor layer. Light emitting element array. 8. The light emitting element array according to claim 3, wherein the light amount adjusting section is formed only on one side of each of the light emitting sections. 9. The light amount adjusting section is formed on any side in the column direction for a light emitting section closest to one end of a chip in a row of light emitting sections included in the light emitting element array. Of the odd-numbered light-emitting portions counting from the one end of the chip, those other than those closest to the one end, the light-emitting portions on the side of the one end of the chip A light amount adjusting unit is formed, and for even numbered light emitting units counted from the one end of the chip, the light amount adjusting unit is formed on a side opposite to the one end of the chip. The light-emitting element array according to claim 8, wherein: