JPH1140842A - Light-emitting element array, manufacture thereof and printer head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a light emitting element the array of which is small in width. SOLUTION: P-type semiconductor regions 13 are formed on an n-type semiconductor block 11, arranged on a high-resistance semiconductor substrate 2. The prescribed p-type region 13 formed on the n-type semiconductor block 11 is connected with matrix wirings 14 and 4. LEDs, each composed of the p-type region 13 and the n-type block 11 are connected in a matrix to p-side pad electrodes 5 and n-side pad electrodes 55, respectively. The p-side pad electrodes 5 are connected to the prescribed p-side regions 13 via a p-side pad wiring 6 and the matrix wirings 14 and 4, and the n-side pad electrodes 55 are connected to the n-type block 11 via an n-side pad wiring 54 and an n-side contact electrode 52. The p-side pad electrodes 5 and the n-side pad electrodes 55 are formed in layers on the matrix wirings 14 and 4 via interlayered insulating film 12c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting element array in which a plurality of light emitting elements are formed on the same semiconductor substrate, a method for manufacturing the same, and a printer head formed using the light emitting element array.

[0002]

2. Description of the Related Art In an electrophotographic printer, as a printer head used as a light source for exposing a photosensitive member, there is a printer head using a light emitting element array in which a large number of light emitting elements are arranged in one line. A light emitting element array in which light emitting diodes (LEDs) are arranged in one row is called an LED array, and a print head using the LED array is called an LED printer head. The LED printer head consists of an LED array and an LED
And a drive circuit for individually driving the components on a mounting substrate.

In an LED array, by reducing the number of pad electrodes for connecting to a driving circuit, the density of LEDs is increased (for example, 1200 [DPI (dot / inc)).
h)]), there is a matrix type LED array. The matrix-type LED array divides a semiconductor substrate into M semiconductor blocks, forms N LEDs on each block, and forms an n-side pad electrode connected to the cathodes of the N LEDs. Also, N or more p-side pad electrodes are formed on M blocks, and the anodes of the N LED elements in the same block are connected to different p-side pad electrodes by matrix wiring. That is, the matrix-type LED array reduces the number of pad electrodes of the entire LED array by connecting M × N LEDs in a matrix to the n-side pad electrode and the p-side pad electrode, and provides a wire connection with the drive circuit. This facilitates bonding.

In order to optimize the structure of the above matrix type LED array, the present inventors have further proposed an LED array as shown in FIGS. 21 and 22, (a) is a top view and (b) is (a)
It is sectional drawing between AA 'of FIG. FIG. 23 is a sectional view showing the structure of an LED printer head using the LED array shown in FIG. 21, and FIG. 24 is a sectional view showing the structure of an LED printer head using the LED array shown in FIG.

In the LED arrays shown in FIGS. 21 and 22, an n-side pad electrode 115 is connected to an n-type semiconductor block 111.
By directly connecting (contacting) the semiconductor device, the manufacturing process is simplified and the reliability of the n-side pad electrode 115 is improved. In the LED array 121 shown in FIG. 22, the n-side pad electrode 115 is formed on the same side as the p-side pad electrode 105 with respect to the p-type semiconductor region 113, and is bonded to the p-side pad electrode 105 as shown in FIG. The wire 204a and the wire 204b bonded to the n-side pad electrode 115 can be pulled out from one side of the LED array, thereby making the printer head compact.

The LED array shown in FIG. 21 and the LED array shown in FIG. 22 have a plurality of n-type semiconductor blocks 111 separated from each other by a high-resistance semiconductor substrate 102 and an isolation groove 103, and a plurality of n-type semiconductor blocks 111 respectively. A p-type semiconductor region 113 formed individually;
Matrix wiring 114 individually contacting the pattern semiconductor region 113 and a common matrix wiring 104 connected to a predetermined individual matrix wiring 114 between different blocks
A p-side pad electrode 105 and a p-side pad wiring 106 formed integrally with a predetermined individual matrix wiring 114;
and an n-side pad electrode 115 that contacts the n-type semiconductor block 111. n-type semiconductor blocks 111 and 1
The one p-type semiconductor region 113 constitutes one LED. Individual matrix wiring 114 and common matrix wiring 1
04 constitutes a matrix wiring. A first interlayer insulating film 112a and a second interlayer insulating film 112b are formed between the n-type semiconductor block 111 and the individual matrix wiring 114 and between the individual matrix wiring 114 and the common matrix wiring 104, respectively. Common matrix wiring 10
4 is connected to a predetermined individual matrix wiring 114 by a via hole 118.

The LED print head shown in FIGS. 23 and 24 has a mounting substrate 201 provided with an LED array 101 or 121, a driving IC 202, and a scanning pattern 203. Drive IC 202 and scanning pattern 2
Reference numeral 03 denotes a driving circuit for driving the LED array. The p-side pad electrode 105 of the LED array is a wire 20
4a is connected to the driving IC 202, and the n-side pad electrode 115 is connected to the scanning pattern 203 by a wire 204b.
It is connected to the.

[0008]

In the above-mentioned conventional light emitting element array and printer head, there is room for further improvement in terms of the reduction of the array size and the head size, particularly the reduction of the width size.
An object of the present invention is to improve the prior art, and an object of the present invention is to provide a light emitting element array capable of reducing the array size and the head size.

[0009]

In order to achieve the above object, a light emitting element array according to the present invention is formed of a plurality of first conductive type semiconductor blocks separated from each other and a first conductive type semiconductor block. A light emitting device having a second conductive type semiconductor region, a matrix wiring connecting between predetermined second conductive type regions formed in different first conductive type semiconductor blocks, and a second conductive side pad electrode connected to the matrix wiring. In the element array, the second conductive side pad electrode is formed in multiple layers on the matrix wiring.

Further, according to the method of manufacturing a light emitting element array of the present invention, an interlayer insulating film is formed on a semiconductor substrate on which a first conductive type semiconductor block, a second conductive type semiconductor region, and a matrix wiring are formed. Forming a via hole exposing the matrix wiring in the insulating film; forming a conductive film on the semiconductor substrate having the via hole formed thereon; and patterning the conductive film to form a second conductive side pad electrode And forming the second conductive-side pad electrode on the matrix wiring in multiple layers.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment FIGS. 1A and 1B are diagrams showing a structure of an LED array 1 according to a first embodiment of the present invention, wherein FIG. 1A is a top view and FIG. 1B is a cross section taken along line AA ′ in FIG. FIG. LED array 1 is 1
It is a matrix type LED array corresponding to 200 [D @ I], and includes a high-resistance semiconductor substrate 2 and an n-type semiconductor block 11.
P-type semiconductor region (light-emitting portion) 13, individual matrix wiring 14 and common matrix wiring 4 constituting a matrix wiring, p
It has a side pad electrode 5, a p side pad wiring 6, and an n side pad electrode 15. M (M is a positive integer) M n-type semiconductor blocks 11 are arranged in one row on the high-resistance semiconductor substrate 2. FIG. 1 shows three n-type semiconductor blocks 11. The n-type semiconductor block 11 is obtained by dividing an n-type semiconductor layer such as an epitaxial layer formed on a high-resistance semiconductor substrate 2 by a separation groove 3. Therefore, the n-type semiconductor block 11 is isolated from each other by the high-resistance semiconductor substrate 2 and the separation groove 3.

Each n-type semiconductor block 11 has:
N (N is a positive integer) p-type semiconductor regions 13 are formed in one column by a diffusion method or the like. In FIG. 1, N = 5. 1
The p-type semiconductor regions 13 and the n-type semiconductor blocks 11 constitute one LED. That is, N LEDs are formed in the n-type semiconductor block 11. The depth of the p-type semiconductor region 13 is smaller than the thickness of the n-type semiconductor block 11. Therefore, the p-type semiconductor region 13 is formed in the n-type semiconductor block 11 in a floating island shape. On the n-type semiconductor block 11 where the p-type semiconductor region 13 is formed, a first
An interlayer insulating film 12a is formed. In the first interlayer insulating film 12a, a light emitting opening 16 for exposing substantially the entire surface of the light emitting section 13 and a pad opening 17 for exposing the surface of the n-type semiconductor block 11 are formed.

On the n-type semiconductor block 11 on which the first interlayer insulating film 12a is formed, N individual matrix wirings 1 are provided.
4 and an n-side pad electrode 15 are formed. The individual matrix wiring 14 is connected to the light emitting portion 13 at the light emitting opening 16.
Contact each other individually. The n-side pad electrode 15
The n-type semiconductor block 1 formed in the pad opening 17
Contact 1 On the n-type semiconductor block 11 on which the individual matrix wiring 14 and the n-side pad electrode 15 are formed, a second interlayer insulating film 12b is formed.
In the second interlayer insulating film 12b, a light emitting opening 16 for exposing substantially the entire area of the light emitting unit 13, a pad opening 17 for exposing the n-side pad electrode 15, and an individual matrix wiring 1
A matrix via hole 18 and a pad via hole 19 for exposing 4 are formed. The matrix via hole 18 is for contacting the individual matrix wiring 14 and the common matrix wiring 4, and the pad via hole 19 is for connecting the p-side pad electrode 5 to the matrix wiring.

On the n-type semiconductor block 11 on which the second interlayer insulating film 12b is formed, P (P is an integer equal to or greater than N) common matrix wirings 4 are formed. In FIG. 1, P = 5
It is. The common matrix wiring 4 is formed over all the n-type semiconductor blocks 11 and contacts predetermined individual matrix wirings 14 in the matrix via holes 18. Further, a third interlayer insulating film 12c is formed on the n-type semiconductor block 11 on which the common matrix wiring 4 is formed. A light emitting opening 16, a pad opening 17, and a pad via hole 19 are formed in the third interlayer insulating film 12c.

On the n-type semiconductor block 11 on which the third interlayer insulating film 12c is formed, a p-side pad electrode 5 and a p-side pad wiring 6 are formed. The p-side pad electrode 5 and the p-side pad wiring 6 are formed integrally. The p-side pad electrode 5 is formed on the common matrix wiring 4 via the third interlayer insulating film 12c, and is connected to a predetermined individual matrix wiring 14 via the p-side pad wiring 6. The p-side pad wiring 6 is in contact with a predetermined individual matrix wiring 14 in a pad via hole 19. In FIG. 1, p
Two side pad electrodes 5 are formed on each n-type semiconductor block 11.

The LED array 1 has a p-side pad electrode 5 and an n-side pad electrode 5.
When a voltage is applied between the side pad electrodes 15, a light emission phenomenon occurs at a junction surface between the p-type semiconductor region (light emitting portion) 13 and the n-type semiconductor block 11, and the emitted light is emitted from the surface of the light emitting portion 13 to the outside. Is done. The emitted light is emitted vertically upward from the surface of the light emitting section 13 as shown in FIG.

An LED array 1 according to a first embodiment of the present invention
Is characterized in that the p-side pad electrode 5 and the matrix wiring (in this case, the individual matrix wiring 14 and the common matrix wiring 4) have a multilayer structure, and the p-side pad electrode 5 is formed on the matrix wiring. In the conventional LED array, the p-side pad electrode and the matrix wiring are formed in separate regions. However, by forming the p-side pad electrode and the matrix wiring in a multilayer structure, only the width of the p-side pad electrode ( Or by the width of the matrix wiring formation area)
The width size of the LED array can be reduced.

The manufacturing process of the LED array 1 will be described below. 2 to 11 are views showing an example of a manufacturing process of the LED array 1. FIG. 2A, FIG. 6, FIG. 7A to FIG. 11A are top views. 3 to 5, FIG. 7 (b),
FIGS. 8B and 11B are cross-sectional views taken along the line AA ′ in the top view. 7 (c), 8 (c), 11
(C) is a sectional view taken along the line BB 'in the top view. FIGS. 9B and 11D are cross-sectional views taken along the line CC ′ in the top view. FIGS. 10B and 11E are cross-sectional views taken along the line DD ′ in the top view.

First, as shown in FIG. 2, a semiconductor substrate (composite semiconductor substrate) in which an n-type semiconductor layer 20 is formed on a high-resistance semiconductor substrate 2 is manufactured, and a diffusion mask 21 is formed on the surface of the n-type semiconductor layer 20. A first interlayer insulating film 12a is formed, and the first interlayer insulating film 12a is patterned by photolithography and etching to form a light emitting opening 16 and a diffusion mask 2.
Form one. Here, a semi-insulating gallium arsenide substrate (GaAs substrate) is used as the high resistance semiconductor substrate 2.
An n-type AlGaAs is formed on the semi-insulating GaAs substrate.
The s layer is epitaxially grown, and this AlGaAs epitaxial layer is used as the n-type semiconductor layer 20. The thickness of the n-type semiconductor layer 20 (n-type epitaxial layer) is, for example, about 3 [μ].
m]. The first interlayer insulating film 12a (diffusion mask 2)
As 1), for example, an aluminum nitride film (AlN film) is used. This AlN film is formed by a sputtering method, and its thickness is, for example, about 500 to 3000 [Å].

Next, as shown in FIGS. 3 and 4, a p-type semiconductor region 13 is formed on the surface substrate side of the n-type semiconductor layer 20. Here, a Zn solid phase diffusion method is used. That is, the Δn diffusion source film 22 is formed on the surface of the n-type semiconductor layer 20 where the light emitting openings 16 have been formed, and the annealing cap film 23 is further formed thereon (FIG. 3). Ζn diffusion source film 22
For example, a ZnO-SiO2 mixed film is formed.
The ZnO-SiO2 film is a film obtained by mixing zinc oxide (ZnO) and silicon oxide (SiO2) at a ratio of 1: 1.
The film is formed by a sputtering method. Annealed cap film 23
For example, a SiN film is used. The above ZnO-Si
The thickness of the O2 mixed film is, for example, about 500 to 3000 [Å]. The thickness of the SiN film is, for example, 500 to 3
000 [０００].

Further, the n-type semiconductor layer 20 on which the annealing cap film 23 has been formed is subjected to high-temperature annealing to diffuse Zn from the Δn diffusion source film 22 into the n-type semiconductor layer 20 (FIG. 4). At this time, Zn is applied to the n-type semiconductor layer 20 only in the light emitting opening 16 where the diffusion mask 21 is not formed.
The p-type semiconductor region 13 is selectively formed in the formation region of the light-emitting opening 16 in the n-type semiconductor layer 20 because it is diffused in. The conditions of the high-temperature annealing are, for example, an annealing temperature of 700 [° C.] and an annealing time of 2 hours under a nitrogen atmospheric pressure. The depth of about 1 [μ]
m], and a p-type semiconductor region 13 having a surface Zn concentration of about 1020 [cm3] is formed.

Next, as shown in FIG. 5, the p-type semiconductor region 1
In the n-type semiconductor layer 20 on which the third layer 3 has been formed, the annealing cap film 23 and the diffusion source film 22 are entirely removed by, for example, a selective wet etching method, and only the first interlayer insulating film 12a (diffusion mask 21) is formed. Leave.

Next, as shown in FIG. 6, in the n-type semiconductor layer 20 from which the annealing cap film 23 and the diffusion source film 22 have been removed, a pad opening 17 is formed in the first interlayer insulating film 12a by photolithography and etching. I do.

Next, as shown in FIG.
Is formed on the surface of the n-type semiconductor layer 20 on which the individual matrix wiring 14 has been formed, and the conductive film is patterned by a lift-off method to form the individual matrix wiring 1.
4 is formed. That is, a photoresist pattern is formed using a region where the individual matrix wiring 14 is to be formed as a blanking pattern, a conductive film serving as the individual matrix wiring 14 is formed over the entire surface, and the above photoresist and the conductive film formed thereon are formed. The individual matrix wiring 14 is formed by lifting off the film. Part of the individual matrix wiring 14 is formed in the p-type semiconductor region 13 in the light emitting opening 16.
It is formed so as to be in close contact with the surface of. Thereafter, a sintering process (heat treatment) for ohmic connection of the individual matrix wiring 14 to the p-type semiconductor region 13 is performed. For example, an aluminum film (Al film) is used as a conductive film to be the individual matrix wiring 14.

Further, a conductive film serving as the n-side pad electrode 15 is formed on the surface of the n-type semiconductor layer 20 on which the individual matrix wirings 14 have been formed, and the conductive film is patterned by a lift-off method. 15 are formed. The n-side pad electrode 15 is formed in the pad opening 17 in close contact with the surface of the n-type semiconductor layer 20. Thereafter, a sintering process for ohmic connection of the n-side pad electrode 15 to the n-type semiconductor layer 20 is performed. As the conductive film serving as the n-side pad electrode 15, for example, an Au alloy film is used. Examples of the Au alloy film include a laminated metal film of a titanium film, a platinum film, and an Au film, and a laminated alloy film of an alloy film of Au, germanium, and nickel and an Au film. The conductive film serving as the individual matrix wiring 14 may be any material that can be ohmic-connected to the p-type semiconductor region 13, and the conductive film serving as the n-side pad electrode 15 may be a material capable of ohmic connection to the n-type semiconductor layer 20. good.

Next, as shown in FIG.
The separation groove 3 reaching the high-resistance semiconductor substrate 2 is formed in the n-type semiconductor layer 20 on which the formation 5 is completed, and the n-type semiconductor layer 20 is divided into n-type semiconductor blocks 11. That is, the first interlayer insulating film 12a in the region where the isolation groove is to be formed and the n-type semiconductor layer 20 thereunder are etched by photolithography and the etching method to expose the high-resistance semiconductor substrate 2. As a result, an n-type semiconductor block 11 in which elements are separated from each other by the separation groove 3 and the high-resistance semiconductor substrate 2 is formed. N-type semiconductor layer 20 having a thickness of about 3 [μm] and a thickness of 500 to 500 μm;
For the first interlayer insulating film 12a of about 3000 [Å], the depth of the isolation groove 3 is, for example, about 3.5 [μm]. In addition,
The element separation method for dividing the n-type semiconductor layer 20 into blocks is not limited to the air separation method using separation grooves.

Further, a second interlayer insulating film 12b is formed on the surface of the semiconductor substrate (composite semiconductor substrate comprising the high-resistance semiconductor substrate 2 and the n-type semiconductor layer 20) on which the isolation trench 3 has been formed. A light emitting opening 16 is formed in the interlayer insulating film 12b.
The pad opening 17, the matrix via hole 18 reaching the individual matrix wiring 14, and the pad via hole 1
9 are formed. As the second interlayer insulating film 12b, for example, a polyimide film is used. The polyimide film is formed and patterned as follows using, for example, a polyimide dissolved in a photoresist developing solution (alkaline solution). A polyimide source is spin-coated on a semiconductor substrate (wafer) and pre-baked at about 100 ° C. Next, a photoresist is spin-coated on the pre-baked polyimide film, and this photoresist is exposed so that the opening and the via hole form a cut pattern.
During the development of the photoresist, the photoresist region serving as a punch pattern and the polyimide film region thereunder dissolve in the developing solution, and the polyimide film is patterned. Next, the remaining photoresist is removed, and the patterned polyimide film is baked at about 350 ° C.

Next, as shown in FIG. 9, the second interlayer insulating film 1 is formed.
A conductive film to be the common matrix wiring 4 is formed on the entire surface of the semiconductor substrate after the patterning of 2b, and the conductive film is patterned by a lift-off method to form the common matrix wiring 4. Thereafter, a sintering process is performed, and the common matrix wiring 4 is ohmically connected to the predetermined individual matrix wiring 14 in the matrix via hole 18.
As the conductive film serving as the common matrix wiring 4, a conductive film which does not cause disconnection in a contact portion with the individual matrix wiring 14 is used. For example, if the individual matrix wiring 14
When an l film is used, an Al film is used, and when an Au alloy film is used, an Au alloy film is used.

Next, as shown in FIG. 10, a third interlayer insulating film 12c is formed on the entire surface of the semiconductor substrate on which the individual matrix wirings 14 have been formed, and the light emitting opening 16 and the light emitting opening 16 are formed in the third interlayer insulating film 12c. , A pad opening 17 and a pad via hole 19 are formed. As the third interlayer insulating film 12c, for example, the same polyimide film as the second interlayer insulating film 12b is used. The light emitting opening 16 and the pad opening 17 are formed in the interlayer insulating films 12a, 12b and 12c, and the pad via hole 19 is formed in the interlayer insulating films 12b and 12c.
Formed.

Finally, as shown in FIG. 11, a conductive film serving as the p-side pad electrode 5 and the p-side pad wiring 6 is formed on the entire surface of the semiconductor substrate 2 on which the third interlayer insulating film 12c has been completed. Is patterned by a lift-off method to form a p-side pad electrode 5 and a p-side pad wiring 6 integrated therewith. Thereafter, a sintering process is performed, and the p-side pad wiring 6 is ohmically connected to a predetermined individual matrix wiring 14 in the pad via hole 19, and the p-side pad electrode 5 is formed.
Is connected to a predetermined matrix wiring. p-side pad electrode 5
As the conductive film that becomes the p-side pad wiring 6, a conductive film that does not cause disconnection in a contact portion with the individual matrix wiring 14 is used. The individual matrix wiring 14, the common matrix wiring 4, and the p-side pad electrode 5 have a three-layer structure, and the p-side pad electrode 5 is formed in multiple layers on the matrix wiring. As described above, the LED shown in FIG.
Array 1 is manufactured.

Next, the operation of the LED array 1 will be briefly described. In FIG. 1A, the n-side pad electrode 15
15-15, 15-2... 15-M in order from the right side (however, 15-4 to 15-M are not shown). Further, the light emitting units 13 are arranged in order from right to 13- [1, 1], 13- [1,
2] 13- [1, 5], 13- [2, 1] 13
[M, 5] (13- [3, 4] to 13-
[M, 5] is not shown). Similarly, individual matrix wiring 1
4 in order from the right, 14- [1,1], 14- [1,2]
... 14- [M, 5]. The p-side pad electrodes 5 are 5-1, 5-2... 5- (2 × M) in order from the right side (however, 5-6 to 5- (2 × M) are not shown). Further, the common matrix wirings 4 are arranged in the order from 4-1 to -4,
4-2 ... 4-5.

Individual matrix wiring 14- [1, j] to 1
4- [M, j] (j is any integer from 1 to N)
Are connected to a common matrix wiring 4-j. That is, the light emitting units 13- [1, j] to 13- [M, j] are connected to the matrix wiring 4-j. p-side pad electrode 5-
1-5-5 are common matrix wirings 4-1 and 4-
5, 4-3, 4-4, and 4-2. The p-side pad electrodes 5-6 to 5-10 are connected to common matrix wirings 4-5, 4-1 and 4-4, 4-2 and 4-3, respectively. For example, the p-side pad electrode 5-1 is connected to the common matrix wiring 4-1 via the individual matrix wiring 14- [1, 1], and the p-side pad electrode 5-5 is connected to the individual matrix wiring 14- [3 , 2] to the common matrix wiring 4-3. The p-side pad electrode 5-11
.About.5-M are connected to the common matrix wiring 4 like 5-1.about.5-10.

In order to emit light from the light emitting section 13- [i, j] (i is any integer from 1 to M), the p-side pad electrode 5 connected to the matrix wiring 4-j and the n-side pad electrode 15-i. For example, the light emitting unit 13
To make [-[1,1] and 13- [1,3] emit light,
The p-side pad electrode 5 connected to the common matrix wirings 4-1 and 4-3 (for example, the p-side pad electrodes 5-1 and 5-
3) and a voltage is applied between the n-side pad electrode 15-1. To emit light from the light emitting units 13- [2,2] and 13- [3,2], the p-side pad electrode 5 (for example, the p-side pad electrode 5-2) connected to the common matrix wiring 4-2
And a voltage is applied between the n-side pad electrodes 15-2 and 15-3.

FIG. 12 shows an LED according to the first embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a structure of an LED printer head using an array 1. The printer head shown in FIG. 12 includes an LED array 1 and a driving circuit (a driving IC 202 and a scanning pattern 203) on a mounting substrate 201. LE
The p-side pad electrode 5 of the D array 1 is connected to the driving IC 202 by a wire 204a, and the n-side pad electrode 15 is connected to the scanning pattern 203 by a wire 204b. In the printer head shown in FIG.
Alternatively, as compared with the printer head shown in FIG. 24, the width of the head can be reduced by an amount corresponding to the use of the LED array 1 having a smaller width.

As described above, according to the first embodiment, the width of the LED array can be reduced by forming the p-side pad electrode 5 on the matrix wiring in multiple layers. Also, using the LED array of the first embodiment,
By configuring the printer head, the width of the head can be reduced.

Second Embodiment FIGS. 13A and 13B are views showing the structure of an LED array 31 according to a second embodiment of the present invention, wherein FIG. 13A is a top view and FIG.
3 is a cross-sectional view taken along line AA ′ in FIG. 13, the same components as those in FIG. 1 are denoted by the same reference numerals. The LED array 31 is different from the LED array 1 of FIG. 1 in a p-side pad electrode 32 and a pad via hole 33, and is otherwise the same as the LED array 1. The manufacturing process and operation of the LED array 31 are the same as those of the LED array 1. Also LE
The structure of the printer head using the D array 31 is the same as in FIG.

The LED array 31 of the second embodiment has p
The side pad electrode 32 itself is brought into contact with a matrix wiring (common matrix wiring 4). That is, the pad via hole 33 reaching the predetermined common matrix wiring 4 is formed in the third interlayer insulating film 12c, and the p-side pad electrode 32 is formed on the pad via hole 33. The p-side pad electrode 32 is in contact with a predetermined matrix wiring in the area where the common matrix wiring 4 is formed, and the p-side pad wiring and the individual matrix wiring are formed in a region other than the formation area of the common matrix wiring 4 like the LED array 1. It is not necessary to provide the contact region of the above, so that the width size of the LED array can be further reduced.

Since there is no need to contact the third conductive film with the first conductive film (individual matrix wiring 14), the pad via hole 33 is formed in the third interlayer insulating film 1.
What is necessary is just to provide only in 2c. In addition, pad via hole 3
3 may be formed at the same position as the matrix via hole 18 provided in the second interlayer insulating film 12b, that is, on the matrix via hole 18.

As described above, according to the second embodiment, the p-side pad electrode 32 itself is brought into contact with the matrix wiring in the region where the common matrix wiring 4 is formed. Since there is no need to provide a contact region for connecting the p-side pad electrode to the individual matrix wiring, the width of the LED array can be further reduced.

Third Embodiment FIG. 14 is a view showing the structure of an LED array 41 according to a third embodiment of the present invention, wherein (a) is a top view and (b) is (a).
3 is a cross-sectional view taken along line AA ′ in FIG. 14, the same components as those in FIG. 1 are denoted by the same reference numerals. The LED array 41 is different from the LED array 1 of FIG. 1 in the position of the n-side pad electrode 15, and is otherwise the same as the LED array 1.
The manufacturing process and operation of the LED array 41
Similar to array 1.

In the LED array 51 of the third embodiment, the n-side pad electrode 15 is formed on the same side as the matrix wiring and the p-side pad electrode 5 with respect to the light emitting portion 13, that is, the n-side pad electrode 15 has a multilayer structure. It is characterized in that it is formed on the opposite side of the light emitting section 13 with respect to the matrix wiring and the p-side pad electrode 5.

FIG. 15 shows an LED according to a third embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a structure of an LED printer head using an array 41. 15, the same components as those in FIG. 12 are denoted by the same reference numerals. In the printer head shown in FIG. 15, the wire 204a bonded to the p-side pad electrode 5 and the wire 204b bonded to the n-side pad electrode 15 are drawn out from one side of the longitudinal end of the LED array 41. Therefore, the drive circuit may be arranged along one end of the array of the LED array 41, and the drive circuit is connected to the LED array 4 as shown in FIG.
There is no need to place them on both sides of one. Therefore, the width size of the printer head can be reduced. Further, compared to the printer head shown in FIG. 12, the bonding operation is simplified, and the mounting cost of the LED array can be reduced.

As described above, according to the third embodiment, the n-side pad electrode 15 is connected to the light-emitting portion 13 by the p-side pad electrode 5.
By forming the wire on the same side as above, the wire can be pulled out from one side of the array end when mounted on the printer head, so that the width size of the printer head can be made even smaller than in the first embodiment. Further, the mounting cost of the LED array in the printer head can be reduced.

The third embodiment is applied to the second embodiment, and the n-side pad electrode 15 is formed on the same side as the p-side pad electrode 32 with respect to the light emitting section 13 in the second embodiment. You may.

Fourth Embodiment FIGS. 16A and 16B are views showing the structure of an LED array 51 according to a fourth embodiment of the present invention, wherein FIG. 16A is a top view and FIG.
3 is a cross-sectional view taken along line AA ′ in FIG. In FIG.
The same components as those in FIG. 14 are denoted by the same reference numerals. The LED array 51 is different from the LED array 41 of FIG. 1 in an n-side contact electrode 52, a contact opening 53, an n-side pad wiring 54, and an n-side pad electrode 55, and is otherwise the same as the LED array 41. The operation of the LED array 51 is the same as that of the LED array 41.

The LED array 51 of the fourth embodiment is characterized in that n-type pad electrodes 55 are formed in multiple layers on matrix wiring. An n-side contact electrode 52 having a width smaller than that of the n-side pad electrode 15 shown in FIG. 14 is in contact with the n-type semiconductor block 11 in a contact opening 53 formed on the opposite side of the light emitting portion 13 with respect to the matrix wiring. . The n-side pad wiring 54 formed integrally with the p-side pad electrode 55 is in contact with the n-side contact electrode 52. n-side pad electrode 55 and p-side pad electrode 5
Are arranged in one column on the matrix wiring. Since the width of the n-side contact electrode 52 can be made smaller than that of the n-side pad electrode 15 shown in FIG. 14, the width of the LED array can be further reduced.

The manufacturing process of the LED array 51 is basically the same as that of the LED array 41 of the third embodiment.
The contact opening 53 is the pad opening 1 shown in FIG.
7, the interlayer insulating films 12a, 12b, and 12
c is formed. The n-side contact electrode 52 is formed after forming the first interlayer insulating film 12a or the second interlayer insulating film 12b.
It is formed before or after the individual matrix wiring 14 or the common matrix wiring 4 is formed. The n-type pad electrode 55 and the n-side pad wiring 54 are formed before and after the formation of the p-side pad electrode 5 and the p-side pad wiring 6 after the formation of the third interlayer insulating film 12c. As the conductive film serving as the n-side contact electrode 52, a conductive film that can be ohmic-connected to the n-type semiconductor block 11 is used. Also, n-side pad electrode 5
5 and the conductive film to be the n-side pad wiring 54 include n
A conductive film that does not cause disconnection in a contact portion with the side contact electrode 52 is used.

FIG. 17 shows an LED according to a fourth embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a structure of an LED printer head using an array 51. 17, the same components as those in FIG. 15 are denoted by the same reference numerals. The printer head shown in FIG.
By using the LED array 51 having a smaller width than the LED array 41 of the third embodiment, the width of the head can be further reduced than that of the printer head shown in FIG. Further, in the LED array 51, the n-side pad electrode 55 and the p-side pad electrode 5 are arranged in one line, and even if a wire bonding failure occurs when the LED array 51 is mounted, the wires can be easily collected. The mounting cost of the array can be further reduced.

As described above, according to the fourth embodiment, since the n-side pad electrode 55 is formed in multiple layers on the matrix wiring, the width of the LED array can be made smaller than that of the third embodiment. it can. In addition, by configuring the LED printer head using the LED array 51 of the fourth embodiment, the width of the head can be further reduced, and the mounting cost of the LED array can be further reduced.

Note that the fourth embodiment may be applied to the second embodiment, and the n-side pad electrode 15 may be formed in multiple layers on the matrix wiring in the second embodiment.

Fifth Embodiment FIG. 18 is a view showing the structure of an LED array 61 according to a fifth embodiment of the present invention, wherein (a) is a top view and (b) is (a).
3 is a cross-sectional view taken along line AA ′ in FIG. In FIG. 18, the same components as those in FIG. 16 are denoted by the same reference numerals. The LED array 61 includes an n-side contact electrode 62 and an n-side pad wiring 6.
The LED array 51 shown in FIG.
Otherwise, it is the same as the LED array 51 except for this.
The operation of the LED array 61 is the same as that of the LED array 51. The structure of the printer head using the LED array 61 is the same as that shown in FIG.

The LED array 61 of the fifth embodiment has n
The n-side pad electrode 65 and the n-side pad electrode 65 are integrally formed. The manufacturing process of the LED array 61 is basically the same as that of the LED array 51 of the fourth embodiment. The n-side contact electrode 62, the n-side pad wiring 63, and the n-side pad electrode 65 are formed before and after the formation of the p-side pad electrode 5 and the p-side pad wiring after the formation of the third interlayer insulating film 12c. n-side contact electrode 62 and n-side pad wiring 6
Since the third and n-side pad wirings 63 can be formed at the same time, the manufacturing process can be simplified as compared with the LED 51 of the fourth embodiment.

As described above, according to the fifth embodiment, the n-side contact electrode 62, the n-side pad wiring 63, and the n-side pad electrode 65 are integrally formed. Can be simplified, and the manufacturing cost can be reduced.

Sixth Embodiment FIGS. 19A and 19B are views showing the structure of an LED array 71 according to a sixth embodiment of the present invention, wherein FIG. 19A is a top view and FIG.
3 is a cross-sectional view taken along line AA ′ in FIG. 19, the same components as those in FIG. 16 are denoted by the same reference numerals. The LED array 71 includes an individual matrix wiring 72 and a p-type semiconductor region 7.
The LED array 3 and the light emitting opening 74 are different from the LED array 51 of FIG.

The LED array 71 according to the sixth embodiment is similar to the LED array 51 according to the fourth embodiment except that
Applied to arrays. As shown in FIG. 19B, the edge-emitting LED array emits light generated at the junction between the p-type semiconductor region 73 and the n-type semiconductor block 11 in a horizontal direction from the array end face. On the other hand, LE in FIG.
An LED array that emits generated light in the vertical direction from the surface of the light emitting unit, such as the D array 51, is called a top emission type.

The LED array 71 has a structure in which the array end face 75 is close to the position where the p-type semiconductor region 73 and the light emitting opening 74 are formed. The individual matrix wiring 72 is formed so as to contact the entire surface of the p-type semiconductor region 73. In the edge emitting LED array, the entire surface of the p-type semiconductor region can be brought into contact with the individual matrix wiring, so that the contact area can be increased. As a result, light can be emitted with a lower applied voltage than the top emission type LED array, so that power consumption can be reduced. In addition, the edge emitting LED array has a structure in which the array end face is not close to the p-type semiconductor region but a structure in which the array end face is close to the p-type semiconductor region unlike the top-emitting LED array, and is therefore wider than the top-emitting LED array. The size can be reduced.

The manufacturing process of the LED array 71 is basically the same as that of the LED array 51 of the fourth embodiment.
However, a step of processing the array end face 75 may be added. The operation of the LED array 71 is determined by the array end face 7.
LED array 51 except that it emits emitted light from
Is the same as

FIG. 20 shows an LED according to a sixth embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a structure of a printer head using an array 71. 20, the same components as those in FIG. 17 are denoted by the same reference numerals. In the printer head shown in FIG. 20, the width of the head is smaller than that of the printer head shown in FIG. 17 by using the LED array 71 having a smaller width than the LED array 51 of the fourth embodiment. Power consumption can be reduced.

As described above, according to the sixth embodiment, the width can be further reduced by using the edge emission type, and the power consumption can be reduced as compared with the top emission type LED array. Further, by configuring the LED printer head using the edge emitting LED array 71 of the sixth embodiment, the width of the head can be further reduced, and the power consumption can be reduced.

The sixth embodiment is applied to the third or fifth embodiment, and the LED array 41 of the third embodiment or the LED array 51 of the fifth embodiment is applied.
May be an edge emitting type.

In the embodiments of the present invention, only the semiconductor substrate having a homojunction made of the same crystal has been described. However, the present invention can be applied to a semiconductor substrate having a heterojunction made of a different material.

[0062]

As described above, according to the light emitting element array of the present invention, the width of the LED array can be reduced by forming the p-side pad electrode on the matrix wiring in multiple layers. . By configuring a printer head using this light emitting element array, there is an effect that the width of the head can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of an LED array according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 1).

FIG. 3 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 2).

FIG. 4 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 3).

FIG. 5 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 4).

FIG. 6 is a view illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 5).

FIG. 7 is a view illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 6).

FIG. 8 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 7).

FIG. 9 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 8).

FIG. 10 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 9).

FIG. 11 is a view illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 10).

FIG. 12 is a cross-sectional view illustrating a structure of a printer head using the LED array according to the first embodiment of the present invention.

FIG. 13 is a diagram illustrating a structure of an LED array according to a second embodiment of the present invention.

FIG. 14 is a diagram illustrating a structure of an LED array according to a third embodiment of the present invention.

FIG. 15 is a sectional view showing a structure of a printer head using an LED array according to a third embodiment of the present invention.

FIG. 16 is a diagram illustrating a structure of an LED array according to a fourth embodiment of the present invention.

FIG. 17 is a cross-sectional view illustrating a structure of a printer head using an LED array according to a fourth embodiment of the present invention.

FIG. 18 is a diagram illustrating a structure of an LED array according to a fifth embodiment of the present invention.

FIG. 19 is a diagram illustrating a structure of an LED array according to a sixth embodiment of the present invention.

FIG. 20 is a sectional view showing the structure of a printer head using an LED array according to a sixth embodiment of the present invention.

FIG. 21 is a top view showing the structure of a conventional LED array.

FIG. 22 is a diagram showing a structure of a conventional LED array.

FIG. 23 is a cross-sectional view showing a structure of a printer head using a conventional LED array.

FIG. 24 is a cross-sectional view showing a structure of a printer head using a conventional LED array.

[Explanation of symbols]

1,31,41,51,61,71 LED array,
2 High-resistance semiconductor substrate, 3 Separation groove, 4 Common matrix wiring, 5, 32 p-side pad electrode, 6 p-side pad wiring, 11 n-type semiconductor block, 12 interlayer insulating film, 13, 73 p-type semiconductor region (light emitting section ),
14,72 Individual matrix wiring, 15,55,64
n-side pad electrode, 19,33 pad via hole,
52, 62 n-side contact electrode, 54, 63 n
Side pad wiring, 201 mounting board, 202 drive I
C, 203 scan pattern, 204 bonding wire.

Claims (14)

[Claims] A plurality of first conductive type semiconductor blocks separated from each other; a second conductive type semiconductor region formed in the first conductive type semiconductor block; and a predetermined first conductive type semiconductor block formed in a different first conductive type semiconductor block. Matrix wiring connecting between the second conductivity type regions, and a second wiring connecting to the matrix wiring.
A light-emitting element array having a conductive-side pad electrode, wherein the second conductive-side pad electrode is formed in multiple layers on the matrix wiring. 2. The semiconductor device according to claim 1, further comprising: a second conductive pad wiring formed integrally with the second conductive pad electrode, wherein the pad wiring is in contact with the matrix wiring. Light emitting element array. 3. The matrix wiring is formed by forming multiple layers of individual matrix wiring that individually contacts the second conductivity type semiconductor region and common matrix wiring that contacts a predetermined individual matrix wiring. The conductive side pad wiring and the matrix wiring,
3. The light emitting element array according to claim 2, wherein the contact is made in a region other than a region where the common matrix wiring is formed. 4. The light emitting element array according to claim 1, wherein said second conductive side pad electrode is in contact with said matrix wiring. 5. The matrix wiring is formed by forming multiple layers of individual matrix wiring that individually contacts the second conductivity type semiconductor region and common matrix wiring that contacts a predetermined individual matrix wiring. The light emitting element array according to claim 4, wherein the conductive side pad electrode and the matrix wiring are in contact with each other in a region where the common matrix wiring is formed. 6. A semiconductor device having a first conductive side pad electrode connected to a predetermined first conductive type semiconductor block, wherein the first conductive side pad electrode is connected to the second conductive type semiconductor region with respect to the second conductive type semiconductor region. The light emitting element array according to claim 1, wherein the light emitting element array is formed on a side opposite to the pad electrode. 7. A semiconductor device, comprising: a first conductive side pad electrode connected to a predetermined first conductive type semiconductor block; wherein the first conductive side pad electrode is connected to the second conductive type semiconductor region with respect to the second conductive type semiconductor region. The light emitting element array according to claim 1, wherein the light emitting element array is formed on the same side as the pad electrode. 8. The light emitting element array according to claim 7, wherein said first conductive side pad electrode is formed in multiple layers on said matrix wiring. 9. A semiconductor device comprising: a first conductive side pad wiring integrally formed with the first conductive side pad electrode; and a first conductive side contact electrode contacting the first conductive type semiconductor block. 9. The light emitting element array according to claim 8, wherein a side pad wiring and said first conductive side contact electrode are in contact with each other. 10. A first conductive side pad wiring formed integrally with the first conductive side pad electrode, and a first conductive side contact electrode contacting the first conductive type semiconductor block, wherein the first conductive side contact electrode is in contact with the first conductive type semiconductor block. Side pad wiring and the contact electrode,
The light emitting element array according to claim 8, wherein the light emitting element array is formed integrally. 11. The semiconductor device according to claim 1, wherein the second conductivity type semiconductor region is formed near an end face of the first conductivity type semiconductor block, and emitted light is radiated from the end face to the outside. 2. The light emitting element array according to 1. 12. A plurality of first conductive type semiconductor blocks separated from each other, a second conductive type semiconductor region formed in the first conductive type semiconductor block, and a predetermined first conductive type semiconductor block formed in a different first conductive side semiconductor block. A method of manufacturing a light emitting element array having a matrix wiring connecting between the second conductive type regions and a second conductive side pad electrode connected to the matrix wiring, wherein the first conductive type semiconductor block and the second conductive type A step of forming an interlayer insulating film on a semiconductor substrate on which a semiconductor region and the matrix wiring are formed, and forming a via hole exposing the matrix wiring in the interlayer insulating film; and a semiconductor having the via hole formed therein. Forming a conductive film on the substrate and patterning the conductive film to form a second conductive side pad electrode. Is formed on the matrix wiring in a multilayer manner. 13. A printer head comprising a light emitting element array and a drive circuit for individually driving the light emitting elements of the light emitting element array on a mounting board, wherein the light emitting element array according to claim 1 is used as the light emitting element array. A printer head using: 14. A printer head comprising a light emitting element array and a drive circuit for individually driving the light emitting elements of the light emitting element array on a mounting substrate, wherein the light emitting element array is used as the light emitting element array. A wire bonded to the first conductive side pad electrode and a wire bonded to the second conductive side pad electrode are pulled out from one side of a longitudinal end of the light emitting element array, and A printer head which is bonded to a drive circuit.