JP2001007387A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method of manufacturing a semiconductor device and a semiconductor device of high manufacturing efficiency and yield. SOLUTION: An LED array 100 comprises a high-resistance substrate 102, a semiconductor layer 104 and a contact layer 105 formed epitaxially on this layer 104. The contact layer 105 has thin parts 105a formed on element isolation regions 106. Thus when a p-type impurity is diffusion-doped in the semiconductor layer 104 via the contact layer 105, the element isolation regions 106 at a diffusion depth Xj2 reaching the substrate 102 and light emitting parts 110 at a diffusion depth Xj1 which does not reach the substrate 102 are formed at the same time, in the semiconductor layer 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

[0002]

2. Description of the Related Art In recent years, a light emitting element array has been used as a light source of an electrophotographic optical printer, as described in "Design of LED Printers", Trikeps P63.
The light-emitting element array is a semiconductor device in which a plurality of light-emitting elements are formed one-dimensionally (linearly) at equal intervals on a single semiconductor substrate. Generally, a light emitting element array includes a semiconductor laser array using a semiconductor laser as a light emitting element and a light emitting diode (Light Emitting Diode).
de; hereinafter, referred to as “LED”. ) Is used as a light emitting element.

FIG. 17 shows a schematic configuration of an LED array 800 according to the above-mentioned conventional document. Here, FIG.
FIG. 17B is a partial cross-sectional view of the vicinity of the light emitting section 810 of the LED array 800, and FIG. 17B is a plan view of the LED array 800.

As shown in FIG. 17B, in an LED array 800, a plurality of light emitting units 810 are arranged one-dimensionally. As shown in FIG. 17A, in the LED array 800, each light-emitting unit 810 includes a semiconductor substrate 802.
(Gas substrate) and a semiconductor layer 804 (Ga
As _0.6 P _0.4 semiconductor layer). Here, the light emitting portion 810 can be formed by selectively doping a p-type impurity into the semiconductor layer 804 by, for example, selective diffusion.

In the LED array 800, the light emitting section 8
In order to inject a current into a pn junction between the semiconductor substrate 10 and the semiconductor layer 804, an electrode 808 (Au-Ge
−Ni electrode) and a wiring 812 (Al wiring) is connected to the light emitting unit 810. Furthermore,
A portion other than the light emitting portion 810 of the semiconductor layer 804 is connected to the wiring 812.
An interlayer insulating film 814 is formed on the surface of the semiconductor layer 804 to insulate it from the like. As shown in FIG. 17B, a wire bonding pad 816 is connected to the light emitting unit 810 via a wiring 812.

In recent years, the present inventors have proposed a multilayer wiring type LED array having a multilayer wiring for the purpose of reducing the number of electrode pads as an LED array. Such a multilayer wiring type LED array has a configuration in which individual wiring connected to each light emitting unit and a common wiring connected to the p-side electrode pad are laminated via an interlayer insulating film. In such a multilayer wiring type LED array, the individual wiring and the common wiring are formed substantially perpendicularly to each other in a plane direction, and the semiconductor layers forming the light emitting portion are separated into a plurality of blocks (isolated). Has been split.

The multilayer wiring type LED array can be manufactured, for example, by the following method. First, an n-type semiconductor layer is formed on a high resistance substrate. Next, the semiconductor layer is separated into M ′ blocks by forming element isolation regions. Next, p-type impurities are selectively diffused through a diffusion mask to form N 'LEDs (p-side semiconductor regions (light emitting portions)) for each block. Next, N 'LEs
N 'individual p-side electrodes connected one-to-one to D, individual wires connected one-to-one to the individual p-side electrodes, and individual wires selected one by one for each block. A p-side electrode pad is formed for each block. Next, a part of the diffusion mask is peeled off, and the n-type semiconductor layer of each block is one-to-one.
To form an n-side electrode pad to be connected. Next, an interlayer insulating film is formed on the individual wiring. Next, an opening for exposing a predetermined position of each individual wiring is formed in the interlayer insulating film. next,
On the interlayer insulating film, N ′ connected to the selected individual wiring, one for each block, across the N ′ blocks
The common wirings are formed.

[0008]

However, in the above-mentioned conventional LED array and the method of manufacturing the same, the impurity diffusion into the element formation region and the impurity diffusion into the element isolation region are performed in different steps. In the conventional impurity diffusion, two or more regions having different diffusion depths cannot be formed at one time. Therefore, in the conventional LED array and the method of manufacturing the same, the element isolation region and the element forming region having different diffusion depths are different from each other. This is because the region cannot be formed in a single impurity diffusion step.

[0009] Such a problem of impurity diffusion applies to the whole conventional semiconductor device manufacturing method and the whole semiconductor device. That is, in the conventional method of manufacturing a semiconductor device, even if the regions having different depths are formed in the same semiconductor layer of the same wafer by doping with the same impurity, they must be formed in different impurity diffusion steps. .

As shown in FIG. 18, in the selective diffusion using a diffusion mask, the impurity is generally diffused in the lateral direction over the entire surface around the diffusion opening of the diffusion mask (hereinafter, referred to as "diffusion"). The phenomenon is called "side diffusion."
Generally, diffusion depth (diffusion distance in the vertical direction on the top surface of the substrate)
When there is no abnormal side diffusion, there is a relation ds / Xj = approximately 1.3.
Here, ds represents the side diffusion width, Xj represents the diffusion depth, and ds / Xj represents the ratio between the diffusion depth and the side diffusion width.

Therefore, in general, the side diffusion ds increases as the diffusion depth Xj increases. As a result, the conventional LE
In the case of forming the element isolation region relating to the D array, in the selective diffusion using the diffusion mask, as the density of the light emitting portion increases, the impurity diffusion region of the light emitting portion and the impurity diffusion region of the element isolation region are formed in contact. Is more likely to occur.

The present invention has been made in view of the above and other problems of the conventional method of manufacturing a semiconductor device.

[0013]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a semiconductor layer, the method comprising: And a second step of doping a predetermined impurity through the control layer to form two or more impurity-doped regions in the semiconductor layer.

According to the structure described in this form, the control layer formed as a part of the epitaxial wafer in the first step controls the distance of the predetermined impurity entering the semiconductor layer in the second step. Therefore, by changing the control amount by the control layer depending on the position, in the doping performed in the second step, it is possible to simultaneously form two or more impurity-doped regions having different depths in the semiconductor layer. Efficiency can be improved.

Further, the invention according to claim 2 includes a third step of adjusting the thickness distribution of the control layer before the second step,
In the second step, a configuration is employed in which the intrusion distance of the predetermined impurity into the semiconductor layer depends on the thickness of the control layer. In the configuration described in this section, the distribution of the depth of the impurity-doped region formed in the semiconductor layer in the second step can be controlled collectively by adjusting the layer thickness distribution of the control layer in the third step. .
The thickness distribution of the control layer can be adjusted by, for example, selective etching or selective growth. In the invention described in this section, the layer thickness distribution may include a portion where the layer thickness becomes zero.

Further, the invention according to claim 3 includes, before the second step, a fourth step of forming a mask layer having an opening at a portion corresponding to the impurity-doped region on the control layer. A structure in which part or all of the control layer below a predetermined opening is thinned by etching to adjust the thickness distribution of the control layer, and in a second step, a predetermined impurity is doped into the semiconductor layer through the opening and the control layer. Is adopted.

In the structure according to this aspect, impurity-doped regions having different depths are formed in a portion corresponding to the opening whose control layer is thinned in the third step and a portion corresponding to the other opening. The Rukoto. Therefore, in the doping in the second step, the depth of the impurity-doped region to be formed can be adjusted for each opening. Note that, in the invention described in this section, if a configuration is adopted in which a part of the control layer below the predetermined opening is thinned, unnecessary expansion of the impurity-doped region corresponding to the opening can be suppressed.

Further, the invention according to claim 4 includes a fourth step of forming a mask layer having an opening at a portion corresponding to the impurity-doped region on the control layer before the second step. A configuration is adopted in which the thickness of the control layer is adjusted by removing part or all of the control layer below the predetermined opening, and in the second step, a predetermined impurity is doped into the semiconductor layer through the opening and the control layer. I do.

In the structure according to the present mode, the impurity-doped region formed in the second step is formed between the lower part of the opening where part or all of the control layer is removed in the third step and the lower part of the other opening. Of different depths. Therefore, in the doping in the second step, the depth of the impurity-doped region to be formed can be adjusted for each opening. In the invention described in this section, if a configuration is employed in which a part of the control layer below the predetermined opening is removed, unnecessary expansion of the doped region corresponding to the opening can be suppressed.

Further, the fifth aspect of the present invention provides a fifth step of forming a mask layer having an opening at a portion corresponding to an impurity-doped region on the control layer before the second step, And a sixth step of forming another control layer for controlling the distance of the predetermined impurity entering the semiconductor layer. In the second step, the predetermined impurity is added to the semiconductor layer through the other control layer, the opening, and the control layer. Is adopted.

According to the invention having the above structure, the depth of the impurity-doped region formed in the semiconductor layer can be adjusted by both the control layer and the other control layers. Therefore, the depth distribution of the impurity-doped regions that can be formed in the second step is further diversified.

According to a sixth aspect of the present invention, in a method of manufacturing a semiconductor device having a semiconductor layer, a seventh step of partially forming a groove in a surface region of the semiconductor layer is provided. The impurity doped region is simultaneously formed by doping a predetermined impurity from the surface region side with a portion other than the groove.
And a step. According to the invention described in this aspect, by the doping in the eighth step, impurity-doped regions having different depths can be simultaneously formed in the semiconductor layer at the bottom of the groove and the portion other than the groove of the semiconductor layer. Here, as in the invention according to claim 8, in the second step, the semiconductor layer can be doped with a predetermined impurity by solid phase diffusion.

According to a seventh aspect of the present invention, in the second step, two or more light-emitting portions and two or more blocks each including a semiconductor layer as at least one light-emitting portion are provided as impurity-doped regions separated from each other. And a separation region that separates the two. According to the configuration described in this section, the semiconductor device includes a semiconductor layer on which two or more light emitting elements are formed, and the semiconductor layer is formed by at least one element isolation region.
An efficient manufacturing method can be provided for a semiconductor device which is divided into two or more blocks separated from each other including the light emitting element. In addition, as the light emitting element,
For example, an LED or a semiconductor laser can be realized.

According to a ninth aspect of the present invention, there is provided a semiconductor device having a semiconductor layer, wherein a predetermined impurity penetrating into the semiconductor layer is formed epitaxially on the semiconductor layer. A configuration including a control layer to be controlled and two or more impurity-doped regions formed in the semiconductor layer by doping a predetermined impurity through the control layer is employed. Further, according to the present invention, the semiconductor layer is separated into two or more light emitting portions and two or more blocks each including at least one light emitting portion as impurity-doped regions separated from each other. A configuration in which a separation region is formed is adopted.

Further, according to the present invention, the separation region is formed deeper than the light emitting portion, and a part or the whole of the control layer is formed above the separation region more than other portions of the control layer. A configuration that is formed thin is adopted. Furthermore, the invention according to claim 12 employs a configuration in which the separation region is formed deeper than the light emitting portion, and a part or all of the control layer is removed above the separation region. still,
In the invention described in this section, a configuration in which, for example, a light emitting unit of an LED, a light emitting unit of a semiconductor laser, or the like is applied as the light emitting unit can be adopted.

Further, the invention according to claim 13 employs a configuration in which the peripheral portion of the separation region is formed shallower than the central portion of the separation region. Still further, the invention according to claim 14 employs a configuration in which the control layer has a lower entry speed of the predetermined impurity than the semiconductor layer. Further, according to a fifteenth aspect of the present invention, the main component of the semiconductor layer is AlGaAs, the main component of the control layer is GaAs, and the impurity-doped region is doped with the predetermined impurity by thermal diffusion. The configuration that has been formed is adopted.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A preferred embodiment of the present invention will be described in detail with reference to a so-called multilayer wiring type light emitting element array which is a kind of a semiconductor device. In the following description and the accompanying drawings, components having the same functions and configurations are denoted by the same reference numerals, and redundant description will be omitted.

First Embodiment First, a light emitting element array and a method for manufacturing the light emitting element array according to the first embodiment will be outlined. The light emitting element array according to the present embodiment corresponds to a high resistance substrate, a semiconductor layer of the first conductivity type epitaxially formed on the high resistance substrate, and a control layer epitaxially formed on the semiconductor layer. And another semiconductor layer of the first conductivity type (hereinafter referred to as “contact layer”).

In the light emitting device array according to the present embodiment, the semiconductor layer includes, as impurity diffusion regions, a light emitting portion having a diffusion depth not in contact with the high resistance substrate, and an element isolation region having a diffusion depth in contact with the high resistance substrate. Are formed. still,
In the following description and the accompanying drawings, the diffusion depth of the light emitting portion is represented by Xj.
1, and the diffusion depth of the element isolation region is represented by Xj2.

In the present embodiment, the diffusion rate of the second conductivity type impurity is lower than that of the first conductivity type semiconductor layer in the contact layer, and a part of the upper portion of the element isolation region is removed. In the present embodiment, the light emitting portion and the element isolation region are formed in the semiconductor layer by diffusing and doping the second conductive type impurity into the first conductive type semiconductor layer via the contact layer.

Further, in the light emitting element array according to the present embodiment, N light emitting portions are formed in the semiconductor layer in a one-dimensional array. In the light emitting element array according to the present embodiment, the semiconductor layer is divided into M blocks each including one or more light emitting units by L element isolation regions that intersect approximately vertically with the columns of the light emitting units. still,
M and N are any integers of 2 or more, and L is any integer of 1 or more.

Here, the number N of light-emitting parts, the number M of blocks, and the number L of element isolation regions can be set in accordance with the design conditions of an apparatus to which the light-emitting element array according to the present embodiment is applied. For example, when the light-emitting element array according to the present embodiment is applied to an electrophotographic printer, the number of light-emitting units N, the number of blocks M, and the number of element isolation regions L are adjusted according to the resolution (unit: dpi) of the printer. It can be set arbitrarily.

In the method of manufacturing a light emitting element array according to the present embodiment, first, a high resistance substrate, a semiconductor layer, and a contact layer are sequentially laminated to form an epitaxial wafer, and thereafter, a diffusion opening is formed on the contact layer. A diffusion mask corresponding to the mask layer on which is formed is formed. Further, in the method for manufacturing the light emitting element array according to the present embodiment, the contact layer under the predetermined diffusion opening is made thinner than the contact layer in the other part, and thereafter, the epitaxial wafer is interposed via the diffusion mask and the contact layer. Is selectively diffused into the second semiconductor layer.

As a result, an element isolation region is formed below the diffusion opening where the contact layer is thinned as an impurity diffusion region having a depth reaching the high-resistance substrate, and a high isolation region is formed below the diffusion opening where the contact layer is not thinned. The light emitting portion is formed as an impurity diffusion region having a depth that does not reach the resistance substrate. That is,
In the method for manufacturing a light emitting element array according to this embodiment, a light emitting portion and an element isolation region having different diffusion depths can be simultaneously formed in a semiconductor layer.

Hereinafter, the light emitting element array according to the present embodiment will be specifically described by exemplifying the LED arrays 100 and 200, both of which are multilayer wiring type light emitting elements.

(1) LED Array 100 First, referring to FIG. 1 and FIG.
0 will be described. FIG. 1 shows the LED array 100
FIG. 2 is a plan view showing a schematic configuration of the LED array 100, and FIG. In FIG. 2, FIG.
FIG. 2 is a partial sectional view of a portion B in FIG. 1 and FIG. 2B is an enlarged sectional view of a portion C in FIG. 2A.

As shown in FIG. 2A, the LED array 1
Reference numeral 00 denotes a high-resistance substrate 102 made of, for example, GaAs and functioning as a semi-insulating substrate, an n-type semiconductor layer 104 made of, for example, AlGaAs and formed on the high-resistance substrate 102, and a semiconductor layer made of, for example, GaAs. And an n-type contact layer 105 formed epitaxially on the substrate 104.

In the LED array 100, the semiconductor layer 1
04 is divided into four blocks 108 by forming the element isolation region 106 in (4-1) (see FIG. 1). Here, the element isolation region 106 is a diffusion region of a p-type impurity formed between the adjacent blocks 108,
The diffusion depth Xj2 reaches the high-resistance substrate 102.
In the LED array 100 according to the present embodiment, the blocks 108 are electrically and physically separated from each other by the pn junction formed by the element isolation region 106 with the surrounding semiconductor layer 104 and the high-resistance substrate 102. This separates the semiconductor layer 104 into blocks 108.

As shown in FIG. 1, 4 × 4 light emitting units 110 are formed in each of the blocks 108 and the entire LED array 100 is formed. Such a light emitting unit 110 is
The entire ED array 100 is formed so as to form a one-dimensional line at substantially equal intervals.

As shown in FIG. 2A, the light emitting unit 110
Is a diffusion region of a p-type impurity formed by selective diffusion in the semiconductor layer 104, and its diffusion depth Xj 1 does not reach the high-resistance substrate 102. In the LED array 100 according to the present embodiment, a light emitting phenomenon occurs in a pn junction formed by the light emitting unit 110 and the semiconductor layer 104 around the light emitting unit 110.

As shown in FIG. 2B, in the contact layer 105 corresponding to the control layer, a portion on the element isolation region 106 is formed thinner than other portions. Hereinafter, a portion of the contact layer 105 formed thinner than other portions is referred to as a thin portion 105a.

As described above, the semiconductor layer 104 of the LED array 100 has a p
The type impurity is diffusion-doped. In the diffusion doping, the time required for the diffusion region to reach the semiconductor layer 104 becomes longer as the contact layer 105 becomes thicker. Therefore, in the LED array 100, the diffusion region formed in the semiconductor layer 104 below the thin portion 105a is deeper than the diffusion region formed in other portions of the semiconductor layer. As a result, in the semiconductor layer 104, the element isolation region 106 having the diffusion depth Xj2 and the light emitting portion 110 having the diffusion depth Xj1 can be simultaneously formed by, for example, one time of p-type impurity diffusion. In the LED array 100, Xj1 <Xj
2.

Further, the LED array 1 according to the present embodiment
At 00, the contact layer 105 is the semiconductor layer 104
It is formed so that the diffusion rate of the p-type impurity is lower than that. Therefore, the element isolation region 106 and the light emitting unit 11
The difference (Xj2−Xj1) of the diffusion depth to 0 can be efficiently generated.

As shown in FIG. 1, in the LED array 100, one p-side contact electrode 112 is formed on each of the contact layer 105 above the light emitting section 110. In each block 108, one n-side contact electrode 114 is formed in a predetermined portion of the contact layer 105 other than the portion above the light emitting unit 110.
In the LED array 100, these p-side contact electrodes 1
By supplying a current through the contact 12 and the n-side contact electrode 114, each light emitting unit 110 of the semiconductor layer 104 can emit light.

In the LED array 100 according to this embodiment, a multilayer wiring 120 for supplying a current to the light emitting section 110 via the p-side contact electrode 112 and the n-side contact electrode 114 is formed. Such multilayer wiring 1
Reference numeral 20 denotes an n-side electrode pad 130 which is an exposed portion of the individual wiring 122, the p-side electrode pad 128 and the n-side contact electrode 114 formed on the first interlayer insulating film 140, and a second
And a common wiring 126 formed on the interlayer insulating film 150. The multilayer wiring 120 is a kind of a so-called matrix wiring structure, and has a mesh structure including the individual wiring 122 and the common wiring 126.

In the multilayer wiring 120, the first interlayer insulating film 140 is formed on the contact layer 105 of the block 108. In the first interlayer insulating film 140, a first light emitting opening 142 exposing the light emitting unit 110 and the p-side contact electrode 112, and an n-side contact electrode 114 (n
A first opening 144 exposing the side electrode pad 130) is formed.

The individual wiring 122 has a first light emitting opening 142.
Is connected one-to-one with the p-side contact electrode 112 formed at the same time. Further, one p-side electrode pad 128 is formed for each block 108. In the multilayer wiring 120, in each block 108, one of the blocks 108
Are connected to the p-side electrode pad 128. In the LED array 100 according to this embodiment, the p-side contact electrode 112, the individual wiring 122, and the p-side electrode pad 128 are integrated by the same film formation and patterning as shown in FIG. Is formed.

In the multilayer wiring 120, the second interlayer insulating film 150 is formed on the first interlayer insulating film 140 so as to cover the individual wiring 122. Second interlayer insulating film 150
The second light emitting opening 152 exposing the first light emitting opening 142 of the first interlayer insulating film 140 and the first interlayer insulating film 1
N-side contact electrode 1 which communicates with the first opening 144
A second opening 154 exposing a portion of the 14 n-side electrode pad 130 is formed. Further, the second interlayer insulating film 150 has a first
A via hole 156 and a second via hole 158 exposing a part of the individual wiring 122 are formed.

In the multilayer wiring 120, the common wiring 126
Are formed over the entire block 108 via the element isolation region 106. The common wiring 126 is connected to each block 108 via the second via hole 158 in one block.
Are connected to the individual wiring 122. Common wiring 126
Is connected to the individual wiring 122 formed integrally with the p-side electrode pad 128 in one of the blocks 108.

The p-side wire bonding pad p
One side electrode pad 128 is provided for each block 108.
Are formed one by one. Further, the n-side electrode pad 130, which is an n-side wire bonding pad, is
08 one each. The n-side electrode pad 130 is formed as an exposed portion of the n-side contact electrode 114 connected to the semiconductor layer 104 via the first opening 144. In the present embodiment, on the p-side electrode pad 128 and on the n-side electrode pad 130, there are further different heights for convenience of connection with an external electrode, wire bonding, and the like. An electrode pad can also be formed.

The LED array 10 configured as described above
0, the p-side electrode pad 128 and the n-side electrode pad 130
Is selected, and a current is applied between the selected pads, so that the pn junction of the predetermined light emitting unit 110 can emit light. That is, in the LED array 100, the light emitting unit 110 that emits light is determined by the combination of the p-side electrode pad 128 and the n-side electrode pad 130 to which a current is applied.

Next, the LED array 10 according to this embodiment will be described.
0 will be described with reference to FIGS. 4 to 7 are explanatory views of the steps of the present manufacturing method. Here, in FIGS. 4 and 5, an enlarged plan view of the portion B (see FIG. 1) is shown in the right diagram, and a cross-sectional view taken along line AA ′ of the portion B is shown in the left diagram.

(Formation of Epitaxial Wafer) In this manufacturing method, as shown in FIG.
The semiconductor layer 104 and the contact layer 105 are sequentially epitaxially formed on the substrate 02. Here, the contact layer 10
No. 5 is formed to have a thickness capable of realizing a diffusion depth Xj1 at which the light emitting section 110 does not contact the high-resistance substrate 102 in diffusion annealing described later.

If the thickness of the contact layer 105 is too large, light absorption in the contact layer 105 increases, and
The amount of light that can be taken out of the D array 100 is reduced. Therefore, the contact layer 105 needs to be formed with an appropriate layer thickness in consideration of the conditions for partial removal of the contact layer 105 and diffusion annealing described later.

In this embodiment, the high resistance substrate 10
For example, a semi-insulating GaAs substrate can be used for the semiconductor layer 104, and an n-type AlGa
As can be used. In addition, contact layer 1
For example, GaAs (50 to 3000 angstroms) or the like can be used for 05.

(Formation of First Interlayer Insulating Film, Formation of Diffusion Opening) Next, as shown in FIG.
5, a first interlayer insulating film 140 is formed, and an opening 140a is provided in a region where the light emitting unit 110 is to be formed and a region where the element isolation region 106 is to be formed in the first interlayer insulating film 140. Of these openings 140a, those provided on the region where the light emitting unit 110 is to be formed will be described later.
(C) and FIG. 6 (a)).

Here, as the first interlayer insulating film 140,
For example, SiN (for example, 500 to 3000 Å) can be used. Also, the first interlayer insulating film 14
For example, as a film formation method of CVD (Chemica
l Vapor Deposition (chemical vapor deposition) method can be used. Further, the opening section 140a
Can be formed by, for example, photolithography and etching.

(Partial removal of contact layer) Next, FIG.
As shown in FIG. 3C, the thin portion 105 is formed on the contact layer 105 above the region where the element isolation region 106 is to be formed.
a is provided. Here, the thin portion 10 of the contact layer 105 is formed.
5a is formed so that the diffusion depth Xj2 of the element isolation region 106 contacts the high-resistance substrate 102. The removal of the contact layer 105 can be performed by, for example, photolithography and etching.

(Formation of Diffusion Source) Next, as shown in FIG. 4D, a diffusion doped with a predetermined impurity is formed on the first interlayer insulating film 140 so as to cover the opening 140a and the thin portion 105a. An insulating film 160 as a source is formed. Here, for example, Zn can be used as the predetermined impurity. Further, as the insulating film 160, for example, ZnO-Si
O ₂ (for example, 100 to 2000 Å) can be used. As a method for forming the insulating film 160, for example, a sputtering method can be used.

(Formation of Annealed Cap Film) Next, FIG.
As shown in (a), an annealing cap film 170 is formed on the insulating film 160. Here, as the annealing cap film 170, for example, AlN (500 to 3000 Å) can be used. Further, as a method of forming the annealing cap film 170, for example, a sputtering method can be used.

(Diffusion Annealing) Next, as shown in FIG. 5B, diffusion annealing is performed using the first interlayer insulating film 140 as a diffusion mask to form an insulating film 160 in the semiconductor layer 104 via the contact layer 105. A predetermined impurity is diffused.
In the contact layer 105, a thin portion 105a is formed on the element isolation region 106. As a result, in this step, the element isolation region 106 and the light emitting unit 1 having different depths from each other are obtained.
10 are formed at the same time. Here, diffusion annealing
For example, it can be carried out under nitrogen atmospheric pressure.

(Removal of Annealing Cap Film and Diffusion Source) Next, as shown in FIG. 5C, in order to enable the contact formation of the p-side contact electrode 112 on the light emitting portion 110, the annealing cap film is removed. The first light emitting opening 142 is formed by removing the insulating film 160 and the insulating film 160. Here, the removal of the annealing cap film 170 and the insulating film 160 can be performed by, for example, selective etching.

(Removal of Diffusion Mask in Region Where N-Type Contact Electrode is to be Formed) Next, as shown in FIG. 6A, an n-type contact electrode 114 is formed on the contact layer 105 in order to form a contact. The first interlayer insulating film 140 in the region where the contact electrode 114 is to be formed is removed, and the first opening 1 is removed.
44 is formed.

(Formation of p-side contact electrode, individual wiring and p-side electrode pad) Next, a pattern is formed by a lift-off method, and the p-side contact electrode 112 and the p-side contact electrode 112 are individually formed on the light emitting portion 110 of the semiconductor layer 104 by film formation. The wiring 122 and the p-side electrode pad 128 are formed simultaneously. Here, as the p-side contact electrode 112, for example, an Au laminated film can be used.

In this embodiment, the p-side electrode pad 12
8 may be connected to a predetermined light emitting unit 110 via a predetermined individual wiring 122 and a predetermined p-side contact electrode 112. Therefore, the p-side contact electrode 112
And the individual wiring 122 and the p-side electrode pad 128 need not always be formed simultaneously in the same step. That is, in the present embodiment, the p-side contact electrode 112, the individual wiring 122, and the p-side electrode pad 128
The p-side contact electrode 112, the individual wiring 122, or the p-side electrode pad 1
It is also possible to form any of the steps 28 in a separate step.

(Formation of n-side contact electrode and n-side electrode pad) Next, as shown in FIG. 6C, a pattern is formed by a lift-off method, and the contact layer 105 is exposed in the first opening 144. An n-side contact electrode 114 (n-side electrode pad 130) is formed by film formation. here,
As the n-side contact electrode 114 (n-side electrode pad 130), for example, an Au alloy film can be used.

(Formation of Second Interlayer Insulating Film) Next, FIG.
As shown in (a), the second light emitting opening 152, the second opening 154 and the first light emitting opening 152 are formed by photolithography and etching.
A second interlayer insulating film 150 in which the via holes 156 and the second via holes 158 are patterned is formed. here,
As the second interlayer insulating film 150, for example, polyimide can be used.

(Formation of Common Wiring) Next, as shown in FIG. 7B, a pattern is formed by a lift-off method, and a common wiring 126 is formed by film formation. Here, common wiring 1
For example, an Al film can be used as 26.

Next, the depth control of the element isolation region 106 and the light emitting section 110 will be described based on the results of experiments by the inventors and the like. As shown in FIG. 2B, in the LED array 100 according to the present embodiment, by removing a part of the contact layer 105 and forming the thin part 105a, the element isolation region 106 below the thin part 105a is moved upward. The contact layer 105 is formed deeper than the light emitting portion 110 where it is (Xj2> Xj1). That is, one feature of the present embodiment is that the light emitting unit 110 and the element isolation region 106 having different diffusion depths can be formed by the same diffusion annealing. Such a feature can be realized, for example, as follows.

FIG. 3 shows the results of an experiment performed by the inventors. In this experiment, AlGa corresponding to the semiconductor layer 104 was used.
An epitaxial wafer having an As layer and a GaAs layer corresponding to the contact layer 105 laminated on the AlGaAs layer was used. In this experiment, the thermal diffusion
A through an As layer (corresponding to the contact layer 105)
Zn in the lGaAs layer (corresponding to the semiconductor layer 104)
(Corresponding to a p-type impurity). In this experiment, the relationship between diffusion annealing time and diffusion depth was measured for different contact layer thicknesses.

As shown in FIG. 3, according to this experiment, Ga
It can be seen that as the thickness of the As layer increases, the diffusion depth of Zn doped in the AlGaAs layer decreases. This is a phenomenon that occurs mainly because the diffusion coefficient of Zn in AlGaAs is larger than the diffusion coefficient of Zn in GaAs.

As described above, if the semiconductor layer 104 is formed of AlGaAs and the contact layer 105 is formed of GaAs in the LED array 100 according to the present embodiment, the diffusion depth Xj1, Xj2 can be controlled freely. That is,
The diffusion depth Xj2 of the element isolation region 106 and the diffusion depth Xj1 of the light emitting unit 110 can be controlled by adjusting the layer thickness distribution of the contact layer 105.

In the LED array 100, the semiconductor layer 1
Since the impurity is diffused into the semiconductor layer 04 through the contact layer 105, the longer the thickness of the contact layer 105, the longer the time required for the diffusion region to reach the semiconductor layer. Such a phenomenon occurs regardless of, for example, the diffusion coefficient of the semiconductor layer, the diffusion coefficient of the contact layer, or the relationship between the two diffusion coefficients. Therefore, the diffusion depths Xj1 and Xj2 are
Regardless of the material or composition of the semiconductor layer 104 and the contact layer 104, the control can also be performed by simply adjusting the layer thickness distribution of the contact layer 105.

In general, Zn for AlGaAs
Becomes larger as the Al composition of AlGaAs increases. Therefore, in the LED array 100, the semiconductor layer 104 and / or the contact layer 105
If formed from a GaAs-based material, the semiconductor layer 104 and / or
Alternatively, by adjusting the Al composition ratio of the contact layer 105, the diffusion depths Xj1 and Xj2 can be freely controlled.

(2) LED Array 200 Next, another LED array 200 according to this embodiment will be described with reference to FIG. FIG. 8 shows the LED
FIG. 2 is a partial cross-sectional view of the array 200, more specifically, an enlarged cross-sectional view of a portion corresponding to a portion B of the LED array 100 shown in FIG. 1 in the LED array 200.

The LED array 200 has substantially the same structure as the LED array 100 shown in FIG. That is, FIG.
(A) and (b) as shown in FIG.
0 denotes a contact layer 20 having a thin portion 205a on the element isolation region 206 and a thin portion 205b on the light emitting portion 210.
5 is provided.

In the LED array 200, by adopting such a configuration, the influence of light absorption in the contact layer 205 can be reduced, and the amount of light that can be extracted outside the LED array 200 can be increased. Such a configuration,
This is particularly effective when the thickness of the contact layer 205 is large enough to affect light absorption.

The structure of the LED array 200 is as follows.
For example, in the method of manufacturing the LED array 100,
This can be realized by partially removing the contact layer 205 on the light emitting section 210 after the diffusion annealing shown in FIG. Partial removal of the contact layer 105 on the light emitting section 110 can be performed, for example, by removing the p-side contact electrode 1.
It can be realized by etching using the p-side contact electrode 112 as an etching mask after forming 12. Further, the partial removal of the contact layer 105 on the light emitting unit 110 can also be realized by, for example, forming a unique mask pattern and etching the contact layer 105.

As described above, in the present embodiment, by forming a structure in which a part of the contact layer formed on the entire substrate surface is removed in an arbitrary region, each of the different regions formed on the semiconductor substrate is formed. A structure and a manufacturing method capable of controlling the diffusion depth can be provided. In addition, by applying the structure, in a light emitting element array in which a light emitting portion and an element isolation region are formed in a semiconductor layer on a high resistance substrate, a light emitting portion having a shallow diffusion depth and a deep diffusion depth are formed. The element isolation region can be easily formed at a high yield.

(Second Embodiment) A light emitting element array and a method for manufacturing the light emitting element array according to a second embodiment will be outlined. The light emitting element array according to the present embodiment is the first light emitting element array.
The structure of the contact layer differs from the light emitting element array according to the embodiment. The difference will be specifically described. In the light emitting element array according to the first embodiment, the contact layer above the element isolation region is simply thinner than the other parts. In the array, almost all of the contact layer above the element isolation region is removed.

In the light emitting element array according to this embodiment,
By adopting such a configuration, a difference (Xj2−Xj1) in the diffusion depth between the element isolation region and the light emitting portion is easily generated when the impurity is diffused into the semiconductor layer via the contact layer. still,
In other respects, the light emitting element array according to the present embodiment substantially corresponds to the light emitting element array according to the first embodiment.

The method for manufacturing the light emitting element array according to the present embodiment is different from the method for manufacturing the light emitting element array according to the first embodiment in the step of partially removing the contact layer. The difference will be specifically described.
In the method of manufacturing the light emitting element array according to the embodiment, in the step of partially removing the contact layer, the partial removal is performed to reduce the thickness of the contact layer above the element isolation region. In the manufacturing method of (1), in a corresponding step, almost the entire portion of the contact layer above the element isolation region is removed.

In the method of manufacturing the light emitting element array according to the present embodiment, by adopting such a structure, the difference in the diffusion depth between the element isolation region and the light emitting portion (diffusion of impurities into the semiconductor layer via the contact layer) is obtained. Xj2-Xj1). The manufacturing method of the light emitting element array according to the present embodiment substantially corresponds in other steps to the manufacturing method of the light emitting element array according to the first embodiment.

Hereinafter, with reference to FIG. 9, a multilayer wiring type LED array 300 will be specifically described as an example of the light emitting element array according to the present embodiment. Note that FIG.
FIG. 2 is a partial cross-sectional view of a D array 300, more specifically, a part corresponding to a portion B of the LED array 100 shown in FIG. 1 in the LED array 300.

As shown in FIG. 9A, the LED array 3
00 is a high-resistance substrate 30 functioning as a semi-insulating substrate.
2, an n-type semiconductor layer 304 epitaxially formed on the high-resistance substrate 302, and an n-type contact layer 305 epitaxially formed on the semiconductor layer 304,
Have.

In the LED array 300, the semiconductor layer 3
04 is a block 3 formed by forming an element isolation region 306.
08. Here, the element isolation region 306
Is a diffusion region of a p-type impurity having a depth reaching the high-resistance substrate 302, and is formed between adjacent blocks 308.

The light emitting portion 310 is a diffusion region of a p-type impurity formed by selective diffusion in the semiconductor layer 304, and has a depth that does not reach the high-resistance substrate 302, that is, an element isolation region 306.
It is formed shallower than that. In the LED array 300 according to the present embodiment, a light emitting phenomenon occurs in a pn junction formed by the light emitting unit 310 and the semiconductor layer 304 around the light emitting unit 310.

As shown in FIG. 9B, the contact layer 305 corresponding to the control layer has an opening 305a formed by removing almost all of the portion above the element isolation region 306. That is, in the LED array 300, the element isolation region 3
On 06, the layer thickness of the contact layer 305 becomes substantially zero. In the LED array 300 according to the present embodiment, the contact layer 305 is formed so that the diffusion speed of the p-type impurity is lower than that of the semiconductor layer 304.

Further, like the LED array 100 shown in FIG.
One p-side contact electrode is formed on each of the upper portions of the five light emitting portions 310. Also, each block 308
In the contact layer 305, one n-side contact electrode is formed in a predetermined portion other than a portion above the light emitting portion 310.

Further, the LED array 300 is formed with a multilayer wiring for supplying a current to the light emitting section 310 via the p-side contact electrode and the n-side contact electrode. The p-side contact electrode, the n-side contact electrode, and the multilayer wiring have substantially the same functions as the p-side contact electrode 112, the n-side contact electrode 114, and the multilayer wiring 120 according to the first embodiment shown in FIG. The detailed description is omitted.

The LED array 300 having the above-described configuration according to the present embodiment is different from the LED array 100 according to the first embodiment in the steps described below instead of the steps shown in FIG. Can be realized by performing the following.

In this step, substantially the contact layer 105 on the region where the element isolation region 106 is to be formed in the step of FIG. 4C is substantially completely removed. In this step, as a result, an opening 305a is formed on the region where the element isolation region 306 is to be formed. In this embodiment, the opening 305a can be formed by, for example, photolithography and etching.

In the method of manufacturing the LED array 300 described above, the diffusion doping of the p-type impurity into the semiconductor layer 304 is performed indirectly via the contact layer 306 in the light emitting section 310, whereas the element isolation region 306 is formed. Is performed directly without using the contact layer 305.
Therefore, the device isolation region 306 and the light emitting unit 310 having different depths can be formed in the semiconductor layer 304 at the same time.

In this embodiment, a structure in which a contact layer formed on the entire surface of a substrate is entirely removed in an arbitrary region to control the diffusion depth in different regions of the semiconductor substrate is formed. Can be provided. Further, by applying the structure, in a light emitting element array in which a light emitting portion and an element isolation region are formed in a semiconductor layer on a high resistance substrate, a light emitting portion having a small diffusion depth and a deep diffusion depth are formed. The element isolation region can be easily formed at a high yield.

Third Embodiment A light emitting element array and a method of manufacturing the light emitting element array according to a third embodiment will be outlined. The light emitting element array according to the present embodiment is the first light emitting element array.
The configuration of the contact layer and the semiconductor layer is different from the light emitting element array according to the embodiment. The difference will be specifically described. In the light emitting element array according to the first embodiment, the contact layer on the element isolation region is thinner than the other parts. In the array, almost all of the contact layer above the element isolation region is removed. Further, in the light emitting element array according to the above embodiment, the semiconductor layer has a substantially uniform thickness, whereas in the light emitting element array according to the present embodiment,
The thickness of the semiconductor layer is reduced in the element isolation region.

In the light emitting element array according to this embodiment,
By adopting such a configuration, a difference (Xj2−Xj1) in the diffusion depth between the element isolation region and the light emitting portion is easily generated when the impurity is diffused into the semiconductor layer via the contact layer. still,
In other respects, the light emitting element array according to the present embodiment substantially corresponds to the light emitting element array according to the first embodiment.

The method for manufacturing the light emitting element array according to the present embodiment is different from the method for manufacturing the light emitting element array according to the first embodiment in the step of partially removing the contact layer. The difference will be specifically described.
In the method of manufacturing the light emitting element array according to the embodiment, in the step of partially removing the contact layer, the removal is performed to reduce the thickness of the contact layer above the element isolation region. In the manufacturing method of (1), in a corresponding step, substantially the entire portion of the contact layer above the element isolation region is removed, and the semiconductor layer below the removed portion is also removed to a predetermined depth.

In the method of manufacturing the light emitting element array according to the present embodiment, by adopting such a structure, the difference in the diffusion depth between the element isolation region and the light emitting portion (diffusion of impurities into the semiconductor layer via the contact layer) is obtained. Xj2-Xj1). The manufacturing method of the light emitting element array according to the present embodiment substantially corresponds in other steps to the manufacturing method of the light emitting element array according to the first embodiment.

Hereinafter, a multilayer wiring type LED array 400 will be specifically described as an example of a light emitting element array according to this embodiment with reference to FIG. In addition, FIG.
Partial cross-sectional view of LED array 400, more specifically, LED
FIG. 2 is a partial cross-sectional view of a portion corresponding to a portion B of the LED array 400 shown in FIG. 1 in the array 400.

As shown in FIG. 10A, the LED array 400 has a high resistance substrate 4 functioning as a semi-insulating substrate.
02, an n-type semiconductor layer 404 formed epitaxially on the high-resistance substrate 402, and an n-type contact layer 405 formed epitaxially on the semiconductor layer 404.

In the LED array 400, the semiconductor layer 4
04 is a block 4 formed by forming an element isolation region 406.
08. Here, the element isolation region 406
Is a p-type impurity diffusion region having a depth reaching the high-resistance substrate 402 and is formed between adjacent blocks 408.

The light emitting section 410 is a diffusion region of a p-type impurity formed by selective diffusion in the semiconductor layer 404, and has a depth that does not reach the high-resistance substrate 402, that is, an element isolation region 406.
It is formed with a smaller diffusion depth. In the LED array 400 according to the present embodiment, the light emitting portion 410 and the semiconductor layer 404 around the light emitting portion 410 are formed of p.
At the n-junction, a light emission phenomenon occurs.

As shown in FIG. 10B, an opening 405a is formed in the contact layer 405 corresponding to the control layer by removing the entire portion above the element isolation region 406. Further, in the element isolation region 406 of the semiconductor layer 408,
A groove 404a having a predetermined depth communicating with the opening 405a is formed by, for example, etching. as a result,
In the semiconductor layer 408, the layer thickness of the element isolation region 406 is smaller than the layer thickness of other portions. As described above, in the LED array 400 according to the present embodiment, the opening 405a and the groove 4
By forming the light-emitting portion 04a, the element isolation region 406 and the light-emitting portion 410 having different depths can be formed at the same time.

Further, similarly to the LED array 100 shown in FIG.
One p-side contact electrode is formed on each of the upper portions of the five light emitting portions 410. In addition, each block 408
In the contact layer 405, one n-side contact electrode is formed in a predetermined portion other than a portion above the light emitting section 410.

Further, in the LED array 400, a multilayer wiring for supplying a current to the light emitting section 410 via the p-side contact electrode and the n-side contact electrode is formed. The p-side contact electrode, the n-side contact electrode, and the multilayer wiring have substantially the same functions as the p-side contact electrode 112, the n-side contact electrode 114, and the multilayer wiring 120 according to the first embodiment shown in FIG. The detailed description is omitted.

The LED array 400 having the above-described configuration according to the present embodiment is different from the method for manufacturing the LED array 100 according to the first embodiment in the following step instead of the step shown in FIG. Can be realized by performing the following.

In this step, substantially the contact layer 105 on the region where the element isolation region 106 is to be formed is substantially completely removed in the step shown in FIG. 4C, and further, the semiconductor layer exposed in the removed portion is removed. 104 is dug down to a predetermined depth. In this step, as a result, an opening 405a and a groove 404a communicating with each other are formed on the region where the element isolation region 406 is to be formed. The formation of the opening 405a and the groove 404a can be performed by, for example, photolithography and etching.

In the method of manufacturing the LED array 400 described above, the diffusion doping of the p-type impurity into the semiconductor layer 404 is performed via the contact layer 405 in the light emitting section 410, whereas the contact layer is not formed in the element isolation region 406. This is performed at the bottom of the groove 404a without passing through the hole 405.
Therefore, in the semiconductor layer 404, the element isolation region 406 and the light emitting portion 410 having different depths can be formed at the same time.

In the present embodiment, by forming a structure in which a part of the contact layer and the semiconductor layer formed on the entire surface of the substrate is removed in an arbitrary region, the respective diffusion depths in different regions of the semiconductor substrate are different. Can be provided. In addition, by applying the structure, in a light emitting element array in which a light emitting portion and an element isolation region are formed in a semiconductor layer on a high resistance substrate, a light emitting portion having a shallow diffusion depth and a deep diffusion depth are formed. An element isolation region can be easily formed with a high yield.

(Fourth Embodiment) A light emitting element array and a method for manufacturing the light emitting element array according to a fourth embodiment will be outlined. The light emitting element array according to the present embodiment is the first light emitting element array.
The light emitting element array according to the embodiment is different from the light emitting element array in the configuration of the element isolation region and the contact layer. This difference will be specifically described. In the light emitting element array according to the first embodiment, the element isolation region is formed to have a uniform diffusion depth if side diffusion is not taken into consideration.
In the light emitting device array according to the present embodiment, regions having different diffusion depths are formed in the same device isolation region.

In the element isolation region according to this embodiment, the diffusion depth at the center reaches the high-resistance substrate, and the diffusion depth at the peripheral portion does not reach the high-resistance substrate unless side diffusion at the center is considered. Is formed. Further, in the light emitting element array according to the above embodiment, the entire portion of the contact layer above the element isolation region is formed to be thin, whereas in the light emitting element array according to the present embodiment, the portion above the element isolation region of the contact layer is formed. Only the central part of the part is formed thin.

In the light emitting element array according to the present embodiment,
By adopting such a configuration, the expansion of the element isolation region due to side diffusion can be suppressed. It should be noted that the light emitting element array according to this embodiment is different from the first
This is substantially the same as the light emitting element array according to the embodiment.

The method for manufacturing the light emitting element array according to the present embodiment is different from the method for manufacturing the light emitting element array according to the first embodiment in the step of partially removing the contact layer. The difference will be specifically described.
In the method for manufacturing a light emitting element array according to the embodiment, the entire portion of the contact layer on the element isolation region is thinned in the step of partially removing the contact layer. Then, only the central portion of the contact layer on the element isolation region is thinned in a corresponding step.

In the light emitting element array according to this embodiment,
By adopting such a configuration, it is possible to suppress the spread of the element isolation region due to the side diffusion when the impurity is diffused into the semiconductor layer via the contact layer. It should be noted that the light emitting element array according to this embodiment is different from the first
This is substantially the same as the light emitting element array according to the embodiment.

Hereinafter, a multilayer wiring type LED array 500 will be specifically described as a light emitting element array according to the present embodiment with reference to FIG. In addition, FIG.
Partial cross-sectional view of LED array 500, more specifically, LED
FIG. 2 is a partial cross-sectional view of a portion corresponding to a portion B of the LED array 500 shown in FIG. 1 in the array 500.

As shown in FIG. 11A, the LED array 500 includes a high-resistance substrate 5 functioning as a semi-insulating substrate.
02, an n-type semiconductor layer 504 epitaxially formed on the high-resistance substrate 502, and an n-type contact layer 505 epitaxially formed on the semiconductor layer 504.

In the LED array 500, the semiconductor layer 5
04 is a block 5 formed by forming an element isolation region 506.
08. Here, the element isolation region 506
Is a diffusion region of a p-type impurity,
08 is formed.

In this embodiment, the element isolation region 506 has a different diffusion depth between the central portion 506a and the peripheral portion 506b. In the element isolation region 506, the central portion 50
While the diffusion depth of 6a reaches the high-resistance substrate 502,
The diffusion depth of the peripheral portion 506b does not reach the high resistance substrate.

In the LED array 500, the light emitting section 51
Numeral 0 denotes a p-type impurity diffusion region formed in the semiconductor layer 504 by selective diffusion, and the diffusion depth thereof is
02 has not been reached. LED array 5 according to the present embodiment
In 00, a light emitting phenomenon occurs in a pn junction formed by the light emitting unit 510 and the semiconductor layer 504 around the light emitting unit 510.

As shown in FIG. 11B, in the contact layer 505 corresponding to the control layer, the upper part of the central part 506a is formed as a thin part 505a. In the LED array 500 according to the present embodiment, by forming the thin portion 505a on the contact layer 505, the element isolation region 506 and the light emitting unit 510 having different depths from each other are formed at the same time. Central part 506a
And a peripheral portion 506b can be formed with a difference in depth.

Further, like the LED array 100 shown in FIG.
One p-side contact electrode is formed on each of the upper portions of the five light emitting portions 510. Also, each block 508
In the contact layer 505, one n-side contact electrode is formed in a predetermined portion other than a portion above the light emitting portion 510.

Further, the LED array 500 is formed with a multilayer wiring for supplying a current to the light emitting section 510 via the p-side contact electrode and the n-side contact electrode. The p-side contact electrode, the n-side contact electrode, and the multilayer wiring have substantially the same functions as the p-side contact electrode 112, the n-side contact electrode 114, and the multilayer wiring 120 according to the first embodiment shown in FIG. The detailed description is omitted.

The LED array 500 having the above-described configuration according to the present embodiment is different from the method for manufacturing the LED array 100 according to the first embodiment in the following step instead of the step shown in FIG. Can be realized by performing the following.

In this step, in the step shown in FIG. 4C, the contact layer 105 exposed at the diffusion opening 540a is formed.
Is cut off only a predetermined depth at the central part of. In this step, on the region where the element isolation region 506 is to be formed,
A groove having a predetermined depth is formed at the center of the contact layer 505a, and as a result, a thin portion 505a is formed. The formation of the thin portion 505a can be realized by, for example, forming a resist film having an opening at the center of the diffusion opening by photolithography, and etching the contact layer 105 through the resist film. it can.

In the method of manufacturing the LED array 500 described above, the element isolation regions 506 and the light emitting portions 510 having different depths from each other are simultaneously formed in the semiconductor layer 504 in the diffusion doping of the semiconductor layer 504 with the p-type impurity. be able to. Further, in the diffusion doping, the central portion 506a of the element isolation region 506 formed through the thin portion 505a is formed.
Is the depth reaching the high resistance substrate 502,
A peripheral portion 506b of the element isolation region 506 formed through a peripheral portion of the thin portion 505a is formed at a predetermined depth that does not reach the high-resistance substrate 502. Here, the thin portion 505
The thickness of “a” can be arbitrarily determined so that the central portion 506 a contacts the high-resistance substrate 502.

Here, the diffusion doping of the p-type impurity into the semiconductor layer 504 will be described with reference to FIG. FIG. 12 is a conceptual diagram illustrating the state of the semiconductor layer 504 at a predetermined stage in the diffusion annealing process.

(Diffusion Annealing) FIG. 12A shows that
Diffusion opening 540 from which a part of contact layer 505 is peeled off
A state in the middle of diffusion annealing in which a p-type impurity is diffused at the center of a is shown. At this point, the contact layer 5
The thin portion 505a which is an area to be etched of the thin film 505
Only the p-type impurity is diffused into the semiconductor layer 504 from only.

(After Diffusion Annealing) FIG. 12B shows a state after diffusion annealing. In this state, the thin portion 50
5a, the central portion 506a is formed to have a depth in contact with the high-resistance substrate, and the thin portion 505a is formed.
The peripheral portion 506b is formed so as not to contact the high-resistance substrate and shallower than the central portion 506b due to diffusion from the periphery.

According to the method of manufacturing the LED array 500 described above, the diffusion depth is shallow around the diffusion opening 540a, and the diffusion depth is formed at the center of the diffusion opening 540a so as to contact the high-resistance substrate. An element isolation structure can be formed.

As described above, in this embodiment, the peripheral portion of the element isolation region is formed with a shallow diffusion depth, and the central portion of the element isolation region is formed with a large diffusion depth. Usually, the side diffusion caused by the impurity diffusion can be suppressed by reducing the diffusion depth. As a result, according to the present embodiment, the influence of side diffusion can be reduced as compared with a configuration in which the element isolation region is formed with a substantially uniform diffusion depth.

Therefore, according to the present embodiment, it is possible to make the width of the element isolation region narrower than before, and it is possible to provide an element isolation structure having a high yield even if the density of the light emitting portion is increased. . That is, according to the present embodiment, in the device isolation between the blocks, the device isolation can be performed by the small diffusion of the side diffusion. Therefore, the width of the device isolation region is reduced in the light emitting device array in which the high density light emitting unit rows are formed. It becomes possible.

(Fifth Embodiment) A light emitting element array and a method for manufacturing the light emitting element array according to a fifth embodiment will be outlined. The light emitting element array according to the present embodiment is different from the light emitting element array according to the fourth embodiment in the configuration for changing the diffusion depth between the central part and the peripheral part of the element isolation region. That is, in the light emitting element array according to the fourth embodiment, the layer thickness distribution of the contact layer is adjusted to realize the element isolation region, whereas in the light emitting element array according to the present embodiment, the contact layer Is formed with a uniform layer thickness, a diffusion control film corresponding to another control layer is provided on the diffusion mask to realize the element isolation region.
In other respects, the light emitting element array according to this embodiment is substantially the same as the light emitting element array according to the fourth embodiment.

A characteristic configuration of the light emitting element array according to the present embodiment will be described in comparison with the light emitting element array according to the fourth embodiment. In the light emitting element array according to the present embodiment, similarly to the light emitting element array according to the fourth embodiment, the diffusion depth at the center of the element isolation region comes into contact with the high-resistance substrate and the diffusion at the peripheral edge of the element isolation region. The structure has a shallow depth.

In the present embodiment, unlike the fourth embodiment, in order to realize such a configuration, a diffusion control film is further formed on a diffusion mask layer formed on a contact layer.
In the diffusion control film, a diffusion opening (referred to as a “second diffusion opening”) is formed at a central portion of the diffusion opening of the diffusion mask corresponding to the element isolation region.

In this embodiment, the second conductivity type impurity is diffused into the first conductivity type semiconductor layer through the diffusion control film, the diffusion mask layer, and the contact layer in this order, so that the high resistance substrate can be formed. An element isolation region having a central portion having a depth reaching the periphery and a peripheral portion having a depth not reaching the high resistance substrate, and a light emitting portion having a depth not reaching the high resistance substrate can be formed simultaneously.

FIG. 15 shows the results of experiments conducted by the inventors on the relationship between various diffusion control film thicknesses and diffusion depths.
In the experiment shown in FIG. 15, the material A is Al ₂ O ₃ (alumina), the material B is PSG (phosphosilicate glass), and the material C is SiN (silicon nitride).

According to the experimental results shown in FIG. 15, no matter which diffusion control film is used, as the diffusion control film becomes thicker, the diffusion depth becomes shallower. The diffusion control film used in the experiment shown in FIG. 15 is merely an example, and it is considered that the diffusion control film generally has the same tendency. Therefore, by adjusting the diffusion control film thickness, the diffusion depth into the semiconductor layer can be controlled.

In the element isolation structure according to the present embodiment, a diffusion control film is formed around the diffusion opening and no diffusion control film is formed at the center of the diffusion opening. Therefore, since the diffusion control film thickness is zero at the center of the diffusion opening, the p-type impurity diffuses into the epitaxial wafer faster than in the periphery of the diffusion opening where the diffusion control film thickness is positive.

As a result, in the element isolation structure according to the present embodiment, the diffusion depth at the central portion of the diffusion opening is formed larger than the diffusion depth at the peripheral portion of the diffusion opening. It can also be seen that if the thickness of the diffusion control film around the diffusion opening in the light emitting section and the element isolation region is the same, the light emitting section and the element isolation region can be formed in the same process.

Hereinafter, a multilayer wiring type LED array 600 will be specifically described as an example of the light emitting element array according to the present embodiment with reference to FIG. In addition, FIG.
Partial sectional view of the LED array 600, more specifically, LEDs
FIG. 2 is a partial cross-sectional view of a portion corresponding to a portion B of the LED array 600 shown in FIG. 1 in the array 600.

As shown in FIG. 13A, the LED array 600 has a high resistance substrate 6 functioning as a semi-insulating substrate.
02, an n-type semiconductor layer 604 formed epitaxially on the high-resistance substrate 602, and an n-type contact layer 605 formed epitaxially on the semiconductor layer 604.

In the LED array 600, the semiconductor layer 6
04 is a block 6 formed by forming an element isolation region 606.
08. Here, the element isolation region 606
Is a diffusion region of a p-type impurity, and an adjacent block 6
08 is formed.

In this embodiment, the element isolation region 606 has a different diffusion depth between the central portion 606a and the peripheral portion 606b. In the element isolation region 606, the central portion 60
6a reaches the high-resistance substrate 602,
The diffusion depth of the peripheral portion 606b does not reach the high-resistance substrate.

In the LED array 600, the light emitting section 61
Numeral 0 denotes a diffusion region of a p-type impurity formed by selective diffusion in the semiconductor layer 604, the diffusion depth of which is high.
02 has not been reached. LED array 6 according to the present embodiment
In 00, a light emitting phenomenon occurs in a pn junction formed by the light emitting unit 610 and the semiconductor layer 604 around the light emitting unit 610.

Further, similarly to the LED array 100 shown in FIG.
One p-side contact electrode is formed on each of the upper portions of the five light emitting portions 610. Also, each block 608
In the contact layer 605, one n-side contact electrode is formed in a predetermined portion other than a portion above the light emitting portion 610.

Further, in the LED array 600, a multilayer wiring for supplying a current to the light emitting section 610 via the p-side contact electrode and the n-side contact electrode is formed. The p-side contact electrode, the n-side contact electrode, and the multilayer wiring have substantially the same functions as the p-side contact electrode 112, the n-side contact electrode 114, and the multilayer wiring 120 according to the first embodiment shown in FIG. The detailed description is omitted.

The LED array 600 according to the present embodiment having the above-described configuration is different from the method of manufacturing the LED array 100 according to the first embodiment in the following step instead of the step shown in FIG. Can be realized by performing the following.

In this step, instead of partially removing the contact layer 105 in the step shown in FIG.
A diffusion control film in which a second diffusion opening is provided at the center of the diffusion opening 140a is formed on the first interlayer insulating film 140 which is a diffusion mask. The diffusion control film 68
For example, the material of the diffusion control film 680 is formed on the epitaxial wafer on which the first interlayer insulating film 640 is formed by forming the material of the diffusion control film 680 on the epitaxial wafer.
A second diffusion opening 680a is formed in the material of the diffusion control film 680 in the central portion of FIG.

In the method of manufacturing the LED array 600 described above, the diffusion source and the contact layer 605 come into direct contact with each other in the second diffusion opening 680 a in the diffusion doping of the p-type impurity into the semiconductor layer 604. Diffusion opening 6
In the portion where 80a is formed, the diffusion region reaches semiconductor layer 604 faster than in other portions.

Therefore, the diffusion opening 640a in which the second diffusion opening 680a is formed and the second diffusion opening 680a are formed.
The diffusion regions having different diffusion depths are formed with the diffusion openings 640a in which is not formed. That is, the element isolation region 606 and the light emitting portion 610 having different depths are formed in the semiconductor layer 604 at the same time.

Further, also in the diffusion opening 640a in which the second diffusion opening 680a is formed, the second diffusion opening 6a is formed.
The diffusion depth is different between the area under 80a and the surrounding area. That is, a central portion 606 a having a depth reaching the high resistance substrate 602 and a peripheral portion 606 b having a predetermined depth not reaching the high resistance substrate 602 are formed in one element isolation region 606. Here, the thickness of the thin portion 605 a is
6a can be arbitrarily determined so as to contact the high-resistance substrate 602.

Here, the diffusion doping of the p-type impurity into the semiconductor layer 604 will be described with reference to FIG. FIG. 13 is a conceptual diagram illustrating a state of the semiconductor layer 604 at a predetermined stage in the diffusion annealing process.

(Diffusion Annealing) FIG. 13A shows that
The state during the diffusion annealing in which the p-type impurity is diffused through the second diffusion opening 680a at the center of the diffusion opening 640a is shown. In the diffusion state at this point, the p-type impurity is mainly diffused from the second diffusion opening 680a to the semiconductor layer 604.

(After Diffusion Annealing) FIG. 13B shows a state after diffusion annealing. In this state, the central portion 606a is formed to have a depth in contact with the high-resistance substrate by diffusion from the second diffusion opening 680a, and the peripheral portion 606b is diffused from the periphery of the second diffusion opening 680a.
Are formed so as not to be in contact with the high-resistance substrate and shallower than the central portion 606a.

According to the method of manufacturing the LED array 600 described above, the diffusion depth is shallow around the diffusion opening 640a and the diffusion depth is in contact with the high-resistance substrate at the center of the diffusion opening 640a. An element isolation structure can be formed.

As described above, in the present embodiment, the peripheral portion of the element isolation region is formed with a shallow diffusion depth, and the central portion of the element isolation region is formed with a large diffusion depth. Usually, the side diffusion caused by the impurity diffusion can be suppressed by reducing the diffusion depth. As a result, according to the present embodiment, the influence of side diffusion can be reduced as compared with a configuration in which the element isolation region is formed with a substantially uniform diffusion depth.

Therefore, according to the present embodiment, it is possible to make the width of the element isolation region narrower than before, and it is possible to provide an element isolation structure having a high yield even when the density of the light emitting portion is increased. . That is, according to the present embodiment, in the device isolation between the blocks, the device isolation can be performed by the small diffusion of the side diffusion. Therefore, the width of the device isolation region is reduced in the light emitting device array in which the high density light emitting unit rows are formed. It becomes possible.

Although the preferred embodiment according to the present invention has been described above, the present invention is not limited to this configuration. A person skilled in the art can envisage various modified examples and modified examples within the scope of the technical idea described in the claims, and these modified examples and modified examples are also included in the technical scope of the present invention. It is understood to be included.

For example, in the above embodiment, the semiconductor device to which the single-layer type semiconductor layer is applied and the method of manufacturing the same have been described as an example, but the present invention is not limited to this configuration. The present invention can also be applied to a semiconductor device to which a multilayer semiconductor layer is applied and a method for manufacturing the same.

FIG. 16A shows an example of a semiconductor device having a multilayer semiconductor layer according to the present embodiment. FIG. 16B shows the results of experiments conducted by the inventors on impurity diffusion in a multilayer semiconductor layer. In this experiment, a semiconductor layer having a stacked optical waveguide structure in which a lower n-type clad layer, an n-type active layer, and an upper n-type clad layer were sequentially stacked was used as a semiconductor layer.

As can be seen by comparing FIG. 16B and FIG. 3, the depth of the diffusion region formed in the semiconductor layer is irrespective of whether the semiconductor layer is a single layer or a multilayer. It can be seen that the larger the contact layer becomes, the larger the contact layer becomes. Therefore, the present invention can be applied not only to a semiconductor device having a simple pn junction, but also to a semiconductor device having a stacked optical waveguide structure.
The present invention can be applied to a semiconductor layer provided with an ED, a semiconductor laser, an optical amplifier, an optical modulator, or the like.

In the above embodiment, G is used as the control layer.
Although the semiconductor device to which the contact layer made of aAs is applied and the method of manufacturing the semiconductor device have been described as examples, the present invention is not limited to such a configuration. The present invention can be applied to a semiconductor device to which a control layer made of other various materials, for example, a Si-based material, a glass-based material, a resin material, or the like is applied, and a manufacturing method thereof. That is, the material of the control layer is not particularly limited, and an appropriate material can be used according to the material of the semiconductor layer and the method of doping the semiconductor layer to be used.

Furthermore, in the above embodiment, the semiconductor device using Zn as the predetermined impurity and the method of manufacturing the same have been described as an example, but the present invention is not limited to this configuration. The present invention can be applied to a semiconductor device to which B, P, Sb, Al, An, As, Ga, In, or the like is applied as other various impurities, and a manufacturing method thereof.

Further, in the above embodiment, the semiconductor device using solid-phase diffusion as a method of doping impurities into a semiconductor layer and a method of manufacturing the same have been described as an example, but the present invention is not limited to such a configuration. The present invention provides various other impurity doping methods for doping the semiconductor layer, for example,
For example, the present invention can be applied to a semiconductor device using solid-phase diffusion, vapor-phase diffusion, ion implantation, thermomigration (heat transfer), and the like, and a manufacturing method thereof. That is, according to the present invention, it is only necessary to form a control structure for the impurity penetration distance to the semiconductor layer on the surface of the semiconductor layer and dope the semiconductor layer with the impurity through the control structure. This can be applied to a semiconductor device manufacturing method and a semiconductor device to which any impurity doping method is applied.

In the above embodiment, the method for forming the control layer is not particularly limited, and thus no particular reference is made to the method for forming the control layer. That is, as a method of forming the control layer, for example, various methods such as MBE and epitaxial growth using MOCVD (metal organic chemical vapor deposition) can be used.

[0166]

According to the present invention, a control layer for controlling the doping of the second conductivity type impurity into the semiconductor layer as a part of the epitaxial wafer is provided on the semiconductor layer of the first conductivity type, thereby providing mutual control. Impurity-doped regions having different depths can be simultaneously formed in the semiconductor layer. Therefore, the number of manufacturing steps of the semiconductor device is reduced, and in the semiconductor device and the method of manufacturing the semiconductor device, improvement in manufacturing efficiency, reduction in initial cost, improvement in yield, and the like can be achieved.

Further, according to the present invention, in one impurity-doped region, the peripheral portion is intentionally formed shallower than the central portion, thereby suppressing unnecessary spread of the impurity-doped region such as side diffusion. Can be. Therefore, it is possible to increase the density of the impurity-doped region formed in the semiconductor layer, and in the semiconductor device and the method of manufacturing the semiconductor device, it is possible to reduce the size, increase the functionality, and improve the yield of the device. .

Further, according to the present invention, by providing a control layer and another control layer, the depth of the impurity-doped region can be controlled by various methods. Therefore, it is possible to provide a semiconductor device and a method of manufacturing a semiconductor device capable of simultaneously forming impurity-doped regions having various types, structures, shapes, and the like.

[Brief description of the drawings]

FIG. 1 is a plan view showing a schematic configuration of a semiconductor device to which the present invention can be applied.

FIG. 2 is a partial cross-sectional view of the semiconductor device shown in FIG.

FIG. 3 is a data diagram of an experiment performed by the inventors.

FIG. 4 is a process chart for describing a method of manufacturing a semiconductor device to which the present invention can be applied.

FIG. 5 is another process drawing for explaining the method of manufacturing a semiconductor device to which the present invention can be applied.

FIG. 6 is a process chart for explaining a method of manufacturing a semiconductor device to which the present invention can be applied.

FIG. 7 is a process chart for describing a method of manufacturing a semiconductor device to which the present invention can be applied.

FIG. 8 is a partial cross section showing a schematic configuration of another semiconductor device to which the present invention can be applied.

FIG. 9 is a partial cross section showing a schematic configuration of another semiconductor device to which the present invention can be applied.

FIG. 10 is a partial cross section showing a schematic configuration of another semiconductor device to which the present invention can be applied.

FIG. 11 is a partial cross section showing a schematic configuration of another semiconductor device to which the present invention can be applied.

FIG. 12 is an explanatory diagram illustrating a method for manufacturing another semiconductor device to which the present invention can be applied.

FIG. 13 is a partial cross section showing a schematic configuration of another semiconductor device to which the present invention can be applied.

FIG. 14 is an explanatory diagram illustrating a method for manufacturing another semiconductor device to which the present invention can be applied.

FIG. 15 is a data diagram of another experiment by the inventors.

FIG. 16 is an explanatory diagram illustrating another semiconductor device and a method for manufacturing the semiconductor device of the present invention.

FIG. 17 is an explanatory diagram illustrating a schematic configuration of a conventional LED array.

FIG. 18 is an explanatory diagram of one problem of a conventional LED array and a method of manufacturing the LED array.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 LED array 102 High resistance substrate 104 Semiconductor layer 105 Contact layer 105 a Thin layer portion 106 Element isolation region 108 Block 110 Light emitting portion 140 First interlayer insulating film 140 a Diffusion opening 120 Multilayer wiring 122 Individual wiring 124 Common wiring 305 a Opening 404 a Groove 680 Diffusion control layer 680a Second diffusion opening

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mitsuhiko Ogihara 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Hiroshi Hamano 1-7-12 Toranomon, Minato-ku, Tokyo Offshore F term (reference) in Electric Industries, Ltd. 5F041 AA41 AA42 CA35 CA36 CA46 CA53 CA72 CA74 CB24 FF13

Claims (15)

[Claims] 1. A method of manufacturing a semiconductor device having a semiconductor layer, comprising: a first step of epitaxially forming a control layer on the semiconductor layer for controlling a distance of a predetermined impurity from entering the semiconductor layer; A second step of doping the predetermined impurity through a control layer to form two or more impurity-doped regions in the semiconductor layer. 2. The method according to claim 2, further comprising, before the second step, adjusting a layer thickness distribution of the control layer. In the second step, a distance of the predetermined impurity into the semiconductor layer is reduced. 2. The method according to claim 1, wherein the method depends on the thickness of the control layer. 3. The method according to claim 1, further comprising: before the second step, forming a mask layer having an opening in a corresponding portion of the impurity-doped region on the control layer; Part or all of the control layer below the opening is thinned by etching to adjust the layer thickness distribution of the control layer. In the second step, the predetermined impurity is interposed through the opening and the control layer. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor layer is doped. 4. The method according to claim 1, further comprising: before the second step, forming a mask layer having an opening in a corresponding portion of the impurity-doped region on the control layer; Adjusting a layer thickness distribution of the control layer by removing a part or all of the control layer below the opening, and in the second step, removing the predetermined impurity through the opening and the control layer. 4. The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor layer is doped. 5. A step of forming a mask layer having an opening in a corresponding portion of the impurity-doped region on the control layer before the second step. Forming a further control layer for controlling a distance at which a predetermined impurity enters the semiconductor layer; and a sixth step;
In the step, the predetermined impurity is doped into the semiconductor layer through the other control layer, the opening, and the control layer;
2. The method for manufacturing a semiconductor device according to claim 1, wherein: 6. A method of manufacturing a semiconductor device having a semiconductor layer, comprising: forming a groove partially in a surface region of the semiconductor layer; and a step of forming a groove in the semiconductor layer and a bottom of the groove in the semiconductor layer and the semiconductor layer. An eighth step of simultaneously forming an impurity-doped region by doping a predetermined impurity from the surface region side with a portion other than the groove. 7. In the second step, as the impurity-doped regions separated from each other, two or more light-emitting portions and an isolation region that is separated into two or more blocks each including at least one light-emitting portion are included. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed on a semiconductor layer. 8. The semiconductor device according to claim 1, wherein in the second step, the semiconductor layer is doped with the predetermined impurity by solid phase diffusion. 13. The semiconductor device according to claim 1. 9. A semiconductor device comprising a semiconductor layer, comprising:
A control layer which is formed epitaxially on the semiconductor layer and controls a distance at which a predetermined impurity enters the semiconductor layer; and a control layer formed on the semiconductor layer by doping the predetermined impurity through the control layer. A semiconductor device comprising: an impurity-doped region as described above; 10. The semiconductor layer, wherein the semiconductor layer is separated into two or more light-emitting portions and two or more blocks each including at least one light-emitting portion as the impurity-doped regions separated from each other. The semiconductor device according to claim 9, wherein the region is formed. 11. The isolation region is formed deeper than the light emitting portion, and a part or all of the control layer is formed thinner than other portions of the control layer above the isolation region. The semiconductor device according to claim 10, wherein: 12. The control device according to claim 12, wherein the isolation region is formed deeper than the light emitting portion, and a part or all of the control layer is removed in an upper portion of the isolation region. Item 12. The semiconductor device according to item 10 or 11. 13. The semiconductor device according to claim 10, wherein a peripheral portion of said isolation region is formed shallower than a central portion of said isolation region. 14. The control layer according to claim 1, wherein:
The entry speed of the predetermined impurity is low,
14. The semiconductor device according to claim 9, 10, 11, 12, or 13. 15. The semiconductor layer according to claim 1, wherein the main component is AlGaAs.
s, the main component of the control layer is GaAs, and the impurity-doped region is formed in the semiconductor layer by doping the predetermined impurity by thermal diffusion. Claims 9, 10, 11, 1
16. The semiconductor device according to any one of 2, 14, and 15.