JPH0983015A - Fabrication of monolithic light emitting diode array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fabricate a monolithic light emitting diode array in which the depth of pn junction can be controlled accurately for each light emitting diode while suppressing fluctuation. SOLUTION: An SiO2 selective growth mask 12 is formed on an n-GaAs substrate 10. The mask 12 has a window 14 for exposing a light emitting region, an isolating part 16 covering the isolating region around the light emitting region, a pad part 18 covering a bond pad region, and a lead-out part 20 covering an electrode lead-out region. An n-InGaP clad layer, a nondoped InGaAsP active layer, a p-InGaP clad layer and a p-GaAs contact layer are then grown sequentially on the exposed substrate 10. These semiconductor layers constituting a light emitting diode having double heterostructure are epitaxially grown selectively such that they are not grown on the mask 12 by regulating the width of mask 12, the temperature and pressure of epitaxial growth appropriately. The problem can be solved because each light emitting diode can be formed while being isolated not by diffusion but by selective epitaxial growth.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a monolithic light emitting diode array formed on a GaAs substrate.

[0002]

2. Description of the Related Art A monolithic light emitting diode array is used, for example, as a linear light source, and a manufacturing method thereof is disclosed in Japanese Patent Publication No. 6-36436. In this conventional method, p-GaAlAs is formed on a GaAs substrate.
First carrier confinement layer (lower clad layer), p-Ga
The AlAs active layer and the n-GaAlAs second carrier confinement layer (upper clad layer) are sequentially epitaxially grown, and then p-type impurities are selectively diffused into a specific portion of the light emitting region to form a plurality of arrays. Each of the light emitting diodes is electrically isolated and defined.

[0003]

However, in the above-mentioned conventional method, when the crystal growth is performed once and then the heat treatment such as the impurity diffusion is performed at a high temperature, the impurities in the already crystal-grown portion are also diffused. However, there is a problem that the position of the pn junction is displaced and the luminous efficiency is lowered. Moreover, when the displacement of the pn junction becomes non-uniform, the light emission intensity varies greatly among the light emitting diodes forming the array.

Further, in the above-mentioned conventional method, the individual light emitting diodes are electrically separated by selectively diffusing the impurities through the diffusion mask. This diffusion mask is desired to be one that withstands heating at high temperature for a long time and has few pinholes. However, in order to form a film with few pinholes that is suitable for diffusion processing, it is necessary to strictly control the film forming conditions and the film forming environment, and it is not easy to form the film. Therefore, it is also possible to stack the films in multiple layers to form a diffusion mask with few pinholes, but in this case, the number of steps is increased.

[0005]

In order to solve the above-mentioned problems, a method for manufacturing a monolithic light-emitting diode array according to the invention of claim 1 is such that light-emitting regions are arranged in a matrix.
In manufacturing a monolithic light emitting diode array by forming a double heterostructure light emitting diode in each light emitting region, a dielectric film is used on a GaAs substrate of the first conductivity type, and the substrate surface portion of the light emitting region is exposed. A step of forming a selective growth mask for covering the substrate surface portion of the isolation region, a first conductivity type InGaP lower cladding layer, a first conductivity type, a second conductivity type or a non-doped InGaAsP active layer, and a second conductivity type InGaP upper cladding layer, and
And a step of selectively crystallizing the second conductivity type GaAs contact layer on the surface portion of the substrate exposed outside the selective growth mask.

According to this method, the selective growth mask is first formed on the GaAs substrate of the first conductivity type. Various dielectric films having an insulating property can be used for this selective growth mask, for example, a SiO ₂ film or a Si ₃ N ₄ film can be used. This selective growth mask serves to pattern the light emitting region and at the same time electrically separates the respective light emitting diodes. Therefore, after the crystal growth of each semiconductor layer constituting the light emitting diode, a diffusion process is performed for element separation. The need to do it can be omitted.

Next, on a GaAs substrate of the first conductivity type, a first conductivity type InGaP lower clad layer, a first conductivity type, a second conductivity type or an undoped InGaAsP active layer, and a second conductivity type InGaP upper clad layer. Layer, second conductivity type G
Crystal growth of each layer of the aAs contact layer is sequentially performed.

The crystal growth is performed so that each of these semiconductor layers is selectively grown on a portion other than the portion covered with the selective growth mask. For example, by using a vapor phase growth method such as a metal organic chemical vapor deposition method or a chemical beam epitaxy method and appropriately adjusting the width of the selective growth mask, the temperature and pressure during crystal growth, and performing crystal growth, Selective growth can be performed. Further, the selective growth can also be performed by using the liquid phase growth method and appropriately adjusting the width of the selective growth mask and the temperature during the crystal growth to perform the crystal growth. In order to obtain a semiconductor layer having good crystallinity and to accurately control the layer thickness of the semiconductor layer, crystal growth is performed by using a vapor phase growth method, particularly a metal organic chemical vapor deposition method or a chemical beam epitaxy method. Is preferred.

The double-hetero structure light-emitting diode obtained by stacking these semiconductor layers of the lower clad layer, the active layer, the upper clad layer and the contact layer is dramatically improved as compared with the homo-structure light emitting diode. Has luminous efficiency.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. However, the drawings used for the description merely show the shapes, dimensions, and positional relationships of the respective constituent components to the extent that the present invention can be understood. In addition, in each drawing, the same components are denoted by the same reference numerals, and the duplicate description thereof will be omitted. In addition, it will be apparent to those skilled in the art that various modifications or changes can be made to the present invention, and the present invention is not limited to the following modes in any sense.

1. First Embodiment FIGS. 1A to 1D are sectional views showing step by step the main steps of the first embodiment, showing a manufacturing process focusing on one element of a monolithic light emitting diode array. . FIG. 2 is a plan view showing a state of the same process step as FIG. 1A, and FIG. 3 is a sectional view showing a state of the same process step as FIG.

1 (A) to 1 (D) show cross sections corresponding to the cross section taken along the line I--I of FIG. 2, and FIG. 3 shows II of FIG.
1 is a cross-section corresponding to the cross-section taken along line II in FIG.
The cross section orthogonal to (D) is shown.

(1) A step of forming a selective growth mask using a dielectric film on a GaAs substrate of the first conductivity type to expose the substrate surface portion of the light emitting region and cover the substrate surface portion of the element isolation region.

First, the substrate surface 10a of the n-GaAs substrate 10
A SiO ₂ dielectric film for forming a selective growth mask is laminated thereon to a film thickness of about 0.3 μm by a sputtering method or a thermal CVD method, and then S and S are formed by a photolithography and etching technique.
Selective growth mask 1 by patterning the iO ₂ dielectric film
2 is formed (FIGS. 1A and 2).

The selective growth mask 12 has a light extraction window 14 which exposes the substrate surface portion of the light emitting region, an element isolation portion 16 which covers the substrate surface portion of the element isolation region which also serves as an electrode formation region, and in addition to these, It has a pad portion 18 that covers the bonding pad region and an electrode lead portion 20 that covers the element isolation region to the bonding pad region. The periphery of each light emitting region arranged in a matrix is surrounded by the element separating portion 16, and each light emitting region is separated into an island shape by the element separating portion 16. In FIG. 2, the light emitting region is shown surrounded by a chain line.

The pattern shape and dimensions of the selective growth mask 12 can be arbitrarily set according to the design. However, in order to prevent crystal growth on the selective growth mask 12,
It is necessary to properly select the width of the selective growth mask 12. Although depending on the crystal growth conditions, here, the width of the selective growth mask 12 is set to, for example, 50 μm or less to prevent crystal growth on the selective growth mask 12.

For example, considering the case of manufacturing a monolithic light emitting diode array in which light emitting regions are linearly arranged and used as a linear light source, the light emitting dot density is 62.5 μm.
m (400 DPI), the element isolation portion 16 has a square pattern with a width W ₁ of 10 μm, the spacing W ₂ between adjacent element isolation portions 16 is 2.5 μm, and the light extraction window 14 has a width of 40 μm. The width of the rectangular window and pad section 18 is 50
It can be a μm rectangular pattern.

In the illustrated example, the selective growth masks 12 are formed separately for each light emitting region. However, with the spacing W ₂ = 0, the selective growth masks 12 are formed integrally without being separated. May be.

Further, since the element isolation is carried out without causing the crystal growth on the selective growth mask 12, the diffusion process is unnecessary. In the case of the diffusion mask, it was necessary to strictly control the production conditions and the production environment in order to form those with few pinholes suitable for the diffusion process. Strict control is not required, and a film that is easier to prepare than a diffusion mask, for example, a SiO ₂ or Si ₃ N ₄ film used for ordinary electrical insulation is used.
The selective growth mask 12 can be formed. Alternatively, in the case of the diffusion mask, it was necessary to form a mask with few pinholes as a multilayer film, but in the case of the selective growth mask 12,
Since it is not necessary to form a multi-layered film like a diffusion mask to reduce pinholes, there is also an advantage that the number of steps can be reduced.

(2) First conductivity type InGaP lower clad layer, first conductivity type, second conductivity type or undoped I
an nGaAsP active layer, a second conductivity type InGaP upper cladding layer, and a second conductivity type GaAs contact layer,
A step of selectively growing crystals on the surface of the substrate exposed outside the selective growth mask.

Next, the n-InGaP lower clad layer 22,
Non-doped InGaAsP active layer 24, p-InGaP
Upper cladding layer 26 and p-GaAs contact layer 28
By a vapor phase epitaxy method such as a metal organic vapor phase epitaxy method (MOVP).
E) or chemical beam epitaxy (CBE) or the like is used to sequentially perform crystal growth on the exposed substrate surface 10a without being covered with the selective growth mask 12 (FIG. 1B).

As described above, the width of the selective growth mask 12 is set to 5
Since the crystal growth temperature is 0 μm or less, the crystal growth temperature and the crystal growth pressure during vapor phase growth are set to 680 ° C. and 55 Torr, respectively, so that the crystal is not grown on the selective growth mask 12 and is not covered with the selective growth mask 12. Crystals can be grown on the exposed substrate surface 10a.

The substrate surface 10a in the light emitting region is exposed through the light extraction window 14 of the selective growth mask 12, and therefore, the lower cladding layer 22, the active layer 24, which are sequentially stacked on the substrate surface 10a in the light emitting region, The upper clad layer 26 and the contact layer 28 can form a light emitting diode having a double hetero structure.

Moreover, the light emitting regions of the respective light emitting diodes forming the array are separated into islands by the selective growth mask 12 having an insulating property, and crystal growth does not occur on the selective growth mask 12, so that they are formed in the respective light emitting regions. The light emitting diode can be separated into elements.

The thickness and carrier concentration of each layer forming the light emitting diode are preferably set so that the emission intensity becomes maximum. The composition of the non-doped InGaAsP active layer 24 can be appropriately determined so that a desired emission wavelength can be obtained under the condition that it is within the composition range in which the n-GaAs substrate 10 is lattice-matched. For example, when the longest wavelength is desired, the composition formula In _x Ga _1-x As _y P
_{In 1-y} , x may be brought close to 0 and y may be brought close to 1, and conversely, when the shortest wavelength is desired, x may be brought close to 0.5 and y should be brought close to 0.

For example, in order to maximize the emission intensity when the emission wavelength is 740 nm, the thickness of the n-InGaP lower cladding layer 22 is 0.3 μm and the carrier concentration is 1 × 10 ¹⁸ cm ^-3 . Non-doped InGaAsP active layer 2
4 has a thickness of 0.2 μm, the p-InGaP upper cladding layer 26 has a thickness of 0.3 μm, and the carrier concentration is 1 × 10 ^18.
cm ⁻³ , the thickness of the p-GaAs contact layer 28 is 0.1
The μm and carrier concentration are preferably set to 1 × 10 ¹⁹ cm ⁻³ .

(3) A step of forming an electrode from a part of the light emitting region on the contact layer to a selective growth mask, and using the electrode as a mask to selectively remove the exposed contact layer of the light emitting region by etching.

Next, in order to form an electrode 30 connected to the p-GaAs contact layer 28 in the light emitting region, the electrode material is laminated on the p-GaAs contact layer 28 and the selective growth mask 12 over the entire substrate surface 10a. Here, the electrode material is an Au / Zn alloy (an alloy of Au and Zn).
And Au, and these Au / Zn alloy and Au are sequentially laminated on the p-GaAs contact layer 28 by the vapor deposition method. The Au / Zn alloy is an electrode material for ohmic-connecting the electrode 30 to the p-GaAs contact layer 28, and Au is an electrode material for facilitating bonding with a bonding wire.

After that, the electrode material is etched by photolithography and etching techniques to form p-Ga in the light emitting region.
An electrode 30 is formed from a part of the As contact layer 28 to the selective growth mask 12 (FIG. 1C). Electrode 30
Are individually separated for each light-emitting diode forming the array and electrically separated. A gap provided between the adjacent electrodes 30 for this electrical separation is indicated by reference numeral 32 in FIG.

Here, the p-GaAs contact layer 28 in the peripheral portion of the light emitting region is covered with an electrode 30 over the entire periphery of the light emitting region (see FIGS. 1D and 3), and the p-GaAs contact in the central portion of the light emitting region is formed. A window 30a exposing the layer 28 is formed in the electrode 30. By covering the p-GaAs contact layer 28 around the entire periphery of the light emitting region in this manner, it is possible to promote uniform current injection over the entire light emitting region, and thus to increase the emission intensity.

The electrode 30 may be formed by the lift-off method. If the lift-off method is used, p
A resist mask is formed on the GaAs contact layer 28 and the selective mask 12 to expose a region where the electrode 30 is formed (electrode forming region) and cover a region where the electrode 30 is not formed (electrode non-forming region). Then, an electrode material is laminated on the resist mask, and thereafter, the electrode material in the electrode non-forming region is removed together with the resist mask to obtain the electrode 30 made of the electrode material remaining in the electrode forming region.

Next, using the electrode 30 as an etching mask, the p-G exposed in the light emitting region without being covered with the electrode 30 is exposed.
The aAs contact layer 28 is removed by etching, and p-I
The nGaP upper cladding layer 26 is exposed (FIG. 1D).
And FIG. 3).

At this time, H ₂ SO ₄ as an etchant for etching the p-GaAs contact layer 28,
When the p-GaAs contact layer 28 is etched by wet etching using a mixed solution of H ₂ O ₂ and H ₂ O, this etchant does not etch the p-InGaP upper cladding layer 26.
It can be stopped when it reaches the nGaP upper cladding layer 26.

Further, since the electrode 30 made of Au / Zn alloy and Au has resistance to the etchant of the p-GaAs contact layer 28, it is necessary to use the electrode 30 as an etching mask to form a separate etching mask. Therefore, the process can be simplified and the process can be simplified.

Next, although not shown, on the other substrate surface 10b of the n-GaAs substrate 10 (see FIG. 1D), an ohmic electrode common to each light emitting diode forming the array is formed to form a monolithic substrate. A light emitting diode array is completed.

2. Second Embodiment In the second embodiment, the electrode 30 does not have resistance to an etchant for etching the p-GaAs contact layer 28, but the electrode 30 is formed using an inexpensive electrode material, for example, Al. It is a suitable embodiment in some cases.

FIGS. 4A to 4C are sectional views showing the main steps of the second embodiment in stages, showing the manufacturing steps focusing on one element of the monolithic light emitting diode array. 4A to 4D show cross sections corresponding to the cross section taken along the line I-I in FIG.

The points different from the first embodiment will be described below, and the detailed description of the same points as those of the first embodiment will be omitted.

(1) A step of forming a selective growth mask by using a dielectric film on a GaAs substrate of the first conductivity type and exposing the substrate surface portion of the light emitting region and covering the substrate surface portion of the element isolation region.

First, SiO ₂ is deposited on the n-GaAs substrate 10.
The selective growth mask 12 is formed (FIG. 1A).

(2) First conductivity type InGaP lower clad layer, first conductivity type, second conductivity type or undoped I
an nGaAsP active layer, a second conductivity type InGaP upper cladding layer, and a second conductivity type GaAs contact layer,
A step of selectively growing crystals on the surface of the substrate exposed outside the selective growth mask.

Next, the n-InGaP lower clad layer 22,
Non-doped InGaAsP active layer 24, p-InGaP
Upper cladding layer 26 and p-GaAs contact layer 28
Of the substrate surface 1 exposed without being covered with the selective growth mask 12.
Crystals are sequentially grown on 0a (FIG. 1 (B)).

(3) A step of forming an etching mask so as to cover a part of the light emitting region on the contact layer, and selectively etching away the exposed contact layer of the light emitting region.

Next, an etching mask 34 made of resist or SiO ₂ is formed (FIG. 4A). here,
The etching mask 34 covers the selective growth mask 12 and the p-GaAs contact layer 28 in the peripheral portion of the light emitting region over the entire periphery of the light emitting region, and exposes the p-GaAs contact layer 28 in the central portion of the light emitting region. 34a.

Then, the p-GaAs contact layer 28 exposed in the light emitting region is removed by etching through the etching mask 34 to expose the p-InGaAsP upper cladding layer 26 in the light emitting region (FIG. 4B). This etching may be performed by wet etching using a mixed solution of H ₂ SO ₄ , H ₂ O ₂ and H ₂ O as an etchant.

(4) After removing the etching mask, a step of forming an electrode on the contact layer portion remaining in the light emitting region from the contact layer portion to the selective growth mask on the upper side thereof.

Next, the etching mask 34 is removed. When the etching mask 34 is formed of a resist, a resist removing agent is used, and the etching mask 34 is made of SiO 2.
If it is formed of ₂ , HF may be used.

After that, the Al electrode 3 is formed by the lift-off method.
0 is formed (FIG. 4C). Here, the Al electrode 30
Is formed from the p-GaAs contact layer 28 left in the peripheral portion of the light emitting region to the selective growth mask 12. In this case, since the Al electrode 30 is connected to the p-GaAs contact layer 28 at the peripheral portion of the light emitting region over the entire peripheral region of the light emitting region, it is possible to promote uniform current injection over the entire light emitting region, Therefore, the emission intensity can be increased.

Next, although not shown, on the other substrate surface 10b of the n-GaAs substrate 10 (see FIG. 1D), an ohmic electrode common to each light emitting diode forming the array is formed to form a monolithic substrate. A light emitting diode array is completed.

The invention is not limited to the above-mentioned embodiments, and therefore various modifications can be made within the scope of the invention as described below.

In both the first and second embodiments described above, the p-GaAs contact layer 28 in the light emitting region is partially removed by etching, and the p-InGa in the light emitting region is removed.
Since the P upper clad layer 26 is exposed, p-Ga
When the As contact layer 28 has a large light absorption, the light output can be improved.

However, when the light absorption of the p-GaAs contact layer 28 is small, p-Ga in the light emitting region is formed.
It is not necessary to etch away the As contact layer 28 to expose the p-InGaP upper cladding layer 26 in the light emitting region. This is because the p-GaAs contact layer 28 left over the entire light emitting region promotes uniform current injection over the entire light emitting region, which is considered to contribute to the improvement of light output. In this case, the p-GaAs contact layer 28 is left over the entire light emitting region, and the p-GaAs contact layer 2 is formed.
The electrode 30 may be formed from a part of 8 to the selective growth mask 12.

The first conductivity type may be n-type and second conductivity type p-type, and the first conductivity type may be p-type and the second conductivity type may be n-type. Further, the active layer may be a non-doped layer or a layer of the first conductivity type or the second conductivity type.

[0054]

As is apparent from the above description, according to the method for manufacturing a monolithic light emitting diode array of the present invention, the pn junction of the light emitting diode is formed by crystal growth instead of impurity diffusion, so that the pn junction depth is increased. Can be controlled with high accuracy, and variation in pn junction depth can be reduced. Therefore, the light emission efficiency of the light emitting diode can be improved, and the variation in the light emission intensity among the light emitting diodes can be reduced.

Further, it is said that each light emitting diode can be formed in a device-isolated state by a simple process of selectively crystallizing the semiconductor layer constituting each light emitting diode on the surface of the substrate exposed outside the selective growth mask. There are advantages.

[Brief description of drawings]

1A to 1D are cross-sectional views showing stepwise the main steps of the first embodiment.

FIG. 2 is a plan view showing a state of the same process step as FIG.

FIG. 3 is a cross-sectional view showing a state in the same process step as FIG.

FIGS. 4A to 4C are cross-sectional views showing the main steps of the second embodiment in stages.

[Explanation of symbols]

10: n-GaAs substrate 12: SiO ₂ selective growth mask 22: n-InGaP lower clad layer 24: undoped InGaAsP active layer 26: p-InGaP upper clad layer 28: p-GaAs contact layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshinori Yamauchi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (3)

[Claims] 1. When manufacturing a monolithic light emitting diode array by arranging light emitting regions in a matrix and forming a light emitting diode of a double hetero structure in each light emitting region, a dielectric film is formed on a GaAs substrate of the first conductivity type. A step of forming a selective growth mask for exposing the substrate surface portion of the light emitting region and covering the substrate surface portion of the element isolation region, and using a first conductivity type InGaP lower clad layer, a first conductivity type,
A second conductivity type or non-doped InGaAsP active layer, a second conductivity type InGaP upper clad layer, and a second conductivity type GaAs contact layer are selectively crystal-grown on the substrate surface portion exposed outside the selective growth mask. A method of manufacturing a monolithic light emitting diode array, comprising: 2. The method for manufacturing a monolithic light emitting diode array according to claim 1, wherein an electrode is formed from a part of the contact layer of the light emitting region to a selective growth mask, and the electrode is used as a mask to form the light emitting region of the light emitting region. A method of manufacturing a monolithic light emitting diode array, comprising the step of selectively etching away the exposed contact layer. 3. The method for manufacturing a monolithic light emitting diode array according to claim 1, wherein an etching mask is formed to cover a part of the contact layer in the light emitting region, and the contact layer exposed in the light emitting region is selectively formed. A monolithic light-emitting diode, comprising: a step of removing by etching; and a step of removing the etching mask and then forming an electrode on the upper side of the contact layer portion remaining in the light emitting region through a selective growth mask. Array manufacturing method.