JP3500310B2 - Light emitting diode array - Google Patents
Light emitting diode arrayInfo
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- JP3500310B2 JP3500310B2 JP24420498A JP24420498A JP3500310B2 JP 3500310 B2 JP3500310 B2 JP 3500310B2 JP 24420498 A JP24420498 A JP 24420498A JP 24420498 A JP24420498 A JP 24420498A JP 3500310 B2 JP3500310 B2 JP 3500310B2
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- type semiconductor
- semiconductor layer
- electrode
- conductivity type
- light emitting
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Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は発光ダイオードアレ
イに関し、特にぺージプリンタ用感光ドラムの露光源な
どに用いられる発光ダイオードアレイに関する。
【０００２】
【従来の技術および発明が解決しようとする課題】従来
の発光ダイオードアレイを図４および図５に示す。図５
は、図４中のＡ−Ａ線断面図である。図４および図５に
おいて、２１は半導体基板、２２は一導電型半導体層、
２３は逆導電型半導体層、２４は第１の電極、２５は第
２の電極である。
【０００３】半導体基板２１上に一導電型半導体層２２
を設けると共に、この一導電型半導体層２２上に一導電
型半導体層２２よりも小面積な逆導電型半導体層２３を
設け、一導電型半導体層２２の露出部Ｒに第１の電極２
４（２４ａ、２４ｂ）を接続して設けると共に、逆導電
型半導体層２３に第２の電極２５を接続して設けてい
る。なお、図５中、２６は窒化シリコン膜などから成る
絶縁膜である。
【０００４】このように構成すると、第１の電極２４と
第２の電極２５を半導体基板２１の同じ側に一回の工程
で同時に形成できることから、発光ダイオードアレイの
製造工程が簡略化されると共に、ワイヤボンディング法
などによる外部回路との接続作業も容易になる。
【０００５】また、第１の電極２４（２４ａ、２４ｂ）
は、図４に示すように、隣接する一導電型半導体層２２
が異なる群に属するように二群に分けて設けられ、第２
の電極２５は異なる群に属し、且つ隣接する逆導電型半
導体層２３が同じ第２の電極２５に接続されるように設
けられている。
【０００６】この従来の発光ダイオードアレイでは、隣
接する一導電型半導体層２２の反対の端部側が交互に露
出するように発光素子列の両側に振り分けて露出部Ｒを
設け、この露出部Ｒに第１の電極２４（２４ａ、２４
ｂ）を接続したものであり、第２の電極２５も隣接する
逆導電型半導体層２３ごとに反対の端部側に接続して設
けられている。
【０００７】ところが、第２の電極２５を逆導電型半導
体層２３の両端部側に交互に接続して設けると、第２の
電極２５の形成過程でマスクパターンに位置ずれが発生
した場合、隣接する発光素子の発光部の面積が変化し、
発光素子ごとに発光ばらつきが発生するという問題があ
った。
【０００８】そこで、本発明者等は特願平９−１７２５
８４号において、図６および図７に示すように、基板３
１上に島状の一導電型半導体層３２を列状に複数設け、
この一導電型半導体層３２の同じ端部側に露出部Ｒが形
成されるように、この一導電型半導体層３２上に逆導電
型半導体層３３を積層して設け、この隣接する逆導電型
半導体層３３毎に同じ第１の電極３５を接続して設ける
と共に、異なる第１の電極３５が接続された逆導電型半
導体層３３下の一導電型半導体層３２の露出部に同じ第
２の電極３４（３４ａ、３４ｂ）が接続されるようにし
た発光ダイオードアレイを提案した。
【０００９】このように同じ端部側の露出部Ｒに第２の
電極３４（３４ａ、３４ｂ）を接続して設け、逆導電型
半導体層３３の同じ側に第１の電極３５を接続して設け
ると、第１の電極３５の形成過程で電極パターンに位置
ずれが発生しても、全ての発光素子で同様な位置ずれが
発生することから、発光素子ごとの発光ばらつきは発生
しない。なお、同一基板上の発光素子全体の発光強度は
電流を調整することによって容易に調整できる。
【００１０】ところが、上述のような構成では、図８に
示すように、最端部の配線をＢ−Ｂ線部分でカットし
て、島状になる第２の電極３４（３４ｃ）を外部回路に
別途接続したり、図９に示すように、最端部の一導電型
半導体層３２ａのみは発光素子列の反対の端部側に露出
部Ｒを形成して、第２の電極３４ｂを接続すると共に、
逆導電型半導体層３３の対向する側に第１の電極３５を
接続したりするが、前者の場合は外部回路との接続が難
しくなり、後者の場合は最端部の発光素子のみは位置ず
れの影響を受けて、発光ばらつきの原因になったり、最
端部の発光素子のみが素子内の発光強度分布が異なるの
で、印画むらを引き起こすという欠点を有していた。
【００１１】本発明は上記欠点に鑑みてなされたもので
あり、すべての発光素子において電極パターンの位置ず
れに起因する発光素子の発光ばらつきを解消し、またす
べての発光素子において発光素子の発光強度分布を均一
化することのできる発光ダイオードアレイを提供するも
のである。
【００１２】
【課題を解決するための手段】上述の目的を達成するた
めに、本発明の発光ダイオードアレイでは、基板上に島
状の一導電型半導体層を列状に複数設け、この複数の一
導電型半導体層の同じ端部側に露出部が形成されるよう
に、この一導電型半導体層上に逆導電型半導体層を積層
して設け、この隣接する逆導電型半導体層毎に同じ第１
の電極を接続して設けると共に、異なる第１の電極が接
続された逆導電型半導体層下の前記一導電型半導体層の
露出部に同じ第２の電極が接続されるようにした発光ダ
イオードアレイにおいて、前記列状に設けた最端部の露
出部に、前記第２の電極を前記島状半導体層の間を経由
して接続したことを特徴とする。
【００１３】
【作用】上記のように構成すると、全露出部が同様に配
置されることから、電極パターンの位置ずれに起因する
発光素子の発光ばらつきがなく、すべての発光素子につ
いて発光強度分布が同様となって、印画品質が向上す
る。
【００１４】
【発明の実施の形態】以下、本発明の実施形態を添付図
面に基づき詳細に説明する。図１、図２は本発明に係る
発光ダイオードアレイの一実施形態を示す図であり、図
３は図１中のＡ−Ａ線断面図である。図１、図２および
図３において、１は基板、２は一導電型半導体層、３は
逆導電型半導体層、４は第１の電極、５（５ａ、５ｂ）
は第２の電極である。
【００１５】基板１は、例えばシリコン（Ｓｉ）やガリ
ウム砒素（ＧａＡｓ）などの単結晶半導体基板、あるい
はサファイア（Ａｌ2 Ｏ3 ）などの単結晶絶縁基板から
成る。基板１として半導体基板を用いる場合でも、でき
るだけ高抵抗な半導体基板を用いることが望ましい。ま
た、単結晶半導体基板の場合、（１００）面などが用い
られ、サファイアの場合、Ｃ面などが用いられる。
【００１６】一導電型半導体層２は、ガリウム砒素やガ
リウム砒素とアルミニウムガリウム砒素の多層膜などか
ら成り、例えばシリコンやセレン（Ｓｅ）などの一導電
型半導体不純物をｌ×１０16〜１０19ａｔｏｍ／ｃｍ3
程度含有する。この一導電型半導体層２は、例えばＭＯ
ＣＶＤ法やＭＢＥ法などで形成される。すなわち、基板
１として半導体基板を用いてＭＯＣＶＤ法で形成する場
合、半導体基板の自然酸化膜を８００〜１０００℃の高
温で除去し、次に４５０℃以下の低温で核となるアモル
ファスガリウム砒素膜を０．１〜２μｍ程度の厚みに成
長させた後、５００〜７００℃まで昇温して再結晶化し
てガリウム砒素単結晶を成長させる（二段階成長法）。
この場合、ガリウムの原料としてはトリメチルガリウム
（（ＣＨ3 ）3 Ｇａ）などが用いられ、砒素の原料とし
てはアルシン（ＡｓＨ3 ）などが用いられる。次に、７
５０〜１０００℃の高温でのアニールと６００℃以下の
低温への急冷を数回繰り返す（温度サイクル法）等のポ
ストアニールを行う。ガリウム砒素とアルミニウム砒素
の二層構造にする場合は、さらにアルミニウムガリウム
砒素層を形成する。アルミニウムの原料としては、トリ
メチルアルミニウム（（ＣＨ3 ）3 Ａｌ）などが用いら
れる。
【００１７】一導電型半導体層２上には、逆導電型半導
体層３が形成される。逆導電型半導体層３も、アルミニ
ウムガリウム砒素（ＡｌＧａＡｓ）などの化合物半導体
から成り、亜鉛（Ｚｎ）やストロンチウム（Ｓｒ）など
の逆導電型半導体不純物を１×１０18〜１０19ａｔｏｍ
／ｃｍ3 程度含有する。一導電型半導体層２と逆導電型
半導体層３の界面部で半導体接合部が形成される。この
一導電型半導体層２と逆導電型半導体層３とは島状に形
成される。なお、この逆導電型半導体層３は、化合物の
混晶比が異なる複数の層で形成してもよい。
【００１８】基板１上の全面もしくは一部に一導電型半
導体層２と逆導電型半導体層３を積層して形成した後
に、一導電型半導体層２および逆導電型半導体層３を島
状にエッチングし、さらに一導電型半導体層２の一端部
側が露出するように逆導電型半導体層３をエッチングし
て一導電型半導体層２に露出部Ｒを形成する。
【００１９】島状に形成された一導電型半導体層２と逆
導電型半導体層３は例えば窒化シリコン膜などから成る
保護膜６で被覆され、一導電型半導体層２の露出部Ｒか
ら半導体基板１上に延在するように、例えば金（Ａｕ）
などから成る第２の電極５ａ、５ｂが形成される。一導
電型半導体層２は、一つおきに異なる第２の電極５ａ、
５ｂに交互に接続されている。すなわち、一導電型半導
体層２を二つの群に分けて異なる第２の電極５ａ、５ｂ
に接続している。
【００２０】また、逆導電型半導体層３の表面から第２
の電極５とは反対側の壁面を経由して半導体基板１上に
延在するように第１の電極４が形成されている。すなわ
ち、異なる群に属する発光ダイオードごとに第１の電極
４を接続して設けている。第１の電極４の幅広部分がワ
イヤボンディングなどにより外部回路と接続するための
端子部となる。第２の電極５ａ、５ｂと第１の電極４の
組み合わせを選択することにより、個々の発光ダイオー
ドを選択して発光させることができる。
【００２１】本発明に係る発光ダイオードアレイでは、
一導電型半導体層２の同じ端部側が露出するように露出
部Ｒを設けて、この露出部Ｒに第２の電極５ａ、５ｂを
接続して設けると共に、逆導電型半導体層３の反対の端
部側に第１の電極４を接続して設け、最端部には個々の
発光素子に対応するように第１の電極４ａ、４ｂを接続
して配置すると共に、一導電型半導体層２間を経由して
第２の電極５ｃを露出部Ｒに接続されるように設けてい
る。外部回路との接続の際には、第１の電極４ａ、４ｂ
を同じ端子に接続すれば、最端部についても他の発光素
子と同様に動作させることが可能である。
【００２２】このように、同じ端部側の露出部Ｒに第２
の電極５ａ、５ｂ、５ｃを接続して設け、逆導電型半導
体層３の同じ端部側に第１の電極４を接続して設けると
共に、最端部については第２の電極５ｃを一導電型半導
体層２の内側に配置されるように接続して設け、逆導電
型半導体層３には、個々に第１の電極４ａ、４ｂを接続
して設けると、第１の電極４、４ａ、４ｂの形成過程で
電極パターンに位置ずれが発生しても、全ての発光素子
で同様な位置ずれが発生することから、発光素子ごとの
発光ばらつきは発生しない。したがって、すべての発光
素子の発光強度分布が同一となる。なお、発光素子の発
光強度は電流を調節することによって容易に調節でき、
同一基板上の発光素子全体の発光強度の強弱は容易に調
節できる。
【００２３】この実施形態によれば、一導電型半導体層
２がｎ型、逆導電型半導体層３がｐ型とすれば、逆導電
型半導体層３と一導電型半導体層２との間に電流を順方
向に流した場合、一方の第２の電極５ａを開放した状態
で他方の第２の電極５ｂを接続すれば、他方の第２の電
極５ｂに接続されている発光ダイオードだけが発光す
る。したがって、隣接する逆導電型半導体層３ごとに共
通する第１の電極４を設けても、第２の電極５ａ、５ｂ
は別々に接続されていることから、この第２の電極５
ａ、５ｂと第１の電極４との間の接続状態を変えること
で、隣接する発光ダイオードを選択的に発光させること
が可能となる。最端部に関しても第１の電極４ａ、４ｂ
は同じ外部回路に接続されていることから、逆導電型半
導体層３と一導電型半導体層２との間に順方向に電流を
流した場合、一方の第２の電極５ａを開放した状態で他
方の第２の電極５ｂを接続すれば、第１の電極４ｂに接
続されている発光ダイオードだけが発光する。
【００２４】
【発明の効果】以上のように、本発明に係る発光ダイオ
ードアレイによれば、複数の一導電型半導体層の露出部
を発光素子列の同じ側に設けて、列状の最端部の露出部
には島状半導体層の間を経由して第２の電極を接続した
ことから、電極パターンに位置ずれが発生しても、発光
素子に発光ばらつきが発生することは極力低減できる。
また、すべての発光素子が等しく配置されることによ
り、すべての発光素子について発光強度分布を均一化で
き、印画品質を向上させることができる。
【００２５】さらに、電極パターンに多少の位置ずれが
発生しても発光素子に発光ばらつきが発生しないことか
ら、電極を形成する際のマスクパターンの位置合わせを
短時間で行うことができ、製造が容易になる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array, and more particularly to a light emitting diode array used as an exposure source of a photosensitive drum for a page printer. 2. Description of the Related Art FIGS. 4 and 5 show a conventional light emitting diode array. FIG.
FIG. 5 is a sectional view taken along line AA in FIG. 4. 4 and 5, 21 is a semiconductor substrate, 22 is a semiconductor layer of one conductivity type,
23 is a reverse conductivity type semiconductor layer, 24 is a first electrode, and 25 is a second electrode. [0003] One conductivity type semiconductor layer 22 is formed on a semiconductor substrate 21.
And a reverse conductivity type semiconductor layer 23 having a smaller area than the one conductivity type semiconductor layer 22 is provided on the one conductivity type semiconductor layer 22, and the first electrode 2 is provided on the exposed portion R of the one conductivity type semiconductor layer 22.
4 (24 a, 24 b) are connected to each other, and the second electrode 25 is connected to the opposite conductivity type semiconductor layer 23. In FIG. 5, reference numeral 26 denotes an insulating film made of a silicon nitride film or the like. With this configuration, the first electrode 24 and the second electrode 25 can be simultaneously formed on the same side of the semiconductor substrate 21 in one step, so that the manufacturing process of the light emitting diode array is simplified. Also, connection work with an external circuit by a wire bonding method or the like becomes easy. The first electrodes 24 (24a, 24b)
Is, as shown in FIG. 4, the adjacent one conductivity type semiconductor layer 22.
Are provided in two groups so as to belong to different groups,
The electrodes 25 belong to different groups, and are provided such that adjacent opposite conductivity type semiconductor layers 23 are connected to the same second electrode 25. In this conventional light emitting diode array, exposed portions R are provided on both sides of a light emitting element row so that opposite end portions of adjacent one conductivity type semiconductor layers 22 are alternately exposed. The first electrode 24 (24a, 24
b), and the second electrode 25 is also connected to the opposite end side for each adjacent opposite conductivity type semiconductor layer 23. However, if the second electrodes 25 are alternately provided on both ends of the opposite conductivity type semiconductor layer 23, if the mask pattern is misaligned in the process of forming the second electrodes 25, the adjacent electrodes may be adjacent to each other. The area of the light emitting portion of the light emitting element changes,
There is a problem that light emission variation occurs for each light emitting element. Accordingly, the present inventors have filed a Japanese Patent Application No. Hei 9-1725.
No. 84, as shown in FIG. 6 and FIG.
A plurality of island-shaped one conductivity type semiconductor layers 32 are provided in a row on
The opposite conductivity type semiconductor layer 33 is laminated on the one conductivity type semiconductor layer 32 so that the exposed portion R is formed on the same end side of the one conductivity type semiconductor layer 32. The same first electrode 35 is connected and provided for each semiconductor layer 33, and the same second electrode is provided on the exposed portion of the one conductivity type semiconductor layer 32 under the opposite conductivity type semiconductor layer 33 to which the different first electrode 35 is connected. A light emitting diode array in which the electrodes 34 (34a, 34b) are connected has been proposed. As described above, the second electrode 34 (34a, 34b) is connected to the exposed portion R on the same end side, and the first electrode 35 is connected to the same side of the opposite conductivity type semiconductor layer 33. With this arrangement, even if a positional shift occurs in the electrode pattern in the process of forming the first electrode 35, the same positional shift occurs in all the light emitting elements, so that there is no variation in light emission among the light emitting elements. Note that the light emission intensity of the entire light emitting element on the same substrate can be easily adjusted by adjusting the current. However, in the above-described configuration, as shown in FIG. 8, the outermost wiring is cut along the line BB to form the island-shaped second electrode 34 (34c) into an external circuit. Alternatively, as shown in FIG. 9, only the outermost one-conductivity-type semiconductor layer 32a forms an exposed portion R on the opposite end side of the light-emitting element row, and connects the second electrode 34b. Along with
The first electrode 35 is connected to the opposite side of the opposite conductivity type semiconductor layer 33, but in the former case, it is difficult to connect to an external circuit. In the latter case, only the light emitting element at the end is misaligned. In addition, there is a disadvantage that light emission variation is caused by the influence of the light emission, and that only the light-emitting element at the extreme end has a different light emission intensity distribution in the element, thereby causing uneven printing. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned disadvantages, and eliminates variations in light emission of light emitting elements caused by misalignment of electrode patterns in all light emitting elements. An object of the present invention is to provide a light emitting diode array capable of making the distribution uniform. In order to achieve the above object, in the light emitting diode array of the present invention, a plurality of island-shaped one-conductivity-type semiconductor layers are provided on a substrate in a row. The opposite conductivity type semiconductor layer is provided on the one conductivity type semiconductor layer so that the exposed portion is formed on the same end side of the one conductivity type semiconductor layer, and the same is applied to each of the adjacent opposite conductivity type semiconductor layers. First
A light emitting diode array in which the same second electrode is connected to an exposed portion of the one conductivity type semiconductor layer below the opposite conductivity type semiconductor layer to which a different first electrode is connected. Wherein the second electrode is connected to the exposed end portion provided in the row via the island-shaped semiconductor layers. With the above arrangement, since all the exposed portions are arranged in the same manner, there is no variation in the light emission of the light emitting elements due to the displacement of the electrode pattern, and the light emission intensity distribution of all the light emitting elements is improved. Similarly, the printing quality is improved. Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 1 and 2 are views showing one embodiment of a light emitting diode array according to the present invention, and FIG. 3 is a cross-sectional view taken along line AA in FIG. 1, 2 and 3, 1 is a substrate, 2 is a semiconductor layer of one conductivity type, 3 is a semiconductor layer of opposite conductivity type, 4 is a first electrode, and 5 (5a, 5b).
Is a second electrode. The substrate 1 is made of, for example, a single crystal semiconductor substrate such as silicon (Si) or gallium arsenide (GaAs), or a single crystal insulating substrate such as sapphire (Al 2 O 3 ). Even when a semiconductor substrate is used as the substrate 1, it is desirable to use a semiconductor substrate having as high a resistance as possible. In the case of a single crystal semiconductor substrate, a (100) plane or the like is used, and in the case of sapphire, a C plane or the like is used. The one conductivity type semiconductor layer 2 is made of gallium arsenide or a multi-layered film of gallium arsenide and aluminum gallium arsenide, and contains one conductivity type semiconductor impurity such as silicon or selenium (Se) at l × 10 16 to 10 19 atoms. / Cm 3
Content. This one conductivity type semiconductor layer 2 is formed, for example, of MO
It is formed by a CVD method, an MBE method, or the like. That is, when the semiconductor substrate is used as the substrate 1 and formed by MOCVD, a natural oxide film of the semiconductor substrate is removed at a high temperature of 800 to 1000 ° C., and then an amorphous gallium arsenide film serving as a nucleus at a low temperature of 450 ° C. or less is formed. After growing to a thickness of about 0.1 to 2 μm, the temperature is raised to 500 to 700 ° C. and recrystallized to grow a gallium arsenide single crystal (two-step growth method).
In this case, trimethyl gallium ((CH 3 ) 3 Ga) or the like is used as a raw material of gallium, and arsine (AsH 3 ) or the like is used as a raw material of arsenic. Next, 7
Post-annealing such as repeating annealing at a high temperature of 50 to 1000 ° C. and rapid cooling to a low temperature of 600 ° C. or less several times (temperature cycle method) is performed. In the case of a two-layer structure of gallium arsenide and aluminum arsenide, an aluminum gallium arsenide layer is further formed. As a raw material of aluminum, trimethyl aluminum ((CH 3 ) 3 Al) or the like is used. On the one conductivity type semiconductor layer 2, an opposite conductivity type semiconductor layer 3 is formed. The opposite conductivity type semiconductor layer 3 is also made of a compound semiconductor such as aluminum gallium arsenide (AlGaAs), and contains 1 × 10 18 to 10 19 atoms of opposite conductivity type semiconductor impurities such as zinc (Zn) and strontium (Sr).
/ Cm 3 . A semiconductor junction is formed at the interface between the one conductivity type semiconductor layer 2 and the opposite conductivity type semiconductor layer 3. The one conductivity type semiconductor layer 2 and the opposite conductivity type semiconductor layer 3 are formed in an island shape. The opposite conductivity type semiconductor layer 3 may be formed of a plurality of layers having different compound crystal ratios of the compounds. After laminating the one conductivity type semiconductor layer 2 and the opposite conductivity type semiconductor layer 3 on the entire surface or a part of the substrate 1, the one conductivity type semiconductor layer 2 and the opposite conductivity type semiconductor layer 3 are formed into an island shape. Etching is performed, and then the opposite conductivity type semiconductor layer 3 is etched so that one end side of the one conductivity type semiconductor layer 2 is exposed to form an exposed portion R in the one conductivity type semiconductor layer 2. The one-conductivity-type semiconductor layer 2 and the opposite-conductivity-type semiconductor layer 3 formed in an island shape are covered with a protective film 6 made of, for example, a silicon nitride film or the like. 1, for example, gold (Au)
The second electrodes 5a and 5b are formed. The one-conductivity-type semiconductor layer 2 includes second electrodes 5a that are different from each other.
5b are connected alternately. That is, the one-conductivity-type semiconductor layer 2 is divided into two groups and different second electrodes 5a, 5b
Connected to The second surface of the opposite conductivity type semiconductor layer 3
The first electrode 4 is formed so as to extend on the semiconductor substrate 1 via a wall surface opposite to the electrode 5. That is, the first electrode 4 is connected and provided for each light emitting diode belonging to a different group. The wide portion of the first electrode 4 becomes a terminal portion for connecting to an external circuit by wire bonding or the like. By selecting a combination of the second electrodes 5a and 5b and the first electrode 4, individual light emitting diodes can be selected to emit light. In the light emitting diode array according to the present invention,
An exposed portion R is provided so that the same end portion of the one conductivity type semiconductor layer 2 is exposed, and the second electrode 5a, 5b is connected to the exposed portion R and provided opposite to the opposite conductivity type semiconductor layer 3. The first electrode 4 is connected and provided on the end side, and the first electrodes 4a and 4b are connected and arranged on the outermost end so as to correspond to the individual light emitting elements. The second electrode 5c is provided so as to be connected to the exposed portion R via a space. When connecting to an external circuit, the first electrodes 4a, 4b
Are connected to the same terminal, it is possible to operate the extreme end in the same manner as other light emitting elements. As described above, the second exposed portion R on the same end portion is
And the first electrode 4 is connected and provided on the same end side of the opposite conductivity type semiconductor layer 3, and the second electrode 5c is connected to one end of the opposite end. When the first conductive layers 4a and 4b are individually connected to the opposite conductive type semiconductor layer 3, the first conductive layers 4 and 4a are connected to each other. Even if a displacement occurs in the electrode pattern in the process of forming 4b, the same displacement occurs in all the light emitting elements, so that there is no variation in light emission among the light emitting elements. Therefore, the light emission intensity distribution of all the light emitting elements becomes the same. The light emission intensity of the light emitting element can be easily adjusted by adjusting the current,
The intensity of the light emission intensity of the entire light emitting element on the same substrate can be easily adjusted. According to this embodiment, if the one-conductivity-type semiconductor layer 2 is n-type and the opposite-conductivity-type semiconductor layer 3 is p-type, there is a space between the opposite-conductivity-type semiconductor layer 3 and the one-conductivity-type semiconductor layer 2. When a current flows in the forward direction, if the other second electrode 5b is connected while one second electrode 5a is open, only the light emitting diode connected to the other second electrode 5b emits light. I do. Therefore, even if the common first electrode 4 is provided for each adjacent opposite conductivity type semiconductor layer 3, the second electrodes 5a, 5b
Are connected separately, the second electrode 5
By changing the connection state between a and 5b and the first electrode 4, it becomes possible to selectively cause adjacent light emitting diodes to emit light. The first electrodes 4a, 4b also at the end portions
Are connected to the same external circuit, so that when a current flows between the opposite conductivity type semiconductor layer 3 and the one conductivity type semiconductor layer 2 in the forward direction, one of the second electrodes 5a is opened. When the other second electrode 5b is connected, only the light emitting diode connected to the first electrode 4b emits light. As described above, according to the light emitting diode array according to the present invention, the exposed portions of the plurality of one conductivity type semiconductor layers are provided on the same side of the light emitting element column, and Since the second electrode is connected to the exposed portion of the portion via the island-shaped semiconductor layer, even if the electrode pattern is displaced, the occurrence of light emission variation in the light emitting element can be reduced as much as possible. .
Further, by arranging all the light-emitting elements equally, it is possible to make the light-emission intensity distribution uniform for all the light-emitting elements and to improve the printing quality. Further, since even if a slight displacement occurs in the electrode pattern, there is no variation in light emission in the light emitting element, the mask pattern can be aligned in a short time when the electrode is formed, and the manufacturing can be simplified. It will be easier.
【図面の簡単な説明】
【図１】本発明に係る発光ダイオードアレイの一端部側
を示す平面図である。
【図２】本発明に係る発光ダイオードアレイの他の端部
側を示す平面図である。
【図３】本発明に係る発光ダイオードアレイを示す断面
図である。
【図４】従来の発光ダイオードアレイを示す平面図であ
る。
【図５】図４のＡ−Ａ線断面図である。
【図６】従来の他の発光ダイオードアレイの一端部側を
示す平面図である。
【図７】図６のＡ−Ａ線断面図である。
【図８】従来の他の発光ダイオードアレイの他の端部側
を示す平面図である。
【図９】従来の他の発光ダイオードアレイを改良したも
のの他の端部側を示す平面図である。
【符号の説明】
１‥‥‥基板、２‥‥‥一導電型半導体層、３‥‥‥逆
導電型半導体層、４‥‥‥第１の電極、５（５ａ、５
ｂ）‥‥‥第２の電極、Ｒ‥‥‥露出部BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing one end of a light emitting diode array according to the present invention. FIG. 2 is a plan view showing another end side of the light emitting diode array according to the present invention. FIG. 3 is a sectional view showing a light emitting diode array according to the present invention. FIG. 4 is a plan view showing a conventional light emitting diode array. FIG. 5 is a sectional view taken along line AA of FIG. 4; FIG. 6 is a plan view showing one end side of another conventional light emitting diode array. FIG. 7 is a sectional view taken along line AA of FIG. 6; FIG. 8 is a plan view showing another end portion of another conventional light emitting diode array. FIG. 9 is a plan view showing another end portion obtained by improving another conventional light emitting diode array. [Description of Signs] 1 substrate, 2 semiconductor layer of one conductivity type, 3 semiconductor layer of opposite conductivity type, 4 first electrode, 5 (5a, 5
b) {Second electrode, R} exposed part
Claims (1)
に複数設け、この複数の一導電型半導体層の同じ端部側
に露出部が形成されるように、この一導電型半導体層上
に逆導電型半導体層を積層して設け、この隣接する逆導
電型半導体層毎に同じ第１の電極を接続して設けると共
に、異なる第１の電極が接続された逆導電型半導体層下
の前記一導電型半導体層の露出部に同じ第２の電極が接
続されるようにした発光ダイオードアレイにおいて、前
記列状に設けた最端部の露出部に、前記第２の電極を前
記島状半導体層の間を経由して接続したことを特徴とす
る発光ダイオードアレイ。(57) [Claim 1] A plurality of island-shaped one-conductivity-type semiconductor layers are provided in a row on a substrate, and an exposed portion is formed on the same end side of the plurality of one-conductivity-type semiconductor layers. As described above, a reverse conductivity type semiconductor layer is laminated on the one conductivity type semiconductor layer, and the same first electrode is connected and provided for each adjacent reverse conductivity type semiconductor layer. In a light-emitting diode array in which the same second electrode is connected to an exposed portion of the one-conductivity-type semiconductor layer below the opposite-conductivity-type semiconductor layer to which the electrode is connected, an endmost portion provided in the column is exposed. A light-emitting diode array, wherein the second electrode is connected to the portion via the island-shaped semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24420498A JP3500310B2 (en) | 1998-08-28 | 1998-08-28 | Light emitting diode array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24420498A JP3500310B2 (en) | 1998-08-28 | 1998-08-28 | Light emitting diode array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000077715A JP2000077715A (en) | 2000-03-14 |
| JP3500310B2 true JP3500310B2 (en) | 2004-02-23 |
Family
ID=17115328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24420498A Expired - Fee Related JP3500310B2 (en) | 1998-08-28 | 1998-08-28 | Light emitting diode array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3500310B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5366409B2 (en) * | 2008-01-24 | 2013-12-11 | ローム株式会社 | Semiconductor device |
-
1998
- 1998-08-28 JP JP24420498A patent/JP3500310B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000077715A (en) | 2000-03-14 |
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