JP2000077715A - Light-emitting diode array - Google Patents
Light-emitting diode arrayInfo
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- JP2000077715A JP2000077715A JP24420498A JP24420498A JP2000077715A JP 2000077715 A JP2000077715 A JP 2000077715A JP 24420498 A JP24420498 A JP 24420498A JP 24420498 A JP24420498 A JP 24420498A JP 2000077715 A JP2000077715 A JP 2000077715A
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- type semiconductor
- conductivity type
- electrode
- semiconductor layer
- light emitting
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は発光ダイオードアレ
イに関し、特にぺージプリンタ用感光ドラムの露光源な
どに用いられる発光ダイオードアレイに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array, and more particularly to a light emitting diode array used as an exposure source of a photosensitive drum for a page printer.
【0002】[0002]
【従来の技術および発明が解決しようとする課題】従来
の発光ダイオードアレイを図4および図5に示す。図5
は、図4中のA−A線断面図である。図4および図5に
おいて、21は半導体基板、22は一導電型半導体層、
23は逆導電型半導体層、24は第1の電極、25は第
2の電極である。2. Description of the Related Art FIGS. 4 and 5 show a conventional light emitting diode array. FIG.
FIG. 5 is a sectional view taken along line AA in FIG. 4. 4 and 5, 21 is a semiconductor substrate, 22 is a semiconductor layer of one conductivity type,
23 is a reverse conductivity type semiconductor layer, 24 is a first electrode, and 25 is a second electrode.
【0003】半導体基板21上に一導電型半導体層22
を設けると共に、この一導電型半導体層22上に一導電
型半導体層22よりも小面積な逆導電型半導体層23を
設け、一導電型半導体層22の露出部Rに第1の電極2
4(24a、24b)を接続して設けると共に、逆導電
型半導体層23に第2の電極25を接続して設けてい
る。なお、図5中、26は窒化シリコン膜などから成る
絶縁膜である。[0003] One conductivity type semiconductor layer 22 is formed on a semiconductor substrate 21.
And a reverse conductivity type semiconductor layer 23 having a smaller area than the one conductivity type semiconductor layer 22 is provided on the one conductivity type semiconductor layer 22, and the first electrode 2 is provided on an exposed portion R of the one conductivity type semiconductor layer 22.
4 (24a, 24b) are connected and provided, and the second electrode 25 is connected to the opposite conductivity type semiconductor layer 23. In FIG. 5, reference numeral 26 denotes an insulating film made of a silicon nitride film or the like.
【0004】このように構成すると、第1の電極24と
第2の電極25を半導体基板21の同じ側に一回の工程
で同時に形成できることから、発光ダイオードアレイの
製造工程が簡略化されると共に、ワイヤボンディング法
などによる外部回路との接続作業も容易になる。With this configuration, the first electrode 24 and the second electrode 25 can be simultaneously formed on the same side of the semiconductor substrate 21 in one step, so that the manufacturing process of the light emitting diode array is simplified and Also, connection work with an external circuit by a wire bonding method or the like becomes easy.
【0005】また、第1の電極24(24a、24b)
は、図4に示すように、隣接する一導電型半導体層22
が異なる群に属するように二群に分けて設けられ、第2
の電極25は異なる群に属し、且つ隣接する逆導電型半
導体層23が同じ第2の電極25に接続されるように設
けられている。The first electrodes 24 (24a, 24b)
Is, as shown in FIG. 4, the adjacent one conductivity type semiconductor layer 22.
Are provided in two groups so as to belong to different groups.
The electrodes 25 belong to different groups, and are provided such that adjacent opposite conductivity type semiconductor layers 23 are connected to the same second electrode 25.
【0006】この従来の発光ダイオードアレイでは、隣
接する一導電型半導体層22の反対の端部側が交互に露
出するように発光素子列の両側に振り分けて露出部Rを
設け、この露出部Rに第1の電極24(24a、24
b)を接続したものであり、第2の電極25も隣接する
逆導電型半導体層23ごとに反対の端部側に接続して設
けられている。In this conventional light emitting diode array, exposed portions R are provided on both sides of a light emitting element row so that opposite end portions of adjacent one conductivity type semiconductor layers 22 are alternately exposed. The first electrode 24 (24a, 24
b), and the second electrode 25 is also connected to the opposite end side for each adjacent opposite conductivity type semiconductor layer 23.
【0007】ところが、第2の電極25を逆導電型半導
体層23の両端部側に交互に接続して設けると、第2の
電極25の形成過程でマスクパターンに位置ずれが発生
した場合、隣接する発光素子の発光部の面積が変化し、
発光素子ごとに発光ばらつきが発生するという問題があ
った。However, if the second electrodes 25 are provided alternately on both ends of the opposite conductivity type semiconductor layer 23, if the mask pattern is misaligned in the process of forming the second electrodes 25, the adjacent electrodes may be adjacent to each other. The area of the light emitting portion of the light emitting element changes,
There is a problem that light emission variation occurs for each light emitting element.
【0008】そこで、本発明者等は特願平9−1725
84号において、図6および図7に示すように、基板3
1上に島状の一導電型半導体層32を列状に複数設け、
この一導電型半導体層32の同じ端部側に露出部Rが形
成されるように、この一導電型半導体層32上に逆導電
型半導体層33を積層して設け、この隣接する逆導電型
半導体層33毎に同じ第1の電極35を接続して設ける
と共に、異なる第1の電極35が接続された逆導電型半
導体層33下の一導電型半導体層32の露出部に同じ第
2の電極34(34a、34b)が接続されるようにし
た発光ダイオードアレイを提案した。Accordingly, the present inventors have filed a Japanese Patent Application No. Hei 9-1725.
No. 84, as shown in FIG. 6 and FIG.
A plurality of island-shaped one conductivity type semiconductor layers 32 are provided in a row on
The opposite conductivity type semiconductor layer 33 is provided on the one conductivity type semiconductor layer 32 so as to form an exposed portion R on the same end side of the one conductivity type semiconductor layer 32. The same first electrode 35 is connected and provided for each semiconductor layer 33, and the same second electrode 35 is provided on an exposed portion of the one conductivity type semiconductor layer 32 under the opposite conductivity type semiconductor layer 33 to which a different first electrode 35 is connected. A light emitting diode array in which the electrodes 34 (34a, 34b) are connected has been proposed.
【0009】このように同じ端部側の露出部Rに第2の
電極34(34a、34b)を接続して設け、逆導電型
半導体層33の同じ側に第1の電極35を接続して設け
ると、第1の電極35の形成過程で電極パターンに位置
ずれが発生しても、全ての発光素子で同様な位置ずれが
発生することから、発光素子ごとの発光ばらつきは発生
しない。なお、同一基板上の発光素子全体の発光強度は
電流を調整することによって容易に調整できる。As described above, the second electrode 34 (34a, 34b) is connected to the exposed portion R on the same end side, and the first electrode 35 is connected to the same side of the opposite conductivity type semiconductor layer 33. When provided, even if a positional shift occurs in the electrode pattern in the process of forming the first electrode 35, the same positional shift occurs in all the light emitting elements, so that there is no variation in light emission among the light emitting elements. Note that the light emission intensity of the entire light emitting element on the same substrate can be easily adjusted by adjusting the current.
【0010】ところが、上述のような構成では、図8に
示すように、最端部の配線をB−B線部分でカットし
て、島状になる第2の電極34(34c)を外部回路に
別途接続したり、図9に示すように、最端部の一導電型
半導体層32aのみは発光素子列の反対の端部側に露出
部Rを形成して、第2の電極34bを接続すると共に、
逆導電型半導体層33の対向する側に第1の電極35を
接続したりするが、前者の場合は外部回路との接続が難
しくなり、後者の場合は最端部の発光素子のみは位置ず
れの影響を受けて、発光ばらつきの原因になったり、最
端部の発光素子のみが素子内の発光強度分布が異なるの
で、印画むらを引き起こすという欠点を有していた。However, in the above-described configuration, as shown in FIG. 8, the wiring at the end is cut along the line BB to form the second electrode 34 (34c) having an island shape in an external circuit. In addition, as shown in FIG. 9, only the outermost one-conductive-type semiconductor layer 32a forms an exposed portion R on the opposite end side of the light-emitting element row, and connects the second electrode 34b. Along with
The first electrode 35 is connected to the opposite side of the opposite conductivity type semiconductor layer 33, but in the former case, it is difficult to connect to an external circuit, and in the latter case, only the light emitting element at the end is misaligned. The light-emitting device has a drawback that it causes uneven light emission and that only the light-emitting element at the end has a different light-emitting intensity distribution in the element, thereby causing uneven printing.
【0011】本発明は上記欠点に鑑みてなされたもので
あり、すべての発光素子において電極パターンの位置ず
れに起因する発光素子の発光ばらつきを解消し、またす
べての発光素子において発光素子の発光強度分布を均一
化することのできる発光ダイオードアレイを提供するも
のである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and eliminates variations in light emission of light emitting elements due to misalignment of electrode patterns in all light emitting elements. An object of the present invention is to provide a light emitting diode array capable of making the distribution uniform.
【0012】[0012]
【課題を解決するための手段】上述の目的を達成するた
めに、本発明の発光ダイオードアレイでは、基板上に島
状の一導電型半導体層を列状に複数設け、この複数の一
導電型半導体層の同じ端部側に露出部が形成されるよう
に、この一導電型半導体層上に逆導電型半導体層を積層
して設け、この隣接する逆導電型半導体層毎に同じ第1
の電極を接続して設けると共に、異なる第1の電極が接
続された逆導電型半導体層下の前記一導電型半導体層の
露出部に同じ第2の電極が接続されるようにした発光ダ
イオードアレイにおいて、前記列状に設けた最端部の露
出部に、前記第2の電極を前記島状半導体層の間を経由
して接続したことを特徴とする。In order to achieve the above object, in the light emitting diode array of the present invention, a plurality of island-shaped semiconductor layers of one conductivity type are provided on a substrate, and the plurality of islands of one conductivity type are provided. The opposite conductivity type semiconductor layer is provided on the one conductivity type semiconductor layer so as to form an exposed portion on the same end side of the semiconductor layer, and the same first conductivity type semiconductor layer is provided for each of the adjacent opposite conductivity type semiconductor layers.
A light emitting diode array in which the same second electrode is connected to an exposed portion of the one conductivity type semiconductor layer below the opposite conductivity type semiconductor layer to which a different first electrode is connected. Wherein the second electrode is connected to the exposed end portion provided in the row via the island-shaped semiconductor layers.
【0013】[0013]
【作用】上記のように構成すると、全露出部が同様に配
置されることから、電極パターンの位置ずれに起因する
発光素子の発光ばらつきがなく、すべての発光素子につ
いて発光強度分布が同様となって、印画品質が向上す
る。With the above construction, since all the exposed portions are arranged in the same manner, there is no variation in the light emission of the light emitting elements due to the displacement of the electrode pattern, and the light emission intensity distribution is the same for all the light emitting elements. The printing quality is improved.
【0014】[0014]
【発明の実施の形態】以下、本発明の実施形態を添付図
面に基づき詳細に説明する。図1、図2は本発明に係る
発光ダイオードアレイの一実施形態を示す図であり、図
3は図1中のA−A線断面図である。図1、図2および
図3において、1は基板、2は一導電型半導体層、3は
逆導電型半導体層、4は第1の電極、5(5a、5b)
は第2の電極である。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 1 and 2 are views showing one embodiment of a light emitting diode array according to the present invention, and FIG. 3 is a cross-sectional view taken along line AA in FIG. 1, 2 and 3, 1 is a substrate, 2 is a semiconductor layer of one conductivity type, 3 is a semiconductor layer of opposite conductivity type, 4 is a first electrode, and 5 (5a, 5b).
Is a second electrode.
【0015】基板1は、例えばシリコン(Si)やガリ
ウム砒素(GaAs)などの単結晶半導体基板、あるい
はサファイア(Al2 O3 )などの単結晶絶縁基板から
成る。基板1として半導体基板を用いる場合でも、でき
るだけ高抵抗な半導体基板を用いることが望ましい。ま
た、単結晶半導体基板の場合、(100)面などが用い
られ、サファイアの場合、C面などが用いられる。The substrate 1 is made of, for example, a single crystal semiconductor substrate such as silicon (Si) or gallium arsenide (GaAs) or a single crystal insulating substrate such as sapphire (Al 2 O 3 ). Even when a semiconductor substrate is used as the substrate 1, it is desirable to use a semiconductor substrate having as high a resistance as possible. In the case of a single crystal semiconductor substrate, a (100) plane or the like is used, and in the case of sapphire, a C plane or the like is used.
【0016】一導電型半導体層2は、ガリウム砒素やガ
リウム砒素とアルミニウムガリウム砒素の多層膜などか
ら成り、例えばシリコンやセレン(Se)などの一導電
型半導体不純物をl×1016〜1019atom/cm3
程度含有する。この一導電型半導体層2は、例えばMO
CVD法やMBE法などで形成される。すなわち、基板
1として半導体基板を用いてMOCVD法で形成する場
合、半導体基板の自然酸化膜を800〜1000℃の高
温で除去し、次に450℃以下の低温で核となるアモル
ファスガリウム砒素膜を0.1〜2μm程度の厚みに成
長させた後、500〜700℃まで昇温して再結晶化し
てガリウム砒素単結晶を成長させる(二段階成長法)。
この場合、ガリウムの原料としてはトリメチルガリウム
((CH3 )3 Ga)などが用いられ、砒素の原料とし
てはアルシン(AsH3 )などが用いられる。次に、7
50〜1000℃の高温でのアニールと600℃以下の
低温への急冷を数回繰り返す(温度サイクル法)等のポ
ストアニールを行う。ガリウム砒素とアルミニウム砒素
の二層構造にする場合は、さらにアルミニウムガリウム
砒素層を形成する。アルミニウムの原料としては、トリ
メチルアルミニウム((CH3 )3 Al)などが用いら
れる。The one conductivity-type semiconductor layer 2 is made of a multilayer film of gallium arsenide or gallium arsenide and aluminum gallium arsenide, for example, silicon or selenium (Se) one conductivity type semiconductor impurity l × 10 16 ~10 19 atom, such as / Cm 3
Content. This one conductivity type semiconductor layer 2 is formed, for example, of MO
It is formed by a CVD method, an MBE method, or the like. That is, when the semiconductor substrate is used as the substrate 1 and formed by the MOCVD method, a natural oxide film of the semiconductor substrate is removed at a high temperature of 800 to 1000 ° C., and then an amorphous gallium arsenide film serving as a nucleus at a low temperature of 450 ° C. or less is formed. After growing to a thickness of about 0.1 to 2 μm, the temperature is raised to 500 to 700 ° C. and recrystallized to grow a gallium arsenide single crystal (two-step growth method).
In this case, trimethyl gallium ((CH 3 ) 3 Ga) or the like is used as a raw material of gallium, and arsine (AsH 3 ) or the like is used as a raw material of arsenic. Next, 7
Post annealing such as repeating annealing at a high temperature of 50 to 1000 ° C. and rapid cooling to a low temperature of 600 ° C. or less several times (temperature cycle method) is performed. In the case of a two-layer structure of gallium arsenide and aluminum arsenide, an aluminum gallium arsenide layer is further formed. As a raw material of aluminum, trimethyl aluminum ((CH 3 ) 3 Al) or the like is used.
【0017】一導電型半導体層2上には、逆導電型半導
体層3が形成される。逆導電型半導体層3も、アルミニ
ウムガリウム砒素(AlGaAs)などの化合物半導体
から成り、亜鉛(Zn)やストロンチウム(Sr)など
の逆導電型半導体不純物を1×1018〜1019atom
/cm3 程度含有する。一導電型半導体層2と逆導電型
半導体層3の界面部で半導体接合部が形成される。この
一導電型半導体層2と逆導電型半導体層3とは島状に形
成される。なお、この逆導電型半導体層3は、化合物の
混晶比が異なる複数の層で形成してもよい。On the one conductivity type semiconductor layer 2, a reverse conductivity type semiconductor layer 3 is formed. The opposite conductivity type semiconductor layer 3 is also made of a compound semiconductor such as aluminum gallium arsenide (AlGaAs), and contains 1 × 10 18 to 10 19 atoms of opposite conductivity type semiconductor impurities such as zinc (Zn) and strontium (Sr).
/ Cm 3 . A semiconductor junction is formed at the interface between the one conductivity type semiconductor layer 2 and the opposite conductivity type semiconductor layer 3. The one conductivity type semiconductor layer 2 and the opposite conductivity type semiconductor layer 3 are formed in an island shape. The opposite conductivity type semiconductor layer 3 may be formed of a plurality of layers having different compound crystal ratios.
【0018】基板1上の全面もしくは一部に一導電型半
導体層2と逆導電型半導体層3を積層して形成した後
に、一導電型半導体層2および逆導電型半導体層3を島
状にエッチングし、さらに一導電型半導体層2の一端部
側が露出するように逆導電型半導体層3をエッチングし
て一導電型半導体層2に露出部Rを形成する。After laminating the one conductivity type semiconductor layer 2 and the opposite conductivity type semiconductor layer 3 on the entire surface or a part of the substrate 1, the one conductivity type semiconductor layer 2 and the opposite conductivity type semiconductor layer 3 are formed into an island shape. Etching is performed, and then the opposite-conductivity-type semiconductor layer 3 is etched so that one end of the one-conductivity-type semiconductor layer 2 is exposed to form an exposed portion R in the one-conductivity-type semiconductor layer 2.
【0019】島状に形成された一導電型半導体層2と逆
導電型半導体層3は例えば窒化シリコン膜などから成る
保護膜6で被覆され、一導電型半導体層2の露出部Rか
ら半導体基板1上に延在するように、例えば金(Au)
などから成る第2の電極5a、5bが形成される。一導
電型半導体層2は、一つおきに異なる第2の電極5a、
5bに交互に接続されている。すなわち、一導電型半導
体層2を二つの群に分けて異なる第2の電極5a、5b
に接続している。The island-shaped one-conductivity-type semiconductor layer 2 and the opposite-conductivity-type semiconductor layer 3 are covered with a protective film 6 made of, for example, a silicon nitride film. 1 to extend over, for example, gold (Au)
The second electrodes 5a and 5b are formed. One-conductivity-type semiconductor layer 2 includes second electrodes 5a that are alternately different from each other.
5b are connected alternately. That is, the one-conductivity-type semiconductor layer 2 is divided into two groups and different second electrodes 5a, 5b
Connected to.
【0020】また、逆導電型半導体層3の表面から第2
の電極5とは反対側の壁面を経由して半導体基板1上に
延在するように第1の電極4が形成されている。すなわ
ち、異なる群に属する発光ダイオードごとに第1の電極
4を接続して設けている。第1の電極4の幅広部分がワ
イヤボンディングなどにより外部回路と接続するための
端子部となる。第2の電極5a、5bと第1の電極4の
組み合わせを選択することにより、個々の発光ダイオー
ドを選択して発光させることができる。The second surface of the opposite conductivity type semiconductor layer 3
The first electrode 4 is formed so as to extend on the semiconductor substrate 1 via the wall surface opposite to the electrode 5. That is, the first electrode 4 is connected and provided for each light emitting diode belonging to a different group. The wide portion of the first electrode 4 becomes a terminal portion for connecting to an external circuit by wire bonding or the like. By selecting a combination of the second electrodes 5a and 5b and the first electrode 4, individual light emitting diodes can be selected to emit light.
【0021】本発明に係る発光ダイオードアレイでは、
一導電型半導体層2の同じ端部側が露出するように露出
部Rを設けて、この露出部Rに第2の電極5a、5bを
接続して設けると共に、逆導電型半導体層3の反対の端
部側に第1の電極4を接続して設け、最端部には個々の
発光素子に対応するように第1の電極4a、4bを接続
して配置すると共に、一導電型半導体層2間を経由して
第2の電極5cを露出部Rに接続されるように設けてい
る。外部回路との接続の際には、第1の電極4a、4b
を同じ端子に接続すれば、最端部についても他の発光素
子と同様に動作させることが可能である。In the light emitting diode array according to the present invention,
An exposed portion R is provided so that the same end portion of the one conductivity type semiconductor layer 2 is exposed, and the second electrode 5a, 5b is connected to the exposed portion R and provided opposite to the opposite conductivity type semiconductor layer 3. A first electrode 4 is connected and provided on the end side, and first electrodes 4a and 4b are connected and arranged on the extreme end so as to correspond to individual light emitting elements. The second electrode 5c is provided so as to be connected to the exposed portion R via a space. When connecting to an external circuit, the first electrodes 4a, 4b
Are connected to the same terminal, it is possible to operate the extreme end in the same manner as other light emitting elements.
【0022】このように、同じ端部側の露出部Rに第2
の電極5a、5b、5cを接続して設け、逆導電型半導
体層3の同じ端部側に第1の電極4を接続して設けると
共に、最端部については第2の電極5cを一導電型半導
体層2の内側に配置されるように接続して設け、逆導電
型半導体層3には、個々に第1の電極4a、4bを接続
して設けると、第1の電極4、4a、4bの形成過程で
電極パターンに位置ずれが発生しても、全ての発光素子
で同様な位置ずれが発生することから、発光素子ごとの
発光ばらつきは発生しない。したがって、すべての発光
素子の発光強度分布が同一となる。なお、発光素子の発
光強度は電流を調節することによって容易に調節でき、
同一基板上の発光素子全体の発光強度の強弱は容易に調
節できる。As described above, the second exposed portion R on the same end portion is
And the first electrode 4 is connected to the same end of the opposite conductivity type semiconductor layer 3 and the second electrode 5c is connected to the other end of the semiconductor layer 3 at one end. When the first electrodes 4a and 4b are individually connected to the opposite conductivity type semiconductor layer 3, the first electrodes 4 and 4a are connected to each other. Even if a displacement occurs in the electrode pattern in the process of forming 4b, the same displacement occurs in all the light emitting elements, so that there is no variation in light emission among the light emitting elements. Therefore, the light emission intensity distribution of all the light emitting elements becomes the same. The light emission intensity of the light emitting element can be easily adjusted by adjusting the current,
The intensity of the light emission intensity of the entire light emitting element on the same substrate can be easily adjusted.
【0023】この実施形態によれば、一導電型半導体層
2がn型、逆導電型半導体層3がp型とすれば、逆導電
型半導体層3と一導電型半導体層2との間に電流を順方
向に流した場合、一方の第2の電極5aを開放した状態
で他方の第2の電極5bを接続すれば、他方の第2の電
極5bに接続されている発光ダイオードだけが発光す
る。したがって、隣接する逆導電型半導体層3ごとに共
通する第1の電極4を設けても、第2の電極5a、5b
は別々に接続されていることから、この第2の電極5
a、5bと第1の電極4との間の接続状態を変えること
で、隣接する発光ダイオードを選択的に発光させること
が可能となる。最端部に関しても第1の電極4a、4b
は同じ外部回路に接続されていることから、逆導電型半
導体層3と一導電型半導体層2との間に順方向に電流を
流した場合、一方の第2の電極5aを開放した状態で他
方の第2の電極5bを接続すれば、第1の電極4bに接
続されている発光ダイオードだけが発光する。According to this embodiment, if the one conductivity type semiconductor layer 2 is n-type and the opposite conductivity type semiconductor layer 3 is p-type, the space between the opposite conductivity type semiconductor layer 3 and the one conductivity type semiconductor layer 2 is provided. When a current flows in the forward direction, if the other second electrode 5b is connected while one second electrode 5a is open, only the light emitting diode connected to the other second electrode 5b emits light. I do. Therefore, even if the common first electrode 4 is provided for each of the adjacent opposite conductivity type semiconductor layers 3, the second electrodes 5a, 5b
Are connected separately, the second electrode 5
By changing the connection state between a and 5b and the first electrode 4, it becomes possible to selectively cause adjacent light emitting diodes to emit light. The first electrodes 4a, 4b also at the end portions
Are connected to the same external circuit. Therefore, when a current flows between the opposite conductivity type semiconductor layer 3 and the one conductivity type semiconductor layer 2 in the forward direction, one second electrode 5a is opened. When the other second electrode 5b is connected, only the light emitting diode connected to the first electrode 4b emits light.
【0024】[0024]
【発明の効果】以上のように、本発明に係る発光ダイオ
ードアレイによれば、複数の一導電型半導体層の露出部
を発光素子列の同じ側に設けて、列状の最端部の露出部
には島状半導体層の間を経由して第2の電極を接続した
ことから、電極パターンに位置ずれが発生しても、発光
素子に発光ばらつきが発生することは極力低減できる。
また、すべての発光素子が等しく配置されることによ
り、すべての発光素子について発光強度分布を均一化で
き、印画品質を向上させることができる。As described above, according to the light-emitting diode array according to the present invention, the exposed portions of the plurality of one-conductivity-type semiconductor layers are provided on the same side of the light-emitting element row, and the exposed end of the row is exposed. Since the second electrode is connected to the portion via the island-shaped semiconductor layer, even if the electrode pattern is displaced, it is possible to minimize the occurrence of light emission variation in the light emitting element.
Further, by arranging all the light emitting elements equally, it is possible to make the light emission intensity distribution uniform for all the light emitting elements and to improve the printing quality.
【0025】さらに、電極パターンに多少の位置ずれが
発生しても発光素子に発光ばらつきが発生しないことか
ら、電極を形成する際のマスクパターンの位置合わせを
短時間で行うことができ、製造が容易になる。Further, even if a slight displacement occurs in the electrode pattern, there is no variation in light emission in the light emitting element. Therefore, the mask pattern can be aligned in the formation of the electrode in a short time, and the manufacturing can be simplified. It will be easier.
【図1】本発明に係る発光ダイオードアレイの一端部側
を示す平面図である。FIG. 1 is a plan view showing one end side of a light emitting diode array according to the present invention.
【図2】本発明に係る発光ダイオードアレイの他の端部
側を示す平面図である。FIG. 2 is a plan view showing another end of the light emitting diode array according to the present invention.
【図3】本発明に係る発光ダイオードアレイを示す断面
図である。FIG. 3 is a sectional view showing a light emitting diode array according to the present invention.
【図4】従来の発光ダイオードアレイを示す平面図であ
る。FIG. 4 is a plan view showing a conventional light emitting diode array.
【図5】図4のA−A線断面図である。FIG. 5 is a sectional view taken along line AA of FIG. 4;
【図6】従来の他の発光ダイオードアレイの一端部側を
示す平面図である。FIG. 6 is a plan view showing one end side of another conventional light emitting diode array.
【図7】図6のA−A線断面図である。FIG. 7 is a sectional view taken along line AA of FIG. 6;
【図8】従来の他の発光ダイオードアレイの他の端部側
を示す平面図である。FIG. 8 is a plan view showing another end portion of another conventional light emitting diode array.
【図9】従来の他の発光ダイオードアレイを改良したも
のの他の端部側を示す平面図である。FIG. 9 is a plan view showing another end portion obtained by improving another conventional light emitting diode array.
1‥‥‥基板、2‥‥‥一導電型半導体層、3‥‥‥逆
導電型半導体層、4‥‥‥第1の電極、5(5a、5
b)‥‥‥第2の電極、R‥‥‥露出部1 substrate, 2 semiconductor layer of one conductivity type, 3 semiconductor layer of opposite conductivity type, 4 first electrode, 5 (5a, 5
b) {Second electrode, R} exposed part
Claims (1)
に複数設け、この複数の一導電型半導体層の同じ端部側
に露出部が形成されるように、この一導電型半導体層上
に逆導電型半導体層を積層して設け、この隣接する逆導
電型半導体層毎に同じ第1の電極を接続して設けると共
に、異なる第1の電極が接続された逆導電型半導体層下
の前記一導電型半導体層の露出部に同じ第2の電極が接
続されるようにした発光ダイオードアレイにおいて、前
記列状に設けた最端部の露出部に、前記第2の電極を前
記島状半導体層の間を経由して接続したことを特徴とす
る発光ダイオードアレイ。A plurality of island-shaped one-conductivity-type semiconductor layers are provided in a row on a substrate, and the one-conductivity-type semiconductor layers are formed such that exposed portions are formed on the same end side of the plurality of one-conductivity-type semiconductor layers. A reverse conductivity type semiconductor layer is provided by laminating a reverse conductivity type semiconductor layer on a semiconductor layer, and the same first electrode is connected and provided for each adjacent reverse conductivity type semiconductor layer, and a different first electrode is connected. In a light-emitting diode array in which the same second electrode is connected to an exposed portion of the one-conductivity-type semiconductor layer below the layer, the second electrode is provided at an exposed portion at the end provided in the row. A light emitting diode array connected between the island-shaped semiconductor layers.
Priority Applications (1)
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Application Number | Priority Date | Filing Date | Title |
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JP24420498A JP3500310B2 (en) | 1998-08-28 | 1998-08-28 | Light emitting diode array |
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JP2000077715A true JP2000077715A (en) | 2000-03-14 |
JP3500310B2 JP3500310B2 (en) | 2004-02-23 |
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ID=17115328
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009176906A (en) * | 2008-01-24 | 2009-08-06 | Rohm Co Ltd | Semiconductor device |
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1998
- 1998-08-28 JP JP24420498A patent/JP3500310B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009176906A (en) * | 2008-01-24 | 2009-08-06 | Rohm Co Ltd | Semiconductor device |
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