JP3517101B2 - Light emitting diode array - Google Patents

Light emitting diode array

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Publication number
JP3517101B2
JP3517101B2 JP32845297A JP32845297A JP3517101B2 JP 3517101 B2 JP3517101 B2 JP 3517101B2 JP 32845297 A JP32845297 A JP 32845297A JP 32845297 A JP32845297 A JP 32845297A JP 3517101 B2 JP3517101 B2 JP 3517101B2
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JP
Japan
Prior art keywords
semiconductor layer
island
conductivity type
light emitting
emitting diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP32845297A
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Japanese (ja)
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JPH11163408A (en
Inventor
勝信 北田
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Kyocera Corp
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Kyocera Corp
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Priority to JP32845297A priority Critical patent/JP3517101B2/en
Publication of JPH11163408A publication Critical patent/JPH11163408A/en
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Description

【発明の詳細な説明】 【0001】 【発明が属する技術分野】本発明は発光ダイオードアレ
イに関し、特にページプリンタ用感光ドラムの露光用光
源などに用いられる発光ダイオードアレイに関する。 【0002】 【従来の技術および発明が解決しようとする課題】従来
の発光ダイオードアレイを図4および図5に示す。図4
は発光ダイオードアレイを平面視した状態を示し、図5
は一つの発光素子の断面を示す。図4および図5におい
て、11は基板、12は一導電型半導体層、13は逆導
電型半導体層、14は個別電極、15は共通電極、16
は絶縁膜である。 【0003】基板11上にガリウム砒素などから成る一
導電型半導体層12と逆導電型半導体層13とを積層し
た島状の半導体層を列状に配置している。また、一導電
型半導体層12の一部が露出するように、逆導電型半導
体層13は一導電型半導体層12よりも小面積に形成し
ている。 【0004】一導電型半導体層12の露出部には共通電
極15が接続され、逆導電型半導体層13の上部には個
別電極14が接続されている。図4に示すように、隣接
する逆導電型半導体層13毎に一つの個別電極14が接
続して設けられ、同じ個別電極14に接続された逆導電
型半導体層13下部の一導電型半導体層12が別々の共
通電極15a、15bに振り分けて接続されるように構
成されている。島状半導体層と個別電極14と共通電極
15で個々の発光ダイオードが構成される。 【0005】個別電極14と共通電極15の組み合わせ
を選択して個別電極14から共通電極15a、15bに
電流を流して複数の発光ダイオードを選択的に発光させ
ることによって、ページプリンタ用感光ドラムの露光用
光源として用いられる。 【0006】ところが、この従来の発光ダイオードアレ
イでは、一導電型半導体層12の一部が露出するよう
に、逆導電型半導体層13をパターニングする際に、マ
スクパターンに基板1の短手方向の位置ずれが発生した
場合、島状半導体層ごとに逆導電型半導体層13が大き
くなったり、小さくなったりして、発光面積の異なる発
光ダイオードが形成され、発光ばらつきが発生するとい
う問題があった。 【0007】そこで、図6に示すように、一導電型半導
体層12の同じ側が露出するように一導電型半導体層上
に逆導電型半導体層13を形成し、島状半導体層の配列
方向と交差する方向の同じ側から個別電極14を接続し
て、この個別電極14を島状半導体層の配列方向と交差
する方向の両側に交互に振り分けて引き出す発光ダイオ
ードアレイもある。この場合も、共通電極15は島状半
導体層の配列方向と交差する方向の両側に振り分けて引
き出される。 【0008】このように、一導電型半導体層12の露出
部を島状半導体層の配列方向と交差する方向の同じ側に
設けると、逆導電型半導体層13をパターニングする際
にマスクパターンに位置ずれが発生しても、発光ダイオ
ードごとの発光ばらつきは防止できる。すなわち、逆導
電型半導体層13をパターニングする際にマスクパター
ンに基板11の短手方向の位置ずれが発生しても、全て
の逆導電型半導体層が大きくなったり、小さくなったり
することから、個々の発光ダイオード毎の発光ばらつき
は発生しない。 【0009】ところが、この従来の発光ダイオードアレ
イでは、島状半導体層の両側に電極の配線パターンが存
在する発光ダイオードと、島状半導体層の片側にしか電
極の配線パターンが存在しない発光ダイオードが混在
し、この電極の配線パターンの有無によって、発光した
光の反射状態が不規則なり、発光ばらつきが発生すると
いう問題が生じる。 【0010】本発明はこのような従来の技術の問題点に
鑑みてなされたものであり、島状半導体層の近傍におけ
る電極の配線パターンの有無によって発光ダイオードに
発光ばらつきが発生することを解消した発光ダイオード
アレイを提供することを目的とする。 【0011】 【課題を解決するための手段】上記目的を達成するため
に、本発明に係る発光ダイオードアレイによれば、一導
電型半導体層と逆導電型半導体層とが積層された複数の
島状半導体層を基板上に列状に配置して、この一導電型
半導体層に共通電極を接続して設けると共に、前記逆導
電型半導体層に個別電極を接続して設けた発光ダイオー
ドアレイにおいて、前記島状半導体層の配列方向と交差
する方向の同じ側から前記隣接する逆導電型半導体層毎
に同じ個別電極に接続して前記基板の対向する端面側に
交互に引き出すと共に、前記島状半導体層の配列方向と
交差する方向の両側に前記共通電極を設けて、前記島状
半導体層の配列方向と交差する方向の反対側から前記同
じ個別電極に接続された逆導電型半導体層下部の一導電
型半導体層毎に前記両側の共通電極に交互に振り分けて
接続し、この個別電極と共通電極に接続するための配線
が通過しない前記島状半導体層間にダミー配線を設け
た。 【0012】 【発明の実施の形態】以下、本発明を添付図面に基づき
詳細に説明する。図1は本発明に係る発光ダイオードア
レイを平面視した状態を示す図、図2は図1中のA−A
線断面図、図3は図1のB−B線断面図である。図1な
いし図3において、1は基板、2は一導電型半導体層、
3は逆導電型半導体層、4は個別電極、5は共通電極、
6は絶縁膜、7はダミー配線である。 【0013】基板1はシリコン(Si)やガリウム砒素
(GaAs)などの単結晶半導体基板、またはサファイ
ア(Al2 3 )などの単結晶絶縁基板から成る。単結
晶半導体基板の場合、(100)面を<011>方向に
2〜7°オフさせた基板などが好適に用いられる。ま
た、サファイアの場合、C面基板などが好適に用いられ
る。 【0014】一導電型半導体層2は、バッファ層2a、
オーミックコンタクト層2b、およびクラッド層2cで
構成される。バッファ層2aは1〜3μm程度の厚みに
形成され、オーミックコンタクト層2bは0.01〜
0.1μm程度の厚みに形成され、クラッド層2cは
0.2〜0.4μm程度の厚みに形成される。バッファ
層2a、オーミックコンタクト層2bはガリウム砒素な
どで形成され、クラッド層2cはアルミニウムガリウム
砒素(AlGaAs)などで形成される。オーミックコ
ンタクト層2bはシリコン(Si)やセレン(Se)な
どの一導電型半導体不純物を1×1019〜1022ato
ms/cm3 程度含有し、クラッド層2cはシリコン
(Si)やセレン(Se)などの一導電型半導体不純物
を1×1016〜1019atoms/cm3 程度含有す
る。バッファ層2aは、基板1と島状半導体層2、3と
の格子定数の相違に基づくミスフィット転位を防止する
ために設けるものであり、必ずしも半導体不純物を含有
させる必要はない。 【0015】逆導電型半導体層3は、発光層3a、第2
のクラッド層3b、および第2のオーミックコンタクト
層3cで構成される。発光層3aと第2のクラッド層3
bは0.2〜0.4μm程度の厚みに形成され、第2の
オーミックコンタクト層3cは0.01〜0.1μm程
度の厚みに形成される。発光層3a、第2のクラッド層
3bはアルミニウムガリウム砒素などで形成され、第2
のオーミックコンタクト層3cはガリウム砒素などで構
成される。 【0016】発光層3aと第2のクラッド層3bは、電
子の閉じ込め効果と光の取り出し効果を考慮してAlA
sとGaAsの混晶比が異なるように構成される。発光
層3a、第2のクラッド層3bは亜鉛(Zn)などの逆
導電型半導体不純物を1×1016〜1019atoms/
cm3 程度含有し、第2のオーミックコンタクト層3c
は亜鉛(Zn)などの逆導電型半導体不純物を1×10
19〜1022atoms/cm3 程度含有する。 【0017】絶縁膜6は窒化シリコン(SiNx )膜な
どから成り、厚み3000Å程度に形成される。個別電
極4と共通電極5は、金(Au)や金(Au)とクロム
(Cr)の二層膜などから成り、厚み1μm程度に形成
される。 【0018】基板1上に複数の島状半導体層が列状に配
置され、一導電型半導体層2の同じ側が露出するよう
に、逆導電型半導体層3が形成されている。この逆導電
型半導体層3上に、島状半導体層の配列方向と交差する
方向の同じ側から個別電極4を接続し、島状半導体層の
配列方向と交差する方向の両側に振り分けて引き出され
ている。また、同じ個別電極4に接続された逆導電型半
導体層3の下部に位置する一導電型半導体層2が異なる
共通電極5a、5bに接続されるように、交互に振り分
けて基板1の長手方向の端面側に引き出されている。個
別電極4と共通電極5の組み合わせを選択して個別電極
4から共通電極5に電流を流して、選択的に発光させる
ことにより、ページプリンタ用感光ドラムの露光用光源
として用いられる。 【0019】このように一導電型半導体層2の露出部を
島状半導体層の配列方向と交差する方向の同じ側に設け
ることによって、逆導電型半導体層3を形成する際のパ
ターンずれによる逆導電型半導体層の面積のばらつきを
防止でき、その結果、発光ダイオード毎の発光ばらつき
を防止できる。 【0020】また、一導電型半導体層2の露出部を島状
半導体層の配列方向と交差する方向の同じ側に設けて、
個別電極4と共通電極5を半導体基板1の長手方向の端
面側に交互に引き出すと、両側に電極の配線パターンが
存在する島状半導体層と、片側にしか電極の配線パター
ンが存在しない島状半導体層ができる。図1に示す発光
ダイオードアレイでは、例えば二番目、三番目、四番
目、七番目、八番目の島状半導体層
はその両側に電極の配線パターンが存在するが、五番
目、六番目、九番目、十番目の島状半導体層
10はその片側にしか電極の配線パターンが存在し
ない。そこで、本発明では、五番目と六番目の島状半導
体層間、および九番目と十番目の島状半導体層
10間にダミー配線7を設け、最端部の島状半導体
層を除く全ての島状半導体層の両側に電極の配線パター
ンが位置するように構成する。 【0021】このダミー配線7の幅や厚みや材料は、光
の反射の均一性や製造工程からして、個別電極4や共通
電極5と全く同じ構成であることが望ましい。すなわ
ち、金(Au)や金(Au)とクロム(Cr)の二層膜
などから成り、厚み1μm程度、幅1〜20μm程度に
形成される。長さは、各島状半導体層の長さと同じかそ
れ以上であればよい。さらに、このダミー配線7は、島
状半導体層からの光を適正に反射させるためだけのもの
であり、必ずしも他の配線部材と接続される必要はな
い。 【0022】このように、全ての島状半導体層の両側に
電極の配線パターンやダミー配線7が存在すると、全て
の島状半導体層から発する光の反射状態が同じになり、
発光ダイオード毎の発光ばらつきが無くなる。 【0023】次に、上述のような半導体発光素子の製造
方法を説明する。まず、単結晶基板1上に、一導電型半
導体層2、逆導電型半導体層3をMOCVD法などで順
次積層して形成する。 【0024】これらの半導体層2、3を形成する場合、
まず基板温度を400〜500℃に設定して200〜2
000Åの厚みにアモルファス状のガリウム砒素膜を形
成した後に、基板温度を700〜900℃に上げて所望
厚みの半導体層2、3を形成する。 【0025】この場合、原料ガスとしてはTMG((C
3 3 Ga)、TEG((C2 5 3 Ga)、アル
シン(AsH3 )、TMA((CH3 3 Al)、TE
A((C2 5 3 Al)などが用いられ、導電型を制
御するめのガスとしてはシラン(SiH4 )、水素化セ
レン(SeH2 )、DMZ((CH3 3 Zn)などが
用いられ、キャリアガスとしては水素(H2 )などが用
いられる。 【0026】次に、隣接する素子同志が電気的に分離さ
れるように、半導体層2、3が島状にパターニングさ
れ、さらに一導電型半導体層2と共通電極5との接続部
が露出するように、逆導電型半導体層3の一部がパター
ニングされる。このような半導体層2、3のエッチング
は、硫酸過酸化水素系のエッチング液を用いたウェット
エッチングや、CCl2 2 ガスを用いたドライエッチ
ングなどで行われる。 【0027】次に、絶縁膜6をシランガス(SiH4
とアンモニガス(NH3 )を用いたプラズマCVD法な
どで形成した後に、弗酸(HF)系のエッチング液を用
いたドライエッチングやCF4 ガスを用いたドライエッ
チングなどで半導体層2、3と電極4、5の接続部であ
るコンタクトホールC1 、C2 (図3参照)を形成す
る。 【0028】最後に、個別電極4、共通電極5、および
ダミー配線7を蒸着法やスパッタリング法で形成してパ
ターニングすることにより完成する。 【0029】 【発明の効果】以上のように、本発明に係る発光ダイオ
ードアレイによれば、基板上に形成した島状半導体層の
配列方向と交差する方向の同じ側から隣接する逆導電型
半導体層毎に同じ個別電極に接続して基板の対向する端
面側に交互に引き出すと共に、島状半導体層の配列方向
と交差する方向の両側に共通電極を設けて、島状半導体
層の配列方向と交差する方向の反対側から上記同じ個別
電極に接続された逆導電型半導体層下部の一導電型半導
体層毎に上記両側の共通電極に交互に振り分けて接続
し、この個別電極と共通電極に接続するための配線が通
過しない島状半導体層間にダミー配線を設けたことか
ら、最端部を除いた全ての島状半導体層の両側に電極の
配線パターンもしくはダミー配線が位置し、島状半導体
層近傍の配線材料の有無によって島状半導体層から発す
る光の反射状態が異なることがなくなって、駆動回路に
よる発光状態の補正が不要か容易になる。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array, and more particularly to a light emitting diode array used as a light source for exposing a photosensitive drum for a page printer. 2. Description of the Related Art FIGS. 4 and 5 show a conventional light emitting diode array. FIG.
FIG. 5 shows a plan view of the light emitting diode array, and FIG.
Indicates a cross section of one light emitting element. 4 and 5, 11 is a substrate, 12 is a semiconductor layer of one conductivity type, 13 is a semiconductor layer of the opposite conductivity type, 14 is an individual electrode, 15 is a common electrode, 16
Is an insulating film. [0003] On a substrate 11, an island-shaped semiconductor layer in which a one-conductivity-type semiconductor layer 12 made of gallium arsenide or the like and a reverse-conductivity-type semiconductor layer 13 are stacked is arranged in a row. The opposite conductivity type semiconductor layer 13 is formed in a smaller area than the one conductivity type semiconductor layer 12 so that a part of the one conductivity type semiconductor layer 12 is exposed. A common electrode 15 is connected to an exposed portion of the one conductivity type semiconductor layer 12, and an individual electrode 14 is connected to an upper portion of the opposite conductivity type semiconductor layer 13. As shown in FIG. 4, one individual electrode 14 is provided to be connected to each adjacent opposite conductive semiconductor layer 13, and one conductive semiconductor layer below the opposite conductive semiconductor layer 13 connected to the same individual electrode 14. 12 are configured to be separately connected to the common electrodes 15a and 15b. Each light emitting diode is composed of the island-shaped semiconductor layer, the individual electrode 14 and the common electrode 15. A combination of the individual electrode 14 and the common electrode 15 is selected, and a current flows from the individual electrode 14 to the common electrodes 15a and 15b to selectively emit light from a plurality of light emitting diodes, thereby exposing the photosensitive drum for a page printer. Used as a light source. However, in this conventional light emitting diode array, when patterning the opposite conductivity type semiconductor layer 13 so that a part of the one conductivity type semiconductor layer 12 is exposed, the mask pattern is formed in the short direction of the substrate 1. When the misalignment occurs, the opposite conductivity type semiconductor layer 13 becomes larger or smaller for each island-shaped semiconductor layer, so that light emitting diodes having different light emitting areas are formed, and there is a problem that light emission variation occurs. . Therefore, as shown in FIG. 6, a reverse conductivity type semiconductor layer 13 is formed on the one conductivity type semiconductor layer so that the same side of the one conductivity type semiconductor layer 12 is exposed. There is also a light emitting diode array in which the individual electrodes 14 are connected from the same side in the direction intersecting, and the individual electrodes 14 are alternately distributed and drawn out on both sides in the direction intersecting with the arrangement direction of the island-shaped semiconductor layers. Also in this case, the common electrode 15 is distributed and drawn out on both sides in a direction intersecting the arrangement direction of the island-shaped semiconductor layers. As described above, when the exposed portion of the one conductivity type semiconductor layer 12 is provided on the same side in the direction intersecting the arrangement direction of the island-shaped semiconductor layers, the position of the mask pattern when patterning the opposite conductivity type semiconductor layer 13 is increased. Even if the displacement occurs, it is possible to prevent light emission variation between the light emitting diodes. That is, even when the mask pattern is misaligned in the lateral direction of the substrate 11 when patterning the opposite conductivity type semiconductor layer 13, all the opposite conductivity type semiconductor layers become larger or smaller. Light emission variation does not occur for each light emitting diode. However, in this conventional light-emitting diode array, light-emitting diodes having electrode wiring patterns on both sides of the island-like semiconductor layer and light-emitting diodes having electrode wiring patterns on only one side of the island-like semiconductor layer coexist. However, depending on the presence or absence of the wiring pattern of the electrodes, the reflection state of the emitted light becomes irregular, which causes a problem that light emission variation occurs. The present invention has been made in view of such a problem of the prior art, and has solved the problem that light emission variation occurs in a light emitting diode due to the presence or absence of an electrode wiring pattern near an island-shaped semiconductor layer. An object is to provide a light emitting diode array. In order to achieve the above object, according to a light emitting diode array according to the present invention, a plurality of islands in which a semiconductor layer of one conductivity type and a semiconductor layer of opposite conductivity type are stacked. The semiconductor layers are arranged in a row on a substrate, and a common electrode is connected to the one-conductivity-type semiconductor layer, and the individual electrodes are connected to the opposite-conductivity-type semiconductor layer. Connected to the same individual electrode for each of the adjacent opposite conductivity type semiconductor layers from the same side in a direction intersecting with the arrangement direction of the island-shaped semiconductor layers and alternately pulled out to the opposite end face side of the substrate, The common electrodes are provided on both sides in a direction intersecting the arrangement direction of the layers, and a lower conductive type semiconductor layer connected to the same individual electrode from a side opposite to the direction intersecting the arrangement direction of the island-shaped semiconductor layers. Conductive type half Each conductor layer was alternately divided and connected to the common electrodes on both sides, and dummy wires were provided between the island-shaped semiconductor layers through which wires for connecting to the individual electrodes and the common electrode did not pass. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing the light emitting diode array according to the present invention in a plan view, and FIG.
FIG. 3 is a sectional view taken along line BB of FIG. 1. 1 to 3, 1 is a substrate, 2 is a semiconductor layer of one conductivity type,
3 is a reverse conductivity type semiconductor layer, 4 is an individual electrode, 5 is a common electrode,
6 is an insulating film and 7 is a dummy wiring. The substrate 1 is formed of a single crystal semiconductor substrate such as silicon (Si) or gallium arsenide (GaAs) or a single crystal insulating substrate such as sapphire (Al 2 O 3 ). In the case of a single crystal semiconductor substrate, a substrate whose (100) plane is turned off by 2 to 7 ° in the <011> direction is preferably used. In the case of sapphire, a C-plane substrate or the like is preferably used. The one conductivity type semiconductor layer 2 includes a buffer layer 2a,
It comprises an ohmic contact layer 2b and a cladding layer 2c. The buffer layer 2a has a thickness of about 1 to 3 μm, and the ohmic contact layer 2b has a thickness of 0.01 to 3 μm.
The cladding layer 2c is formed to a thickness of about 0.2 to 0.4 μm. The buffer layer 2a and the ohmic contact layer 2b are formed of gallium arsenide or the like, and the cladding layer 2c is formed of aluminum gallium arsenide (AlGaAs) or the like. The ohmic contact layer 2b is made of one conductivity type semiconductor impurity such as silicon (Si) or selenium (Se) at 1 × 10 19 to 10 22 at.
contains about ms / cm 3, the cladding layer 2c is one conductivity type semiconductor impurity such as silicon (Si) or selenium (Se) containing approximately 1 × 10 16 ~10 19 atoms / cm 3. The buffer layer 2a is provided to prevent misfit dislocation due to a difference in lattice constant between the substrate 1 and the island-shaped semiconductor layers 2, 3, and does not necessarily need to contain semiconductor impurities. The opposite conductivity type semiconductor layer 3 includes the light emitting layer 3a, the second
And a second ohmic contact layer 3c. Light emitting layer 3a and second cladding layer 3
b is formed to a thickness of about 0.2 to 0.4 μm, and the second ohmic contact layer 3c is formed to a thickness of about 0.01 to 0.1 μm. The light emitting layer 3a and the second cladding layer 3b are formed of aluminum gallium arsenide or the like.
Is formed of gallium arsenide or the like. The light emitting layer 3a and the second cladding layer 3b are made of AlA in consideration of an electron confinement effect and a light extraction effect.
It is configured such that the mixed crystal ratio of s and GaAs is different. The light emitting layer 3a and the second cladding layer 3b contain opposite conductive semiconductor impurities such as zinc (Zn) at 1 × 10 16 to 10 19 atoms /.
cm 3 , the second ohmic contact layer 3c
Represents 1 × 10 of a reverse conductivity type semiconductor impurity such as zinc (Zn).
It contains about 19 to 10 22 atoms / cm 3 . The insulating film 6 is made of a silicon nitride (SiN x ) film or the like and has a thickness of about 3000 °. The individual electrode 4 and the common electrode 5 are made of gold (Au) or a two-layer film of gold (Au) and chromium (Cr), and have a thickness of about 1 μm. A plurality of island-shaped semiconductor layers are arranged in a row on a substrate 1, and a semiconductor layer 3 of the opposite conductivity type is formed such that the same side of the semiconductor layer 2 of one conductivity type is exposed. The individual electrodes 4 are connected to the opposite conductivity type semiconductor layer 3 from the same side in the direction intersecting the arrangement direction of the island-shaped semiconductor layers, and are separated and drawn out on both sides in the direction intersecting the arrangement direction of the island-shaped semiconductor layers. ing. In addition, the one conductivity type semiconductor layer 2 located under the opposite conductivity type semiconductor layer 3 connected to the same individual electrode 4 is alternately distributed so as to be connected to different common electrodes 5a and 5b. It is pulled out to the end face side. A combination of the individual electrode 4 and the common electrode 5 is selected, and a current is supplied from the individual electrode 4 to the common electrode 5 to selectively emit light, thereby being used as an exposure light source for a photosensitive drum for a page printer. By providing the exposed portion of the one-conductivity-type semiconductor layer 2 on the same side in the direction intersecting with the arrangement direction of the island-shaped semiconductor layers, the reverse conductivity due to the pattern shift when the opposite-conductivity-type semiconductor layer 3 is formed is provided. Variations in the area of the conductive semiconductor layer can be prevented, and as a result, variations in light emission for each light emitting diode can be prevented. Further, the exposed portion of the one conductivity type semiconductor layer 2 is provided on the same side in a direction intersecting the arrangement direction of the island-shaped semiconductor layers,
When the individual electrodes 4 and the common electrode 5 are alternately pulled out to the end face side in the longitudinal direction of the semiconductor substrate 1, an island-shaped semiconductor layer having electrode wiring patterns on both sides and an island-shaped layer having electrode wiring patterns on only one side are provided. A semiconductor layer is formed. In the light emitting diode array shown in FIG. 1, for example, the second, third, fourth, seventh, and eighth island-shaped semiconductor layers 2 , 3 , 4 , 7 , 8,
Has electrode wiring patterns on both sides thereof, but the fifth, sixth, ninth, and tenth island-shaped semiconductor layers 5 , 6 , and.
9 and 10 have an electrode wiring pattern only on one side thereof. Therefore, in the present invention, the fifth and sixth island-shaped semiconductor layers 5 , 6 and the ninth and tenth island-shaped semiconductor layers
Dummy wirings 7 are provided between 9 and 10, and the wiring patterns of the electrodes are located on both sides of all the island-shaped semiconductor layers except for the endmost island-shaped semiconductor layers. It is desirable that the width, thickness, and material of the dummy wiring 7 be exactly the same as those of the individual electrode 4 and the common electrode 5 from the viewpoint of uniformity of light reflection and the manufacturing process. That is, it is made of gold (Au) or a two-layer film of gold (Au) and chromium (Cr) and has a thickness of about 1 μm and a width of about 1 to 20 μm. The length may be equal to or longer than the length of each island-shaped semiconductor layer. Further, the dummy wiring 7 is only for appropriately reflecting light from the island-shaped semiconductor layer, and does not necessarily need to be connected to another wiring member. As described above, when the electrode wiring patterns and the dummy wirings 7 exist on both sides of all the island-shaped semiconductor layers, the reflection state of light emitted from all the island-shaped semiconductor layers becomes the same,
Emission variations between light emitting diodes are eliminated. Next, a method for manufacturing the above-described semiconductor light emitting device will be described. First, a semiconductor layer 2 of one conductivity type and a semiconductor layer 3 of opposite conductivity type are sequentially formed on a single crystal substrate 1 by MOCVD or the like. When these semiconductor layers 2 and 3 are formed,
First, the substrate temperature is set to 400 to 500 ° C. and 200 to 2
After forming an amorphous gallium arsenide film to a thickness of 000 °, the substrate temperature is raised to 700 to 900 ° C. to form semiconductor layers 2 and 3 having a desired thickness. In this case, TMG ((C
H 3 ) 3 Ga), TEG ((C 2 H 5 ) 3 Ga), arsine (AsH 3 ), TMA ((CH 3 ) 3 Al), TE
A ((C 2 H 5 ) 3 Al) or the like is used, and silane (SiH 4 ), selenium hydride (SeH 2 ), DMZ ((CH 3 ) 3 Zn) or the like is used as a gas for controlling the conductivity type. Hydrogen (H 2 ) is used as the carrier gas. Next, the semiconductor layers 2 and 3 are patterned in an island shape so that adjacent elements are electrically separated from each other, and a connection portion between the one conductivity type semiconductor layer 2 and the common electrode 5 is exposed. Thus, a part of the opposite conductivity type semiconductor layer 3 is patterned. Such etching of the semiconductor layers 2 and 3 is performed by wet etching using a sulfuric acid-hydrogen peroxide-based etchant, dry etching using CCl 2 F 2 gas, or the like. Next, the insulating film 6 is made of silane gas (SiH 4 ).
After forming the semiconductor layers 2 and 3 by dry etching using a hydrofluoric acid (HF) -based etchant or dry etching using a CF 4 gas, the electrodes are formed by a plasma CVD method or the like using an ammonia gas (NH 3 ). Contact holes C 1 and C 2 (see FIG. 3), which are connection portions of 4, 5 are formed. Finally, the individual electrodes 4, the common electrodes 5, and the dummy wirings 7 are formed by vapor deposition or sputtering, and are completed by patterning. As described above, according to the light emitting diode array according to the present invention, the opposite conductivity type semiconductor adjacent from the same side in the direction intersecting the arrangement direction of the island-shaped semiconductor layers formed on the substrate is provided. Each layer is connected to the same individual electrode and alternately pulled out to the opposite end face side of the substrate, and common electrodes are provided on both sides in a direction intersecting with the arrangement direction of the island-like semiconductor layers, and the arrangement direction of the island-like semiconductor layers is From the opposite side of the intersecting direction, alternately connecting to the common electrodes on both sides for each one conductive semiconductor layer below the opposite conductive semiconductor layer connected to the same individual electrode, and connecting to this individual electrode and the common electrode Since the dummy wiring is provided between the island-shaped semiconductor layers through which the wiring for the wiring does not pass, the wiring pattern of the electrode or the dummy wiring is located on both sides of all the island-shaped semiconductor layers except for the end portion, and the island-shaped semiconductor layer is formed. Nearby The reflection state of the light emitted from the island-shaped semiconductor layer does not differ depending on the presence or absence of the wiring material, and it becomes unnecessary or easy to correct the emission state by the drive circuit.

【図面の簡単な説明】 【図1】本発明に係る発光ダイオードアレイの一実施形
態を示す平面図である。 【図2】図1中のA−A線断面図である。 【図3】図1中のB−B線断面図である。 【図4】従来の発光ダイオードアレイを示す平面図であ
る。 【図5】図4中のA−A線断面図である。 【図6】従来の他の発光ダイオードアレイを示す平面図
である。 【符号の説明】 1‥‥‥基板、2‥‥‥一導電型半導体層、3‥‥‥逆
導電型半導体層、4‥‥‥個別電極、5‥‥‥共通電
極、6‥‥‥絶縁膜、7‥‥‥ダミー配線
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing one embodiment of a light emitting diode array according to the present invention. FIG. 2 is a sectional view taken along line AA in FIG. FIG. 3 is a sectional view taken along line BB in FIG. 1; FIG. 4 is a plan view showing a conventional light emitting diode array. FIG. 5 is a sectional view taken along line AA in FIG. 4; FIG. 6 is a plan view showing another conventional light emitting diode array. [Description of Signs] 1 substrate, 2 semiconductor layer of one conductivity type, 3 semiconductor layer of reverse conductivity type, 4 individual electrodes, 5 common electrode, 6 insulation Film, 7mm dummy wiring

Claims (1)

(57)【特許請求の範囲】 【請求項1】 一導電型半導体層と逆導電型半導体層と
が積層された複数の島状半導体層を基板上に列状に配置
して、この一導電型半導体層に共通電極を接続して設け
ると共に、前記逆導電型半導体層に個別電極を接続して
設けた発光ダイオードアレイにおいて、前記島状半導体
層の配列方向と交差する方向の同じ側から前記隣接する
逆導電型半導体層毎に同じ個別電極に接続して前記基板
の対向する端面側に交互に引き出すと共に、前記島状半
導体層の配列方向と交差する方向の両側に前記共通電極
を設けて、前記島状半導体層の配列方向と交差する方向
の反対側から前記同じ個別電極に接続された逆導電型半
導体層下部の一導電型半導体層毎に前記両側の共通電極
に交互に振り分けて接続し、この個別電極と共通電極に
接続するための配線が通過しない前記島状半導体層間に
ダミー配線を設けたことを特徴とする発光ダイオードア
レイ。
(57) [Claim 1] A plurality of island-like semiconductor layers in which a semiconductor layer of one conductivity type and a semiconductor layer of opposite conductivity type are stacked are arranged in a row on a substrate, and In a light emitting diode array provided with a common electrode connected to the type semiconductor layer and connected with an individual electrode to the opposite conductivity type semiconductor layer, the light emitting diode array is formed from the same side in a direction intersecting the arrangement direction of the island-shaped semiconductor layers. Connected to the same individual electrode for each adjacent opposite conductivity type semiconductor layer and alternately drawn to the opposite end face side of the substrate, and the common electrodes are provided on both sides in a direction intersecting the arrangement direction of the island-shaped semiconductor layers. The common electrodes on both sides are alternately arranged for each one conductive type semiconductor layer below the opposite conductive type semiconductor layer connected to the same individual electrode from a side opposite to the direction intersecting the arrangement direction of the island-shaped semiconductor layers. And connect them to the individual electrodes. Light-emitting diode array, wherein a wiring for connecting to the electrode provided with dummy wirings to the island-like semiconductor layers which does not pass through.
JP32845297A 1997-11-28 1997-11-28 Light emitting diode array Expired - Fee Related JP3517101B2 (en)

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Application Number Priority Date Filing Date Title
JP32845297A JP3517101B2 (en) 1997-11-28 1997-11-28 Light emitting diode array

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Application Number Priority Date Filing Date Title
JP32845297A JP3517101B2 (en) 1997-11-28 1997-11-28 Light emitting diode array

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Publication Number Publication Date
JPH11163408A JPH11163408A (en) 1999-06-18
JP3517101B2 true JP3517101B2 (en) 2004-04-05

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Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP3517101B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001085740A (en) * 1999-09-09 2001-03-30 Nippon Sheet Glass Co Ltd Method for designing mask dimension of surface-emitting element
JP5202042B2 (en) 2008-03-10 2013-06-05 シチズン電子株式会社 LED lamp

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