JP2001085740A - Method for designing mask dimension of surface-emitting element - Google Patents
Method for designing mask dimension of surface-emitting elementInfo
- Publication number
- JP2001085740A JP2001085740A JP25558299A JP25558299A JP2001085740A JP 2001085740 A JP2001085740 A JP 2001085740A JP 25558299 A JP25558299 A JP 25558299A JP 25558299 A JP25558299 A JP 25558299A JP 2001085740 A JP2001085740 A JP 2001085740A
- Authority
- JP
- Japan
- Prior art keywords
- width
- mask
- wiring
- electrode
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70216—Mask projection systems
- G03F7/70358—Scanning exposure, i.e. relative movement of patterned beam and workpiece during imaging
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、面発光素子の外部
発光効率のばらつきを抑えた金属配線形状を得るための
マスク寸法の設計方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a mask dimension for obtaining a metal wiring shape in which a variation in external light emitting efficiency of a surface light emitting element is suppressed.
【0002】[0002]
【従来の技術】面発光型発光ダイオードのような面発光
素子では、必然的に電流を注入するための電極が発光面
の一部を覆うため、外部発光効率の低下が少なく、かつ
発光面ができるだけ均一に発光するような構造が要求さ
れる。図1は、このような要求を満たすメサ型発光ダイ
オードの構造の一例である。(A)は平面図、(B)は
断面図である。2. Description of the Related Art In a surface light emitting device such as a surface emitting light emitting diode, an electrode for injecting current necessarily covers a part of the light emitting surface, so that the decrease in external light emitting efficiency is small and the light emitting surface is small. A structure that emits light as uniformly as possible is required. FIG. 1 shows an example of the structure of a mesa light emitting diode satisfying such a requirement. (A) is a plan view and (B) is a sectional view.
【0003】この発光ダイオードでは、基板10上に形
成された半導体層よりなる発光部12のpn接合表面の
中央部にオーミック接触したAu電極14が設けられ、
発光面全体を透明な絶縁膜16で覆われる。この絶縁膜
に孔開けをしてコンタクトホール18とし、その上部に
金属(Al)配線20を設ける。In this light-emitting diode, an Au electrode 14 in ohmic contact is provided at the center of the pn junction surface of a light-emitting portion 12 made of a semiconductor layer formed on a substrate 10;
The entire light emitting surface is covered with a transparent insulating film 16. A hole is formed in this insulating film to form a contact hole 18, and a metal (Al) wiring 20 is provided thereon.
【0004】この構造によれば、オーミック電極14が
発光面中央の対称な位置に設けられているので、発光の
均一性がよく、この電極の面積を小さくする(例えば発
光部20μm角に対し、5μm角)ことにより、外部発
光効率の低下を防ぐことができる。According to this structure, since the ohmic electrode 14 is provided at a symmetrical position at the center of the light emitting surface, the uniformity of light emission is good, and the area of this electrode is reduced (for example, for a light emitting portion of 20 μm square). (5 μm square) can prevent a decrease in external luminous efficiency.
【0005】[0005]
【発明が解決しようとする課題】オーミック電極(A
u)は一般に0.1μm程度の厚さがあればよいので、
繰り返し精度よくパターニングができるが(±0.5μ
m以下)、上部のAl配線は発光部から外へ出る際、メ
サの段差を通るので、段切れを防止するため1μm程度
に厚く形成する必要がある。このような厚さのAl膜の
パターニング精度は良くない(±1μm程度)。これは
Alをエッチングする際、パターン側面がエッチングさ
れるためである。このAl側面のエッチングのばらつき
により、パターニングの結果Au電極よりAl電極の幅
が広くなる場合があった。この場合、Al配線による遮
光により、光出力が低下する。特に、この発光ダイオー
ドをアレイにし、光プリント・ヘッドに応用するような
場合、素子間の光出力のばらつきの主要原因となるとい
う問題点があった。SUMMARY OF THE INVENTION An ohmic electrode (A
Since u) generally needs only to have a thickness of about 0.1 μm,
Patterning can be performed with high repeatability (± 0.5μ
m), since the upper Al wiring passes through the step of the mesa when it goes out of the light emitting portion, it needs to be formed to a thickness of about 1 μm to prevent disconnection. The patterning accuracy of the Al film having such a thickness is not good (about ± 1 μm). This is because when etching Al, the pattern side surface is etched. Due to the variation in etching of the Al side surface, the width of the Al electrode may be wider than the Au electrode as a result of patterning. In this case, light output is reduced due to light shielding by the Al wiring. In particular, when the light emitting diodes are formed into an array and applied to an optical print head, there is a problem that the light output becomes a major cause of variation in light output between elements.
【0006】本発明の目的は、金属配線の幅を、オーミ
ック電極の幅よりも小さく、かつ、コンタクトホールの
幅よりも大きくできるように、金属配線をエッチングに
より形成する際のマスク寸法の設計方法を提供すること
にある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for designing a mask dimension when etching a metal wiring so that the width of the metal wiring can be made smaller than the width of the ohmic electrode and larger than the width of the contact hole. Is to provide.
【0007】[0007]
【課題を解決するための手段】本発明は、基板上に形成
された半導体層よりなる発光部にオーミック接触した金
属電極が、絶縁膜に開けられたコンタクトホールを介し
て金属配線に接続されている面発光素子において、前記
金属配線をマスクを用いたエッチングにより形成する際
のマスク寸法の設計方法であって、前記マスクの幅をW
とした場合、 L+2(S+dS)+a>W>C+2(S+dS)+2
a ただし、Lは前記金属電極の幅、Cは前記コンタクトホ
ールの幅、Sは前記金属配線の側面のエッチング量の
幅、dSはエッチング量のばらつき、aはマスクのアラ
イメントのずれである を満たすように、Wを選ぶことを特徴とするマスク寸法
の設計方法である。According to the present invention, a metal electrode which is in ohmic contact with a light emitting portion comprising a semiconductor layer formed on a substrate is connected to a metal wiring via a contact hole formed in an insulating film. A method for designing mask dimensions when forming the metal wiring by etching using a mask, wherein the width of the mask is W
L + 2 (S + dS) + a>W> C + 2 (S + dS) +2
a where L is the width of the metal electrode, C is the width of the contact hole, S is the width of the etching amount on the side surface of the metal wiring, dS is the variation of the etching amount, and a is the misalignment of the mask. As described above, this is a method of designing a mask dimension characterized by selecting W.
【0008】このようなマスク寸法の設計方法により、
金属配線の幅をオーミック電極の幅よりも小さくするこ
とができるので、外部発光効率のばらつきを抑えること
が可能となる。According to such a mask dimension designing method,
Since the width of the metal wiring can be made smaller than the width of the ohmic electrode, it is possible to suppress variations in external luminous efficiency.
【0009】[0009]
【発明の実施の形態】図2は、本発明の実施例に係る発
光ダイオードを示す図であり、(A)は平面図、(B)
は断面図である。図において、図1と同じ構成要素に
は、同じ参照番号を付して示してある。FIG. 2 is a view showing a light emitting diode according to an embodiment of the present invention, wherein (A) is a plan view and (B).
Is a sectional view. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals.
【0010】Al電極20の幅が、Au電極14の幅よ
り小さくなるように、Al電極がパターニングされる。
このようなAl電極20をパターニングする際のマスク
寸法の設計寸法を、図3を参照して以下に詳細に説明す
る。なお、図3は、Au電極,コンタクトホール,Al
配線用マスクの位置関係を示している。The Al electrode is patterned so that the width of the Al electrode 20 is smaller than the width of the Au electrode.
The design dimensions of the mask dimensions when patterning such an Al electrode 20 will be described in detail below with reference to FIG. FIG. 3 shows an Au electrode, a contact hole, and an Al electrode.
The positional relationship of the wiring mask is shown.
【0011】今、半導体層12上のAu電極14の幅を
Lとする。この電極パターンは、リフトオフ法により形
成するための寸法のばらつきは小さい。次に絶縁膜16
を被せ、これに幅Cのコンタクトホール18を開ける。
孔開けはドライエッチングで行うため、幅Cのばらつき
は少ない。ただしコンタクトホール18の位置は、マス
クのアライメントずれによりAu電極14の中央線22
から最大±aずれる。次に、Alを堆積し、マスク24
を設けて、Alをパターニングする。このときのマスク
24の幅をWとする。Alは段切れ防止のため厚さ1μ
m程度と厚くするので、このマスクを使用してパターニ
ングし、リン酸系エッチング液によりエッチングする
と、不要部分のAlが除去される間に配線部分の側面の
エッチングが進み、マスク幅Wに比べて仕上がりのAl
幅W′は小さくなる。今、配線の側面のエッチング量
(幅)をSとする。ただしこのエッチング量には、ばら
つき±dSが生じる。これらを考慮すると、 W′=W−2(S±dS) (1) となる。Here, the width of the Au electrode 14 on the semiconductor layer 12 is L. This electrode pattern has a small dimensional variation to be formed by the lift-off method. Next, the insulating film 16
To form a contact hole 18 having a width C.
Since the holes are formed by dry etching, variations in the width C are small. However, the position of the contact hole 18 is set at the center line 22 of the Au electrode 14 due to misalignment of the mask.
From the maximum ± a. Next, Al is deposited and the mask 24 is deposited.
Is provided and Al is patterned. The width of the mask 24 at this time is W. Al is 1μ thick to prevent disconnection
Therefore, when patterning is performed using this mask and etching is performed using a phosphoric acid-based etchant, etching of the side surface of the wiring portion proceeds while Al in an unnecessary portion is removed, and the etching proceeds in comparison with the mask width W. Finished Al
The width W 'becomes smaller. Now, let S be the etching amount (width) of the side surface of the wiring. However, a variation ± dS occurs in this etching amount. Considering these, W ′ = W−2 (S ± dS) (1)
【0012】この発明の目的である外部発光効率のばら
つきの抑制のためには、Al配線20がAu電極14の
外側に出ないようにする必要がある。この条件はW′が
Lより小さければよいが、実際にはAu電極14の中央
線22に対してAl配線用のマスク24のアライメント
は、コンタクトホールのマスクと同様±aだけずれる恐
れがある。したがって必要とされる条件は、最悪の状態
を考慮して L>W−2(S+dS)−a (2) となる。ただしAl配線20の幅が狭くなり、Al配線
のいずれかの縁がコンタクトホール18にかかってはな
らない。これを考慮すると、 L>W−2(S+dS)−a>C+a (3) となるようにAl配線用マスク24の幅Wを決める必要
がある。上式を書き直すと、 L+2(S+dS)+a>W>C+2(S+dS)+2a (4) 今、L=10μm,C=3μmの発光ダイオードを作製
する場合の設計例は、次のようになる。Sは約1μm,
dSは約0.5μmで、aは約1μmであるとし、これ
を(4)式に代入すると、マスク幅Wは9〜14μmと
すれば良いことになる。この範囲の中心値11.5μm
程にWを選び、発光ダイオードを作製した。For the purpose of the present invention, in order to suppress variations in external light emission efficiency, it is necessary to prevent the Al wiring 20 from protruding outside the Au electrode 14. As long as W 'is smaller than L, the alignment of the Al wiring mask 24 with respect to the center line 22 of the Au electrode 14 may be shifted by ± a as in the case of the contact hole mask. Therefore, the required condition is L> W−2 (S + dS) −a (2) in consideration of the worst state. However, the width of the Al wiring 20 is reduced, and any edge of the Al wiring must not overlap the contact hole 18. In consideration of this, it is necessary to determine the width W of the Al wiring mask 24 such that L> W−2 (S + dS) −a> C + a (3) Rewriting the above equation, L + 2 (S + dS) + a>W> C + 2 (S + dS) + 2a (4) Now, a design example in the case of manufacturing a light emitting diode with L = 10 μm and C = 3 μm is as follows. S is about 1 μm,
Assuming that dS is about 0.5 μm and a is about 1 μm, and substituting this into Equation (4), the mask width W should be 9 to 14 μm. The central value of this range is 11.5 μm
W was selected in a suitable manner, and a light emitting diode was produced.
【0013】以上のようなマスク寸法の設計によれば、
Alのパターニングにばらつきがあっても、Al配線2
0がAu電極14の外側に出ることがなく、遮光は常に
安定したサイズであるAu電極によって起こるので、外
部発光効率のばらつきは小さい。According to the design of the mask dimensions as described above,
Even if the patterning of Al varies, the Al wiring 2
Since 0 does not come out of the Au electrode 14 and the light shielding always occurs with the Au electrode having a stable size, the variation in the external luminous efficiency is small.
【0014】n個の発光ダイオードをアレイとしたとき
の光出力のばらつきMを、 M=(最大光出力−最小光出力)/平均光出力×100
(%) で定義すると、n=128のとき、従来例の典型値は約
15%であったが、この発明のマスク寸法設計方法によ
るマスクにより形成されたAl配線によれば約10%に
減少した。The variation M of the light output when the n light emitting diodes are arranged in an array is expressed as follows: M = (maximum light output−minimum light output) / average light output × 100
(%), The typical value of the conventional example is about 15% when n = 128, but is reduced to about 10% according to the Al wiring formed by the mask according to the mask dimension designing method of the present invention. did.
【0015】以上の実施例では、面発光ダイオードを例
に説明したが、本発明はダイオードに限られず、pnp
n構造の面発光サイリスタなどの面発光素子に一般に適
用できることは、当業者には明らかであろう。In the above embodiment, the surface light emitting diode has been described as an example. However, the present invention is not limited to a diode.
It will be apparent to those skilled in the art that it is generally applicable to surface emitting devices such as n-type surface emitting thyristors.
【0016】[0016]
【発明の効果】本発明のマスク寸法の設計方法によれ
ば、金属配線の幅をオーミック電極の幅よりも小さくす
ることができるので、外部発光効率のばらつきを抑える
ことが可能となる。According to the mask dimension designing method of the present invention, since the width of the metal wiring can be made smaller than the width of the ohmic electrode, it is possible to suppress variations in external light emission efficiency.
【図1】メサ型発光ダイオードの構造の一例であり、
(A)は平面図、(B)は断面図である。FIG. 1 is an example of a structure of a mesa light emitting diode,
(A) is a plan view and (B) is a sectional view.
【図2】本発明に係る発光ダイオードを示す図であり、
(A)は平面図、(B)は断面図である。FIG. 2 is a view showing a light emitting diode according to the present invention;
(A) is a plan view and (B) is a sectional view.
【図3】Au電極,コンタクトホール,マスクの位置関
係を示す図である。FIG. 3 is a diagram showing a positional relationship between an Au electrode, a contact hole, and a mask.
10 基板 12 発光部 14 Au電極 16 絶縁膜 18 コンタクトホール 20 金属(Al)配線 DESCRIPTION OF SYMBOLS 10 Substrate 12 Light emitting part 14 Au electrode 16 Insulating film 18 Contact hole 20 Metal (Al) wiring
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大野 誠治 大阪府大阪市中央区道修町3丁目5番11号 日本板硝子株式会社内 Fターム(参考) 5F041 AA14 CA12 CA74 CA77 CA98 CB22 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Seiji Ohno 3-5-11 Doshomachi, Chuo-ku, Osaka-shi, Osaka F-term in Nippon Sheet Glass Co., Ltd. 5F041 AA14 CA12 CA74 CA77 CA98 CB22
Claims (3)
部にオーミック接触した金属電極が、絶縁膜に開けられ
たコンタクトホールを介して金属配線に接続されている
面発光素子において、前記金属配線をマスクを用いたエ
ッチングにより形成する際のマスク寸法の設計方法であ
って、 前記マスクの幅をWとした場合、 L+2(S+dS)+a>W>C+2(S+dS)+2
a ただし、Lは前記金属電極の幅、Cは前記コンタクトホ
ールの幅、Sは前記金属配線の側面のエッチング量の
幅、dSはエッチング量のばらつき、aはマスクのアラ
イメントのずれである を満たすように、Wを選ぶことを特徴とするマスク寸法
の設計方法。1. A surface-emitting device in which a metal electrode in ohmic contact with a light-emitting portion formed of a semiconductor layer formed on a substrate is connected to a metal wiring via a contact hole formed in an insulating film. This is a method of designing a mask dimension when wiring is formed by etching using a mask, where W is the width of the mask, and L + 2 (S + dS) + a>W> C + 2 (S + dS) +2
a where L is the width of the metal electrode, C is the width of the contact hole, S is the width of the etching amount on the side surface of the metal wiring, dS is the variation of the etching amount, and a is the misalignment of the mask. As described above, a mask dimension designing method characterized by selecting W.
徴とする請求項1記載のマスク寸法の設計方法。2. The method according to claim 1, wherein said metal wiring is an Al wiring.
リスタであることを特徴とする請求項1または2記載の
マスク寸法の設計方法。3. The method according to claim 1, wherein the surface light emitting device is a diode or a thyristor.
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25558299A JP2001085740A (en) | 1999-09-09 | 1999-09-09 | Method for designing mask dimension of surface-emitting element |
CN00801754A CN1321339A (en) | 1999-09-06 | 2000-09-05 | Method for designing mask pattern of self scanning light emitting device |
KR1020017005625A KR20010089400A (en) | 1999-09-06 | 2000-09-05 | Method for designing mask pattern of self scanning light emitting device |
EP00956928A EP1143523A1 (en) | 1999-09-06 | 2000-09-05 | Method for designing mask pattern of self scanning light emitting device |
TW089118112A TW457735B (en) | 1999-09-06 | 2000-09-05 | Method of designing mask for self-scanning light emitting devices |
US09/831,110 US6496973B1 (en) | 1999-09-06 | 2000-09-05 | Method for designing mask pattern of a self scanning light emitting device |
PCT/JP2000/006015 WO2001018868A1 (en) | 1999-09-06 | 2000-09-05 | Method for designing mask pattern of self scanning light emitting device |
CA002349624A CA2349624A1 (en) | 1999-09-06 | 2000-09-05 | Method of designing mask pattern for a self-scanning light-emitting device |
Applications Claiming Priority (1)
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JP25558299A JP2001085740A (en) | 1999-09-09 | 1999-09-09 | Method for designing mask dimension of surface-emitting element |
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JP2001085740A true JP2001085740A (en) | 2001-03-30 |
Family
ID=17280729
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JP25558299A Pending JP2001085740A (en) | 1999-09-06 | 1999-09-09 | Method for designing mask dimension of surface-emitting element |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108206234A (en) * | 2016-12-20 | 2018-06-26 | 乐金显示有限公司 | Light-emitting diode chip for backlight unit and the emitting diode display device including the chip |
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