JPH0716081B2 - Semiconductor light emitting device - Google Patents
Semiconductor light emitting deviceInfo
- Publication number
- JPH0716081B2 JPH0716081B2 JP19682187A JP19682187A JPH0716081B2 JP H0716081 B2 JPH0716081 B2 JP H0716081B2 JP 19682187 A JP19682187 A JP 19682187A JP 19682187 A JP19682187 A JP 19682187A JP H0716081 B2 JPH0716081 B2 JP H0716081B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inp
- light emitting
- emitting device
- semiconductor light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims description 20
- 230000012010 growth Effects 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000005253 cladding Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/002—Devices characterised by their operation having heterojunctions or graded gap
- H01L33/0025—Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/072—Heterojunctions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/099—LED, multicolor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、集積化を容易にした半導体発光装置に関す
るものである。The present invention relates to a semiconductor light emitting device that facilitates integration.
第５図は、例えば従来の埋込型レーザの構造を示す断面
図である。FIG. 5 is a sectional view showing the structure of a conventional embedded laser, for example.
この図において、１はn-InP基板、２はp-InPブロック
層、３はn-InP層、51はn-InPクラッド層、70,71はInGaA
sP活性層、80はp-InPクラッド層、90はp-InGaAsPコンタ
クト層、100はｐ電極、110はｎ電極である。In this figure, 1 is an n-InP substrate, 2 is a p-InP block layer, 3 is an n-InP layer, 51 is an n-InP clad layer, and 70 and 71 are InGaA.
sP active layer, 80 is p-InP clad layer, 90 is p-InGaAsP contact layer, 100 is p electrode, and 110 is n electrode.
次に動作について説明する。Next, the operation will be described.
ｐ電極100より流入した電流は、p-InPブロック層２中に
形成されたＶ溝中のみを流れ、Ｖ溝中に埋め込まれたIn
GaAsP活性層71において発光する。The current flowing from the p-electrode 100 flows only in the V-groove formed in the p-InP block layer 2 and is buried in the V-groove.
Light is emitted in the GaAsP active layer 71.
上記のように構成された従来の埋込型レーザは、Ｖ溝中
に形成されたInGaAsP活性層71の位置制御が難しく、周
囲にもpn接合があるため、寄生容量が大きく、高速応答
ができない問題点があり、また、ｐ電極100およびｎ電
極110がn-InP基板１の相対する面に形成されるため、他
の電子素子などと組み合わせて集積化する場合、その集
積化に困難が生じるなどの問題点があった。In the conventional buried type laser configured as described above, it is difficult to control the position of the InGaAsP active layer 71 formed in the V groove, and there is a pn junction in the surroundings, so that the parasitic capacitance is large and high-speed response cannot be achieved. There is a problem, and since the p-electrode 100 and the n-electrode 110 are formed on the opposite surfaces of the n-InP substrate 1, integration with other electronic elements or the like causes difficulty in integration. There were problems such as.
この発明は、上記のような問題点を解消するためになさ
れたもので、活性層の位置制御が容易で、かつ電流のリ
ークがなく、寄生容量を少なくし、高速応答が実現でき
るとともに、両電極を同一面上に形成できる半導体発光
装置を得ることを目的とする。The present invention has been made in order to solve the above problems, the position of the active layer is easy to control, there is no current leakage, parasitic capacitance is reduced, and high-speed response can be realized. An object is to obtain a semiconductor light emitting device in which electrodes can be formed on the same surface.
この発明に係る半導体発光装置は、半絶縁性または絶縁
性の基板の主面に形成された開口部と、この開口部に連
通した横穴と、開口部ならびに横穴に充填された導電性
の半導体層と、横穴の一端部に設けられ基板の表面から
半導体層に達する溝と、この溝内に形成され半導体層と
接続するとともに発光領域が埋め込まれた発光素子とを
備えたものである。A semiconductor light emitting device according to the present invention is an opening formed in a main surface of a semi-insulating or insulating substrate, a lateral hole communicating with the opening, and a conductive semiconductor layer filled in the opening and the lateral hole. And a groove which is provided at one end of the lateral hole and reaches the semiconductor layer from the surface of the substrate, and a light emitting element which is formed in the groove and which is connected to the semiconductor layer and has a light emitting region embedded therein.
この発明においては、発光領域が半絶縁性または絶縁性
の基板中に埋め込まれているため、電流狭窄が完全に行
われ、かつ周囲にｐ−ｎ接合が存在しないため、寄生容
量がなくなる。また、一方の電極が横穴に埋め込まれた
半導体層を通じて基板面上に取り出されているため、プ
レーナ構造とすることができる。In the present invention, since the light emitting region is embedded in the semi-insulating or insulating substrate, the current confinement is completely performed, and the pn junction does not exist in the periphery, so that the parasitic capacitance is eliminated. Further, since one electrode is taken out on the substrate surface through the semiconductor layer embedded in the lateral hole, a planar structure can be obtained.
以下、この発明の一実施例について説明する。 An embodiment of the present invention will be described below.
まず、第１図（ａ）〜（ｅ）によって、この発明の半導
体発光装置を得るための製造方法の一実施例を説明す
る。First, one embodiment of a manufacturing method for obtaining the semiconductor light emitting device of the present invention will be described with reference to FIGS.
第１図において、10は基板で、例えばS.I（semi insula
ting）‐InP基板、20はInGaAsP層、30はS.I-InP成長
層、40はレジスト、50はn-InP層、51はn-InPクラッド
層、60Aは前記S.I-InP基板10面に形成された開口部、60
Bはこの開口部60Aに連通して形成された横穴、60Cはこ
の横穴60Bの一端部にInGaAsP層20に達するまでエッチン
グされて形成された溝、70はInGaAsP活性層、80はp-InP
クラッド層、90はp-InGaAsPコンタクト層、100はｐ電
極、110はｎ電極である。In FIG. 1, 10 is a substrate, for example, SI (semi insula).
ing) -InP substrate, 20 is an InGaAsP layer, 30 is a SI-InP growth layer, 40 is a resist, 50 is an n-InP layer, 51 is an n-InP cladding layer, and 60A is formed on the SI-InP substrate 10 surface. Aperture, 60
B is a lateral hole formed in communication with the opening 60A, 60C is a groove formed by etching at one end of the lateral hole 60B until reaching the InGaAsP layer 20, 70 is an InGaAsP active layer, and 80 is p-InP.
A cladding layer, 90 is a p-InGaAsP contact layer, 100 is a p-electrode, and 110 is an n-electrode.
まず、第１図（ａ）に示すように、S.I-InP基板10上にI
nGaAsP層20,S.I-InP成長層30を気相成長法などによって
順次形成し、写真製版によってレジスト40をパターニン
グする。First, as shown in FIG. 1 (a), I is placed on the SI-InP substrate 10.
The nGaAsP layer 20 and the SI-InP growth layer 30 are sequentially formed by a vapor phase growth method or the like, and the resist 40 is patterned by photolithography.
次に第１図（ｂ）に示すように、S.I-InP成長層30をInG
aAsP層20に達するまでエッチングして開口部60Aを形成
した後、InGaAsP層20を硫酸：過酸化水素：水等のエッ
チング液で選択エッチングし、横穴60Bを形成する。Next, as shown in FIG. 1 (b), the SI-InP growth layer 30 is formed into InG.
After etching to reach the aAsP layer 20 to form the opening 60A, the InGaAsP layer 20 is selectively etched with an etching solution such as sulfuric acid: hydrogen peroxide: water to form a lateral hole 60B.
次に第１図（ｃ）に示すように、エッチングした開口部
60Aおよび横穴60B部分に、n-InP層50を選択的に成長さ
せる。Next, as shown in FIG. 1 (c), the etched opening
An n-InP layer 50 is selectively grown on the portions 60A and the lateral holes 60B.
次に、S.I-InP成長層30に、第１図（ｄ）に示すよう
に、エッチングによって溝60Cをn-InP層50に達するよう
に形成する。Next, in the SI-InP growth layer 30, as shown in FIG. 1D, a groove 60C is formed so as to reach the n-InP layer 50.
そして第１図（ｅ）に示すように、溝60C中に、n-InPク
ラッド層51,InGaAsP活性層70,p-InPクラッド層80,p-InG
aAsPコンタクト層90を順次成長させ、S.I-InP成長層30
中に埋込レーザを形成し、さらにｐ電極100,n電極110を
同一平面上に形成する。Then, as shown in FIG. 1 (e), in the groove 60C, the n-InP clad layer 51, the InGaAsP active layer 70, the p-InP clad layer 80, and the p-InG are formed.
SI-InP growth layer 30 is grown by sequentially growing aAsP contact layer 90.
An embedded laser is formed therein, and a p-electrode 100 and an n-electrode 110 are formed on the same plane.
次に上記のようにして形成された半導体発光装置の動作
について説明する。Next, the operation of the semiconductor light emitting device formed as described above will be described.
第１図（ｅ）において、ｐ電極100より流入した電流
は、S.I-InP成長層30中に埋め込まれたInGaAsP活性層70
で光出力に変換される。このとき、InGaAsP活性層70の
周囲は半絶縁性のS.I-InP成長層30であるため、電流は
周囲にもれ出ることはない。また、n-InPクラッド層51
は横穴60B中に埋め込まれた導電性のn-InP層50に接続さ
れているので、ｎ電極110をウエハの表面に取り出すこ
とができる。In FIG. 1 (e), the current flowing from the p-electrode 100 is caused by the InGaAsP active layer 70 embedded in the SI-InP grown layer 30.
Is converted into light output. At this time, since the periphery of the InGaAsP active layer 70 is the semi-insulating SI-InP growth layer 30, the current does not leak to the periphery. In addition, the n-InP clad layer 51
Is connected to the conductive n-InP layer 50 embedded in the lateral hole 60B, the n-electrode 110 can be taken out to the surface of the wafer.
なお、上記実施例では、n-InP層50をストライプ状に形
成したが、第２図のように、n-InP層52を一部分のみに
形成しても同様の効果が得られる。また、GaAs等の他の
材料を使用しても可能である。Although the n-InP layer 50 is formed in a stripe shape in the above embodiment, the same effect can be obtained by forming the n-InP layer 52 only in a part as shown in FIG. It is also possible to use other materials such as GaAs.
第３図（ａ）〜（ｅ）は他の製造工程を示す断面図で、
この工程は、まず、S.I-InP基板10に開口部11を形成し
た後、SiO2マスク12をスパッタおよび写真製版によって
第３図（ａ）のように形成する。3 (a) to 3 (e) are sectional views showing other manufacturing steps.
In this step, first, after forming the opening 11 in the SI-InP substrate 10, the SiO 2 mask 12 is formed by sputtering and photolithography as shown in FIG. 3 (a).
次に第３図（ｂ）に示すように、開口部11を下方にさら
にエッチングした後、開口部11の底部に蒸着によってSi
O2マスク13を形成し、さらにエッチングすることによっ
て、第３図（ｃ）に示すように横穴14を形成する。Next, as shown in FIG. 3B, after the opening 11 is further etched downward, Si is deposited on the bottom of the opening 11 by vapor deposition.
An O 2 mask 13 is formed and further etched to form a lateral hole 14 as shown in FIG. 3 (c).
次に第３図（ｄ）に示すように、開口部11と横穴14部分
にn-InP層50を成長させた後、第１図の工程と同様に第
３図（ｅ）に示すように、埋込レーザを形成する。この
方法によると結晶成長回数が２回になる利点がある。Next, as shown in FIG. 3 (d), after growing the n-InP layer 50 in the opening 11 and the lateral hole 14, as shown in FIG. 3 (e), as in the step of FIG. Forming an embedded laser. This method has the advantage that the number of crystal growths is twice.
第４図（ａ）〜（ｃ）はさらに他の製造工程を示す断面
図である。FIGS. 4A to 4C are cross-sectional views showing still another manufacturing process.
まず、S.I-InP基板10にn-InP層50を所要深さに埋め込
み、さらにn-InP層50中に、このn-InP層50より浅く、S.
I-InP成長層30を埋め込むことによって開口部および横
穴にn-InP層50が成長された状態となる。さらに、S.I-I
nP成長層30の端部に埋込レーザを形成することによって
も、結果的に第１図，第３図の実施例と同様に開口部，
横穴，溝が形成され、この発明の半導体発光装置を構成
することができる。First, the n-InP layer 50 is embedded in the SI-InP substrate 10 to a required depth, and further, in the n-InP layer 50, shallower than the n-InP layer 50, S.
By embedding the I-InP growth layer 30, the n-InP layer 50 is grown in the openings and the lateral holes. Furthermore, SI-I
By forming an embedded laser at the end of the nP growth layer 30, as a result, similar to the embodiment of FIG. 1 and FIG.
Lateral holes and grooves are formed, and the semiconductor light emitting device of the present invention can be constructed.
以上説明したように、この発明は、半絶縁性または絶縁
性の基板の主面に形成された開口部と、この開口部に連
通した横穴と、開口部ならびに横穴に充填された導電性
の半導体層と、横穴の一端部に設けられ基板の表面から
半導体層に達する溝と、この溝内に形成され半導体層と
接続するとともに発光領域が埋め込まれた発光素子とを
備えたので、発光領域が半絶縁性または絶縁性の基板中
に埋め込まれた状態となり、したがって、周囲にpn接合
が存在しないことから、電流リークがなくなり、寄生容
量の少ない半導体発光装置が歩留り良く構成できる。ま
た、p,n両電極は基板主面上に設けることができるの
で、プレーナ型の構造とすることができ、集積化が容易
となる等の効果が得られる。As described above, the present invention is directed to the opening formed in the main surface of the semi-insulating or insulating substrate, the lateral hole communicating with the opening, and the conductive semiconductor filled in the opening and the lateral hole. Since the light emitting region is provided with a layer, a groove which is provided at one end of the lateral hole and reaches the semiconductor layer from the surface of the substrate, and a light emitting element which is formed in the groove and is connected to the semiconductor layer and in which the light emitting region is embedded, Since the semiconductor light emitting device is embedded in a semi-insulating or insulating substrate, and therefore there is no pn junction in the periphery, current leakage is eliminated, and a semiconductor light emitting device with a small parasitic capacitance can be configured with high yield. Further, since both the p and n electrodes can be provided on the main surface of the substrate, a planar structure can be obtained, and the effects such as easy integration can be obtained.
第１図（ａ）〜（ｅ）はこの発明の一実施例の半導体発
光装置の製造工程を示す断面図、第２図はこの発明の他
の実施例を示す半導体発光装置の斜視図、第３図（ａ）
〜（ｅ）はこの発明の半導体発光装置の他の製造工程を
示す断面図、第４図（ａ）〜（ｃ）はこの発明の半導体
発光装置のさらに他の製造工程を示す断面図、第５図は
従来の半導体発光装置の断面図である。 図において、10はS.I-InP基板、20はInGaAsP層、30はS.
I-InP成長層、40はレジスト、50はn-InP層、51はn-InP
クラッド層、60Aは開口部、60Bは横穴、60Cは溝、70,71
はInGaAsP活性層、80はp-InPクラッド層、90はp-InGaAs
Pコンタクト層、100はｐ電極、110はｎ電極である。 なお、各図中の同一符号は同一または相当部分を示す。1 (a) to 1 (e) are sectional views showing manufacturing steps of a semiconductor light emitting device according to an embodiment of the present invention, and FIG. 2 is a perspective view of a semiconductor light emitting device showing another embodiment of the present invention. Figure 3 (a)
~ (E) is a cross-sectional view showing another manufacturing process of the semiconductor light-emitting device of the present invention, Fig. 4 (a) ~ (c) is a cross-sectional view showing yet another manufacturing process of the semiconductor light-emitting device of the present invention, FIG. 5 is a sectional view of a conventional semiconductor light emitting device. In the figure, 10 is an SI-InP substrate, 20 is an InGaAsP layer, and 30 is an S.InP substrate.
I-InP growth layer, 40 is resist, 50 is n-InP layer, 51 is n-InP
Cladding layer, 60A opening, 60B side hole, 60C groove, 70,71
Is an InGaAsP active layer, 80 is a p-InP clad layer, 90 is p-InGaAs
A P contact layer, 100 is a p electrode, and 110 is an n electrode. The same reference numerals in each drawing indicate the same or corresponding parts.
Claims (1)
された開口部と、この開口部に連通した横穴と、前記開
口部ならびに横穴に充填された導電性の半導体層と、前
記横穴の一端部に設けられ前記基板の表面から前記半導
体層に達する溝と、この溝内に形成され前記半導体層と
接続するとともに発光領域が埋め込まれた発光素子とを
備えたことを特徴とする半導体発光装置。1. An opening formed in a main surface of a semi-insulating or insulating substrate, a lateral hole communicating with the opening, a conductive semiconductor layer filled in the opening and the lateral hole, and A groove which is provided at one end of the lateral hole and reaches the semiconductor layer from the surface of the substrate; and a light emitting element which is formed in the groove and which is connected to the semiconductor layer and has a light emitting region embedded therein. Semiconductor light emitting device.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19682187A JPH0716081B2 (en) | 1987-08-05 | 1987-08-05 | Semiconductor light emitting device |
| US07/227,124 US5003358A (en) | 1987-08-05 | 1988-08-02 | Semiconductor light emitting device disposed in an insulating substrate |
| US07/607,044 US5100833A (en) | 1987-08-05 | 1990-10-31 | Method of producing a semiconductor light emitting device disposed in an insulating substrate |
| US07/767,685 US5194399A (en) | 1987-08-05 | 1991-09-30 | Method of producing a semiconductor light emitting device disposed in an insulating substrate |
| US07/983,308 US5275968A (en) | 1987-08-05 | 1992-11-30 | Method of producing a semiconductor light emitting device disposed in an insulating substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19682187A JPH0716081B2 (en) | 1987-08-05 | 1987-08-05 | Semiconductor light emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6439792A JPS6439792A (en) | 1989-02-10 |
| JPH0716081B2 true JPH0716081B2 (en) | 1995-02-22 |
Family
ID=16364222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19682187A Expired - Lifetime JPH0716081B2 (en) | 1987-08-05 | 1987-08-05 | Semiconductor light emitting device |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US5003358A (en) |
| JP (1) | JPH0716081B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5179040A (en) * | 1990-07-16 | 1993-01-12 | Mitsubishi Denki Kabushiki Kaisha | Method of making a semiconductor laser device |
| US5789772A (en) * | 1994-07-15 | 1998-08-04 | The Whitaker Corporation | Semi-insulating surface light emitting devices |
| US5608234A (en) * | 1994-11-14 | 1997-03-04 | The Whitaker Corporation | Semi-insulating edge emitting light emitting diode |
| US5629232A (en) * | 1994-11-14 | 1997-05-13 | The Whitaker Corporation | Method of fabricating semiconductor light emitting devices |
| EP0712169A1 (en) | 1994-11-14 | 1996-05-15 | The Whitaker Corporation | Semi-insulating edge emitting light emitting diode |
| JP5343272B2 (en) | 2005-09-30 | 2013-11-13 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Single crystal semiconductor manufacturing apparatus and manufacturing method |
Family Cites Families (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5630775A (en) * | 1979-08-21 | 1981-03-27 | Oki Electric Ind Co Ltd | Light emitting diode |
| JPS5671987A (en) * | 1979-11-15 | 1981-06-15 | Mitsubishi Electric Corp | Semiconductor laser |
| JPS56135994A (en) * | 1980-03-28 | 1981-10-23 | Fujitsu Ltd | Semiconductor light emitting device |
| JPS5730385A (en) * | 1980-07-29 | 1982-02-18 | Fujitsu Ltd | Semiconductor light emitting element |
| JPS57162483A (en) * | 1981-03-31 | 1982-10-06 | Fujitsu Ltd | Semiconductor luminous device |
| JPS57162484A (en) * | 1981-03-31 | 1982-10-06 | Fujitsu Ltd | Semiconductor luminous device |
| JPS5812389A (en) * | 1981-07-16 | 1983-01-24 | Nec Corp | Semiconductor laser |
| JPS58204587A (en) * | 1982-05-24 | 1983-11-29 | Omron Tateisi Electronics Co | Semiconductor laser device |
| JPS58213491A (en) * | 1982-06-07 | 1983-12-12 | Omron Tateisi Electronics Co | Semiconductor laser |
| JPS5961982A (en) * | 1982-09-30 | 1984-04-09 | Sony Corp | Semiconductor laser |
| JPS59108382A (en) * | 1982-12-14 | 1984-06-22 | Fujitsu Ltd | Semiconductor device |
| GB2139422B (en) * | 1983-03-24 | 1987-06-03 | Hitachi Ltd | Semiconductor laser and method of fabricating the same |
| JPS59202676A (en) * | 1983-04-30 | 1984-11-16 | Sumitomo Electric Ind Ltd | Planar type light-emitting element |
| JPS59215785A (en) * | 1983-05-24 | 1984-12-05 | Matsushita Electric Ind Co Ltd | Semiconductor laser |
| JPS60154689A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Light emitting element and lighr communication equipment using the same |
| US4766093A (en) * | 1984-07-30 | 1988-08-23 | International Business Machines Corp. | Chemically formed self-aligned structure and wave guide |
| JPS6149484A (en) * | 1984-08-18 | 1986-03-11 | Matsushita Electric Ind Co Ltd | Compound semiconductor element and manufacture thereof |
| JPS61102086A (en) * | 1984-10-24 | 1986-05-20 | Mitsubishi Electric Corp | Semiconductor laser |
| JPH0766994B2 (en) * | 1985-02-19 | 1995-07-19 | シャープ株式会社 | Semiconductor laser device |
| JPS61242091A (en) * | 1985-04-19 | 1986-10-28 | Matsushita Electric Ind Co Ltd | Semiconductor light-emitting element |
| JPS61244082A (en) * | 1985-04-22 | 1986-10-30 | Hitachi Ltd | Semiconductor laser device |
| DE3689809D1 (en) * | 1985-06-27 | 1994-06-01 | Nec Corp | Embedded heterostructure semiconductor laser. |
| US4764246A (en) * | 1985-08-06 | 1988-08-16 | American Telephone And Telegraph Company, At&T Bell Laboratories | Buried undercut mesa-like waveguide and method of making same |
| US4725112A (en) * | 1985-08-06 | 1988-02-16 | American Telephone And Telegraph Company, At&T Bell Laboratories | Buried undercut mesa-like waveguide |
| JPS6252985A (en) * | 1985-09-02 | 1987-03-07 | Toshiba Corp | Semiconductor light emitting element |
| JPS6272185A (en) * | 1985-09-26 | 1987-04-02 | Agency Of Ind Science & Technol | Negative resistance optical device |
| US4663831A (en) * | 1985-10-08 | 1987-05-12 | Motorola, Inc. | Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers |
| FR2593966B1 (en) * | 1986-02-04 | 1988-09-09 | Ankri David | MONOLITHIC SEMICONDUCTOR STRUCTURE OF A HETEROJUNCTION BIPOLAR TRANSISTOR AND A LASER |
| US4788159A (en) * | 1986-09-18 | 1988-11-29 | Eastman Kodak Company | Process for forming a positive index waveguide |
| US4849371A (en) * | 1986-12-22 | 1989-07-18 | Motorola Inc. | Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices |
| JPS63166266A (en) * | 1986-12-27 | 1988-07-09 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS63211788A (en) * | 1987-02-27 | 1988-09-02 | Mitsubishi Electric Corp | Semiconductor laser and manufacture thereof |
| JPH0231488A (en) * | 1988-07-20 | 1990-02-01 | Mitsubishi Electric Corp | Semiconductor laser device and its manufacture |
-
1987
- 1987-08-05 JP JP19682187A patent/JPH0716081B2/en not_active Expired - Lifetime
-
1988
- 1988-08-02 US US07/227,124 patent/US5003358A/en not_active Expired - Fee Related
-
1990
- 1990-10-31 US US07/607,044 patent/US5100833A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US5100833A (en) | 1992-03-31 |
| US5003358A (en) | 1991-03-26 |
| JPS6439792A (en) | 1989-02-10 |
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