JPS63166266A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the high-frequency characteristics by forming single crystal base extraction electrodes on a silicon oxide film using a solid-phase epitaxial method, and simultaneously using the selective oxidation of a solid-phase epitaxial silicon film and the side walls of polycrystalline silicon. CONSTITUTION:A film 12 is formed on the surface of a substrate 11, and a window 13 reaching the substrate 11 is opened. Then, after depositing silicon 14 in the window section 13, a polycrystalline silicon film is deposited on the whole surface and changed to an amorphous silicon film by Si implantation. Subsequently it is changed to a film 14' to increase the film thickness of the film 14'. And the film 14' is removed till the film 12. Then, after forming a film 15 on the surface of the film 14' by thermal oxidation, a film 18 and a resist 19 are formed on the whole surface. Next, leaving the film 18 only on the window region 13, boron is introduced to form a base extraction region 17. And the thickness of the film 15 is increased except for the window region 13, and simultaneously boron is diffused to form a region 16, removing the film 18. Further, a polycrystalline film is deposited to form a side wall region 110. Then, removing only the film 15, a layer 111 is formed, and a region 112 is formed. Moreover, electrodes 113, 114 are formed on a film 15'. With this, the parasitic capacitance and parasitic resistance of a transistor can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention] (Industrial Field of Application) This invention relates to two half-width body parts constituting a Takumei bipolar bond cycle and how to make and use them.

(Prior Art) Conventional nopibora transistors are, for example, NPNI
If shown in Figure 2, the structure is as shown in Figure 2.

In Figure 8, 21 is the collector term, a certain N-type silicon, spring plate, and 22 is the P-type base T formed on the first eroded surface.
IJi area, 23 is an emitter area formed within the base area 22, and 24 is an 8i0. Call, Sin from 25i4 base 1 or 22
, a polycrystalline silicon field 26 including a polycrystalline silicon field 26 extending over the base 24 is provided so as to cover the polycrystalline silicon 25, the entire surface 3 of the emitter 1 base 23, and the exposed portion 4 of the base 22. sio, @, 27 is the polycrystalline silicon layer 25
outside @ part of Eko8i0. [Base electrode provided through the window in 26, 28TI's, S on emitter 4 region 23
iQ, 26i is open and the window is set at + electrode L/4 emitters, and 29 is 4 collectors.

(Problems to be Solved by the Invention) Figure 2 (Cross-sectional view of the bipolar transistor shown in this figure) The diagonal portion is an unnecessary portion for the essence of device operation. The essence of the operation is that the four regions are injected into the base region ζ, passed through these four regions in an enlarged manner, and are delivered to the collector region, so it is sufficient if the necessary region exists for this purpose. The other parts (diagonal and lined parts) are not only unnecessary but also degrade the performance of the device. The purpose of the present invention is to provide a semiconductor package consisting of only essential parts and a method for manufacturing the same.

[Structure of the invention]

(Means for solving the constant point between) The @! of the bipolar transistor shown in Figure 2. ] The reason why it was not possible to manufacture an element in which only the essential part for the production was made using the conventional technology was that one base drawer could not be taken out from the X side of the base. Therefore, in our invention, we used solid-phase epitaxial technology to create a Rin crystal base on a silicon oxide model. - I refuse to create one.

In addition, as a means to reduce the emitter degradation range, a technique is proposed in which a selective aperture shield of the solid-phase epitaxial silicon type is used in combination with a polycrystalline silicon sidewall.

(For 1) The bipolar transistor fabricated by the above method has a low single-temperature resistance of the base drawer and a narrow emitter width, so it has the power to improve the high frequency FF of the transistor. It will be demonstrated.

(IA example) The details of the present invention will be explained based on the Yi Kai series.

The manufacturing process of an NPN transistor based on the unexploded D-implementation row is shown in Figure 1 (a1 to (h)).

First, as shown in FIG. 1(a), N-type silicon Reisaka 11
A layer 12 consisting of Sin is formed on one surface of the substrate by a tetraoxidation method, CVD removal, or the like. The thickness of the diagonal 12 at this time is 1.0 μm. This is etched using a plasma etching process to open up a predetermined pattern that reaches silicon 1*1. This Noloe pattern is the 6th pattern that determines the 8th order of the transistor.・After cleaning the N-type silicone at the bottom of the window, remove the seedlings with H6-containing air in a vacuum chamber.

As shown in Section 1 J(b), He and S are separated in a vacuum chamber.
t, H, or HHe and SiH, or He and SiH, (1
Single-crystal silicon 14 is formed in the window 13 by selective epitaxial growth using a mixed gas of 20°C or a mixed gas thereof as a raw material. A polycrystalline silicon film is deposited on the entire surface of the specimen. Then, the polycrystalline silicon pattern 14 is transformed into an amorphous silicon film by Si ion implantation. Then, the amorphous silicon film is transformed into a substantially crystalline silicon layer 14' by adding heat in a vacuum waste chamber. Subsequently, the film thickness of the single crystal silicon layer 14' is increased by the low pressure selective epitaxial growth method.

As shown in Figure A1 (C), the single crystal silicon film 14
'Then, the oxide film 1 is etched using plasma etching, etc.
Place the thought 13 until you reach 2. J'7) Remove it leaving only the su area.

After thermal standardization, 1000 yen was applied to the face of the silicone crystal 14'.
Form A's SiO, olfactory 15. - Next, a silicon value film 18 and then a resist 19 are formed on the entire surface.

Next, as shown in 1a(d), the chisel silicon nitride film 18 is left on the window region 13 by removing the resist etch pack using plasma. Subsequently, poron ions are implanted to form a base value range 16P+extraction Ltffl region 17.

Then, as shown in FIG. 1(e), thermal oxidation is performed to increase the thickness of the 8i0.degree. film 15 except for the window region 13. Koto &
Poron is simultaneously diffused to form the base region 16. Subsequently, the silicon nitride film 16 is removed by chemical dry etching.

Furthermore, as shown in FIG. 2g1(f) tζ, sidewall regions 110 of polycrystalline silicon are formed using plasma anisotropic etching after depositing polycrystalline silicon.

Next, wash as shown in Figure 1 (g) #.
Single-crystal silicon film 14' in the part where the emitter hole is formed
Only the oxide film 15 on the surface is removed. Next, arsenic-doped polycrystalline silicon 1ill19 is formed to a thickness of about 0.5 μm and heat treated to form an emitter region 112.

Furthermore, as shown in Figure 1 (h), P drawer 1f
A contact window for the base Km is opened in a predetermined portion of the silicon oxide film 15 on the fl region 17, and a contact window for the base Km is formed here.
, the emitter on the multi-connected 91 silicon lii 111
A pot 114 is formed.

〔Effect of the invention〕

According to the present invention, since the base drawer lLm=tributary region 17 is made of single crystal, the base drawer resistance is reduced. Furthermore, since the base lead-out electrode is structured to extend from the side surface of the base region, the parasitic capacity and parasitic resistance of the transistor can be significantly reduced.

Furthermore, with the introduction of self-alignment techniques, it has become possible to form narrow emitter widths. From the above points, the present invention exhibits tremendous power in improving the high-III gain of transistors.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing an example of the manufacturing method according to the invention, and FIG. 2 is a four-sided view showing a conventional bipolar transistor D structure. 11.21...N silicon substrate, 12,15°24
．． 26...Silicon oxide film, 13...Window, 14...
・Silicon scent deposited by vacuum @ deposition, 16.22・
... Base tilting castle, 17 ... Base drawer area, 18
...Silicon nitride film, 19...Resist, 11o.
...Multi, bond crystal silicon model, 111.28...N ten crystal silicon fa% 112t 23 =--emitter region, 23.24, 25°27...Fri, 1A sound. 1 patent attorney Nori Chika Kikuo Takehana, f? , f5 Fig. 1 Fig. 1 Fig. 1

Claims (5)

[Claims] (1) A first insulating film having an opening is formed on a first conductivity type single crystal silicon substrate, and then a first conductivity type single crystal silicon film is formed, and the opening and the opening are formed from the main surface side. A second conductivity type region is formed around the opening, and a second insulating film is formed on the second conductivity type region, on the outer edge of the opening, and on the outer edge of the second conductivity type region. , a first conductivity type region is formed within the second conductivity type region and above the opening from the main surface side, and the substrate, the second conductivity type region, and the first conductivity type region are respectively connected to collector regions. , a bipolar transistor having a base region and an emitter region is formed, a polycrystalline silicon layer including a first conductivity type impurity extending from above the emitter region is formed, and an emitter electrode is formed on the polycrystalline silicon layer,
A semiconductor device characterized in that a base electrode is formed on a second conductivity type region and in a region not covered by the second insulating film and the polycrystalline silicon layer. (2) forming a first silicon dioxide film on the main surface of the first conductivity type silicon substrate, and forming an opening in the first conductivity type silicon substrate in a predetermined shape reaching the surface of the first conductivity type silicon substrate; a step of providing a first hole in the opening;
A step of cleaning the surface of the conductive type silicon substrate, a step of forming a silicon film containing a first conductive type impurity on the main surface side of the silicon substrate with a recess above the opening, and then a step of simply cleaning the silicon film. A step of crystallizing it to transform it into a single-crystal silicon film, a step of forming a second silicon dioxide film on the single-crystal silicon film, and a step of forming a silicon nitride film and then etching the silicon nitride film with the recesses left behind using an etch pack. removing the film until it reaches the second silicon dioxide, and then implanting ions from the main surface side of the substrate to remove the single crystal silicon film on the first silicon dioxide film and the silicon dioxide film on the opening. A step of implanting a second conductivity type impurity into a portion near the surface of a single crystal silicon film to form a base region, and then forming a second silicon dioxide film on the single crystal silicon film from which the recessed region is removed by thermal oxidation. a step of increasing the thickness of the silicon nitride film, a step of removing the silicon nitride film, and a step of removing the silicon nitride film, and then changing the second silicon dioxide film until it reaches the single crystal silicon film located in the recess, leaving the part excluding the recess. removing the polycrystalline silicon by directional etching to form a second opening, forming polycrystalline silicon containing a first conductivity type impurity to cover the second opening, and then performing heat treatment to form a second opening in the base region. forming an emitter region;
manufacturing a semiconductor device, comprising: providing an opening in the silicon dioxide film leading to the base region; forming a base electrode through the opening; and forming an emitter electrode on the polycrystalline silicon layer. Method. (3) The method for manufacturing a semiconductor device according to claim 2, characterized in that the step of cleaning the surface of the first conductivity type silicon substrate within the opening uses a heat treatment method in a vacuum apparatus. A method for manufacturing a semiconductor device. (4) In the method for manufacturing a semiconductor device according to claim 2, the amorphous silicon film containing the first conductivity type impurity is formed using a vapor deposition method using an ultra-high vacuum apparatus. A method for manufacturing a semiconductor device. (5) The method for manufacturing a semiconductor device according to claim 4, characterized in that a solid phase epitaxial growth method in an ultra-high vacuum apparatus is used for single crystallization of the amorphous silicon film. Production method.