JPS6149484A - Compound semiconductor element and manufacture thereof - Google Patents
Compound semiconductor element and manufacture thereofInfo
- Publication number
- JPS6149484A JPS6149484A JP59171938A JP17193884A JPS6149484A JP S6149484 A JPS6149484 A JP S6149484A JP 59171938 A JP59171938 A JP 59171938A JP 17193884 A JP17193884 A JP 17193884A JP S6149484 A JPS6149484 A JP S6149484A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductivity type
- recess
- type
- inp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 150000001875 compounds Chemical class 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 description 46
- 230000001681 protective effect Effects 0.000 description 10
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 240000002329 Inga feuillei Species 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000013307 optical fiber Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910015363 Au—Sn Inorganic materials 0.000 description 2
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000010581 sealed tube method Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体へテロ接合を有するフォトダイ ・
オードなどの化合物半導体素子及びその製造方法に関す
る。[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a photo die having a semiconductor heterojunction.
The present invention relates to compound semiconductor devices such as odes and methods for manufacturing the same.
従来例の構成とその問題点
１．０〜１．７μｍ帯（長波長帯）の光フアイバ通信は
、高純度光ファイバがこの波長帯域で低分散。Conventional configuration and its problems In optical fiber communication in the 1.0 to 1.7 μm band (long wavelength band), high-purity optical fiber has low dispersion in this wavelength band.
低損失の特性を示すため、長距離伝送の手段として注目
されている。この長波長帯域における受光素子として現
在Ｇｅ−ＰＩＮフォトダイオード、Ｇｅ −アバランシ
ェフォトダイオード（Ｇ６−ＡＰＤ）などが用いられて
いるが、０．８μｍ帯の光フアイバ通信で用いられてい
る５ｉ−ＰＩＮフォトダイオードや５ｉ−ＡＰＤに比べ
、暗電流が大きい、温度特性が悪いなどの欠点があり、
長波長帯域でＳｉに匹敵する特性を有する受光素子の開
発が望まれており、Ｇｏにかわる材料として化合物半導
体を用いた”０．５３Ｇａ［１，４７Ａｓ（以後ＩｎＧ
ａＡｓ と記す）或は：［ｎｘＧ２Ｌ１ 、、Ａｓ１
−ｙＰｙ （以後ＩｎＧａＡｓＰと記す）のＰＩＮフォ
トダイオード或はＡＰＤの開発が行われている。Because it exhibits low loss characteristics, it is attracting attention as a means of long-distance transmission. Ge-PIN photodiodes, Ge-avalanche photodiodes (G6-APD), etc. are currently used as photodetectors in this long wavelength band, but 5i-PIN photodiodes, which are used in optical fiber communications in the 0.8 μm band, are currently used. Compared to diodes and 5i-APDs, they have drawbacks such as large dark current and poor temperature characteristics.
There is a desire to develop a photodetector with characteristics comparable to Si in the long wavelength band, and the use of compound semiconductors such as ``0.53Ga[1,47As'' (hereinafter referred to as InG
aAs ) or: [nxG2L1 , , As1
-yPy (hereinafter referred to as InGaAsP) PIN photodiodes or APDs are being developed.
第１図に従来のＩｎＧａＡｓ ／ Ｉ ｎ Ｐ拡散型プ
レナーＰＩＮフォトダイオードの断面構造を示す。第１
図において、１は高濃度ｎ型ＩｎＰ基板、２は低、
濃度”−型”３°′キパル層”ｔ’？＋Ｉ
Ｊア密度は５Ｘ１０１５（７＋１ ’ 、３は低濃度
ｎ−型ＩｎＧａＡｓ ｘビタキシャル層でキャリア密
度は５Ｘ１０ ｃｍ。FIG. 1 shows a cross-sectional structure of a conventional InGaAs/InP diffused planar PIN photodiode. 1st
In the figure, 1 is a high concentration n-type InP substrate, 2 is a low concentration,
Concentration "-type"3°' Kipal layer "t'?+I
JA density is 5X1015 (7+1', 3 is a low concentration n-type InGaAs x bitaxial layer and carrier density is 5X10 cm.
４はＺｎ を拡散した高濃度、Ｐ＋型ＩｎＧａＡｓ層で
ある。５はＰ＋型工ｎｔ；ａＡｓ層４にオーミック接触
する電極でＡｕ −Ｚｎの蒸着膜、６は計則ＩｎＰ基板
１にオーミック接触する電極でＡｕ −Ｓｎの蒸着膜、
７はＩｎＧａＡｓ のｐ−ｎ−接合の保護膜を兼ねた無
反射コーテイング膜でプラズマＣｖＤ法により堆積した
Ｓｉ３Ｎ４膜である。人は受光部である。この構造にお
いてｎ−型ＩｎＧａＡｓ層３とＰ＋型ＩｎＧａＡｓ層４
との接合の表面即ちＳｉ３Ｎ４膜７との界面でリーク電
流が発生し、暗電流が大きくなってしまう。4 is a high concentration, P+ type InGaAs layer in which Zn is diffused. 5 is a P+ type electrode; 6 is an electrode that is in ohmic contact with the aAs layer 4 and is a deposited film of Au-Zn; 6 is an electrode that is in ohmic contact with the InP substrate 1 and is a deposited film of Au-Sn;
7 is a non-reflection coating film which also serves as a protective film for the InGaAs p-n junction, and is a Si3N4 film deposited by the plasma CVD method. A person is a light receiver. In this structure, an n-type InGaAs layer 3 and a p+-type InGaAs layer 4
A leakage current occurs at the surface of the junction with the Si3N4 film 7, that is, at the interface with the Si3N4 film 7, resulting in an increase in dark current.
第１図の構造で、直径３００μｍのＰＩＮフォトダイオ
ードの場合、暗電流は逆バイアスが５ｖのとき数１０μ
人と大きい。一方Ｓｉ３Ｎ４膜７を除去すると、暗電流
は逆バイアス６ｖのとき、１００ｎＡ程度と小さくなる
が表面に保護膜が無い状態であるので素子の信頼性が問
題となる。In the case of a PIN photodiode with a diameter of 300 μm in the structure shown in Figure 1, the dark current is several tens of μm when the reverse bias is 5 V.
big with people On the other hand, if the Si3N4 film 7 is removed, the dark current is reduced to about 100 nA at a reverse bias of 6 V, but since there is no protective film on the surface, the reliability of the device becomes a problem.
一方メサ型ｔＴ） ＩｎＧａＡｓ ／ Ｉ ｎＰ 、或
はＩｎＧａＡｓＰ ／ＩｎＰＰＩＮフォトダイオードに
してｐ−ｎ接合部がＩｎＧａＡｓ 層、或はＩｎＧａＡ
ｓＰ層の表面に形成されない構造にする事により、暗電
流を低下させる方式は発明されているが、ＦＥＴ等他の
素子との集積化を考えると、メサ構造では、集積密度や
配線等に問題があシ、プレナー構造の低暗電流の受光素
子の開発が要請されている。On the other hand, in a mesa type (tT) InGaAs/InP or InGaAsP/InPPIN photodiode, the p-n junction is an InGaAs layer or an InGaA photodiode.
A method has been invented to reduce dark current by creating a structure that is not formed on the surface of the sP layer, but when considering integration with other elements such as FETs, the mesa structure has problems with integration density, wiring, etc. There is a need for the development of light-receiving elements with a planar structure and low dark current.
発明の目的
本発明はこの様な従来のＩｎＧａＡｓ ／ ＩｎＰ 、
或はＩｎＧａＡｓＰ ／ Ｉ ｎ Ｐ−Ｐ Ｉ Ｎ ７
オトダイオードにおける問題点を解決するためになされ
たものであり、表面保護膜が形成された状態でもなおか
つ、低暗電流の化合物半導体素子の製造方法を提供する
事を目的としている。OBJECTS OF THE INVENTION The present invention is directed to such conventional InGaAs/InP,
Or InGaAsP/I n P-P I N 7
This was developed in order to solve the problems with photodiodes, and the purpose is to provide a method for manufacturing a compound semiconductor element that has a low dark current even when a surface protective film is formed.
発明の構成
本発明はＩｎＰ基板表面に第１の凹部を形成しこの凹部
内に第１導電形のＩｎＰ層、或はＩｎｘＧａ、−ｘＡｓ
１ 、Ｐｙ層が形成され、更にそのＩｎＰ或はＩｎＧａ
ＡｓＰ層に第２の凹部が形成され、その中に第１導電形
ノＩｎＧａＡｓ 或は工ｎｘＩＧａ１−ｘｌＡｓ、−ｙ
ｌＰｙｌ（ｙ’＜ ｙ ）層を有し、上記第２の凹部を
含む領域の表面に第２導電形の拡散層或はイオン注入層
を形成し、表面でのリーク電流を低減し、暗電流を飛躍
的に低くするものである。Structure of the Invention The present invention forms a first recess on the surface of an InP substrate, and an InP layer of a first conductivity type, InxGa, -xAs, etc. is formed in the recess.
1. A Py layer is formed, and the InP or InGa layer is formed.
A second recess is formed in the AsP layer, and a first conductivity type of InGaAs or InGaAs, -y is formed in the AsP layer.
It has an lPyl (y'< y) layer, and a second conductivity type diffusion layer or ion implantation layer is formed on the surface of the region including the second recess to reduce leakage current at the surface and reduce dark current. This dramatically lowers the
実施例の説明
以下本発明の一実施例について説明する。第２図にその
構造を示す。同図において、１ｏは半絶縁性ＩｎＰ 基
板、１２は基板表面に形成された深さ４１１２ｎの第１
の凹部１１内に形成されたｎ−型エピタキシャル層でキ
ャリア密度及び膜厚は例えば５ Ｘ １０１５ｃｎＶ’
、及び２ ｐ ７７２である。１３は更にこのｎ一層１
２に形成場れた第２凹部内に形成されたｎ１型ＩｎＧａ
Ａｓ工ピタキシヤル層で、キャリア密度及び膜厚は、５
Ｘ１０ ｃｍ ％及び２μｍである。１４．１５は
、ｎ ＩｎＧａ蔀の表面全体をおおう様に例えばＺｎ
を拡散したｐ＋型ＩｎＧａＡｓ及ＩｎＰ層で、拡散深さ
は約１μｍである。１６及び１７はそれぞれｐ＋型Ｉｎ
ＧａＡｓ層１５及びｎｕＩｎＰ 層１２表面にオーミ
ック接触をとるだめの金属で例えばそれぞれＡｕ −Ｚ
ｎ及びＡｕ −Ｓｎの蒸着膜である。ＰＩＮフォトダイ
オードの受光部はＢであり、入射した光はｎ−及びｐ型
ＩｎＧａＡｓ層１３．１４で吸収される。１８は受光部
Ｂでは無反射コーティング層となり、ｎ−型ｒｎｐ層１
２とｐ＋型ＩｎＰ層１５との接合表面では表面保護膜と
なる様な膜例えばＳｉ、Ｎ４膜である。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below. Figure 2 shows its structure. In the figure, 1o is a semi-insulating InP substrate, and 12 is a first layer with a depth of 4112n formed on the substrate surface.
The n-type epitaxial layer formed in the recess 11 has a carrier density and film thickness of, for example, 5 x 1015cnV'.
, and 2 p 772. 13 is further this n layer 1
n1 type InGa formed in the second recess formed in 2.
The As pitaxial layer has a carrier density and film thickness of 5.
X10 cm % and 2 μm. In 14.15, for example, Zn is applied so as to cover the entire surface of n InGa.
The p+ type InGaAs and InP layer is diffused with a diffusion depth of approximately 1 μm. 16 and 17 are p+ type In
A metal for making ohmic contact with the surfaces of the GaAs layer 15 and the nuInP layer 12, for example, Au-Z.
This is a vapor deposited film of n and Au-Sn. The light receiving part of the PIN photodiode is B, and the incident light is absorbed by the n- and p-type InGaAs layers 13 and 14. 18 is a non-reflective coating layer in the light receiving part B, and is an n-type RNP layer 1.
On the bonding surface between 2 and the p+ type InP layer 15, a film such as a Si or N4 film is used as a surface protective film.
本発明の一実施例の特徴とするところは次の通りである
。The features of one embodiment of the present invention are as follows.
ｎ−型ＩｎＧａＡｓ層１３とｐ＋型ＩｎＧａＡｓ層１４
との接合が表面に露出しない構造をとっているだめ表面
リーク電流が少ない。本発明者の実験によると、従来例
に示した構造のプレナー型フォトダイオードの暗電流は
ｐ−ｎ接合の周辺長に比例する結果が得られており、従
ってＩｎＧａＡｓ でのｐ−ｎ接合表面でのリークが
生じているといえる。一方ＩｎＰのｐ−ｎ接合ダイオー
ドの試作を行うと、リーク電流は同じ条件下で、２桁以
上も小さく、ＩｎＰ接合表面のリーク電流は、ＩｎＣｒ
ａＡｓ接合表面のリーク電流に比べてはるかに小さい事
が判明した。n-type InGaAs layer 13 and p+-type InGaAs layer 14
Since the structure does not expose the junction with the surface, surface leakage current is small. According to experiments conducted by the present inventors, it has been found that the dark current of a planar photodiode having the structure shown in the conventional example is proportional to the peripheral length of the p-n junction. It can be said that a leak has occurred. On the other hand, when we prototyped an InP p-n junction diode, the leakage current was more than two orders of magnitude smaller under the same conditions, and the leakage current at the InP junction surface was lower than that of the InCr.
It was found that the leakage current was much smaller than the leakage current at the aAs junction surface.
更に本発明では表面保護膜が形成されている。Furthermore, in the present invention, a surface protective film is formed.
従来例の説明でも述べた様に、工ｎＧ１ＬＡｓ のｐ−
ｎ接合表面に表面保護膜を形成するとリーク電流が増加
するが、本発明ではｘｎｐの表面に接合が形成される事
になるので表面保護膜を形成した場合でも従来例よりも
小さく、しかも高い信頼性が得られる。As mentioned in the explanation of the conventional example, the p-
When a surface protective film is formed on the n-junction surface, leakage current increases, but in the present invention, the junction is formed on the xnp surface, so even if a surface protective film is formed, the leakage current is smaller than that of the conventional example, and is highly reliable. You can get sex.
次に本発明の一実施例のＰＩＮフォトダイオードの製造
方法について説明する。工程の概略を第３図（２Ｌ）〜
（ｄ）に示す・
（ａ）’ｎ＋型ＩｎＰ基板１０の表面にｓｉＮ又は５１
０２等の絶縁膜１９をスパッタリング法等で形成し、フ
ォトリソグラフィーと化学エツチングによりｎＩｎＰ
層の形成される領域の絶縁膜を除去する。その後、この
絶縁膜をエツチングマスクとして、ＩｎＰ基板中に深さ
約４μｍの凹部１１を形成する。（第３図（ａ））
（ｂ） 次に上記の基板即ち表面に凹部１１を有し、
しかも凹部以外の表面には絶縁膜の付着された基板上に
ｎ−型ＩｎＰ層１２（例えばキャリア密度５ Ｘ １０
１５ｃｍ ’、厚さ４μｍ）を気相エピタキシャル成長
法等で成長させる。この成長は、他の成長方法例えばＭ
ＯＣＶ Ｄ （Ｍｅｔａｌ ＱｒｇａｎｉｃＣｈｅｍ
ｉｃａｌ Ｖａｐ ｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法、
又はＭＢＫ（Ｍｏ１ｃｃｕｌａｒ Ｂｅａｍ Ｅｐｉｔ
ａｘｉａｌ ） 法などであってもよい。Next, a method for manufacturing a PIN photodiode according to an embodiment of the present invention will be described. The outline of the process is shown in Figure 3 (2L)~
As shown in (d), (a) siN or 51
An insulating film 19 such as 02 is formed by sputtering or the like, and nInP is formed by photolithography and chemical etching.
The insulating film in the region where the layer is to be formed is removed. Thereafter, using this insulating film as an etching mask, a recess 11 having a depth of about 4 μm is formed in the InP substrate. (FIG. 3(a)) (b) Next, having a recess 11 on the above substrate, that is, on the surface,
Furthermore, an n-type InP layer 12 (for example, a carrier density of 5 x 10
15 cm' and a thickness of 4 μm) using a vapor phase epitaxial growth method or the like. This growth can be achieved using other growth methods such as M
OCV D (Metal QrganicChem
ical Vapor or Deposition) method,
Or MBK (Mo1ccular Beam Epit
axial) method, etc. may be used.
次に、上記の基板を弗酸系の溶液に浸漬する事により、
第１の凹部以外のＩｎＰ層１２を絶縁膜１９と共にリフ
トオフ法で除去し、第１の凹部の内部をＩｎＰ層１２と
する。（第３図（ｂ））（Ｃ）次にこのｎ−型ＩｎＰ層
の埋め適寸れだ基板表面にｓｉＮ、又は８１０２等の絶
縁膜２０をスパッタリング法等で形成し、フォトリソグ
ラフィーと化学エツチングによりｎ−−ＩｎＧａＡｓ層
の形成される領域（この領域は受光部となる）の絶縁膜
を除去する。その後、この絶縁膜をエツチングマスクと
してｎ−−ＩｎＰ 層に深さ約２μ２ｎの凹部１３を形
成する。そしてこの基板にｎ−型ＩｎＧａＡｓ 層１４
（例えばキャリア密度、５×１０”Ｃｍ ’ 、厚さ２
μｙｙｚ ）を気相エピタキシャル成長法で成長させる
。この成長も他の成長方法例えばＭＯＣＶＤ 、ＭＢＫ
法であっても良い。Next, by immersing the above substrate in a hydrofluoric acid solution,
The InP layer 12 other than the first recessed portion is removed together with the insulating film 19 by a lift-off method, and the inside of the first recessed portion is left as the InP layer 12. (FIG. 3(b)) (C) Next, an insulating film 20 of SiN or 8102 is formed on the surface of the substrate with an appropriate gap by filling this n-type InP layer with a sputtering method, and then photolithography and chemical etching are performed. The insulating film in the region where the n--InGaAs layer is to be formed (this region will become the light receiving section) is removed by the following steps. Thereafter, using this insulating film as an etching mask, a recess 13 having a depth of about 2 μ2n is formed in the n--InP layer. Then, on this substrate, an n-type InGaAs layer 14 is formed.
(e.g. carrier density, 5 x 10"Cm', thickness 2
μyyz) is grown by vapor phase epitaxial growth. This growth can also be achieved using other growth methods such as MOCVD, MBK.
It may be a law.
その次に、この基板を弗酸系の溶液に浸漬する事により
、第２の凹部１３以外のＩｎＧａＡｓ 層を絶縁膜と共
にリフトオフ法で除去し１、第２の凹部１３の内部をＩ
ｎＧａＡｓ 層１４とする。（第３図（Ｃ））
次にｎ−型１ｎＧａＡｓ層１４の表面全体とその周辺部
のＩｎＰ基板表面に、ｐ型不純物を選択拡散し、ｐ＋型
ＩｎＧａＡｓ層１６及びｐ＋型ＩｎＰ層１６を形成する
。（第３図（ｄ））
このｐ型不純物の選択拡散はたとえばｓｉ、Ｎ４膜を選
択拡散のマスクとして封管法によりＺｎを１μｍの拡散
深さに拡散する。この場合の拡散温度、及び拡散時間は
それぞれ５００°Ｃ及び９分である。このｐ型不純物の
選択拡散は他の方法、たとえば封管法によるＣ（１の拡
散あるいはＺｎ 、 Ｃｄ 、 Ｍｇ 、 Ｂｅなどの
イオン注入法などによってもよい（ｄ）。Next, by immersing this substrate in a hydrofluoric acid solution, the InGaAs layer other than the second recess 13 is removed together with the insulating film by a lift-off method 1, and the inside of the second recess 13 is
An nGaAs layer 14 is used. (FIG. 3(C)) Next, p-type impurities are selectively diffused into the entire surface of the n-type 1nGaAs layer 14 and the surface of the InP substrate in the surrounding area to form a p+-type InGaAs layer 16 and a p+-type InP layer 16. do. (FIG. 3(d)) In this selective diffusion of the p-type impurity, Zn is diffused to a diffusion depth of 1 μm by a sealed tube method using, for example, a Si or N4 film as a selective diffusion mask. The diffusion temperature and diffusion time in this case are 500°C and 9 minutes, respectively. This selective diffusion of the p-type impurity may be performed by other methods, such as diffusion of C (1) using a sealed tube method or ion implantation of Zn, Cd, Mg, Be, etc. (d).
次にオーミック接触をとるだめの金属、たとえばＡｕ−
Ｚｎ蒸着膜１了、Ａｕ −Ｓｎ蒸着膜１８を形成する。Next, use a metal to make ohmic contact, such as Au-
After completing the Zn vapor deposition film 1, an Au--Sn vapor deposition film 18 is formed.
Ａｕ −Ｚｎ蒸着膜１７及びＡｕ−８ｎ蒸着膜１８は他
の金属、例えばＡｕ 、 Ｎｉ 、 Ｃｒ。The Au-Zn deposited film 17 and the Au-8n deposited film 18 are made of other metals, such as Au, Ni, and Cr.
）、ｇ 、 Ｇｅなどオーミック接触が得られるもので
あれば良い。), g, Ge, etc., which can provide ohmic contact, may be used.
最後に第２図の如く、表面保護膜２１を形成する。２１
は無反射コーテイング膜でもあり、たとえばプラダ−ｑ
ＣＶ Ｄ法によりＳｉ３Ｎ ４膜を１７６１ｍの厚さ
に堆積すると波長１．３μｍの光に対する無反射コーテ
イング膜となる。２１はたとえばＣＶＤ法、スパッタ蒸
着法々どによって形成したＳｉ、Ｎ４膜でもよく、また
８１０２ などの他の材質のものであっても良い。ま
た上記実施例では、２１は表面保護膜と無反射コーテイ
ング膜とを兼用しているが、第２図のｎ＋型ＩｎＰ１１
とｐ＋型ＩｎＰ層１６との接合表面の保護膜と受光部Ｂ
の無反射コーティング膜、とを異なる膜で形成しても良
い。まだ上記実施例でｐ型とｎ型とが逆であってもよい
事は勿論である。上記説明においてはＰＩＮフォトダイ
オードとして説明したが、インパットダイオードなどの
電気素子にも応用可能である。Finally, as shown in FIG. 2, a surface protective film 21 is formed. 21
is also a non-reflective coating film, for example Prada-q
When a Si3N4 film is deposited to a thickness of 1761 m by the CVD method, it becomes a non-reflective coating film for light with a wavelength of 1.3 μm. 21 may be, for example, a Si or N4 film formed by CVD or sputter deposition, or may be made of other materials such as 8102. Further, in the above embodiment, 21 serves both as a surface protection film and a non-reflection coating film, but the n+ type InP 11 in FIG.
and the protective film on the bonding surface of the p+ type InP layer 16 and the light receiving part B
The non-reflective coating film and the non-reflective coating film may be formed using different films. Of course, the p-type and n-type may be reversed in the above embodiments. In the above description, a PIN photodiode has been described, but it can also be applied to electric elements such as impact diodes.
、 本発明は・半絶縁性１”２基板を
用“る事が１き、しかも、プラナ−構造であるので、他
の光素子或は電気素子との集積化が行いやすく、いわゆ
る光ＩＣへの応用が可能である。The present invention allows the use of semi-insulating substrates and has a planar structure, making it easy to integrate with other optical devices or electrical devices, making it suitable for so-called optical ICs. can be applied.
発明の詳細
な説明した様に本発明は、長波長帯の受光素子として低
暗電流かつ高信頼度の特性が得られ、光通信の発展に大
きく寄与するものである。As described in detail, the present invention provides low dark current and high reliability characteristics as a long wavelength band light receiving element, and greatly contributes to the development of optical communications.
第１図は従来ｔニア） ＩｎＧａＡｓ ／ ＩｎＰ −
Ｐ Ｉ Ｎ ７ ｔトダイオードの構造断面図、第２図
は本発明の一実施例であるＩｎＧａＡｓ ／ ＩｎＰ−
Ｐ Ｉ Ｎフォトダイオードの構造断面図、第３図（ａ
）〜（ｄ）は本発明の一実施例であるＩｎＧａＡｓ ｙ
ＩｎＰ −Ｐ Ｉ Ｎフォトダイオードの構造断面図
である。
１１．１３・・・・・・第１．第２の凹部、１２・・・
「型ＩｎＰ層、１４−−−ｎ−型ＩｎＧａＡｓ層、１５
・・・・・・ｐ＋型ＩｎＧａＡｓ層、１６・・・・・・
ｐ＋型ＩｎＰ層、２１・・・・・表面保護膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
第３図Figure 1 shows conventional t-nia) InGaAs/InP -
FIG. 2 is a cross-sectional view of the structure of a PIN7T diode, which is an InGaAs/InP diode according to an embodiment of the present invention.
Structural cross-sectional view of PIN photodiode, Figure 3 (a
) to (d) are InGaAs y which is an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the structure of an InP-P I N photodiode. 11.13...1st. Second recess, 12...
"type InP layer, 14---n-type InGaAs layer, 15
...p+ type InGaAs layer, 16...
p+ type InP layer, 21...surface protective film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3
Claims (2)
第１の凹部内に第１導電形のＩｎＰ或は Ｉｎ＿ｘＧａ＿１＿−＿ｘＡｓ＿１＿−＿ｙＰ＿ｙなる
第１の層が形成され、更に前記第１層の表面から第２の
凹部が形成され、その中に第１導電形のＩｎ＿０＿．＿
５＿３Ｇａ＿０＿．＿４＿７Ａｓあるいは上記第１導電
形Ｉｎ＿ｘＧａ＿１＿−＿ｘＡｓ＿１＿−＿ｙＰ＿ｙ層
よりも組成がＩｎ＿０＿．＿５＿３Ｇａ＿０＿．＿４＿
７Ａｓに近いＩｎ＿ｘ＿′Ｇａ＿１＿−＿ｘ＿′Ａｓ＿
１＿−＿ｙ＿′Ｐ＿ｙ＿′なる第２の層を有し、前記第
２の層の表面全体及び前記第２の凹部の周囲の前記第１
の層もしくは第１導電形或は半絶縁性ＩｎＰ基板表面に
第２導電形の拡散層或はイオン注入層が形成されている
事を特徴とする化合物半導体素子。(1) A first layer of InP of a first conductivity type or In_xGa_1_-_xAs_1_-_yP_y is formed in a first recess formed in a first conductivity type or semi-insulating InP substrate, and A second recess is formed from the surface of the layer and In_0_. of the first conductivity type is formed therein. ＿
5_3Ga_0_. _4_7As or the composition of In_0_. _5_3Ga_0_. ＿４＿
In_x_'Ga_1_-_x_'As_ close to 7As
1_-_y_'P_y_';
1. A compound semiconductor device characterized in that a second conductivity type diffusion layer or an ion implantation layer is formed on the surface of a first conductivity type or semi-insulating InP substrate.
部を形成する工程、前記第１の凹部内に第１導電形のＩ
ｎＰ或はＩｎ＿ｘＧａ＿１＿−＿ｘＡｓ＿１＿−＿ｙＰ
＿ｙ層をエピタキシャル成長する工程、及び前記エピタ
キシャル成長した層に第２の凹部を形成する工程、そし
て、その第２の凹部に第１導電形の Ｉｎ＿０＿．＿５＿３Ｇａ＿０＿．＿４＿７Ａｓ或は上
記Ｉｎ＿ｘＧａ＿１＿−＿ｘＡｓ＿１＿−＿ｙＰ＿ｙ層
よりも組成がＩｎ＿０＿．＿５＿３Ｇａ＿０＿．＿４＿
７Ａｓに近いＩｎ＿ｘ＿′Ｇａ＿１＿−＿ｘ＿′Ａｓ＿
１＿−＿ｙ＿′Ｐ＿ｙ＿′層エピタキシャル成長する工
程、及び前記第１導電形のＩｎＧａＡｓ或はＩｎ＿ｘ＿
′Ｇａ＿１＿−＿ｘ＿′Ａｓ＿１＿−＿ｙ＿′Ｐ＿ｙ＿
′の表面全体及び前記第２の凹部の周囲の上記第１導電
形エピタキシャル層、もしくは第１導電型或は半絶縁性
ＩｎＰ基板表面に、第２導電形の不純物を拡散或は注入
する工程を含む事を特徴とする化合物半導体素子の製造
方法。(2) forming a first recess on a first conductivity type or semi-insulating InP substrate; forming a first conductivity type I in the first recess;
nP or In_xGa_1_-_xAs_1_-_yP
_y layer epitaxially grown, a second recess formed in the epitaxially grown layer, and a first conductivity type In_0_. _5_3Ga_0_. _4_7As or the composition of In_0_. _5_3Ga_0_. ＿４＿
In_x_'Ga_1_-_x_'As_ close to 7As
1_-_y_'P_y_' layer epitaxial growth, and the first conductivity type InGaAs or In_x_
'Ga_1_-_x_'As_1_-_y_'P_y_
a step of diffusing or implanting impurities of a second conductivity type into the first conductivity type epitaxial layer or the first conductivity type or semi-insulating InP substrate surface around the entire surface of the second conductivity type and the second recess; 1. A method for manufacturing a compound semiconductor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59171938A JPS6149484A (en) | 1984-08-18 | 1984-08-18 | Compound semiconductor element and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59171938A JPS6149484A (en) | 1984-08-18 | 1984-08-18 | Compound semiconductor element and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6149484A true JPS6149484A (en) | 1986-03-11 |
Family
ID=15932602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59171938A Pending JPS6149484A (en) | 1984-08-18 | 1984-08-18 | Compound semiconductor element and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6149484A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0251458A2 (en) * | 1986-05-16 | 1988-01-07 | AT&T Corp. | Process for manufacturing indium-phosphide devices |
| US5100833A (en) * | 1987-08-05 | 1992-03-31 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor light emitting device disposed in an insulating substrate |
| US5194399A (en) * | 1987-08-05 | 1993-03-16 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor light emitting device disposed in an insulating substrate |
| US5275968A (en) * | 1987-08-05 | 1994-01-04 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor light emitting device disposed in an insulating substrate |
| WO2017098769A1 (en) * | 2015-12-11 | 2017-06-15 | ソニー株式会社 | Light-receiving element, manufacturing method for light-receiving element, imaging element, and electronic device |
-
1984
- 1984-08-18 JP JP59171938A patent/JPS6149484A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0251458A2 (en) * | 1986-05-16 | 1988-01-07 | AT&T Corp. | Process for manufacturing indium-phosphide devices |
| US5100833A (en) * | 1987-08-05 | 1992-03-31 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor light emitting device disposed in an insulating substrate |
| US5194399A (en) * | 1987-08-05 | 1993-03-16 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor light emitting device disposed in an insulating substrate |
| US5275968A (en) * | 1987-08-05 | 1994-01-04 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor light emitting device disposed in an insulating substrate |
| WO2017098769A1 (en) * | 2015-12-11 | 2017-06-15 | ソニー株式会社 | Light-receiving element, manufacturing method for light-receiving element, imaging element, and electronic device |
| US10483299B2 (en) | 2015-12-11 | 2019-11-19 | Sony Semiconductor Solutions Corporation | Light-receiving element, method of manufacturing light-receiving element, imaging device, and electronic apparatus |
| US10943932B2 (en) | 2015-12-11 | 2021-03-09 | Sony Semiconductor Solutions Corporation | Light-receiving element, method of manufacturing light-receiving element, imaging device, and electronic apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR890004963B1 (en) | Semiconductor optical detector | |
| EP0156156A1 (en) | Avalanche photodiodes | |
| US6489635B1 (en) | Epitaxially grown p-type diffusion source for photodiode fabrication | |
| JPS6016474A (en) | Hetero multiple junction type photo detector | |
| CA1199097A (en) | Preparation of photodiodes | |
| US4700209A (en) | Avalanche photodiode and a method of making same | |
| JPS6149484A (en) | Compound semiconductor element and manufacture thereof | |
| CA1280196C (en) | Avanlanche photodiode | |
| JP4109159B2 (en) | Semiconductor photo detector | |
| US7009224B2 (en) | Metamorphic long wavelength high-speed photodiode | |
| Ohnaka et al. | A planar InGaAs PIN/JFET fiber-optic detector | |
| JPH07118548B2 (en) | III-V group compound semiconductor PIN photo diode | |
| JPS6149485A (en) | Compound semiconductor element and manufacture thereof | |
| JPS6398158A (en) | Photodiode | |
| JPS59149070A (en) | Photodetector | |
| JPH0344967A (en) | Manufacture of semiconductor device | |
| KR970009732B1 (en) | Fabrication method of planar pin photodiode | |
| JPH0316275A (en) | Manufacture of semiconductor photodetector | |
| JPS6080282A (en) | Compound semiconductor element and manufacture thereof | |
| JPS6222475B2 (en) | ||
| GB2240874A (en) | Photodiode | |
| JPS6259905B2 (en) | ||
| JPH041740Y2 (en) | ||
| JPH0722641A (en) | Photodetector | |
| JPS639986A (en) | Semiconductor photodetector |