KR970009732B1 - Fabrication method of planar pin photodiode - Google Patents
Fabrication method of planar pin photodiode Download PDFInfo
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- KR970009732B1 KR970009732B1 KR1019940014062A KR19940014062A KR970009732B1 KR 970009732 B1 KR970009732 B1 KR 970009732B1 KR 1019940014062 A KR1019940014062 A KR 1019940014062A KR 19940014062 A KR19940014062 A KR 19940014062A KR 970009732 B1 KR970009732 B1 KR 970009732B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 16
- 239000010410 layer Substances 0.000 claims abstract description 56
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 37
- 239000002344 surface layer Substances 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 238000002161 passivation Methods 0.000 claims abstract description 4
- 229910000679 solder Inorganic materials 0.000 claims abstract description 3
- 238000010521 absorption reaction Methods 0.000 claims abstract 5
- 238000000151 deposition Methods 0.000 claims abstract 3
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims description 36
- 229910052738 indium Inorganic materials 0.000 claims description 22
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 22
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 15
- 230000031700 light absorption Effects 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000005253 cladding Methods 0.000 claims description 5
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical group [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 claims description 5
- 125000002524 organometallic group Chemical group 0.000 claims description 2
- 230000003667 anti-reflective effect Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 21
- 239000002184 metal Substances 0.000 abstract description 21
- 230000003287 optical effect Effects 0.000 abstract 5
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910052790 beryllium Inorganic materials 0.000 description 4
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 4
- 229910052793 cadmium Inorganic materials 0.000 description 4
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L31/03046—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
Abstract
Description
제1(a) 및 1(b)도는 종래의 평면형 광검출기 구조의 단면도.1 (a) and 1 (b) are cross-sectional views of a conventional planar photodetector structure.
제2(a) 및 2(b)도는 본 발명에 따른 구조를 나타낸 단면도.2 (a) and 2 (b) are cross-sectional views showing the structure according to the present invention.
제3도의 (a)~(h)는 본 발명에 따른 제조공정도.Figure 3 (a) ~ (h) is a manufacturing process diagram according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
27,37 : n형 인듐인(InP) 기판 28,38 : n형 인듐인 버퍼층27,37: n-type indium phosphorus (InP) substrate 28,38: n-type indium phosphorus buffer layer
29,39: 도우평이 안된 인듐갈륨비소(InGaAs)광흡수층29,39: Undoped indium gallium arsenide (InGaAs) light absorption layer
30,40 : 도우핑이 안된 인듐인(InP) 클래드 층30,40: Undoped indium phosphorus (InP) cladding layer
31 : 인듐갈륨비소 오믹접촉층 41p : p형 인듐갈륨비소층31: indium gallium arsenide ohmic contact layer 41p: p-type indium gallium arsenide layer
41n : n형 인듐갈륨비소층 32,42 : 인듐인(InP) 표면층41n: n-type indium gallium arsenide layer 32, 42: indium phosphorus (InP) surface layer
43 : 제1실리콘 질화막(SiNx) 33,44 : p형 영역43: first silicon nitride film (SiNx) 33,44: p-type region
34,45 : 제2실리콘 질화막 35p,46p : p형 금속전극34,45: second silicon nitride film 35p, 46p: p-type metal electrode
35n46n : n형 금속전극 36,47 : 제3실리콘 질화막.35n46n: n-type metal electrode 36,47: third silicon nitride film.
본 발명은 평면형 광검출기의 제조방법에 관한 것으로서, 특히 p형 및 n형 전극을 모두 전면에 형성하는 평면형 광검출기의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a planar photodetector, and more particularly, to a method of manufacturing a planar photodetector in which both p-type and n-type electrodes are formed on the entire surface.
종래기술로, 제1도의 (a)는 통상적인 평면형 광검출기 구조의 단면도를 나타낸 것이다. 그 대표적인 실시예들은 다음과 같다.In the prior art, FIG. 1A shows a cross-sectional view of a conventional planar photodetector structure. Representative embodiments thereof are as follows.
먼저, n형 인듐인(InP) 기판(11) 위에 2 내지 3μm 가량의 두께를 갖는 도우핑(dopping)이 안된 인듐갈륨비소(InGaAs)(12), 1μm 가량의 두께를 갖는 n형 인듐인(InP)(13)층을 성장시킨 후, 아연(Zn) 또는 카드늄(Cd)의 확산방법을 사용하거나 또는 베릴륨(Be)등의 이온주입(ion implantation)을 통해 (14) 영역을 p형으로 변질시켜 p+-InP층을 형성한다. 그리고 p형 금속전극(16)을 상기 p+-InP층(14) 위에 n형 금속전극(17)을 상기 기판(11) 밑에 형성하여 제1도의 (a)와 같은 평면형 광검출기를 제작한다.First, an undoped indium gallium arsenide (InGaAs) 12 having a thickness of about 2 to 3 μm on the n-type indium phosphorous (InP) substrate 11 and an n-type indium phosphorus having a thickness of about 1 μm ( After the InP (13) layer is grown, the region (14) is changed to p-type by diffusion of zinc (Zn) or cadmium (Cd) or by ion implantation such as beryllium (Be). To form a p + -InP layer. A p-type metal electrode 16 is formed on the p + -InP layer 14 to form an n-type metal electrode 17 under the substrate 11 to fabricate a planar photodetector as shown in FIG.
그러나, 상기 종래의 통상적 평면형 광검출기 구조는 외부 회로와 광검출기와의 전기적 접촉을 위한 p형 금속전극(16)과 n형 금속전극(17)이 인듐인(InP) 반도체(14) 및 (11)과 오믹접촉(ohmic contact)을 이루고 있어 음접촉 저항(ohmic contact resistance)이 커서 소자의 면적을 줄이기 어려울 뿐만 아니라, 고속 동작에서 수신감도를 저하시키는 문제점이 있다.However, in the conventional conventional planar photodetector structure, the p-type metal electrode 16 and the n-type metal electrode 17 are indium (InP) semiconductors 14 and 11 for electrical contact between the external circuit and the photodetector. ) And ohmic contact, so that the ohmic contact resistance (ohmic contact resistance) is large, it is difficult to reduce the area of the device, there is a problem in reducing the reception sensitivity in high-speed operation.
따라서, 상기 종래의 통상적인 평면형 광검출기의 문제점을 해결하기 위하여 개선된 평면형 광검출기 구조가 제안되었으며(대한민국 특허 출원중 : 출원번호 93-26785호) 그 구조가 제1도의 (b)에 나타나 있다.Therefore, an improved planar photodetector structure has been proposed to solve the problems of the conventional planar photodetector (Korean Patent Pending Application No. 93-26785). The structure is shown in FIG. .
상기 개선된 평면형 광검출기의 실시예에 따르면, n형 인듐인(InP) 기판(18)위에 도우핑이 안된 인듐갈륨비소(InGaAs) 광흡수층(19), 도우핑이 안된 인듐인(InP) 클래드층(20), 및 500~1,000A의 얇은 두께의 인듐갈륨비소(InGaAs) 오믹접촉(ohmic contact)층(21)과 인듐인 표면층(22)을 형성한 후, 광의 흡수가 일어나는 소정의 영역에 아연(Zn) 또는 카드늄(Cd)의 확산방법을 사용하거나 또는 베릴륨(Be) 등의 이온주입(ionimplantation)을 통해 (23) 영역을 p형으로 변질시켜 p+-InP층을 형성한다. 그 후에 p형 금속전극(25)을 형성하는 소정 위치 하부의 인듐인(InP)층(22) 표면층(22)을 선택적으로 식각해내고 p형 금속전극(25)을 인듐갈륨비소(InGaAs)층(21) 위에 형성되도록 한다.According to an embodiment of the improved planar photodetector, an undoped indium gallium arsenide (InGaAs) light absorbing layer 19, an undoped indium phosphorus (InP) cladding on an n-type indium phosphorus (InP) substrate 18 After forming the layer 20 and the thin layer of indium gallium arsenide (InGaAs) ohmic contact layer 21 of 500 to 1,000 A and the surface layer 22 which is indium, a predetermined region where light absorption takes place is formed. The p + -InP layer is formed by deforming the (23) region to p-type using a diffusion method of zinc (Zn) or cadmium (Cd) or through ionimplantation such as beryllium (Be). Thereafter, the surface layer 22 of the indium phosphorus (InP) layer 22 under the predetermined position forming the p-type metal electrode 25 is selectively etched, and the p-type metal electrode 25 is indium gallium arsenide (InGaAs) layer. (21) to be formed.
상기 제1도의 (b)와 같은 개선된 구조의 평면형 광검출기는 표면에 노출되는 pn접합부분은 에너지 밴드갭(energy bandgap)이 큰 인듐인(InP)층(22)에 형성되도록 하여 표면 누설전류를 감소시키고 p형 오믹접합은 에너지 갭이 작은 인듐갈륨비소(InGaAs)층(21) 위에 형성시킴으로써 옴접촉 저항(ohmic contact resistance)을 줄이 수 있는 효과를 얻을 수 있다.The planar photodetector of the improved structure as shown in (b) of FIG. 1 allows the pn junction portion exposed to the surface to be formed on the indium (InP) layer 22 having a large energy bandgap. In addition, the p-type ohmic junction may be formed on the InGaAs layer 21 having a small energy gap, thereby reducing ohmic contact resistance.
그러나, 상기 종래의 평면형 광검출기 구조는 모두 p형 전극이 칩의 전면에, n형 전극은 칩의 뒷면에 형성되어 있어 와이어 본딩에 의한 패키지만을 사용할 수 밖에 없는 문제점이 있다.However, the conventional planar photodetector structure has a problem in that only p-type electrodes are formed on the front of the chip and n-type electrodes are formed on the back of the chip, so that only a package by wire bonding can be used.
상기 문제점을 해결하기 위하여 본 발명은 평면형 광검출기에 있어서 p형 및 n형 금속전극을 모두 칩의 전면에 형성하므로써 플립 칩 본딩이 가능하도록 하여 광검출기의 동작특성을 향상시키고 대량생산에 유리한 평면형 광검출기의 제조방법을 제공하는데 목적이 있다.In order to solve the above problems, the present invention provides a flip-chip bonding by forming both p-type and n-type metal electrodes on the front surface of the chip in the planar photodetector, thereby improving the operating characteristics of the photodetector and advantageous in mass production. It is an object to provide a method of manufacturing a detector.
아울러, 상기 개선된 구조에서는 광흡수 영역에 비록 얇은 두께이기는 하지만 상기 제1(b)도에서 p형 인듐갈륨비소층(21)이 존재하고 있어 수신감도를 저하시키는 용인이 되고 있으나 본 발명에서는 추가의 공정없이 이 부분을 제거함으로써 수신감도의 향상을 꾀하고 있다.In addition, although the p-type indium gallium arsenide layer 21 is present in FIG. 1 (b), although the thickness is thin in the light absorbing region in the improved structure, it is acceptable to reduce the reception sensitivity. By removing this part without any step, the reception sensitivity is improved.
상기 목적을 달성하기 위하여 본 발명에서는 첨부된 도면에 의거하여 그 상세한 설명을 한다.In the present invention to achieve the above object will be described in detail based on the accompanying drawings.
먼저, 본 발명에서 제안한 p형 및 n형 금속전극(35p,35n)이 전면에 형성된 평면형 광검출기의 평면도와 A-B 방향으로 절단하였을때의 단면도가 제2도의 (a)와 (b)에 각각 나타나 있다.First, a plan view of a planar photodetector formed on the front surface of the p-type and n-type metal electrodes 35p and 35n proposed in the present invention and a cross-sectional view when cut in the AB direction are shown in FIGS. 2A and 2B, respectively. have.
상기 제2도의 (a)의 구조를 설명하면 다음과 같다.The structure of FIG. 2 (a) is as follows.
먼저, n형 인듐인(InP) 기판(27) 위에 n형 인듐인(InP) 버퍼(buffer)층(28), 도우핑이 안된 인듐갈륨비소(InGaAs) 광흡수층(29), 도우핑이 안된 인듐인 클래드(clad)층(30), 인듐갈륨비소 오믹접촉층(31), 및 인듐인 표면층(32)이 유기금속 화학증착법(MOCVD)등의 에피택시법에 의해 성장된다. 여기에 소정의 광흡수 영역에 위치한 상기 인듐인(InP) 클래드층(30), 인듐갈륨비소 오믹접촉층(31), 및 인듐인 표면층(32)을 아연(Zn)또는 카드늄(Cd)의 확산 또는 베릴륨(Be)등의 이온주입에 의하여 p형 영역(33)으로 변질시킨다.First, an n-type indium phosphide (InP) buffer layer 28, an undoped indium gallium arsenide (InGaAs) light absorbing layer 29, an undoped An indium clad layer 30, an indium gallium arsenide ohmic contact layer 31, and an indium surface layer 32 are grown by epitaxy methods such as organometallic chemical vapor deposition (MOCVD). The indium phosphorus (InP) cladding layer 30, the indium gallium arsenide ohmic contact layer 31, and the indium surface layer 32, which are located in a predetermined light absorption region, are diffused into zinc (Zn) or cadmium (Cd). Alternatively, the p-type region 33 is altered by ion implantation such as beryllium (Be).
그리고, p형 금속전극(35p)은 광흡수창이 있는 p형 영역(33)의 p형 인듐갈륨비소 오믹접촉층(31) 위에 n형 금속전극(35n)은 n형 인듐갈륨비소 이믹접촉층(31) 위에 형성시킨 후, 광흡수창의 무반사막 및 플립 칩본딩(flip chip bonding)용 패시베이션(passivation; 표면안정화)을 위한 제3실리콘 질화막(36)을 형성한 구조를 갖고 있다.The p-type metal electrode 35p is disposed on the p-type indium gallium arsenide ohmic contact layer 31 of the p-type region 33 having the light absorption window, and the n-type metal electrode 35n is the n-type indium gallium arsenide dynamic contact layer ( 31), a third silicon nitride film 36 for passivation (surface stabilization) for flip chip bonding and an antireflection film of the light absorption window is formed.
제3도의 (a)~(h)는 본 발명의 구체적인 실시방법에 따른 제조공정의 단면도를 나타낸다.(A)-(h) of FIG. 3 show sectional drawing of the manufacturing process which concerns on the specific implementation method of this invention.
먼저, (a)공정은, n형 인듐인(InP) 기판(37) 위에 n형 인듐인(InP) 버퍼(buffer)층(38), 도우핑이 안된 인듐갈륨비소(InGaAs) 광흡수층(39), 도우핑이 안된 인듐인(InP) 클래드층(40), 인듐갈륨비소(InGaAs) 오믹접촉층(41), 및 인듐인(InP) 표면층(42)이 각각 순차적으로 형성된 에피층을 유기금속 화학증착법(Metal-Organic Chemical Vapor Deposition)등의 에피택시법에 의해 성장한다.First, in the step (a), the n-type indium-phosphorus (InP) buffer layer 38 and the undoped indium-gallium arsenide (InGaAs) light absorption layer 39 are formed on the n-type indium-phosphorus (InP) substrate 37. ), An in-doped indium phosphorus (InP) cladding layer 40, an indium gallium arsenide (InGaAs) ohmic contact layer 41, and an indium phosphorus (InP) surface layer 42 are sequentially formed of an epitaxial metal layer It grows by epitaxy methods, such as a chemical vapor deposition (Metal-Organic Chemical Vapor Deposition).
(b)공정은, 상기 인듐인 표면층(42) 위에 플라즈마에 의한 화학증착법(PECVD : Plasma Enhanced Chemical Vapor Deposition)등에 의해 소정의 패턴을 갖는 제1실리콘 질화막(SiNx)(43)을 증착하고, 이 제1실리콘 질화막(43)을 통상의 포토리소그라피에 의해 소정의 패턴을 형성을 갖도록 식각해내고, 상기 인듐인 클래드층(40)가지 제1불순물인 아연(Zn) 또는 카드늄(Cd)의 확산 또는 베릴륨(Be)등의 이온주입을 행하여 이부분을 p형 영역(44)으로 만든다.In the step (b), a first silicon nitride film (SiNx) 43 having a predetermined pattern is deposited on the surface layer 42, which is indium, by a plasma enhanced chemical vapor deposition (PECVD). The first silicon nitride film 43 is etched to form a predetermined pattern by ordinary photolithography, and the diffusion of zinc (Zn) or cadmium (Cd), which is the first impurity of the clad layer 40 of indium, Ion implantation, such as beryllium (Be), is performed to make this portion the p-type region 44.
(c)공정은, 상기 확산공정에서 마스크로 사용한 제1실리콘 질화막(43)을 그대로 식각 마스크로 사용하여 표면의 인듐인 표면층(42)을 선택적으로 습식식각해낸다.In the step (c), the surface layer 42, which is indium on the surface, is selectively wet-etched using the first silicon nitride film 43 used as the mask in the diffusion step as it is as an etching mask.
이때 염산과 인산을 혼합한 용액을 사용하면 인듐갈륨비소층(41)은 식각되지 않고 인듐인 표면층(42)만을 식각해낼 수 있다.In this case, when a solution mixed with hydrochloric acid and phosphoric acid is used, the indium gallium arsenide layer 41 may not be etched, but only the surface layer 42 which is indium may be etched.
(d)공정은, 상기 확산 및 식각을 위해서 제1마스크로 사용한 제1실리콘 질화막(43)을 불산용액에서 제거한 후, 다시 PECVD 등의 방법으로 소정의 패턴을 갖는 제2실리콘 질화막(45)을 증착하고, 이 제2실리콘 질화막을 제2마스크로 하여 광흡수차 영역과 p형 및 n형 전극형성 부분만을 식각해낸다.In step (d), the first silicon nitride film 43 used as the first mask for the diffusion and etching is removed from the hydrofluoric acid solution, and then the second silicon nitride film 45 having a predetermined pattern is removed by PECVD or the like. The film is deposited, and only the light absorption region and the p-type and n-type electrode forming portions are etched using the second silicon nitride film as the second mask.
(e)공정은, 다시 염산과 인산의 혼합용액에서 인듐인 표면층(42)을 선택적 습식식각하면 광흡수창의 표면에 노출된 p형 인듐갈륨비소층(41p)은 식각되지 않고, n형 금속전극 형성 영역의 표면에 있는 상기 인듐인 표면층(42)은 선택식각되어 n형 인듐갈륨비소층(41n)이 노출된다.In the step (e), if the surface layer 42 which is indium is selectively wet-etched again in the mixed solution of hydrochloric acid and phosphoric acid, the p-type indium gallium arsenide layer 41p exposed on the surface of the light absorption window is not etched, and the n-type metal electrode The indium surface layer 42 on the surface of the formation region is selectively etched to expose the n-type indium gallium arsenide layer 41n.
(f)공정은, 상기 p형 및 n형 인듐갈륨빕소층(41p,41n) 전면에 소정의 전극용 금속을 증착한 다음, 이 위에 p형 금속전극(46p) 및 n형 금속전극(46n)을 리프트-오프(lift-off) 방법으로 어닐링(annealing)하여 오믹접촉을 형성한다.In the step (f), a predetermined electrode metal is deposited on the p-type and n-type indium gallium bisoxo layers 41p and 41n, and then the p-type metal electrode 46p and the n-type metal electrode 46n thereon. Is annealed by a lift-off method to form an ohmic contact.
(h)공정은, 광흡수창의 무반사막 코팅(coathing) 및 플립 칩 본딩용(flip chip bonding) 패시베이션(passivation)을 위하여 제3실리콘 질화막(47)을 PECVD등의 방법으로 증착하고 플립 칩 본딩용 솔더(solder)가 형성되는 영역만을 식각해낸다.In step (h), the third silicon nitride film 47 is deposited by PECVD or the like for flip chip bonding for anti-reflective coating and flip chip bonding passivation of the light absorption window. Only the area where solder is formed is etched away.
상기 제3도의 변형예는 제2도에 나타낸 평면형 광검출기의 구조에서 칩의 전면에 배치된 n형 전극을 칩의 뒷면에 형성한 구조로서, 구체적인 실시예는 제3도에 나타낸 제조공정 순서중 (d)공정을 생략하고, (h)공정까지 끝난후 상기 n형 인듐인 기판(37)의 뒷면에 n형 급속전극을 증착할 수 있다.The modification of FIG. 3 is a structure in which the n-type electrode disposed on the front of the chip is formed on the back of the chip in the structure of the planar photodetector shown in FIG. 2, and a specific embodiment of the manufacturing process shown in FIG. After the step (d) is omitted and after step (h), the n-type rapid electrode may be deposited on the back surface of the n-type indium substrate 37.
이상과 같은 본 발명은 다음과 같은 효과들을 갖는다.The present invention as described above has the following effects.
첫째로, p형 및 n형 전극이 모두 전면에 형성되어 있어 본딩용 와이어가 없는 플립 칩 본딩 패키지에 적용할 수 있어서 광검출기 모듈의 특성을 향상시킬 수 있을 뿐만 아니라, 대량생산에 유리하다.First, since both p-type and n-type electrodes are formed on the front surface, the p-type and n-type electrodes can be applied to a flip chip bonding package without a bonding wire, so that the characteristics of the photodetector module can be improved as well as advantageous for mass production.
둘째로, 상기 제1(b)도에 나타낸 구조의 평면형 광검출기에서 p형 인듐갈륨비소층(21)을 제거함으로써 수신감도를 향상시킬 수 있다.Second, the reception sensitivity can be improved by removing the p-type indium gallium arsenide layer 21 from the planar photodetector having the structure shown in FIG. 1 (b).
세째로, 상기 제1(b)도에 나타낸 구조의 평면형 광검출기에서 p형 금속전극만을 인듐갈륨비소층(21) 위에 형성하지만, 본 발명에서는 p형 및 n형 금속전극 모두를 에너지 밴드갭이 작은 인듐갈륨비소 오믹접촉층(31) 위에 형성함으로써 오믹접촉저항을 줄일 수 있어 고속동작에 유리한 특성을 갖는다.Third, in the planar photodetector having the structure shown in FIG. 1 (b), only the p-type metal electrode is formed on the indium gallium arsenide layer 21. However, in the present invention, both the p-type and n-type metal electrodes have an energy band gap. By forming on the small indium gallium arsenide ohmic contact layer 31, the ohmic contact resistance can be reduced, which is advantageous for high-speed operation.
네째로, 상기 본 발명에서 제안한 구조의 평면형 광검출기를 제조하는 공정이 주로 자기정렬기법을 사용하므로 종래의 평면형 광검출기 제조공정에 비해 추가의 포토리소그라피 마스크 없이도 쉽게 제작 가능하다.Fourth, since the process of manufacturing the planar photodetector having the structure proposed in the present invention mainly uses a self-aligning technique, it can be easily manufactured without an additional photolithography mask as compared with the conventional planar photodetector manufacturing process.
Claims (7)
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