JP2005260118A - Photo detector and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photo detector having rapid responsibility, excellent sensitivity, and little dark current by solving the problem that, in the most prevailing photo detector having such a structure that an p-type light receiving layer is grown on an n-type substrate and then an n-type dopant is selectively diffused via a mask to form a p-type region in the light receiving layer, diffusion is difficult to be controlled and hence the depth of a pn junction varies, causing a variation in sensitivity and dark current, and electrostatic capacitance increases by reverse bias, causing slow responsibility, and in a mesa-type photo detector having such a structure that an n-type light receiving layer and a p-type light receiving layer are epitaxially grown on an n-type substrate and then the periphery is mesa-etched and covered with an SiN and InP films, the dark current increases due to the leakage, causing a poor yield. <P>SOLUTION: On top of an n-type substrate, an n-type buffer layer, an n-type light receiving layer, and a p-type light receiving layer are epitaxially grown. Then, an n-type dopant is heavily introduced into the periphery by diffusion or ion implantation to form an n-type shielding region from the top face to a buffer layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a light receiving element for optical communication having a pin structure with low dark current and excellent high-speed response, and a method for manufacturing a light receiving element with high yield.

Ichiro Karauchi, Yasushi Fujimura, Takashi Iwasaki, Hitoshi Terauchi, Naoyuki Yamabayashi, “Large Intensity Area InGaAs PIN-PD”, Sumitomo Electric, 141, September 1992, p21-26

Ichiro Tonai, TakashiYano and Hiroshi Okuda, "InGaAs PIN Photodiodes for Monitoring the OpticalOutput Power of Semiconductor Laser Diodes, IEEE Tokyo Section, Denshi Tokyo No. 28 (1989), p78-81

Kentaro Michiguchi, Hiroshi Yano, Sosaku Sawada, Go Sekiguchi, Hiroyuki Kamiyama, Masataka Kuroda “InP Passivation Structure pinPD and its Applications” SEI Technical Review 151, September 1997, p18-22

  2. Description of the Related Art Conventionally, a semiconductor light-receiving element (Photodiode) is formed by epitaxial growth of an n-type light-receiving layer on an n-type semiconductor substrate that is undoped or doped with a small amount of n-type impurities, and a p-type material such as Zn is formed in a portion serving as a light-receiving region through a mask opening. A p-type region is formed by selectively diffusing type impurities, a pn junction is provided in the light receiving layer, an n-electrode is formed on the n-type substrate, and a p-electrode is formed on the p-region.

The carrier (electron) concentration of the n-type light-receiving layer before doping with the p-type impurity is 1 × 10 ¹⁶ cm ⁻³ or less. Selective diffusion means that impurities are thermally diffused locally through a mask. Selection means simply choosing a place. It does not mean diffusion using differences such as diffusion coefficients.

  A general manufacturing process of a light receiving element by selective diffusion according to a conventional example will be described with reference to FIG. This is a top-incident light receiving element, but the back-illuminated light receiving element has the same diffusion process.

  As shown in FIG. 1A, an n-type buffer layer 3 and an n-type light-receiving layer 4 are epitaxially grown on a heavily doped n-type substrate crystal (InP, GaAs, Si, etc.) 2. The light receiving layer 4 is undoped or lightly doped. Even undoped becomes n-type. An n-type window layer may be provided on the light-receiving layer 4, but here, a window layer without a window layer is shown. That is an epi-wafer. As shown in FIG. 1B, a SiN film 5 to be a diffusion mask is coated on the light receiving layer 4 by a P-CVD method or the like.

  As shown in FIG. 1 (3), patterning is performed by photolithography, and a hole is made in a portion corresponding to the central portion of the SiN film 5. Zn is diffused from the gas phase through the hole to form a p region 6 in the center of the inside of the n-type light receiving layer 4. Dish-shaped pn junctions 26 and 25 are formed at the boundary between the p region 6 and the n-type light receiving layer 4 (FIG. 1 (4)). A transparent antireflection film (SiON or the like) 7 is formed on the surface side by a P-CVD method or the like (FIG. 1 (5)). Next, a part of the antireflection film 7 is removed, and a p-electrode 8 is deposited thereon and heated to be alloyed (FIG. 1 (6)). It can be ohmic joined. An n-electrode 9 is vapor-deposited on the back surface of the n-type substrate 2 and alloyed to make ohmic contact. That is an ordinary method for manufacturing a light receiving element. This is top incidence.

  The back-illuminated type is one in which the p-electrode is widened and a hole is formed in a part of the n-electrode on the back surface and covered with an antireflection film so that light can enter from the back surface. The p region generation method is the same for both the top-incident type and the back-side incident type.

  It is a general technique to produce a dish-shaped p region and pn junction by selective impurity diffusion as described above to obtain a light receiving element. For this reason, light-receiving elements using diffusion are still mainstream.

However, the light receiving element by Zn diffusion still has a drawback. Although a pn junction must be formed between the light receiving layers, the light receiving layer is thin and about 2 μm. Even if it is thick, it is up to 6 μm. The pn junction is a plane connecting points (p = n) where the electron concentration n and the hole concentration p are equal, but the gradient of the hole concentration due to diffusion is large, and its position (depth) is given accurately. difficult. That difficulty reduces product yield.
In general, in order to improve the high-speed response of the light receiving element, the pn junction needs to be a stair-like steep junction. A pn junction obtained by thermally diffusing a p-type impurity such as Zn has a gentle slope. Therefore, a pn junction made by thermal diffusion is inferior in high-speed response.

Furthermore, since Zn is thermally diffused through the mask opening to form the dish-shaped p region 6 and pn junctions 26 and 25, not only the lateral pn junction 26 but also the pn junction 25 extending in the vertical direction can be formed. Since there is an n-type crystal layer of 1 × 10 ¹⁶ cm ⁻³ or less in which the undoped or n-type impurity is slightly doped around the pn junction, when a reverse bias is applied, the depletion layer is only in the vertical direction from the pn junction. It spreads in the horizontal direction as well. As the depletion layer spreads in the lateral direction, the effective light receiving area increases, the capacitance increases, the delay time increases, and the response speed decreases.

  FIG. 3 (1) shows lateral enlargement of the pn junction. When a reverse bias is applied, a depletion layer spreads from the pn junction to both sides. In particular, the depletion layer expands inside the n-type light receiving layer 4 having a low concentration. The depletion layer 32 extending downward from the horizontal pn junction 26 is beneficial to increase sensitivity, but the lateral depletion layer 33 extending laterally from the vertical pn junction 25 enlarges the effective junction capacitance. A large junction capacitance is not preferable because the delay time (τ = CR) becomes long.

  Further, when Zn is doped by thermal diffusion, the pn junction depth is controlled with time while keeping the amount and temperature of the dopant raw material constant. However, in practice, depth control is difficult, and the depth of selective diffusion (depth of the pn junction) varies. The pn junction depth d varies even within the plane of the wafer, and the pn junction depth d varies between different wafers. The same concentration of dopant is diffused in the gas phase, liquid phase, and solid phase through the same mask, but there are places where Zn can enter well depending on the portion of the wafer, but there are also portions where it does not readily enter. This is because the surface state of the wafer differs depending on the part. There is an oxide film in part, and the diffusion speed of Zn is greatly different. For this reason, the pn junction depth in the light receiving layer varies and the pn junction position is not stable. For this reason, sensitivity and capacity vary, and the yield of light receiving elements is reduced.

  Such is unavoidable as long as the p region is formed by thermal diffusion of the p-type dopant through the mask. There is also a method of forming a pn junction without using thermal diffusion. It is a method for producing a pn junction of a light receiving layer by epitaxial growth. On the n-type semiconductor substrate, a light-receiving layer doped with undoped or n-type impurities and a light-receiving layer doped with p-type impurities are epitaxially grown in order to form a pn junction at the interface of the epilayer. In that case, since the boundary surface between the n-type light receiving layer and the p-type light receiving layer is entirely a pn junction, the pn junction becomes a steep stepped junction. High-speed response is excellent because the boundary becomes steep. Above all, since the boundary between the n-type layer and the p-type layer is a pn junction, the height of the pn junction is surely determined and the depth does not vary. The position of the pn junction is determined and the variation in characteristics should be reduced.

  FIG. 2 illustrates a method of manufacturing such an epitaxial growth type light receiving element. This is also a top-illuminated type, but the back-illuminated type has the same problem. An n-type buffer layer 3, an n-type light-receiving layer 22, and a p-type light-receiving layer 23 are epitaxially grown on an n-type substrate (InP, GaAs, Si, etc.) (FIG. 2 (1)). Instead of diffusing impurities, the p-type light-receiving layer 23 is formed by epi growth. Therefore, the boundary between the n-type and p-type light receiving layers 22 and 23 becomes a pn junction 26. It is a horizontal pn junction 26 and does not have a vertical portion.

  As shown in FIG. 2B, the SiN mask 27 is formed by a P-CVD method or the like, and this can also function as an antireflection film. As shown in FIG. 2C, a resist pattern is formed by photolithography, and the portions on both sides of the element are mesa-etched. This is to reduce the area of the pn junction. This is called mesa etching because the raised part is mesa type. The side surfaces 29 and 29 of the n-type buffer layer 3, the n-type light receiving layer 22 and the p-type light receiving layer 23 are exposed, and the intermediate portion upper surfaces 28 and 28 of the buffer layer 3 are also partially exposed. When the pn junction is exposed to the space, a short circuit occurs and a leakage current flows, so that the peripheral wall surface 29 and the buffer layer upper surface 28 are covered with a passivation film 30 such as an InP film (FIG. 2 (4)). A part of the SiN film 27 is removed, and a p-electrode 8 is deposited thereon to form a heat alloy. An n-electrode material is deposited on the back surface of the n-type substrate 2 and alloyed to form an n-electrode 9.

  There is also a light receiving element made by the above process. The reason for mesa etching is as follows. A pn junction is formed by forming a p-type layer on the n-type layer. However, if it is left as it is, the pn junction area is equal to the chip area and is too wide. If the pn junction is wide, the capacitance increases, the delay time increases, and there is no high-speed response. Therefore, the four sides around the light receiving layer are mesa-etched to narrow the pn junction. When the pn junction is exposed to the side, when a reverse bias is applied due to a large number of junction levels, a leakage current (leakage current) flows there. Since the leakage current flows even when there is no optical signal, it is called dark current. This is noise but the temperature change is large, so that the photocurrent generated by the signal cannot be extracted accurately.

  Since the end of the pn junction cannot be exposed on the side surface, the end of the pn junction exposed by mesa etching may be covered with an InP film, SiN film, or the like. This is called a passivation film, but has the effect of covering the pn junction and reducing the leakage current. This reduces the dark current.

  However, even in such a structure in which the exposed end of the pn junction is covered with InP or SiN, current leaks because the end face after mesa etching is contaminated or the crystal quality of the covered InP film varies. The dark current is not necessarily improved and the yield is poor. As with the selective diffusion method, when a reverse bias is applied, the depletion layer also spreads to the side. This is shown in (2) of FIG. Depletion layers 32 and 33 spread from the pn junction 26 downward and diagonally downward. As the depletion layer area increases, the capacitance increases and the delay time increases.

  There are also problems with mesa etching. Etching includes dry etching and wet etching. Either etching can be performed to cut the side of the light receiving layer. If the peripheral part of the light receiving layer is removed by wet etching, the remaining part becomes a trapezoid and becomes a shape suitable for the name of mesa. Since the etched surface becomes an inclined surface, the pn junction area varies due to variations in the etching amount. This causes variations in capacitance and photocurrent. That is undesirable.

  If the periphery of the light-receiving layer is removed by dry etching, the etched surface is cleanly perpendicular to the bottom surface. The pn junction area is constant. However, the plasma is blown in the depth direction and the sides are shaved, so the damage to the crystal is great. As a result, the dark current may increase. There is still a difficulty in the structure in which the n-type and p-type light-receiving layers thus formed by epitaxial growth are mesa-etched and covered with InP and SiN films. For this reason, the p region of the light receiving element is often formed by thermal diffusion of Zn or the like.

  In the present invention, an n-type light-receiving layer and a p-type light-receiving layer are epitaxially grown on an n-type substrate, and a n-type impurity is selectively diffused on both sides while leaving a central p-type region. As a mold area, no current was passed here. Rather than etching off both sides, n-type impurities are diffused or ion-implanted into both sides to make both sides n-type regions and the pn junction is limited to a narrow range in the center. As a result, generation of leakage current from the end of the pn junction and dark current are prevented, and enlargement of the depletion layer is suppressed and high-speed response is obtained.

  In order to distinguish from the n-type substrate and the n-type of the n-type light-receiving layer, the n-type region provided by diffusion and ion implantation around the light-receiving region at the center is referred to as an “n-type shielding region”. Since the n-type shielding region is obtained by subsequently doping an epitaxially grown n-type impurity, the layer composition is not uniform. A p-type window layer having an n-type shielding region is an n-type having the same composition as the window layer. The p-type light-receiving layer and the n-type light-receiving layer used as the n-type shielding region are n-type having the same composition as the light-receiving layer. An n-type buffer layer that is an n-type shielding region is an n-type having a buffer layer composition.

Of course, the dopant concentration is not uniform. The portion in which the p-type window layer and the p-type light-receiving layer are n-type shielding regions is effectively obtained by subtracting the acceptor concentration (N _A ) of the original p-type impurity from the donor concentration (N _D ) of the n-type impurity. n-type impurity concentration becomes _{(n D '= n D -N} a). Since p-type acceptor concentration N _A of the light receiving layer is significant, it is necessary that the high-concentration n-type doping (N _{D> N A)} above it. Therefore, the doping concentration of the n-type shielding region is 10 ¹⁸ cm ⁻³ or more (N _D ≧ 10 ¹⁸ cm ⁻³ ). The n-type light shielding layer and the n-type shielding layer on both sides of the n-type buffer layer have the sum of the original donor concentration N _D0 and the doping amount of the shielding region (N _D ′ = N _D + N _D0 ). Therefore, the donor concentration in the n-type shield region is non-uniform, but carriers do not run through the shield region, which is acceptable.

  The passivation film is not attached after removing both sides of the pn junction once by etching. Therefore, an irregular crystal structure creates a lot of boundary levels, which does not cause leakage current. Similarly, there are n-type shielding regions on both sides of the p-region, which are formed by n-type diffusion and ion implantation, and a buried laser for epi-growing an n-type layer after removing both sides of the pn junction. Is different. Since the buried laser needs to make the light emitting portion have a very narrow stripe, both sides are removed by etching and the n-type layer is epitaxially grown. However, the present invention is not buried because it is not necessary. Since the n-type shielding region is formed by diffusion or ion implantation, there is no moment when both sides of the pn junction are exposed. Therefore, crystallinity does not deteriorate.

  In the present invention, a pn junction is formed by an epitaxial growth method, not by selective diffusion through a mask. Therefore, there is no variation in the depth of the pn junction, and the depth can be determined accurately. The variation in the position of the pn junction within the wafer and between the wafers is reduced. Therefore, it is possible to improve the low yield due to variations in sensitivity and capacitance, which have been a problem with conventional light-receiving elements using the impurity selective diffusion method. Since the side surface of the pn junction is a high-concentration n-type shielding region, the depletion layer does not extend. This is because the thickness of the depletion layer is proportional to the square root of the reciprocal of the dopant concentration. Therefore, the depletion layer extends in the lateral direction and the capacitance does not increase excessively. Since the pn junction can be made into a steep step type, it has excellent high-speed response. This is an advantage over the light diffusion element of the thermal diffusion method.

  In the present invention, the periphery of the light receiving region is not temporarily removed, but the peripheral n type shielding region is generated by diffusion of n type impurities and ion implantation. Compared to the conventional method in which a pn junction is formed by epitaxial growth and mesa etching is performed to form a passivation film, the present invention in which the pn junction is surrounded by an n-type shielding region does not require mesa etching, and the pn junction caused by mesa etching This eliminates the problem of current leakage from the end of the. Therefore, the dark current is small and stable, and the temperature characteristics are also stable. Therefore, the yield increases.

  Since the light receiving region is surrounded by the n-type shielding region containing a high concentration of n-type impurities, it is possible to prevent the depletion layer from spreading laterally when a bias voltage is applied. When the depletion layer spreads laterally, the capacity increases. However, in the present invention, the depletion layer does not extend in the lateral direction, so that the capacitance does not increase. In order to increase the high-speed response of the light receiving element, it is necessary to reduce the light receiving diameter and the capacity. For example, in order to obtain a high-speed response of 10 Gbps, the light receiving diameter needs to be 20 μm to 30 μm in the conventional method. Still, since the pn junction extends about 10 μm in the lateral direction by applying a reverse bias, the diameter is effectively 30 μm to 40 μm.

  In the present invention, since the depletion layer does not spread laterally even when a reverse bias is applied, the light receiving diameter can be increased by about 10 μm (30 μm to 40 μmφ) as compared with the conventional device. Therefore, the electrode formation (p-electrode) process becomes easier as compared with the conventional method.

InP-based, GaAs-based, and Si-based light-receiving elements can be manufactured by the method of the present invention.
Describe the layer structure from above.

(A) InP system
p-electrode: Anti-reflection film (top-incident type)
p-type InP window layer: n-type InP shielding region
p-type InGaAs absorption layer: n-type InGaAs shielding region
n-type InGaAs light receiving layer: n-type InGaAs shielding region
n-type InP buffer layer: n-type InP shielding region
n-type InP substrate
n-electrode: Antireflection film (back-illuminated type)
In the case of the top incidence type, the antireflection film is on the upper surface, and in the case of the back side incidence type, the antireflection film is on the lower side.

(A) In the case of GaAs (FIG. 9)
p-electrode: Anti-reflection film (top-incident type)
p-type GaAs window layer: n-type GaAs shielding region
p-type GaInNAs light-receiving layer: n-type GaInNAs shielding region
n-type GaInNAs light-receiving layer: n-type GaInNAs shielding region
n-type GaAs buffer layer: n-type GaAs shielding region
n-type GaAs substrate
n-electrode: Antireflection film (back-illuminated type)
In the case of the top incidence type, the antireflection film is on the upper surface, and in the case of the back side incidence type, the antireflection film is on the lower side.

  According to the present invention, a top-incident type and a back-incident type light receiving element can be manufactured.

[(A). Manufacturing method of top-illuminated light receiving element (FIG. 4)]
A manufacturing process when the present invention is applied to a top-illuminated type light receiving element will be described with reference to FIG. An n-type buffer layer 3, an n-type light-receiving layer 22, and a p-type light-receiving layer 23 are epitaxially grown on the heavily doped n-type substrate 2 (FIG. 4 (1)). That is an epi-wafer. The light receiving layer is divided into an n-type light receiving layer 22 and a p-type light receiving layer 23. The boundary is a pn junction 26. The p-type is heavily doped, while the n-type is lightly doped or undoped. This is because it is necessary to extend the depletion layer widely toward the n-type. As shown in FIG. 4B, a SiN film 27 serving as a diffusion mask is formed on the epi layer by a P-CVD method or the like. SiN etches away the peripheral portion while leaving the central portion. Instead of opening at the center of the element, a window is opened at the periphery.

  As shown in FIG. 4 (3), n-type impurities are thermally diffused or ion-implanted from above through the peripheral window. The portions of the light receiving layers 23 and 22 and the buffer layer 3 on both sides serve as the n-type shielding region 38. A part of the n-type region is applied to the buffer layer 3. The n-type shielding region 38 may be provided below the upper boundary of the buffer layer 3, and may be recessed into a part of the substrate 2. The limitation of the depth is gentle and the control of the n-type dopant is easy. Thus, since both sides are n-type, the pn junction 26 is narrowed. The size of the pn junction 26 is fixed because it is determined by the mask 27. An SiON film, for example, is formed thereon as an antireflection film (AR film; Anti-reflection film) (FIG. 4 (4)). This is a film for all incident light to be incident without being reflected. As shown in FIG. 4 (5), a part of the antireflection film 7 is removed by etching, a p-electrode material is deposited, alloyed, and ohmic-bonded. That is the p-electrode 8. As shown in FIG. 4 (6), an n-electrode material is deposited on the back surface of the n-type substrate 2 and heated to be alloyed. As a result, an n-electrode 9 in ohmic contact is formed.

  A specific example of a top-illuminated light receiving element is shown in FIG. This is because an n-type InP buffer layer, an n-type InGaAs light-receiving layer, and a p-type InGaAs light-receiving layer are epitaxially grown on the n-type InP substrate 2, cover the center with an SiN film, and diffuse Sn to form an n-type shielding region 38. The p electrode 8 is attached to the p-type InGaAs light-receiving layer, and the n-electrode 9 is attached to the back surface of the n-type InP substrate 2.

[(B). Manufacturing method of back-illuminated light receiving element (FIG. 5)]
A manufacturing process when the present invention is applied to a back-illuminated type light receiving element will be described with reference to FIG. It is the same as the top incidence type until halfway. An n-type buffer layer 3, an n-type light-receiving layer 22, and a p-type light-receiving layer 23 are epitaxially grown on the heavily doped n-type substrate 2 (FIG. 5 (1)). That is an epi-wafer. The light receiving layer is divided into an n-type light receiving layer 22 and a p-type light receiving layer 23. The boundary is a pn junction 26. The p-type light receiving layer 23 is highly doped, while the n-type light receiving layer 22 is lightly doped or undoped. This is because it is necessary to extend the depletion layer widely toward the n-type. As shown in FIG. 5B, a SiN film 27 serving as a diffusion mask is formed on the epi layer by a P-CVD method or the like. SiN etches away the peripheral portion while leaving the central portion.

  The opening (window) is not opened at the center of the element but at the periphery. As shown in FIG. 5C, n-type impurities are thermally diffused or ion-implanted from above. The portions of the light receiving layers 23 and 22 and the buffer layer 3 on both sides serve as the n-type shielding region 38. The n-type shielding region 38 is partially covered with the buffer layer 3. There may be an n-type shielding region 38 below the upper boundary of the buffer layer 3, or it may be partially embedded in the substrate 2. The limitation of the depth is gentle and the control of the n-type dopant is easy. Thus, since both sides are n-type, the pn junction 26 is narrowed. The size of the pn junction 26 is fixed because it is determined by the mask 27. A part of the mask 27 is removed, and a p-electrode material is deposited on the p-type light-receiving layer 23 and alloyed to form the p-electrode 8 (FIG. 5 (4)). An antireflection film 39 (AR film) is formed on the back surface of the n-type substrate 2 by P-CVD or the like (FIG. 5 (5)). An n-electrode material is deposited on the exposed surface of the substrate 2 by removing the peripheral portion of the antireflection film 39. The n-electrode 9 is formed by heat alloying. The central portion of the back surface of the substrate is an opening for receiving incident light.

  The light receiving element of FIG. 1 is one that thermally diffuses p-type impurities in the center, but the light receiving element of the present invention (FIGS. 4 and 5) diffuses n-type impurities on both sides. Ion implantation may be performed instead of diffusion. SiN or the like is used as a mask, but it prevents n-type impurities from entering the central portion and does not remove the central portion, and is also useful for protecting the p region under it.

  The pn junction thus formed is partitioned into both n-type shielding regions 38. Since the n-type shielding region 38 is a high-concentration n-type region, the depletion layer does not extend in the lateral direction even if reverse bias is applied. Therefore, increasing the reverse bias does not increase the capacity. The n-type impurity is S, Si, or Sn, and the n-type impurity may be introduced by ion implantation or diffusion. In the case of diffusion, it is easy to perform high-concentration n-type impurity diffusion exceeding the p-concentration of the p-type light-receiving layer 23 that is a high-concentration p region. In the case of ion implantation, it is necessary to change the acceleration energy in several steps to form an n-type region extending from the light receiving layer, the buffer layer, and the substrate.

An embodiment of the present invention (FIG. 8) will be described.
On the sulfur (S) -doped n-type InP substrate 2, an Si-doped n-type InP buffer layer 3 (thickness 2 μm, carrier concentration n = 1 × 10 ¹⁸ cm ⁻³ ), an undoped InGaAs light receiving layer 22 (thickness 2.5 μm, n-type, carrier concentration n = 1 × 10 ¹⁵ cm ⁻³ ), zinc (Zn) -doped InGaAs light receiving layer 23 (thickness 1 μm, p-type, carrier concentration p = 5 × 10 ¹⁸ cm ⁻³ ), Zn-doped p-type InP Window layers (thickness 1.5 μm, p-type, carrier concentration p = 5 × 10 ¹⁸ cm ⁻³ ) were sequentially formed by the MOVPE method (metal organic vapor phase epitaxy method). This is an epi-wafer. The layer structure is written from the top as follows.

p-type InP window layer (1.5 μm p = 5 × 10 ¹⁸ cm ⁻³ )
p-type InGaAs absorption layer (1 μm p = 5 × 10 ¹⁸ cm ⁻³ )
n-type InGaAs light-receiving layer (2.5 μm n = 1 × 10 ¹⁵ cm ⁻³ )
n-type InP buffer layer (2 μm n = 1 × 10 ¹⁸ cm ⁻³ )

The raw materials of the OMVPE method are TMIn (trimethylindium (CH ₃ ) ₃ In), TEGa (triethylgallium (C ₂ H ₅ ) ₃ Ga), arsine (AsH ₃ ), phosphine (PH ₃ ), DEZn (diethyl zinc), monosilane (SiH ₄ ) was used. The growth temperature is 650 ° C. The growth pressure was 40 Torr (5320 Pa).

  The portion that becomes the light receiving region is a portion having a center diameter of 40 μm. Covering with a SiN film, the periphery was removed by etching, and only the light receiving region was covered with a circular SiN mask having a diameter of 40 μm, and n-type impurities (for example, Sn) were selectively diffused around the circular light receiving region. This is to make the periphery of the circular light receiving region n-type. Here, for Sn selective diffusion, Sn added with twice the amount of InP saturated at 600 ° C. (referred to as InP / Sn solution) was used. An epi-wafer whose non-light-receiving region other than the light-receiving region is covered with a SiN mask and an InP / Sn solution are placed in the same quartz tube, and evacuated and sealed.

  The quartz tube is put in an electric furnace and heated to 600 ° C. to diffuse Sn into the non-light-receiving region. The diffusion is performed until Sn entering from the upper surface reaches the buffer layer through the p-type window layer, the p-type and the n-type light receiving layer. The diffusion depth is deeper than the sum of the thicknesses of the p-type window layer, the p-type and the n-type light receiving layer, and is shallower than the sum of the thickness of the window layer, the light receiving layer, the buffer layer, and the substrate. The substrate is about 300 μm to 600 μm, and the diffusion does not go to such a length. Therefore, there is almost no upper limit of the diffusion depth.

  In the above example, since the total of the p-type window layer, the p-type and the n-type light receiving layer is 5.0 μm, the diffusion depth may be 5.0 μm or more. There is no problem even if it reaches the InP substrate beyond the buffer layer. In other words, Sn diffusion for creating a dead area may be 5.0 μm or more, so that strict control of Sn diffusion is unnecessary. The diffusion is easy. In the case where the p-type region is formed by Zn diffusion as in the conventional method, the depth of the pn junction has to be a certain depth inside the light receiving layer, which is difficult and has varied characteristics. In the present invention, n-type impurities are diffused in order to form a non-sensitive region (n-type shielding layer), but this is easier because only the lower limit of the diffusion depth is determined and the upper limit is not determined.

  Thereafter, the SiN film on the light receiving region is removed, and an antireflection film (AR film) 7 is formed. Further, a part of the AR film was removed by etching to form a p-electrode 8. The AR film 7 is made of SiON. The p electrode is made of AuZn. Further, an n electrode 9 made of AuGeNi was formed on the back surface of the InP substrate 2.

  Since the device structure was completed, the InP wafer was cut into a large number of chips in element units. FIG. 8 shows the state of the chip. The chip was attached to a package, and a lead and a p-electrode were connected by wire bonding and sealed to form an element. The temperature characteristics of dark current and dark current were measured without applying a reverse bias and irradiating light. The sensitivity was also measured by irradiating light. Sensitivity is good, capacity is small and variation is small. Also, the dark current itself is small and its variation is small. Even when a strong reverse bias was applied, the depletion layer did not spread laterally and the increase in capacitance was slight. Therefore, it has excellent high-speed response. High-speed operation of 10 Gbps or more was possible.

  FIG. 6 shows a light-receiving element manufactured by a conventional method (in which a pn junction formed by epi growth is removed by mesa etching and covered with an InP film: FIG. 2), and a pn junction formed by epi growth using an n-type impurity. What is limited by diffusion and ion implantation: FIG. 4 shows the result of examining the product yield of the wafer for the light receiving element manufactured in FIG. A large number of chips can be cut out from a single wafer, and the ratio of non-defective products that satisfy certain standards is called yield. The vertical axis represents the total product yield (%) based on criteria such as sensitivity, dark current, and capacitance.

  The left side is based on the conventional method. There were 7 wafers of about 80%, but there are 4 wafers of 50% or less. The remainder is about 60% to 70% yield. The average yield is about 70%.

  The right side is according to the present invention. There are 5 sheets between 80% and 90% and 8 sheets over 90%. The average yield is about 90%. When both are compared, it can be seen that the production method of the present invention has a higher yield.

Process drawing which shows the manufacturing method of the light receiving element concerning the prior art example which produces a dish-shaped p area | region by selective diffusion of Zn using a mask. A p-type light-receiving layer is grown on the n-type light-receiving layer, a boundary surface is formed as a pn junction, both sides of the p region are removed by mesa etching, and a pn junction end exposed by a passivation film such as InP or SiN, a side surface of the light-receiving layer, and a buffer layer Process drawing which shows the manufacturing method of the light receiving element concerning the prior art example which coat | covers the top. FIG. 6 is a light-receiving element cross-sectional view for explaining that when a reverse bias is applied to a light-receiving element manufactured by a conventional method, a depletion layer spreads sideways and a capacitance increases. FIG. 3A shows the case of a light receiving element by selective diffusion, and FIG. 3B shows the case of epi growth and a passivation film. FIG. 6 is a process diagram in the case of manufacturing a top-illuminated light receiving element using the method of the present invention. Process drawing in the case of manufacturing a back-illuminated light receiving element using the method of the present invention. Product yield based on sensitivity, dark current, and capacitance when a light receiving element is made by the conventional method (epi-grown pn junction, mesa etching, passivation film), and when the light receiving element is made by the method of the present invention The graph which shows the result of measuring the product yield based on sensitivity, dark current, and capacity. FIG. 2 is a layer structure diagram showing one specific InP-based light receiving element structure of the present invention. FIG. 3 is a layer structure diagram of an InP-based top-incident light receiving element according to an example of the present invention. FIG. 2 is a layer structure diagram showing one specific GaAs-based light receiving element structure of the present invention.

Explanation of symbols

2 Highly doped n-type substrate
3 n-type buffer layer
4 n-type absorption layer
5 SiN film
6 p region
7 Antireflection film (AR film)
8 p-electrode
9 n electrode
20 windows
22 n-type absorption layer
23 p-type absorption layer
25 Vertical pn junction
26 Horizontal pn junction
27 SiN film 28 Upper surface 29 in the middle of the buffer layer Side surface
30 Passivation film
32 Lower depletion layer
33 Horizontal depletion layer
38 n-type shielding region (for example, Sn is diffused)
39 Antireflection film (AR film)

Claims (13)

The central portion is a light receiving region, and an n-type buffer layer, an n-type light receiving layer, and a p-type light receiving layer are formed on the n-type semiconductor substrate by epitaxial growth, and the periphery of the light receiving region is formed by diffusion or ion implantation. The formed light receiving layer is surrounded by an n type shielding region having an n type impurity concentration equal to or higher than the p type impurity concentration, an n electrode is formed on the bottom surface of the n type semiconductor substrate, and the p type light receiving layer has a p electrode. A light receiving element characterized by being formed. 2. The light receiving element according to claim 1, wherein the n-type impurity concentration of the peripheral n-type shielding region is 1 × 10 ¹⁸ cm ⁻³ or more. The p-electrode is formed on a part of the upper surface of the p-type light-receiving layer, the remaining p-type light-receiving layer is covered with a transparent anti-reflection film, and the optical signal to be detected is a top-incident type that enters from the anti-reflection film side. The light receiving element according to claim 1, wherein: 4. The light receiving element according to claim 3, wherein a p type window layer made of a semiconductor having a wider band gap than the p type and n type light receiving layers is provided between the p type light receiving layer and the p electrode. The n-electrode is formed on a part of the back surface of the n-type substrate, and a transparent antireflection film is formed on the back surface of the remaining substrate. The optical signal to be detected is a back-illuminated type in which the light signal to be detected enters through the antireflection film on the back surface of the substrate. The light receiving element according to claim 1, wherein the light receiving element is provided. 6. The light receiving element according to claim 1, wherein the substrate is n-type InP, the buffer layer is n-type InP, and the light-receiving layer is n-type InGaAs and p-type InGaAs. 6. The light receiving element according to claim 1, wherein the substrate is n-type GaAs, the buffer layer is n-type GaAs, and the light-receiving layer is n-type GaInNAs and p-type GaInNAs. 8. The light receiving device according to claim 1, wherein the p type impurity of the p type light receiving layer is Zn, and the n type impurity of the n type substrate and the n type shielding region is S, Si or Sn. element. An n-type buffer layer, an undoped or lightly doped n-type light-receiving layer, and a p-type light-receiving layer are epitaxially grown on an n-type semiconductor substrate, and an n-type, p-type light-receiving layer, and n-type buffer layer are formed as a light-receiving region at the center. The n-type impurity having a concentration higher than the p-type impurity concentration of the p-type light-receiving layer is introduced into the peripheral portion surrounding the central light-receiving region by selective diffusion or ion implantation, and a p-electrode is formed on the p-type light-receiving layer. A method for manufacturing a light receiving element, comprising forming an n-electrode on the back surface of the n-type semiconductor substrate. The semiconductor substrate is n-type InP, the light-receiving layer is n-type InGaAs, and p-type InGaAs. Of the light-receiving layers, the n-type light-receiving layer is undoped or n-type InGaAs epitaxially grown using Si or S as a dopant, and the p-type light-receiving layer is The method for manufacturing a light receiving element according to claim 9, wherein the light receiving element is p-type InGaAs epitaxially grown using Zn as a dopant. The semiconductor substrate is n-type GaAs, the light-receiving layer is n-type GaInNAs, and p-type GaInNAs. Of the light-receiving layers, the n-type light-receiving layer is undoped or epitaxially grown using Si or S as a dopant, and the p-type light-receiving layer is The method of manufacturing a light receiving element according to claim 9, wherein the light receiving element is p-type GaInNAs epitaxially grown using Zn as a dopant. The peripheral n-type shielding region surrounding the light-receiving region is produced by diffusion of Sn from a gas generated when heating to 500 ° C. or higher is added to Sn in excess of the saturation amount at the temperature at which the InP crystal is diffused. The method of manufacturing a light receiving element according to claim 10. 12. The method for manufacturing a light receiving element according to claim 10, wherein the n-type shielding region surrounding the periphery of the light receiving region is formed by ion implantation of Sn, Si, or S.

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